The STM32L486xx devices are the ultra-low-power microcontrollers based on the highperformance Arm ® Cortex ® -M4 32-bit RISC core operating at a frequency of up to 80 MHz.

The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all

Arm ® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.

The STM32L486xx devices embed high-speed memories (1 Mbyte of Flash memory,

128 Kbyte of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), a Quad SPI flash memories interface

(available on all packages) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.

The STM32L486xx devices embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, proprietary code readout protection and Firewall.

The devices offer up to three fast 12-bit ADCs (5 Msps), two comparators, two operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, two general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support four digital filters for external sigma delta modulators (DFSDM).

In addition, up to 24 capacitive sensing channels are available. The devices also embed an integrated LCD driver 8x40 or 4x44, with internal step-up converter.

They also feature standard and advanced communication interfaces.

• Three I2Cs

• Three SPIs

• Three USARTs, two UARTs and one Low-Power UART.

• Two SAIs (Serial Audio Interfaces)

• One SDMMC

• One CAN

• One USB OTG full-speed

• One SWPMI (Single Wire Protocol Master Interface)

The STM32L486xx devices embed AES hardware accelerator.

The STM32L486xx operates in the -40 to +85 °C (+105 °C junction), -40 to +105 °C

(+125 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to

3.6 V V

power supply when using internal LDO regulator and a 1.05 to 1.32V V

DD12 power supply when using external SMPS supply. A comprehensive set of power-saving modes allows the design of low-power applications.

Some independent power supplies are supported: analog independent supply input for

ADC, DAC, OPAMPs and comparators, 3.3 V dedicated supply input for USB and up to 14

I/Os can be supplied independently down to 1.08V. A VBAT input allows to backup the RTC and backup registers. Dedicated V

DD12

power supplies can be used to bypass the internal

LDO regulator when connected to an external SMPS.

The STM32L486xx family offers five packages from 64-pin to 144-pin packages.

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Table 2. STM32L486xx family device features and peripheral counts

Peripheral STM32L486Zx STM32L486Qx STM32L486Vx STM32L486Jx STM32L486Rx

Flash memory 1 MB

External memory controller for static memories

Quad SPI

Advanced control

General purpose

Timers

Comm. interfaces

Basic

Low power

SysTick timer

Watchdog timers

(independent

, window)

SPI

USART

UART

LPUART

SAI

CAN

USB OTG

SDMMC

SWPMI

Digital filters for sigmadelta modulators

Number of channels

RTC

Tamper pins

LCD

COM x SEG

Random generator

AES

Yes

8x40 or 4x44

Yes

8x40 or 4x44

Yes (1)

Yes

2 (16-bit)

5 (16-bit)

2 (32-bit)

2 (16-bit)

Yes

8x40 or 4x44

Yes

Yes (4 filters)

Yes

8x28 or 4x32

Yes

8x28 or 4x32

DS10199 Rev 7

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Description STM32L486xx

Table 2. STM32L486xx family device features and peripheral counts (continued)

Peripheral STM32L486Zx STM32L486Qx STM32L486Vx STM32L486Jx STM32L486Rx

GPIOs

(2)

Wakeup pins

Nb of I/Os down to 1.08 V

Capacitive sensing

Number of channels

12-bit ADCs

Number of channels

114

109

12-bit DAC channels

Internal voltage reference buffer

Analog comparator

Operational amplifiers

Max. CPU frequency

Operating voltage (V

)

Operating voltage (V

DD12

)

Operating temperature

Packages

Yes No

80 MHz

1.71 to 3.6 V

1.05 to 1.32 V

Ambient operating temperature: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C

Junction temperature: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C

LQFP144 UFBGA132 LQFP100 WLCSP72 LQFP64

1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select.

2. In case external SMPS package type is used, 2 GPIO's are replaced by VDD12 pins to connect the SMPS power supplies hence reducing the number of available GPIO's by 2.

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STM32L486xx Description

Figure 1. STM32L486xx block diagram

NJTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

TRACECLK

TRACED[3:0]

8 Groups of

3 channels max as AF

PA[15:0]

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

PF[15:0]

PG[15:0]

PH[1:0]

8 analog inputs common to the 3 ADCs

8 analog inputs common to the ADC1 & 2

8 analog inputs for ADC3

VREF+

114 AF

D[7:0]

CMD, CK as AF

3 compl. channels (TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]),

ETR, BKIN, BKIN2 as AF

3 compl. channels (TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]),

ETR, BKIN, BKIN2 as AF

2 channels,

1 compl. channel, BKIN as AF

1 channel,

1 compl. channel, BKIN as AF

1 channel,

1 compl. channel, BKIN as AF

RX, TX, CK,CTS,

RTS as AF

MOSI, MISO,

SCK, NSS as AF

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK

MCLK_B, SD_B, FS_B, SCK_B as AF

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK

MCLK_B, SD_B, FS_B, SCK_B as AF

SDCKIN[7:0], SDDATIN[7:0],

SDCKOUT,SDTRIG as AF

INP, INN, OUT

JTAG & SW

ETM

ARM Cortex-M4

80 MHz

FPU

MPU

NVIC

D-BUS

I-BUS

S-BUS

DMA2

DMA1

Touch sensing controller

GPIO PORT A

GPIO PORT B

GPIO PORT C

GPIO PORT D

GPIO PORT E

GPIO PORT F

GPIO PORT G

GPIO PORT H

@ VDD

@ VDDA

ADC1

ADC2

ADC3

@ VDDA

VREF Buffer

EXT IT. WKUP

SDIO / MMC

TIM1 / PWM 16b

TIM8 / PWM 16b

TIM15

TIM16

TIM17 smcard

IrDA

USART1

SPI1

SAI1

SAI2

DFSDM

@ VDDA

COMP1

COMP2

16b

Firewall

AHB/APB2

Flexible static memory controller (FSMC):

SRAM, PSRAM, NOR Flash,

NAND Flash

Quad SPI memory interface

@ VDDA

DAC1

DAC2

SRAM 96 KB

SRAM 32 KB

AHB2 80 MHz

AHB/APB1

WWDG

TIM6

TIM7

Flash up to

1 MB

@ VDD

16b

MSI

RC HSI

RC LSI

PLL 1&2&3

Reset & clock control

CRC

ITF

CLK, NE[4:1], NL, NBL[1:0],

A[25:0], D[15:0], NOE, NWE,

NWAIT, NCE3, INT3 as AF

BK1_IO[3:0]

CLK

NCS

@VDDA

TIM2

32b

TIM3

16b

TIM4

16b

TIM5

USART2

USART3

32b smcard

IrDA smcard

IrDA

UART4

UART5

SP2

SP3

I2C1/SMBUS

I2C2/SMBUS

I2C3/SMBUS bxCAN1

OpAmp1

OpAmp2

LCD Booster

LCD 8x40

LPUART1

SWPMI

LPTIM1

LPTIM2

RNG

AES

USB

OTG

@ VDDUSB reset

Int

VDD Power management

Voltage regulator

3.3 to 1.2 V

@ VDD

Supply supervision

BOR

PVD, PVM

@VDD

XTAL OSC

4- 16MHz

IWDG

Standby interface

@VBAT

XTAL 32 kHz

RTC

AWU

Backup register

SCL, SDA, INTN, ID, VBUS, SOF

VDD = 1.71 to 3.6 V

VDD12 = 1.05 to 1.32 V (1)

VSS

VDDIO2, VDDUSB

VDDA, VSSA

VDD, VSS, NRST

OSC_IN

OSC_OUT

VBAT = 1.55 to 3.6 V

OSC32_IN

OSC32_OUT

RTC_TS

RTC_TAMPx

RTC_OUT

4 channels, ETR as AF

RX, TX, CK, CTS, RTS as AF

RX, TX, CTS, RTS as AF

MOSI, MISO, SCK, NSS as AF

SCL, SDA, SMBA as AF

TX, RX as AF

OUT, INN, INP

LCD

= 2.5V to 3.6V

SEGx, COMx as AF

RX, TX, CTS, RTS as AF

SWP

IN1, IN2, OUT, ETR as AF

IN1, OUT, ETR as AF

MSv31749V3 1. Only available when using external SMPS supply mode.

Note: AF: alternate function on I/O pins.

DAC1_OUT DAC2_OUT

DS10199 Rev 7

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Functional overview STM32L486xx

3.1 Arm

®

Cortex

®

-M4 core with FPU

The Arm

Cortex

-M4 with FPU processor is the latest generation of Arm

processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of

MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm

Cortex

-M4 with FPU 32-bit RISC processor features exceptional codeefficiency, delivering the high-performance expected from an Arm

core in the memory size usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.

Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation.

With its embedded Arm

core, the STM32L486xx family is compatible with all Arm

tools and software.

Figure 1 shows the general block diagram of the STM32L486xx family devices.

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard Arm ® Cortex the Arm ® Cortex ®

® -M4 processors. It balances the inherent performance advantage of

-M4 over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies.

To release the processor near 100 DMIPS performance at 80MHz, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 80 MHz.

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

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STM32L486xx

3.4

Functional overview

Embedded Flash memory

STM32L486xx devices feature 1 Mbyte of embedded Flash memory available for storing programs and data. The Flash memory is divided into two banks allowing read-while-write operations. This feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank. The dual bank boot is also supported.

Each bank contains 256 pages of 2 Kbyte.

Flexible protections can be configured thanks to option bytes:

• Readout protection (RDP) to protect the whole memory. Three levels are available:

– Level 0: no readout protection

– Level 1: memory readout protection: the Flash memory cannot be read from or written to if either debug features are connected, boot in RAM or bootloader is selected

– Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This selection is irreversible.

Table 3. Access status versus readout protection level and execution modes

Area

Protection level

User execution

Debug, boot from RAM or boot from system memory (loader)

Read Write Erase Read Write Erase

Main memory

System memory

Option bytes

Backup registers

SRAM2

Yes

1. Erased when RDP change from Level 1 to Level 0.

Yes

N/A

(1)

N/A

Yes (1)

Yes

N/A

Yes

N/A

Yes

N/A

Yes

N/A

Yes

N/A

(1)

N/A

No (1)

N/A

• Write protection (WRP): the protected area is protected against erasing and programming. Two areas per bank can be selected, with 2-Kbyte granularity.

• Proprietary code readout protection (PCROP): a part of the flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU, as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.

One area per bank can be selected, with 64-bit granularity. An additional option bit

(PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0.

DS10199 Rev 7

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Functional overview STM32L486xx

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

• single error detection and correction

• double error detection.

• The address of the ECC fail can be read in the ECC register

STM32L486xx devices feature 128 Kbyte of embedded SRAM. This SRAM is split into two blocks:

• 96 Kbyte mapped at address 0x2000 0000 (SRAM1)

• 32 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).

This block is accessed through the ICode/DCode buses for maximum performance.

These 32 Kbyte SRAM can also be retained in Standby mode.

The SRAM2 can be write-protected with 1 Kbyte granularity.

The memory can be accessed in read/write at CPU clock speed with 0 wait states.

3.6 Firewall

The device embeds a Firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas.

Each illegal access generates a reset which kills immediately the detected intrusion.

The Firewall main features are the following:

• Three segments can be protected and defined thanks to the Firewall registers:

– Code segment (located in Flash or SRAM1 if defined as executable protected area)

– Non-volatile data segment (located in Flash)

– Volatile data segment (located in SRAM1)

• The start address and the length of each segments are configurable:

– Code segment: up to 1024 Kbyte with granularity of 256 bytes

– Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes

– Volatile data segment: up to 96 Kbyte with a granularity of 64 bytes

• Specific mechanism implemented to open the Firewall to get access to the protected areas (call gate entry sequence)

• Volatile data segment can be shared or not with the non-protected code

• Volatile data segment can be executed or not depending on the Firewall configuration

The Flash readout protection must be set to level 2 in order to reach the expected level of protection.

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STM32L486xx Functional overview

At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:

• Boot from user Flash

• Boot from system memory

• Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI, CAN or USB OTG FS in Device mode through DFU (device firmware upgrade).

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

3.9.1

Note:

Power supply schemes

• V

= 1.71 to 3.6 V: external power supply for I/Os (V

DDIO1

), the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD pins.

• V

DD12

= 1.05 to 1.32 V: external power supply bypassing internal regulator when connected to an external SMPS. It is provided externally through VDD12 pins and only available on packages with the external SMPS supply option. VDD12 does not require any external decoupling capacitance and cannot support any external load.

• V

DDA

= 1.62 V (ADCs/COMPs) / 1.8 (DAC/OPAMPs) to 3.6 V: external analog power supply for ADCs, DAC, OPAMPs, Comparators and Voltage reference buffer. The V

DDA voltage level is independent from the V

voltage.

• V

DDUSB

= 3.0 to 3.6 V: external independent power supply for USB transceivers. The

DDUSB

voltage level is independent from the V

voltage.

• V

DDIO2

= 1.08 to 3.6 V: external power supply for 14 I/Os (PG[15:2]). The V

DDIO2 voltage level is independent from the V

voltage.

• V

LCD

= 2.5 to 3.6 V: the LCD controller can be powered either externally through VLCD pin, or internally from an internal voltage generated by the embedded step-up converter.

• V

BAT

= 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V

is not present.

When the functions supplied by V

DDA should preferably be shorted to V

, V

DDUSB

or V

DDIO2

are not used, these supplies

DS10199 Rev 7

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Functional overview

Note:

STM32L486xx

If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V tolerant (refer to

Table 20: Voltage characteristics

DDIOx

DDIO2

is the I/Os general purpose digital functions supply. V

DDIOx

, with V

DDIO1

= V

. V

DDIO2

represents V

DDIO1

supply voltage level is independent from V

DDIO1

Figure 2. Power supply overview

DDA

SSA

DDA

domain

3 x A/D converters

2 x comparators

2 x D/A converters

2 x operational amplifiers

Voltage reference buffer

LCD

DDUSB

LCD

DDIO2

USB transceivers

DDIO2

domain

I/O ring

PG[15:2]

domain

DDIO1

I/O ring

Reset block

Temp. sensor

3 x PLL, HSI, MSI

Standby circuitry

(Wakeup logic, IWDG)

Voltage regulator

DD12

CORE

domain

Core

SRAM1

SRAM2

Digital peripherals

Flash memory

BAT

Low voltage detector

Backup domain

LSE crystal 32 K osc

BKP registers

RCC BDCR register

RTC

MSv45700V1

During power-up and power-down phases, the following power sequence requirements must be respected:

• When V

is below 1 V, other power supplies (V remain below V

+ 300 mV.

DDA

, V

DDUSB

, V

DDIO2

, V

LCD

) must

• When V

is above 1 V, all power supplies are independent.

During the power-down phase, V

can temporarily become lower than other supplies only if the energy provided to the MCU remains below 1 mJ; this allows external decoupling capacitors to be discharged with different time constants during the power-down transient phase.

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STM32L486xx Functional overview

Figure 3. Power-up/down sequence

3.6

DDX

(1)

BOR0

3.9.2

0.3

Power-on Operating mode Power-down time

Invalid supply area V

DDX

< V

+ 300 mV V

DDX

independent from V

MSv47490V1

1. V

DDX

refers to any power supply among V

DDA

, V

DDUSB

, V

DDIO2

, V

LCD

Power supply supervisor

The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes except Shutdown and ensuring proper operation after power-on and during power down.

The device remains in reset mode when the monitored supply voltage V

DD specified threshold, without the need for an external reset circuit.

is below a

The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected through option bytes.The device features an embedded programmable voltage detector

(PVD) that monitors the V

power supply and compares it to the VPVD threshold. An interrupt can be generated when V

drops below the VPVD threshold and/or when V

is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

In addition, the device embeds a Peripheral Voltage Monitor which compares the independent supply voltages V

DDA

, V

DDUSB

, V

DDIO2

with a fixed threshold in order to ensure that the peripheral is in its functional supply range.

DS10199 Rev 7

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Functional overview STM32L486xx

Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR).

• The MR is used in the Run and Sleep modes and in the Stop 0 mode.

• The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is also used to supply the 32 Kbyte SRAM2 in Standby with SRAM2 retention.

• Both regulators are in power-down in Standby and Shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption.

The ultralow-power STM32L486xx supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the Main Regulator that supplies the logic

CORE

) can be adjusted according to the system’s maximum operating frequency.

There are two power consumption ranges:

• Range 1 with the CPU running at up to 80 MHz.

• Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also limited to 26 MHz.

The V

CORE

can be supplied by the low-power regulator, the main regulator being switched off. The system is then in Low-power run mode.

• Low-power run mode with the CPU running at up to 2 MHz. Peripherals with independent clock can be clocked by HSI16.

When the MR is in use, the STM32L486xx with the external SMPS option allows to force an external V

CORE

supply on the VDD12 supply pins.

When V

DD12

is forced by an external source and is higher than the output of the internal

LDO, the current is taken from this external supply and the overall power efficiency is significantly improved if using an external step down DC/DC converter.

The ultra-low-power STM32L486xx supports seven low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wakeup sources.

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DS10199 Rev 7

Mode

Run

LPRun

Sleep

LPSleep

Regulator

(1)

MR range 1

SMPS range 2

High

MR range2

SMPS range 2

Low

Table 4. STM32L486xx modes overview

CPU Flash SRAM Clocks DMA & Peripherals

(2)

Wakeup source

Yes ON

(4)

ON Any

All

All except OTG_FS, RNG

N/A

LPR Yes ON

(4)

Any except

PLL

All except OTG_FS, RNG N/A

MR range

SMPS range 2

High

MR range2

SMPS range 2

Low

No ON

(4)

(7)

Any

All

All except OTG_FS, RNG

Any interrupt or event

LPR No ON

(4)

(7)

Any except

PLL

All except OTG_FS, RNG

Any interrupt or event

Consumption

(3)

112 µA/MHz

40 µA/MHz

(5)

100 µA/MHz

39 µA/MHz

(6)

136 µA/MHz

37 µA/MHz

13 µA/MHz

(5)

35 µA/MHz

15 µA/MHz

(6)

40 µA/MHz

Wakeup time

N/A to Range 1: 4 µs to Range 2: 64 µs

6 cycles

Mode

Regulator

(1)

Table 4. STM32L486xx modes overview (continued)

CPU Flash SRAM Clocks DMA & Peripherals

(2)

Wakeup source Consumption

(3)

Wakeup time

Stop 0

Stop 1

Range 1

(8)

Range 2

(8)

LPR

No Off ON

LSE

LSI

No Off ON

LSE

LSI

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1,2)

DAC1

OPAMPx (x=1,2)

USARTx (x=1...5)

(9)

LPUART1

(9)

I2Cx (x=1...3)

(10)

LPTIMx (x=1,2)

***

All other peripherals are frozen.

Reset pin, all I/Os

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1..2)

USARTx (x=1...5)

(9)

LPUART1

(9)

I2Cx (x=1...3)

(10)

LPTIMx (x=1,2)

OTG_FS

(11)

SWPMI1

(12)

108 µA

0.7 µs in SRAM

4.5 µs in Flash

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1,2)

DAC1

OPAMPx (x=1,2)

USARTx (x=1...5)

(9)

LPUART1

(9)

I2Cx (x=1...3)

(10)

LPTIMx (x=1,2)

***

All other peripherals are frozen.

Reset pin, all I/Os

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1..2)

USARTx (x=1...5)

(9)

LPUART1

(9)

I2Cx (x=1...3)

(10)

LPTIMx (x=1,2)

OTG_FS

(11)

SWPMI1

(12)

6.6 µA w/o RTC

6.9 µA w RTC

4 µs in SRAM

6 µs in Flash

Mode

Regulator

(1)

Table 4. STM32L486xx modes overview (continued)

CPU Flash SRAM Clocks DMA & Peripherals

(2)

Wakeup source Consumption

(3)

Wakeup time

Stop 2

Standby

Shutdown

LPR

OFF

Powered

Off

Powered

Off

SRAM2

Powered

Off

Powered

Off

LSE

LSI

LSE

LSI

LSE

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1..2)

I2C3

(10)

LPUART1

(9)

LPTIM1

***

All other peripherals are frozen.

BOR, RTC, IWDG

***

All other peripherals are powered off.

***

I/O configuration can be floating, pull-up or pull-down

RTC

***

All other peripherals are powered off.

***

I/O configuration can be floating, pull-up or pulldown

(14)

Reset pin, all I/Os

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1..2)

I2C3

(10)

LPUART1

(9)

LPTIM1

Reset pin

5 I/Os (WKUPx)

BOR, RTC, IWDG

Reset pin

5 I/Os (WKUPx)

RTC

(13)

1.1 µA w/o RTC

1.4 µA w/RTC

0.35 µA w/o RTC

0.65 µA w/ RTC

0.12 µA w/o RTC

0.42 µA w/ RTC

0.03 µA w/o RTC

0.33 µA w/ RTC

5 µs in SRAM

7 µs in Flash

256 µs

1. LPR means Main regulator is OFF and Low-power regulator is ON.

2. All peripherals can be active or clock gated to save power consumption.

3. Typical current at V

LPRun/LPSleep.

= 1.8 V, 25°C. Consumptions values provided running from SRAM, Flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in

4. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.

5. Theoretical value based on V

= 3.3 V, DC/DC Efficiency of 85%, V

CORE

= 1.10 V

6. Theoretical value based on V

= 3.3 V, DC/DC Efficiency of 85%, V

CORE

= 1.05 V

7. The SRAM1 and SRAM2 clocks can be gated on or off independently.

14 µs

8. SMPS mode can be used in STOP0 Mode, but no significant power gain can be expected.

9. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

10. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

11. OTG_FS wakeup by resume from suspend and attach detection protocol event.

12. SWPMI1 wakeup by resume from suspend.

13. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.

14. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

STM32L486xx Functional overview

By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the user to select one of the low-power modes described below:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Low-power run mode

This mode is achieved with V

CORE

supplied by the low-power regulator to minimize the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16.

• Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the lowpower run mode.

• Stop 0, Stop 1 and Stop 2 modes

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the V

CORE

domain are stopped, the PLL, the MSI

RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode to detect their wakeup condition.

Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode, most of the V

CORE

domain is put in a lower leakage mode.

Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator remains ON, allowing a very fast wakeup time but with much higher consumption.

The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI up to 48 MHz or HSI16, depending on software configuration.

• Standby mode

The Standby mode is used to achieve the lowest power consumption with BOR. The internal regulator is switched off so that the V

CORE

domain is powered off. The PLL, the

MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.

The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

The brown-out reset (BOR) always remains active in Standby mode.

The state of each I/O during standby mode can be selected by software: I/O with internal pull-up, internal pull-down or floating.

After entering Standby mode, SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in

Standby mode, supplied by the low-power Regulator (Standby with SRAM2 retention mode).

The device exits Standby mode when an external reset (NRST pin), an IWDG reset,

WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).

The system clock after wakeup is MSI up to 8 MHz.

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Functional overview STM32L486xx

• Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off so that the V

CORE

domain is powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off.

The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported.

SRAM1, SRAM2 and register contents are lost except for registers in the Backup domain.

The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper).

The system clock after wakeup is MSI at 4 MHz.

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Peripheral

Functional overview

Table 5. Functionalities depending on the working mode (1)

Stop 0/1 Stop 2 Standby Shutdown

Run Sleep

Lowpower run

Lowpower sleep -

VBAT

CPU

Flash memory

(1 MB)

SRAM1 (96 KB)

SRAM2 (32 KB)

FSMC

Quad SPI

Backup Registers

Brown-out reset

(BOR)

Programmable

Voltage Detector

(PVD)

Peripheral Voltage

Monitor (PVMx; x=1,2,3,4)

DMA

High Speed Internal

(HSI16)

High Speed External

(HSE)

Low Speed Internal

(LSI)

Low Speed External

(LSE)

Multi-Speed Internal

(MSI)

Clock Security

System (CSS)

Clock Security

System on LSE

RTC / Auto wakeup

Number of RTC

Tamper pins

LCD

(2)

(3)

Y (3)

(2)

(3)

Y (3)

O (4)

Y Y

O O

O O O O

(5)

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Functional overview STM32L486xx

Table 5. Functionalities depending on the working mode (1) (continued)

Stop 0/1 Stop 2 Standby Shutdown

Peripheral Run Sleep

Lowpower run

Lowpower sleep -

VBAT

(8)

USB OTG FS

USARTx

(x=1,2,3,4,5)

Low-power UART

(LPUART)

I2Cx (x=1,2)

I2C3

SPIx (x=1,2,3)

CAN

SDMMC1

SWPMI1

SAIx (x=1,2)

DFSDM1

ADCx (x=1,2,3)

DAC1

VREFBUF

OPAMPx (x=1,2)

COMPx (x=1,2)

Temperature sensor

Timers (TIMx)

Low-power timer 1

(LPTIM1)

Low-power timer 2

(LPTIM2)

Independent watchdog (IWDG)

Window watchdog

(WWDG)

SysTick timer

Touch sensing controller (TSC)

Random number generator (RNG)

(8)

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(7)

O O O O

O O -

O O O O O O

STM32L486xx Functional overview

Table 5. Functionalities depending on the working mode (1) (continued)

Stop 0/1 Stop 2 Standby Shutdown

Peripheral Run Sleep

Lowpower run

Lowpower sleep -

VBAT

AES hardware accelerator

CRC calculation unit

GPIOs

(9)

5 pins

(10)

(11)

5 pins

(10)

1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available.

2. The Flash can be configured in power-down mode. By default, it is not in power-down mode.

3. The SRAM clock can be gated on or off.

4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.

5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore.

6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

8. Voltage scaling Range 1 only.

9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.

10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.

11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

In order to improve the consumption under reset, the I/Os state under and after reset is

“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is deactivated when the reset source is internal.

Note:

The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from V

when no external battery and an external supercapacitor are present. The VBAT pin supplies the RTC with LSE and the backup registers. Three antitamper detection pins are available in VBAT mode.

VBAT operation is automatically activated when V

is not present.

An internal VBAT battery charging circuit is embedded and can be activated when V

DD present.

When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation.

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Functional overview STM32L486xx

Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes.

Table 6. STM32L486xx peripherals interconnect matrix

Interconnect source

Interconnect destination

Interconnect action

TIMx

TIM16/TIM17

COMPx

ADCx

RTC

TIMx

ADCx

DAC1

DFSDM1

DMA

COMPx

IRTIM

TIM1, 8

TIM2, 3

LPTIMERx

TIM1, 8

TIM16

LPTIMERx

Timers synchronization or chaining

Conversion triggers

Memory to memory transfer trigger

Comparator output blanking

Infrared interface output generation

Timer input channel, trigger, break from analog signals comparison

Y Y Y Y -

Low-power timer triggered by analog signals comparison

Timer triggered by analog watchdog

Timer input channel from RTC events

Low-power timer triggered by RTC alarms or tampers

Y Y Y Y Y

(1)

Y Y Y Y -

Y Y Y Y Y

(1)

Clock source used as input channel for

RC measurement and trimming

Timer triggered by USB SOF

All clocks sources (internal and external)

TIM2

TIM15, 16, 17

USB

CSS

CPU (hard fault)

RAM (parity error)

Flash memory (ECC error)

COMPx

PVD

DFSDM1 (analog watchdog, short circuit detection)

TIM2

TIM1,8

TIM15,16,17

Timer break Y Y Y Y -

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Table 6. STM32L486xx peripherals interconnect matrix (continued)

Interconnect source

Interconnect destination

Interconnect action

GPIO

TIMx

LPTIMERx

ADCx

DAC1

DFSDM1

External trigger

Conversion external trigger

Y Y Y Y -

Y Y Y Y Y

(1)

Y Y Y Y -

1. LPTIM1 only.

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Functional overview STM32L486xx

3.11 Clocks and startup

The clock controller (see Figure 4

) distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features:

• Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler

• Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register.

• Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

• System clock source: four different clock sources can be used to drive the master clock SYSCLK:

– 4-48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply a PLL. The HSE can also be configured in bypass mode for an external clock.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can supply a PLL

– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate

12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be automatically trimmed by hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the

USB device, saving the need of an external high-speed crystal (HSE). The MSI can supply a PLL.

– System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency at 80 MHz.

• Auxiliary clock source: two ultralow-power clock sources that can be used to drive the LCD controller and the real-time clock:

– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for an external clock.

– 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

The LSI clock accuracy is ±5% accuracy.

• Peripheral clock sources: Several peripherals (USB, SDMMC, RNG, SAI, USARTs,

I2Cs, LPTimers, ADC, SWPMI) have their own independent clock whatever the system clock. Three PLLs, each having three independent outputs allowing the highest flexibility, can generate independent clocks for the ADC, the USB/SDMMC/RNG and the two SAIs.

• Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

• Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI16 and a software

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STM32L486xx Functional overview interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt.

• Clock-out capability:

– MCO: microcontroller clock output: it outputs one of the internal clocks for external use by the application. Low frequency clocks (LSI, LSE) are available down to Stop 1 low power state.

– LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes down to Standby mode. LSE can also be output on LSCO in Shutdown mode.

LSCO is not available in VBAT mode.

Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 80 MHz.

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Functional overview STM32L486xx

Figure 4. Clock tree to IWDG

LSI RC 32 kHz

LSCO to RTC and LCD

OSC32_OUT

OSC32_IN

LSE OSC

32.768 kHz

MCO

/ 1→16

LSE

LSI

MSI

HSE

SYSCLK

HSI16

PLLCLK

OSC_OUT

OSC_IN

HSE OSC

4-48 MHz

Clock detector

PLL

VCO F VCO

HSI RC

16 MHz

MSI RC

100 kHz – 48 MHz

/ P

/ Q

/ R

PLLSAI3CLK

PLL48M1CLK

PLLCLK

PLLSAI1

VCO F VCO / P

/ Q

/ R

PLLSAI1CLK

PLL48M2CLK

PLLADC1CLK

PLLSAI2

VCO F VCO / P

/ Q

/ R

PLLSAI2CLK

PLLADC2CLK

SAI1_EXTCLK

SAI2_EXTCLK

/32

/ M

HSE

MSI

HSI16

Clock source control

SYSCLK to PWR to AHB bus, core, memory and DMA

AHB

PRESC

/ 1,2,..512

HCLK

/ 8

FCLK Cortex free running clock

APB1

PRESC

/ 1,2,4,8,16 to Cortex system timer

PCLK1 to APB1 peripherals x1 or x2 to TIMx x=2..7

LSE

HSI16

SYSCLK to USARTx x=2..5

to LPUART1

HSI16

SYSCLK to I2Cx x=1,2,3

LSI

LSE

HSI16 to LPTIMx x=1,2

MSI

HSI16

HSE

MSI

SYSCLK

HSI16

APB2

PRESC

/ 1,2,4,8,16 to SWPMI

PCLK2 to APB2 peripherals x1 or x2 to TIMx x=1,8,15,16,17

LSE

HSI16

SYSCLK to

USART1

48 MHz clock to USB, RNG, SDMMC to ADC to SAI1 to SAI2

MS32440V3

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STM32L486xx Functional overview

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

3.13 Direct memory access controller (DMA)

The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features

implementation.

Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations.

The two DMA controllers have 14 channels in total, each dedicated to managing memory access requests from one or more peripherals. Each has an arbiter for handling the priority between DMA requests.

The DMA supports:

• 14 independently configurable channels (requests)

• Each channel is connected to dedicated hardware DMA requests, software trigger is also supported on each channel. This configuration is done by software.

• Priorities between requests from channels of one DMA are software programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality

(request 1 has priority over request 2, etc.)

• Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size.

• Support for circular buffer management

• 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together in a single interrupt request for each channel

• Memory-to-memory transfer

• Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers

• Access to Flash, SRAM, APB and AHB peripherals as source and destination

• Programmable number of data to be transferred: up to 65536.

Table 7. DMA implementation

DMA features DMA1

Number of regular channels 7

DMA2

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Functional overview STM32L486xx

3.14.1 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 82 maskable interrupt channels plus the 16 interrupt lines of the Cortex

M4.

The NVIC benefits are the following:

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail chaining

• Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

3.14.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 40 edge detector lines used to generate interrupt/event requests and wake-up the system from Stop mode. Each external line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests.

The internal lines are connected to peripherals with wakeup from Stop mode capability. The

EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 114 GPIOs can be connected to the 16 external interrupt lines.

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3.15 Analog to digital converter (ADC)

The device embeds 3 successive approximation analog-to-digital converters with the following features:

• 12-bit native resolution, with built-in calibration

• 5.33 Msps maximum conversion rate with full resolution

– Down to 18.75 ns sampling time

– Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution)

• Up to 24 external channels, some of them shared between ADC1 and ADC2, or ADC1,

ADC2 and ADC3.

• 5 internal channels: internal reference voltage, temperature sensor, VBAT/3,

DAC1_OUT1 and DAC1_OUT2.

• One external reference pin is available on some package, allowing the input voltage range to be independent from the power supply

• Single-ended and differential mode inputs

• Low-power design

– Capable of low-current operation at low conversion rate (consumption decreases linearly with speed)

– Dual clock domain architecture: ADC speed independent from CPU frequency

• Highly versatile digital interface

– Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions

– Handles two ADC converters for dual mode operation (simultaneous or interleaved sampling modes)

– Each ADC support multiple trigger inputs for synchronization with on-chip timers and external signals

– Results stored into 3 data register or in RAM with DMA controller support

– Data pre-processing: left/right alignment and per channel offset compensation

– Built-in oversampling unit for enhanced SNR

– Channel-wise programmable sampling time

– Three analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers

– Hardware assistant to prepare the context of the injected channels to allow fast context switching

The temperature sensor (TS) generates a voltage V

that varies linearly with temperature.

The temperature sensor is internally connected to the ADC1_IN17 and ADC3_IN17 input channels which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

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Functional overview STM32L486xx

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

Table 8. Temperature sensor calibration values

Calibration value name Description Memory address

TS_CAL1

TS_CAL2

TS ADC raw data acquired at a temperature of 30 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

TS ADC raw data acquired at a temperature of 110 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

0x1FFF 75A8 - 0x1FFF 75A9

0x1FFF 75CA - 0x1FFF 75CB

3.15.2 Internal voltage reference (V

REFINT

)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC1_IN0 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

Table 9. Internal voltage reference calibration values

Calibration value name Description Memory address

VREFINT

Raw data acquired at a temperature of 30 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

0x1FFF 75AA - 0x1FFF 75AB

3.15.3 V

BAT

battery voltage monitoring

This embedded hardware feature allows the application to measure the V

BAT using the internal ADC channel ADC1_IN18 or ADC3_IN18. As the V

BAT higher than V

DDA

battery voltage

voltage may be

, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 3. As a consequence, the converted digital value is one third the V

BAT

voltage.

3.16 Digital to analog converter (DAC)

Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.

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This digital interface supports the following features:

• Up to two DAC output channels

• 8-bit or 12-bit output mode

• Buffer offset calibration (factory and user trimming)

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• Dual DAC channel independent or simultaneous conversions

• DMA capability for each channel

• External triggers for conversion

• Sample and hold low-power mode, with internal or external capacitor

The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.

The STM32L486xx devices embed an voltage reference buffer which can be used as voltage reference for ADCs, DAC and also as voltage reference for external components through the VREF+ pin.

The internal voltage reference buffer supports two voltages:

• 2.048 V

• 2.5 V

An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off.

The VREF+ pin is double-bonded with VDDA on some packages. In these packages the internal voltage reference buffer is not available.

Figure 5. Voltage reference buffer

VREFBUF

Bandgap +

DDA

DAC, ADC

VREF+

Low frequency cut-off capacitor

100 nF

MSv40197V1

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Functional overview STM32L486xx

The STM32L486xx devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity.

The reference voltage can be one of the following:

• External I/O

• DAC output channels

• Internal reference voltage or submultiple (1/4, 1/2, 3/4).

All comparators can wake up from Stop mode, generate interrupts and breaks for the timers and can be also combined into a window comparator.

The STM32L486xx embeds two operational amplifiers with external or internal follower routing and PGA capability.

The operational amplifier features:

• Low input bias current

• Low offset voltage

• Low-power mode

• Rail-to-rail input

3.20 Touch sensing controller (TSC)

The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle.

The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application.

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Note:

Functional overview

The main features of the touch sensing controller are the following:

• Proven and robust surface charge transfer acquisition principle

• Supports up to 24 capacitive sensing channels

• Up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time

• Spread spectrum feature to improve system robustness in noisy environments

• Full hardware management of the charge transfer acquisition sequence

• Programmable charge transfer frequency

• Programmable sampling capacitor I/O pin

• Programmable channel I/O pin

• Programmable max count value to avoid long acquisition when a channel is faulty

• Dedicated end of acquisition and max count error flags with interrupt capability

• One sampling capacitor for up to 3 capacitive sensing channels to reduce the system components

• Compatible with proximity, touchkey, linear and rotary touch sensor implementation

• Designed to operate with STMTouch touch sensing firmware library

The number of capacitive sensing channels is dependent on the size of the packages and subject to I/O availability.

3.21 Liquid crystal display controller (LCD)

The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels.

• Internal step-up converter to guarantee functionality and contrast control irrespective of

. This converter can be deactivated, in which case the VLCD pin is used to provide the voltage to the LCD

• Supports static, 1/2, 1/3, 1/4 and 1/8 duty

• Supports static, 1/2, 1/3 and 1/4 bias

• Phase inversion to reduce power consumption and EMI

• Integrated voltage output buffers for higher LCD driving capability

• Up to 8 pixels can be programmed to blink

• Unneeded segments and common pins can be used as general I/O pins

• LCD RAM can be updated at any time owing to a double-buffer

• The LCD controller can operate in Stop mode

3.22 Digital filter for Sigma-Delta Modulators (DFSDM)

The device embeds one DFSDM with 4 digital filters modules and 8 external input serial channels (transceivers) or alternately 8 internal parallel inputs support.

The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to microcontroller and then to perform digital filtering of the received data streams (which represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse

Density Modulation) microphones and perform PDM to PCM conversion and filtering in

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Functional overview STM32L486xx hardware. DFSDM features optional parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into DFSDM).

DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators). DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution.

The DFSDM peripheral supports:

• 8 multiplexed input digital serial channels:

– configurable SPI interface to connect various SD modulator(s)

– configurable Manchester coded 1 wire interface support

– PDM (Pulse Density Modulation) microphone input support

– maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)

– clock output for SD modulator(s): 0..20 MHz

• alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):

– internal sources: device memory data streams (DMA)

• 4 digital filter modules with adjustable digital signal processing:

– Sinc x filter: filter order/type (1..5), oversampling ratio (up to 1..1024)

– integrator: oversampling ratio (1..256)

• up to 24-bit output data resolution, signed output data format

• automatic data offset correction (offset stored in register by user)

• continuous or single conversion

• start-of-conversion triggered by:

– software trigger

– internal timers

– external events

– start-of-conversion synchronously with first digital filter module (DFSDM1_FLT0)

• analog watchdog feature:

– low value and high value data threshold registers

– dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)

– input from final output data or from selected input digital serial channels

– continuous monitoring independently from standard conversion

• short circuit detector to detect saturated analog input values (bottom and top range):

– up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream

– monitoring continuously each input serial channel

• break signal generation on analog watchdog event or on short circuit detector event

• extremes detector:

– storage of minimum and maximum values of final conversion data

– refreshed by software

• DMA capability to read the final conversion data

• interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence

• “regular” or “injected” conversions:

– “regular” conversions can be requested at any time or even in continuous mode

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– “injected” conversions for precise timing and with high conversion priority

DFSDM features

Number of channels

Number of filters

Input from internal ADC

Supported trigger sources

Pulses skipper

ID registers support

Table 10. DFSDM1 implementation

DFSDM1

3.23 Random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit.

3.24 Advanced encryption standard hardware accelerator (AES)

The devices embed an AES hardware accelerator can be used to both encipher and decipher data using AES algorithm.

The AES peripheral supports:

• Encryption/Decryption using AES Rijndael Block Cipher algorithm

• NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm

• 128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x

32-bit registers)

• Electronic codebook (ECB), Cipher block chaining (CBC), Counter mode (CTR), Galois

Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher

Message Authentication Code mode (CMAC) supported.

• Key scheduler

• Key derivation for decryption

• 128-bit data block processing

• 128-bit, 256-bit key length

• 1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer.

• Register access supporting 32-bit data width only.

• One 128-bit Register for the initialization vector when AES is configured in CBC mode or for the 32-bit counter initialization when CTR mode is selected, GCM mode or

CMAC mode.

• Automatic data flow control with support of direct memory access (DMA) using 2 channels, one for incoming data, and one for outcoming data.

• Suspend a message if another message with a higher priority needs to be processed

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Functional overview STM32L486xx

3.25 Timers and watchdogs

The STM32L486xx includes two advanced control timers, up to nine general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer.

The table below compares the features of the advanced control, general purpose and basic timers.

Timer type

Advanced control

Generalpurpose

Basic

Timer

TIM1, TIM8

TIM2, TIM5

TIM3, TIM4

TIM15

TIM16, TIM17

TIM6, TIM7

Table 11. Timer feature comparison

Counter resolution

Counter type

Prescaler factor

DMA request generation

16-bit

32-bit

16-bit

Up, down,

Up/down

Up, down,

Up/down

Up, down,

Up/down

Any integer between 1 and 65536

Yes

Capture/ compare channels

Complementary outputs

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The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted deadtimes. They can also be seen as complete general-purpose timers. The 4 independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge or center-aligned modes) with full modulation capability (0-

100%)

• One-pulse mode output

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs.

Many features are shared with those of the general-purpose TIMx timers (described in

Section 3.25.2

) using the same architecture, so the advanced-control timers can work

together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

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TIM17)

There are up to seven synchronizable general-purpose timers embedded in the

STM32L486xx (see

Table 11 for differences). Each general-purpose timer can be used to

generate PWM outputs, or act as a simple time base.

• TIM2, TIM3, TIM4 and TIM5

They are full-featured general-purpose timers:

– TIM2 and TIM5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler

– TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler.

These timers feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together, or with the other general-purpose timers via the Timer Link feature for synchronization or event chaining.

The counters can be frozen in debug mode.

All have independent DMA request generation and support quadrature encoders.

• TIM15, 16 and 17

They are general-purpose timers with mid-range features:

They have 16-bit auto-reload upcounters and 16-bit prescalers.

– TIM15 has 2 channels and 1 complementary channel

– TIM16 and TIM17 have 1 channel and 1 complementary channel

All channels can be used for input capture/output compare, PWM or one-pulse mode output.

The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation.

The counters can be frozen in debug mode.

3.25.3 Basic timers (TIM6 and TIM7)

The basic timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit timebases.

The devices embed two low-power timers. These timers have an independent clock and are running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to wakeup the system from Stop mode.

LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.

LPTIM2 is active in Stop 0 and Stop 1 mode.

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Functional overview STM32L486xx

This low-power timer supports the following features:

• 16-bit up counter with 16-bit autoreload register

• 16-bit compare register

• Configurable output: pulse, PWM

• Continuous/ one shot mode

• Selectable software/hardware input trigger

• Selectable clock source

– Internal clock sources: LSE, LSI, HSI16 or APB clock

– External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application).

• Programmable digital glitch filter

• Encoder mode (LPTIM1 only)

The STM32L486xx includes one infrared interface (IRTIM). It can be used with an infrared

LED to perform remote control functions. It uses TIM16 and TIM17 output channels to generate output signal waveforms on IR_OUT pin.

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC (LSI) and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

3.25.7 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

• A 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0.

• Programmable clock source

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The RTC is an independent BCD timer/counter. It supports the following features:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format.

• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.

• Two programmable alarms.

• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock.

• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision.

• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy.

• Three anti-tamper detection pins with programmable filter.

• Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to

VBAT mode.

• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period.

The RTC and the 32 backup registers are supplied through a switch that takes power either from the V

supply when present or from the VBAT pin.

The backup registers are 32-bit registers used to store 128 bytes of user application data when V

power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby or Shutdown mode.

The RTC clock sources can be:

• A 32.768 kHz external crystal (LSE)

• An external resonator or oscillator (LSE)

• The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)

• The high-speed external clock (HSE) divided by 32.

The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the

LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes except Shutdown mode.

All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes.

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Functional overview STM32L486xx

circuit interface (I

2

C)

The device embeds three

I2C. Refer to Table 12: I2C implementation for the features

implementation.

The I

C bus interface handles communications between the microcontroller and the serial

C bus. It controls all I

C bus-specific sequencing, protocol, arbitration and timing.

The I2C peripheral supports:

• I 2 C-bus specification and user manual rev. 5 compatibility:

– Slave and master modes, multimaster capability

– Standard-mode (Sm), with a bitrate up to 100 kbit/s

– Fast-mode (Fm), with a bitrate up to 400 kbit/s

– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os

– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

– Programmable setup and hold times

– Optional clock stretching

• System Management Bus (SMBus) specification rev 2.0 compatibility:

– Hardware PEC (Packet Error Checking) generation and verification with ACK control

– Address resolution protocol (ARP) support

– SMBus alert

• Power System Management Protocol (PMBus TM ) specification rev 1.1 compatibility

• Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. Refer to

Figure 4: Clock tree .

• Wakeup from Stop mode on address match

• Programmable analog and digital noise filters

• 1-byte buffer with DMA capability

Table 12. I2C implementation

I2C features

(1)

I2C1

Standard-mode (up to 100 kbit/s)

Fast-mode (up to 400 kbit/s)

Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)

Programmable analog and digital noise filters

SMBus/PMBus hardware support

Independent clock

Wakeup from Stop 0 / Stop 1 mode on address match

Wakeup from Stop 2 mode on address match

1. X: supported

I2C2

I2C3

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(USART)

The STM32L486xx devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4, UART5).

These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable. They are able to communicate at speeds of up to

10Mbit/s.

USART1, USART2 and USART3 also provide Smart Card mode (ISO 7816 compliant) and

SPI-like communication capability.

All USART have a clock domain independent from the CPU clock, allowing the USARTx

(x=1,2,3,4,5) to wake up the MCU from Stop mode using baudrates up to 204 Kbaud. The wake up events from Stop mode are programmable and can be:

• Start bit detection

• Any received data frame

• A specific programmed data frame

All USART interfaces can be served by the DMA controller.

Table 13. STM32L486xx USART/UART/LPUART features

USART modes/features (1) USART1 USART2 USART3 UART4 UART5 LPUART1

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode

Smartcard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain

Wakeup from Stop 0 / Stop 1 modes

Wakeup from Stop 2 mode

Receiver timeout interrupt

Modbus communication

Auto baud rate detection

Driver Enable

LPUART/USART data length

1. X = supported.

X (4 modes)

X X

7, 8 and 9 bits

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Functional overview STM32L486xx

(LPUART)

The device embeds one Low-Power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication.

The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop mode are programmable and can be:

• Start bit detection

• Any received data frame

• A specific programmed data frame

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates.

LPUART interface can be served by the DMA controller.

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3.30 Serial peripheral interface (SPI)

Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation.

All SPI interfaces can be served by the DMA controller.

The device embeds 2 SAI. Refer to Table 14: SAI implementation for the features

implementation. The SAI bus interface handles communications between the microcontroller and the serial audio protocol.

The SAI peripheral supports:

• Two independent audio sub-blocks which can be transmitters or receivers with their respective FIFO.

• 8-word integrated FIFOs for each audio sub-block.

• Synchronous or asynchronous mode between the audio sub-blocks.

• Master or slave configuration independent for both audio sub-blocks.

• Clock generator for each audio block to target independent audio frequency sampling when both audio sub-blocks are configured in master mode.

• Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.

• Peripheral with large configurability and flexibility allowing to target as example the following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF out.

• Up to 16 slots available with configurable size and with the possibility to select which ones are active in the audio frame.

• Number of bits by frame may be configurable.

• Frame synchronization active level configurable (offset, bit length, level).

• First active bit position in the slot is configurable.

• LSB first or MSB first for data transfer.

• Mute mode.

• Stereo/Mono audio frame capability.

• Communication clock strobing edge configurable (SCK).

• Error flags with associated interrupts if enabled respectively.

– Overrun and underrun detection.

– Anticipated frame synchronization signal detection in slave mode.

– Late frame synchronization signal detection in slave mode.

– Codec not ready for the AC’97 mode in reception.

• Interruption sources when enabled:

– Errors.

– FIFO requests.

• DMA interface with 2 dedicated channels to handle access to the dedicated integrated

FIFO of each SAI audio sub-block.

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Functional overview

Table 14. SAI implementation

SAI features

(1)

SAI1

I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97

Mute mode

Stereo/Mono audio frame capability.

16 slots

Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit

FIFO Size

SPDIF

1. X: supported

X (8 Word)

STM32L486xx

SAI2

X (8 Word)

The Single wire protocol master interface (SWPMI) is the master interface corresponding to the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The main features are:

• full-duplex communication mode

• automatic SWP bus state management (active, suspend, resume)

• configurable bitrate up to 2 Mbit/s

• automatic SOF, EOF and CRC handling

SWPMI can be served by the DMA controller.

3.33 Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and

14 scalable filter banks.

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The CAN peripheral supports:

• Supports CAN protocol version 2.0 A, B Active

• Bit rates up to 1 Mbit/s

• Transmission

– Three transmit mailboxes

– Configurable transmit priority

• Reception

– Two receive FIFOs with three stages

– 14 Scalable filter banks

– Identifier list feature

– Configurable FIFO overrun

• Time-triggered communication option

– Disable automatic retransmission mode

– 16-bit free running timer

– Time Stamp sent in last two data bytes

• Management

– Maskable interrupts

– Software-efficient mailbox mapping at a unique address space

(SDMMC)

The card host interface (SDMMC) provides an interface between the APB peripheral bus and MultiMediaCards (MMCs), SD memory cards and SDIO cards.

The SDMMC features include the following:

• Full compliance with MultiMediaCard System Specification Version 4.2. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit

• Full compatibility with previous versions of MultiMediaCards (forward compatibility)

• Full compliance with SD Memory Card Specifications Version 2.0

• Full compliance with SD I/O Card Specification Version 2.0: card support for two different databus modes: 1-bit (default) and 4-bit

• Data transfer up to 48 MHz for the 8 bit mode

• Data write and read with DMA capability

3.35 Universal serial bus on-the-go full-speed (OTG_FS)

The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that can be provided by the internal multispeed oscillator (MSI) automatically trimmed by 32.768 kHz external oscillator (LSE).This allows to use the USB device without external high speed crystal (HSE).

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Functional overview STM32L486xx

The major features are:

• Combined Rx and Tx FIFO size of 1.25 KB with dynamic FIFO sizing

• Supports the session request protocol (SRP) and host negotiation protocol (HNP)

• 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints

• 12 host channels with periodic OUT support

• HNP/SNP/IP inside (no need for any external resistor)

• USB 2.0 LPM (Link Power Management) support

• Battery Charging Specification Revision 1.2 support

• Internal FS OTG PHY support

For OTG/Host modes, a power switch is needed in case bus-powered devices are connected.

3.36 Flexible static memory controller (FSMC)

The Flexible static memory controller (FSMC) includes two memory controllers:

• The NOR/PSRAM memory controller

• The NAND/memory controller

This memory controller is also named Flexible memory controller (FMC).

The main features of the FMC controller are the following:

• Interface with static-memory mapped devices including:

– Static random access memory (SRAM)

– NOR Flash memory/OneNAND Flash memory

– PSRAM (4 memory banks)

– NAND Flash memory with ECC hardware to check up to 8 Kbyte of data

• 8-,16- bit data bus width

• Independent Chip Select control for each memory bank

• Independent configuration for each memory bank

• Write FIFO

• The Maximum FMC_CLK frequency for synchronous accesses is HCLK/2.

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost effective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration.

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The Quad SPI is a specialized communication interface targeting single, dual or quad SPI flash memories. It can operate in any of the three following modes:

• Indirect mode: all the operations are performed using the QUADSPI registers

• Status polling mode: the external flash status register is periodically read and an interrupt can be generated in case of flag setting

• Memory-mapped mode: the external Flash is memory mapped and is seen by the system as if it were an internal memory

The Quad SPI interface supports:

• Three functional modes: indirect, status-polling, and memory-mapped

• SDR and DDR support

• Fully programmable opcode for both indirect and memory mapped mode

• Fully programmable frame format for both indirect and memory mapped mode

• Each of the 5 following phases can be configured independently (enable, length, single/dual/quad communication)

– Instruction phase

– Address phase

– Alternate bytes phase

– Dummy cycles phase

– Data phase

• Integrated FIFO for reception and transmission

• 8, 16, and 32-bit data accesses are allowed

• DMA channel for indirect mode operations

• Programmable masking for external flash flag management

• Timeout management

• Interrupt generation on FIFO threshold, timeout, status match, operation complete, and access error

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Functional overview STM32L486xx

The Arm

SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with

SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

3.38.2 Embedded Trace Macrocell™

The Arm ® Embedded Trace Macrocell™ provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the

STM32L486xx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors.

The Embedded Trace Macrocell™ operates with third party debugger software tools.

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4 Pinouts and pin description

Pinouts and pin description

Figure 6. STM32L486Zx LQFP144 pinout (1)

PE2

PE3

PE4

PE5

PE6

VBAT

PC13

PC14-OSC32_IN (PC14)

PC15-OSC32_OUT (PC15)

PF0

PF1

PF2

PF3

PF4

PF5

VSS

VDD

PF6

PF7

PF8

PF9

PF10

PH0-OSC_IN (PH0)

PH1-OSC_OUT (PH1)

NRST

PC0

PC1

PC2

PC3

VSSA

VREF-

VREF+

VDDA

PA0

PA1

PA2

LQFP144

1. The above figure shows the package top view.

108 VDD

107 VSS

106

105

104

VDDUSB

PA13 (JTMS-SWDIO)

PA12

103 PA11

102 PA10

101 PA9

100

PA8

PC9

PC8

PC7

PC6

VDDIO2

VSS

PG8

PG7

PG6

PG5

PG4

PG3

PG2

PD15

PD14

VDD

VSS

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

MS31270V5

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105

Pinouts and pin description STM32L486xx

Figure 7. STM32L486Zx, external SMPS device, LQFP144 pinout (1)

PE2

PE3

PE4

PE5

PE6

VBAT

PC13

PC14-OSC32_IN (PC14)

PC15-OSC32_OUT (PC15)

PF0

PF1

PF2

PF3

PF4

PF5

VSS

VDD

PF6

PF7

PF8

PF9

PF10

PH0-OSC_IN (PH0)

PH1-OSC_OUT (PH1)

NRST

PC0

PC1

PC2

PC3

VSSA

VREF-

VREF+

VDDA

PA0

PA1

PA2

LQFP144

1. The above figure shows the package top view.

108 VDD

107 VSS

106

105

104

VDDUSB

PA13 (JTMS-SWDIO)

PA12

103 PA11

102 PA10

101 PA9

100

PA8

PC9

PC8

PC7

PC6

VDDIO2

VSS

PG8

PG7

PG6

PG5

PG4

PG3

PG2

PD15

PD14

VDD

VSS

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

MSv43895V2

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PE3

PE4 PE2

PC13

PC14-

OSC32_IN

PC15-

OSC32_OUT

PE5

PE6

VBAT

PH0-OSC_IN

PH1-

OSC_OUT

PC0

VSS

VDD

NRST

Figure 8. STM32L486Qx UFBGA132 ballout (1)

3 4 5 6 7 8 9 10

PE1 PB8 BOOT0 PD7 PD5 PB4 PB3 PA15 PA14

PB9

PE0

VSS

PF4

PG11

VDD

PB7

VDD

PF2

PF3

PF5

PG6

PG7

PB6

PB5

PF1

PD6

PG14

PF0

VSS

VDD

PD4

PG13

PG12

VSS

VDDIO2

PD3

PD2

PG10

PD1

PD0

PG9

PG5

PG3

PG1

PG0

PC12

PC11

PA9

PC8

PG4

PG2

PD15

VSSA/VREFPC1

PG15 PC3

VREF+

VDDA

PA0

PA1

PC2

PA2

PA4

PA5

PA3 PA6

OPAMP1_

VINM

OPAMP2_

VINM

PA7

PC4

PC5

PB0

PG8

PF11

PB2

PB1

PF12

PF13

PE8

PE7

PF14

PD9

PE10

PE9

PF15

PD8

PE12

PE11

PD12

PB15

PB10

PE13

VDD

PD14

PD11

PB14

PB11

PE14

PA13

PC10

VDDUSB

PA8

PC7

VSS

PC9

PC6

VSS

PA12

PA11

PA10

VDD

PD13

PD10

PB13

PB12

PE15

MSv35003V7

1. The above figure shows the package top view.

Figure 9. STM32L486Vx LQFP100 pinout

(1)

PE2

PE3

PE4

PE5

PE6

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VSS

VDD

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA

VREF-

VREF+

VDDA

PA0

PA1

PA2

LQFP100

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

VDD

VSS

VDDUSB

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

PD15

PD14

MS31271V3

1. The above figure shows the package top view.

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Pinouts and pin description STM32L486xx

VDDUSB

VSS

PA12

PA11

PC9

PC7

PB15

PA10

PA8

PC8

PB14

PA15

PA14

PA13

PC10

PA9

PC6

PB11

PD2

PC12

PC11

PG9

PG10

PG11

PG14

PG13

PG12

WLCSP72

PB3

VDDIO2

PB4

PB7 VSS VDD

PB6 PC13 VBAT

PB5

BOOT0

PC15-

OSC32_OUT

PC14-

OSC32_IN

PH1-

OSC_OUT

PH0-OSC_IN

PB8 PB9 NRST

PC2

PC3

PC1 PC0

VREF+ VSSA/VREFPA1 PA4 PA2

PB12 PB13 PB10 PA7 PA6 PA5 PA3 PA0 VDDA

J VDD VSS PB2 PB1 PB0 PC5 PC4 VDD VSS

1. The above figure shows the package top view.

Figure 11. STM32L486Jx, external SMPS device, WLCSP72 ballout

(1)

1 2 3 4 5 6 7 8 9

MSv35083V7

VDDUSB PC10 PD2 PG9 PG14 PB3 BOOT0 VSS VDD

Figure 10. STM32L486Jx WLCSP72 ballout (1)

2 3 4 5 6 7 8 9

PC9

VDD

PB15

PB12

VDD12

VSS

PA12

PA11

PA8

PC7

PC6

PB13

VSS

PA14

PA13

PA10

PC12

PA15

PC11

PA9

PC8

PB14

PB11

PB10

PG10

PG12

PA2

PA7

PB0

PG13

PB4

WLCSP72

PA0

PA5

PB1

VDDIO2

PB8

PA1

PA4

PB2

PC3

PA3

PC4

PB7

PC13

PB9

PB5

VDD12

PC15-

OSC32_OUT

PC14-

OSC32_IN

PH1-

OSC_OUT

PH0-OSC_IN

PB6

VBAT

NRST

PC2 PC1 PC0

VREF+

VDD

PA6

VSSA/VREF-

VDDA

VSS

MSv43896V1

1. The above figure shows the package top view.

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STM32L486xx Pinouts and pin description

Figure 12. STM32L486Rx LQFP64 pinout (1)

VBAT

PC13

PC14-OSC32_IN (PC14)

PC15-OSC32_OUT (PC15)

PH0-OSC_IN (PH0)

PH1-OSC_OUT (PH1)

NRST

PC0

PC1

PC2

PC3

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

1. The above figure shows the package top view.

LQFP64

VDDUSB

VSS

PA13 (JTMS-SWDIO)

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

MS31272V5

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Pinouts and pin description STM32L486xx

Figure 13. STM32L486Rx, external SMPS device, LQFP64 pinout (1)

VBAT

PC13

PC14-OSC32_IN (PC14)

PC15-OSC32_OUT (PC15)

PH0-OSC_IN (PH0)

PH1-OSC_OUT (PH1)

NRST

PC0

PC1

PC2

PC3

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

LQFP64

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

VDDUSB

VSS

PA13 (JTMS-SWDIO)

PA12

PA11

PA10

PA9

PA8

MSv45744V1

Name

1. The above figure shows the package top view.

Pin name

Pin type

I/O structure

Table 15. Legend/abbreviations used in the pinout table

Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

S Supply pin

I/O

RST

Input only pin

Input / output pin

5 V tolerant I/O

3.6 V tolerant I/O

Dedicated BOOT0 pin

Bidirectional reset pin with embedded weak pull-up resistor

(1)

(2)

(3)

(4)

(5)

Option for TT or FT I/Os

I/O, Fm+ capable

I/O, with LCD function supplied by V

LCD

I/O, with USB function supplied by V

DDUSB

I/O, with Analog switch function supplied by V

DDA

I/O supplied only by V

DDIO2

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STM32L486xx Pinouts and pin description

Name

Table 15. Legend/abbreviations used in the pinout table (continued)

Abbreviation Definition

Notes Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.

Pin functions

Alternate functions

Functions selected through GPIOx_AFR registers

Additional functions

Functions directly selected/enabled through peripheral registers

Pin Number

Table 16. STM32L486xx pin definitions

Pin functions

Pin name

(function after reset) Alternate functions

Additional functions

1 B2 1 1

2 A1 2 2

3 B1 3 3

PE2

PE3

PE4

I/O FT_l -

I/O FT -

TRACECK,

TIM3_ETR,

TSC_G7_IO1,

LCD_SEG38,

FMC_A23,

SAI1_MCLK_A,

EVENTOUT

TRACED0,

TIM3_CH1,

TSC_G7_IO2,

LCD_SEG39,

FMC_A19,

SAI1_SD_B,

EVENTOUT

TRACED1,

TIM3_CH2,

DFSDM1_DATIN3,

TSC_G7_IO3,

FMC_A20,

SAI1_FS_A,

EVENTOUT

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Pinouts and pin description STM32L486xx

Pin Number

Table 16. STM32L486xx pin definitions (continued)

Pin functions

Pin name

(function after reset) Alternate functions

Additional functions

B9 B9

B8 C7

C9 C9

C8 C8

D6 10 10

D4 12 12

E4 13 13

F3 14 14

10 F2 16 16

11 G2 17 17

PE5

PE6

I/O

FT -

TRACED2,

TIM3_CH3,

DFSDM1_CKIN3,

TSC_G7_IO4,

FMC_A21,

SAI1_SCK_A,

EVENTOUT

TRACED3,

TIM3_CH4,

FMC_A22,

SAI1_SD_A,

EVENTOUT

RTC_

TAMP3/

WKUP3

VBAT

PC13

I/O

(1)

(2)

EVENTOUT

RTC_

TAMP1/

RTC_TS/

RTC_OUT/

WKUP2

PC14-

OSC32_IN

(PC14)

PC15-

OSC32_OUT

(PC15)

PF0

PF1

PF2

PF3

PF4

PF5

VSS

VDD

I/O FT

I/O

FT_f

I/O FT_a

(1)

(2)

(1)

(2)

EVENTOUT OSC32_IN

EVENTOUT

OSC32_

OUT

I2C2_SDA, FMC_A0,

EVENTOUT

I2C2_SCL, FMC_A1,

EVENTOUT

I2C2_SMBA,

FMC_A2,

EVENTOUT

FMC_A3,

EVENTOUT

FMC_A4,

EVENTOUT

FMC_A5,

EVENTOUT

ADC3_IN6

ADC3_IN7

ADC3_IN8

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STM32L486xx Pinouts and pin description

Pin Number

Table 16. STM32L486xx pin definitions (continued)

Pin functions

Pin name

(function after reset) Alternate functions

Additional functions

F9 F9

F8 F8

10 10 F7 F7

PF6

PF7

PF8

PF9

PC0

PC1

PC2

I/O FT_a -

22 22 PF10 I/O FT_a -

5 5 D9 D9 12 F1 23 23

6 6 D8 D8 13 G1 24 24

7 7 E9 E9 14 H2 25 25

PH0-OSC_IN

(PH0)

I/O FT

PH1-OSC_OUT

(PH1)

I/O FT

NRST I/O RST

I/O FT_fla -

I/O FT_la -

TIM5_ETR,

TIM5_CH1,

SAI1_SD_B,

EVENTOUT

TIM5_CH2,

SAI1_MCLK_B,

EVENTOUT

TIM5_CH3,

SAI1_SCK_B,

EVENTOUT

TIM5_CH4,

SAI1_FS_B,

TIM15_CH1,

EVENTOUT

TIM15_CH2,

EVENTOUT

ADC3_IN9

ADC3_IN10

ADC3_IN11

ADC3_IN12

ADC3_IN13

OSC_IN

EVENTOUT

LPTIM1_IN1,

I2C3_SCL,

DFSDM1_DATIN4,

LPUART1_RX,

LCD_SEG18,

LPTIM2_IN1,

EVENTOUT

LPTIM1_OUT,

I2C3_SDA,

DFSDM1_CKIN4,

LPUART1_TX,

LCD_SEG19,

EVENTOUT

LPTIM1_IN2,

SPI2_MISO,

DFSDM1_CKOUT,

LCD_SEG20,

EVENTOUT

OSC_OUT

ADC123_

IN1

ADC123_

IN2

ADC123_

IN3

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Pinouts and pin description STM32L486xx

Pin Number

Table 16. STM32L486xx pin definitions (continued)

Pin functions

Pin name

(function after reset) Alternate functions

Additional functions

11 11 G7 G7 18

12 12 G9 G9 -

G8 G8 21

14 14 H8 G5 23

15 15 G4 G6 24

16 16 G6 G4 25

31 31

H9 H9 22 M1 33 33

13 13 -

PC3

VSSA

VREF-

VDDA

VSSA/VREFS

VREF+ S

VDDA/VREF+ S

PA0

OPAMP1_VINM

PA1

PA2

I/O FT_a

I/O FT_la

(3)

LPTIM1_ETR,

SPI2_MOSI,

LCD_VLCD,

SAI1_SD_A,

LPTIM2_ETR,

EVENTOUT

ADC123_

IN4

VREFBUF_

OUT

TIM2_CH1,

TIM5_CH1,

TIM8_ETR,

USART2_CTS,

UART4_TX,

SAI1_EXTCLK,

TIM2_ETR,

EVENTOUT

TIM2_CH2,

TIM5_CH2,

USART2_RTS_DE,

UART4_RX,

LCD_SEG0,

TIM15_CH1N,

EVENTOUT

TIM2_CH3,

TIM5_CH3,

USART2_TX,

LCD_SEG1,

SAI2_EXTCLK,

TIM15_CH1,

EVENTOUT

OPAMP1_

VINP,

ADC12_IN5,

RTC_

TAMP2/

WKUP1

OPAMP1_

VINM,

ADC12_IN6

ADC12_IN7,

WKUP4/

LSCO

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STM32L486xx Pinouts and pin description

Pin Number

Table 16. STM32L486xx pin definitions (continued)

Pin functions

Pin name

(function after reset) Alternate functions

Additional functions

17 17 H7 H7 26

18 18 J9 J9

19 19 J8 H8 28

20 20 G5 H6 29

21 21 H6 H5 30

22 22 H5 J8

23 23 H4 H4 32

PA3

VSS

VDD

PA4

PA5

PA6

OPAMP2_VINM

PA7

I/O TT_la

I/O TT_a

I/O FT_la

(3)

TIM2_CH4,

TIM5_CH4,

USART2_RX,

LCD_SEG2,

TIM15_CH2,

EVENTOUT

SPI1_NSS,

SPI3_NSS,

USART2_CK,

SAI1_FS_B,

LPTIM2_OUT,

EVENTOUT

TIM2_CH1,

TIM2_ETR,

TIM8_CH1N,

SPI1_SCK,

LPTIM2_ETR,

EVENTOUT

TIM1_BKIN,

TIM3_CH1,

TIM8_BKIN,

SPI1_MISO,

USART3_CTS,

QUADSPI_BK1_IO3,

LCD_SEG3,

TIM1_BKIN_COMP2,

TIM8_BKIN_COMP2,

TIM16_CH1,

EVENTOUT

ADC12_

IN9, DAC1_

OUT1

ADC12_

IN10,

DAC1_

OUT2

OPAMP2_

VINP,

ADC12_

IN11

TIM1_CH1N,

TIM3_CH2,

TIM8_CH1N,

SPI1_MOSI,

QUADSPI_BK1_IO2,

LCD_SEG4,

TIM17_CH1,

EVENTOUT

OPAMP1_

VOUT,

ADC12_IN8

OPAMP2_

VINM,

ADC12_

IN12

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Pinouts and pin description STM32L486xx

Pin Number

Table 16. STM32L486xx pin definitions (continued)

Pin functions

Pin name

(function after reset) Alternate functions

Additional functions

24 24 J7 J7 33 K5 44 44

25 J6 34 L5 45 45

26 25 J5 J4 35 M5 46 46

27 26 J4 J5 36 M6 47 47

28 27 J3 J6

37 L6 48 48

K6 49 49

J7 50 50

51 51

52 52

K7 53 53

PC4

PC5

PB0

PB1

PB2

PF11

PF12

VSS

VDD

PF13

I/O FT_la -

I/O TT_la -

I/O FT_la -

I/O FT_a -

I/O

USART3_TX,

LCD_SEG22,

EVENTOUT

USART3_RX,

LCD_SEG23,

EVENTOUT

COMP1_

INM,

ADC12_

IN13

COMP1_

INP,

ADC12_

IN14,

WKUP5

TIM1_CH2N,

TIM3_CH3,

TIM8_CH2N,

USART3_CK,

QUADSPI_BK1_IO1,

LCD_SEG5,

COMP1_OUT,

EVENTOUT

TIM1_CH3N,

TIM3_CH4,

TIM8_CH3N,

DFSDM1_DATIN0,

USART3_RTS_DE,

QUADSPI_BK1_IO0,

LCD_SEG6,

LPTIM2_IN1,

EVENTOUT

RTC_OUT,

LPTIM1_OUT,

I2C3_SMBA,

DFSDM1_CKIN0,

EVENTOUT

FMC_A6,

EVENTOUT

DFSDM1_DATIN6,

FMC_A7,

EVENTOUT

OPAMP2_

VOUT,

ADC12_

IN15

COMP1_

INM,

ADC12_

IN16

COMP1_

INP

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STM32L486xx Pinouts and pin description

Pin Number

Table 16. STM32L486xx pin definitions (continued)

Pin functions

Pin name

(function after reset) Alternate functions

Additional functions

J8 54 54

J9 55 55

38 M7 58 58

39 L7 59 59

40 M8 60 60

F6 61 61

G6 62 62

41 L8 63 63

PF14

PF15

PG0

PG1

PE7

PE8

PE9

VSS

VDD

PE10

I/O FT

DFSDM1_CKIN6,

TSC_G8_IO1,

FMC_A8,

EVENTOUT

TSC_G8_IO2,

FMC_A9,

EVENTOUT

TSC_G8_IO3,

FMC_A10,

EVENTOUT

TSC_G8_IO4,

FMC_A11,

EVENTOUT

TIM1_ETR,

DFSDM1_DATIN2,

FMC_D4,

SAI1_SD_B,

EVENTOUT

TIM1_CH1N,

DFSDM1_CKIN2,

FMC_D5,

SAI1_SCK_B,

EVENTOUT

TIM1_CH1,

DFSDM1_CKOUT,

FMC_D6,

SAI1_FS_B,

EVENTOUT

TIM1_CH2N,

DFSDM1_DATIN4,

TSC_G5_IO1,

QUADSPI_CLK,

FMC_D7,

SAI1_MCLK_B,

EVENTOUT

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Pinouts and pin description STM32L486xx

Pin Number

Table 16. STM32L486xx pin definitions (continued)

Pin functions

Pin name

(function after reset) Alternate functions

Additional functions

42 M9 64 64

43 L9 65 65

44 M10 66 66

45 M11 67 67

46 M12 68 68

PE11

PE12

PE13

PE14

PE15

I/O FT

TIM1_CH2,

DFSDM1_CKIN4,

TSC_G5_IO2,

QUADSPI_NCS,

FMC_D8,

EVENTOUT

TIM1_CH3N,

SPI1_NSS,

DFSDM1_DATIN5,

TSC_G5_IO3,

QUADSPI_BK1_IO0,

FMC_D9,

EVENTOUT

TIM1_CH3,

SPI1_SCK,

DFSDM1_CKIN5,

TSC_G5_IO4,

QUADSPI_BK1_IO1,

FMC_D10,

EVENTOUT

TIM1_CH4,

TIM1_BKIN2,

TIM1_BKIN2_

COMP2, SPI1_MISO,

QUADSPI_BK1_IO2,

FMC_D11,

EVENTOUT

TIM1_BKIN,

TIM1_BKIN_COMP1,

SPI1_MOSI,

QUADSPI_BK1_IO3,

FMC_D12,

EVENTOUT

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STM32L486xx Pinouts and pin description

Pin Number

Table 16. STM32L486xx pin definitions (continued)

Pin functions

Pin name

(function after reset) Alternate functions

Additional functions

29 28 H3 J3 47 L10 69 69

30 29 G3 H3 48 L11 70 -

30 B8 70

31 31 J2 J2 49 F12 71 71

32 32 J1 F1 50 G12 72 72

33 33 H1 H1 51 L12 73 73

PB10

PB11

VDD12

VSS

VDD

PB12

I/O FT_fl -

I/O

FT_l -

TIM2_CH3,

I2C2_SCL,

SPI2_SCK,

DFSDM1_DATIN7,

USART3_TX,

LPUART1_RX,

QUADSPI_CLK,

LCD_SEG10,

COMP1_OUT,

SAI1_SCK_A,

EVENTOUT

TIM2_CH4,

I2C2_SDA,

DFSDM1_CKIN7,

USART3_RX,

LPUART1_TX,

QUADSPI_NCS,

LCD_SEG11,

COMP2_OUT,

EVENTOUT

TIM1_BKIN,

TIM1_BKIN_COMP2,

I2C2_SMBA,

SPI2_NSS,

DFSDM1_DATIN1,

USART3_CK,

LPUART1_RTS_DE,

TSC_G1_IO1,

LCD_SEG12,

SWPMI1_IO,

SAI2_FS_A,

TIM15_BKIN,

EVENTOUT

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Pinouts and pin description STM32L486xx

Pin Number

Table 16. STM32L486xx pin definitions (continued)

Pin functions

Pin name

(function after reset) Alternate functions

Additional functions

34 34 H2 H2 52 K12 74 74

35 35 G2 G3 53 K11 75 75

36 36 G1 G1 54 K10 76 76

55 K9 77 77

56 K8 78 78

76/259

PB13

PB14

PB15

PD8

PD9

I/O FT_fl -

I/O

FT_l

TIM1_CH1N,

I2C2_SCL,

SPI2_SCK,

DFSDM1_CKIN1,

USART3_CTS,

LPUART1_CTS,

TSC_G1_IO2,

LCD_SEG13,

SWPMI1_TX,

SAI2_SCK_A,

TIM15_CH1N,

EVENTOUT

TIM1_CH2N,

TIM8_CH2N,

I2C2_SDA,

SPI2_MISO,

DFSDM1_DATIN2,

USART3_RTS_DE,

TSC_G1_IO3,

LCD_SEG14,

SWPMI1_RX,

SAI2_MCLK_A,

TIM15_CH1,

EVENTOUT

RTC_REFIN,

TIM1_CH3N,

TIM8_CH3N,

SPI2_MOSI,

DFSDM1_CKIN2,

TSC_G1_IO4,

LCD_SEG15,

SWPMI1_SUSPEND,

SAI2_SD_A,

TIM15_CH2,

EVENTOUT

USART3_TX,

LCD_SEG28,

FMC_D13,

EVENTOUT

USART3_RX,

LCD_SEG29,

FMC_D14,

SAI2_MCLK_A,

EVENTOUT

DS10199 Rev 7

STM32L486xx Pinouts and pin description

Pin Number

Table 16. STM32L486xx pin definitions (continued)

Pin functions

Pin name

(function after reset) Alternate functions

Additional functions

57 J12 79 79

58 J11 80 80

59 J10 81 81

60 H12 82 82

83 83

84 84

61 H11 85 85

62 H10 86 86

G10 87 87

PD10

PD11

PD12

PD13

VSS

VDD

PD14

PD15

PG2

I/O

FT_l

I/O FT_s -

USART3_CK,

TSC_G6_IO1,

LCD_SEG30,

FMC_D15,

SAI2_SCK_A,

EVENTOUT

USART3_CTS,

TSC_G6_IO2,

LCD_SEG31,

FMC_A16,

SAI2_SD_A,

LPTIM2_ETR,

EVENTOUT

TIM4_CH1,

USART3_RTS_DE,

TSC_G6_IO3,

LCD_SEG32,

FMC_A17,

SAI2_FS_A,

LPTIM2_IN1,

EVENTOUT

TIM4_CH2,

TSC_G6_IO4,

LCD_SEG33,

FMC_A18,

LPTIM2_OUT,

EVENTOUT

TIM4_CH3,

LCD_SEG34,

FMC_D0,

EVENTOUT

TIM4_CH4,

LCD_SEG35,

FMC_D1,

EVENTOUT

SPI1_SCK,

FMC_A12,

SAI2_SCK_B,

EVENTOUT

DS10199 Rev 7

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Pinouts and pin description STM32L486xx

Pin Number

Table 16. STM32L486xx pin definitions (continued)

Pin functions

Pin name

(function after reset) Alternate functions

Additional functions

F9 88 88

F10 89 89

E9 90 90

G4 91 91

H4 92 92

J6 93 93

37 37 F3 G2 63 E12 96 96

38 38 F1 F2 64 E11 97 97

PG3

PG4

PG5

PG6

PG7

PG8

VSS

VDDIO2

PC6

PC7

I/O FT_s -

I/O FT_fs -

I/O

FT_l

SPI1_MISO,

FMC_A13,

SAI2_FS_B,

EVENTOUT

SPI1_MOSI,

FMC_A14,

SAI2_MCLK_B,

EVENTOUT

SPI1_NSS,

LPUART1_CTS,

FMC_A15,

SAI2_SD_B,

EVENTOUT

I2C3_SMBA,

LPUART1_RTS_DE,

EVENTOUT

I2C3_SCL,

LPUART1_TX,

FMC_INT,

EVENTOUT

I2C3_SDA,

LPUART1_RX,

EVENTOUT

TIM3_CH1,

TIM8_CH1,

DFSDM1_CKIN3,

TSC_G4_IO1,

LCD_SEG24,

SDMMC1_D6,

SAI2_MCLK_A,

EVENTOUT

TIM3_CH2,

TIM8_CH2,

DFSDM1_DATIN3,

TSC_G4_IO2,

LCD_SEG25,

SDMMC1_D7,

SAI2_MCLK_B,

EVENTOUT

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STM32L486xx Pinouts and pin description

Pin Number

Table 16. STM32L486xx pin definitions (continued)

Pin functions

Pin name

(function after reset) Alternate functions

Additional functions

39 39 F2 F3

40 40 E1 E1

41 41 E2 E2

42 42 E3 E3

65 E10 98

66 D12 99

67 D11 100 100

68 D10 101 101

43 43 D2 D2 69 C12 102 102 PA10

44 44 D1 D1 70 B12 103 103

PC8

PC9

PA8

PA9

PA11

I/O

FT_l

I/O FT_lu -

I/O FT_u -

TIM3_CH3,

TIM8_CH3,

TSC_G4_IO3,

LCD_SEG26,

SDMMC1_D0,

EVENTOUT

TIM8_BKIN2,

TIM3_CH4,

TIM8_CH4,

TSC_G4_IO4,

OTG_FS_NOE,

LCD_SEG27,

SDMMC1_D1,

SAI2_EXTCLK,

TIM8_BKIN2_

COMP1, EVENTOUT

MCO, TIM1_CH1,

USART1_CK,

OTG_FS_SOF,

LCD_COM0,

LPTIM2_OUT,

EVENTOUT

TIM1_CH2,

USART1_TX,

LCD_COM1,

TIM15_BKIN,

EVENTOUT

TIM1_CH3,

USART1_RX,

OTG_FS_ID,

LCD_COM2,

TIM17_BKIN,

EVENTOUT

TIM1_CH4,

TIM1_BKIN2,

USART1_CTS,

CAN1_RX,

OTG_FS_DM,

TIM1_BKIN2_COMP1

, EVENTOUT

OTG_FS_

VBUS

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105

Pinouts and pin description STM32L486xx

Pin Number

Table 16. STM32L486xx pin definitions (continued)

Pin functions

Pin name

(function after reset) Alternate functions

Additional functions

45 45 C1 C1 71 A12 104 104

46 46 C2 C2 72 A11 105 105

PA12

PA13

(JTMS-SWDIO)

47 47 B1 B1 -

48 48 A1 A1 73 C11 106 106

74 F11 107 107

75 G11 108 108

VSS

VDDUSB

VSS

VDD

49 49 B2 B2 76 A10 109 109

PA14

(JTCK-SWCLK)

50 50 A2 C3 77

51 51 D3 A2 78

A9 110 110

B11 111 111

PA15 (JTDI)

PC10

I/O FT_u

I/O

I/O FT

I/O

FT_l

(4)

TIM1_ETR,

USART1_RTS_DE,

CAN1_TX,

OTG_FS_DP,

EVENTOUT

JTMS-SWDIO,

IR_OUT,

OTG_FS_NOE,

EVENTOUT

JTCK-SWCLK,

EVENTOUT

JTDI, TIM2_CH1,

TIM2_ETR,

SPI1_NSS,

SPI3_NSS,

UART4_RTS_DE,

TSC_G3_IO1,

LCD_SEG17,

SAI2_FS_B,

EVENTOUT

SPI3_SCK,

USART3_TX,

UART4_TX,

TSC_G3_IO2,

LCD_COM4/

LCD_SEG28/

LCD_SEG40,

SDMMC1_D2,

SAI2_SCK_B,

EVENTOUT

80/259

DS10199 Rev 7

STM32L486xx Pinouts and pin description

Pin Number

Table 16. STM32L486xx pin definitions (continued)

Pin functions

Pin name

(function after reset) Alternate functions

Additional functions

52 52 C3 D3 79 C10 112 112 PC11

53 53 B3 B3 80 B10 113 113 PC12

A3 A3

C9 114 114

B9 115 115

C8 116 116

B8 117 117

PD0

PD1

PD2

PD3

I/O FT_l

I/O

I/O FT_l

I/O

SPI3_MISO,

USART3_RX,

UART4_RX,

TSC_G3_IO3,

LCD_COM5/

LCD_SEG29/

LCD_SEG41,

SDMMC1_D3,

SAI2_MCLK_B,

EVENTOUT

SPI3_MOSI,

USART3_CK,

UART5_TX,

TSC_G3_IO4,

LCD_COM6/

LCD_SEG30/

LCD_SEG42,

SDMMC1_CK,

SAI2_SD_B,

EVENTOUT

SPI2_NSS,

DFSDM1_DATIN7,

CAN1_RX, FMC_D2,

EVENTOUT

SPI2_SCK,

DFSDM1_CKIN7,

CAN1_TX, FMC_D3,

EVENTOUT

TIM3_ETR,

USART3_RTS_DE,

UART5_RX,

TSC_SYNC,

LCD_COM7/LCD_

SEG31/LCD_SEG43,

SDMMC1_CMD,

EVENTOUT

SPI2_MISO,

DFSDM1_DATIN0,

USART2_CTS,

FMC_CLK,

EVENTOUT

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105

Pinouts and pin description STM32L486xx

Pin Number

Table 16. STM32L486xx pin definitions (continued)

Pin functions

Pin name

(function after reset) Alternate functions

Additional functions

B4 B4 D8 125 125 PG10

A4 A4

C4 -

86 A6 119 119

B7 118 118

120 120

121 121

B6 122 122

A5 123 123

D9 124 124

G3 126 126

PD4

PD5

VSS

VDD

PD6

PD7

PG9

PG11

I/O

I/O FT_s -

SPI2_MOSI,

DFSDM1_CKIN0,

USART2_RTS_DE,

FMC_NOE,

EVENTOUT

USART2_TX,

FMC_NWE,

EVENTOUT

DFSDM1_DATIN1,

USART2_RX,

FMC_NWAIT,

SAI1_SD_A,

EVENTOUT

DFSDM1_CKIN1,

USART2_CK,

FMC_NE1,

EVENTOUT

SPI3_SCK,

USART1_TX,

FMC_NCE/

FMC_NE2,

SAI2_SCK_A,

TIM15_CH1N,

EVENTOUT

LPTIM1_IN1,

SPI3_MISO,

USART1_RX,

FMC_NE3,

SAI2_FS_A,

TIM15_CH1,

EVENTOUT

LPTIM1_IN2,

SPI3_MOSI,

USART1_CTS,

SAI2_MCLK_A,

TIM15_CH2,

EVENTOUT

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DS10199 Rev 7

STM32L486xx Pinouts and pin description

Pin Number

Table 16. STM32L486xx pin definitions (continued)

Pin functions

Pin name

(function after reset) Alternate functions

Additional functions

C5 C4

B5 B5

A5 A5

B6 B6

F7 130 130

G7 131 131

VSS

VDDIO2

55 54 A6 A6 89 A8 133 132

PB3

(JTDO-

TRACESWO)

56 55 C6 C5 90

D7 127 127

C7 128 128

C6 129 129

K1 132 -

A7 134 133

PG12

PG13

PG14

PG15

PB4

(NJTRST)

I/O FT_s

I/O FT_fs

I/O FT_s

I/O FT_la

(4)

I/O FT_la

(4)

LPTIM1_ETR,

SPI3_NSS,

USART1_RTS_DE,

FMC_NE4,

SAI2_SD_A,

EVENTOUT

I2C1_SDA,

USART1_CK,

FMC_A24,

EVENTOUT

I2C1_SCL,

FMC_A25,

EVENTOUT

LPTIM1_OUT,

I2C1_SMBA,

EVENTOUT

JTDO-TRACESWO,

TIM2_CH2,

SPI1_SCK,

SPI3_SCK,

USART1_RTS_DE,

LCD_SEG7,

SAI1_SCK_B,

EVENTOUT

NJTRST, TIM3_CH1,

SPI1_MISO,

SPI3_MISO,

USART1_CTS,

UART5_RTS_DE,

TSC_G2_IO1,

LCD_SEG8,

SAI1_MCLK_B,

TIM17_BKIN,

EVENTOUT

COMP2_

INM

COMP2_

INP

DS10199 Rev 7

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105

Pinouts and pin description STM32L486xx

Pin Number

Table 16. STM32L486xx pin definitions (continued)

Pin functions

Pin name

(function after reset) Alternate functions

Additional functions

57 56 C7 E7

58 57 B7 E8

59 58 A7 B7

C5 135 134

B5 136 135

B4 137 136

PB5

PB6

PB7

60 59 D7 A7 94 A4 138 137 BOOT0

I/O FT_la -

I/O FT_fa -

I/O FT_fla -

I -

LPTIM1_IN1,

TIM3_CH2,

I2C1_SMBA,

SPI1_MOSI,

SPI3_MOSI,

USART1_CK,

UART5_CTS,

TSC_G2_IO2,

LCD_SEG9,

COMP2_OUT,

SAI1_SD_B,

TIM16_BKIN,

EVENTOUT

LPTIM1_ETR,

TIM4_CH1,

TIM8_BKIN2,

I2C1_SCL,

DFSDM1_DATIN5,

USART1_TX,

TSC_G2_IO3,

TIM8_BKIN2_

COMP2, SAI1_FS_B,

TIM16_CH1N,

EVENTOUT

LPTIM1_IN2,

TIM4_CH2,

TIM8_BKIN,

I2C1_SDA,

DFSDM1_CKIN5,

USART1_RX,

UART4_CTS,

TSC_G2_IO4,

LCD_SEG21,

FMC_NL,

TIM8_BKIN_COMP1,

TIM17_CH1N,

EVENTOUT

COMP2_

INP

COMP2_

INM,

PVD_IN

84/259

DS10199 Rev 7

STM32L486xx Pinouts and pin description

Pin Number

Table 16. STM32L486xx pin definitions (continued)

Pin functions

Pin name

(function after reset) Alternate functions

Additional functions

61 60 E7 C6 95

62 61 E8 D7 96

A3 139 138

B3 140 139

C3 141 140

A2 142 141

PB8

PB9

PE0

PE1

I/O FT_fl

I/O

FT_l

FT_l -

TIM4_CH3,

I2C1_SCL,

DFSDM1_DATIN6,

CAN1_RX,

LCD_SEG16,

SDMMC1_D4,

SAI1_MCLK_A,

TIM16_CH1,

EVENTOUT

IR_OUT, TIM4_CH4,

I2C1_SDA,

SPI2_NSS,

DFSDM1_CKIN6,

CAN1_TX,

LCD_COM3,

SDMMC1_D5,

SAI1_FS_A,

TIM17_CH1,

EVENTOUT

TIM4_ETR,

LCD_SEG36,

FMC_NBL0,

TIM16_CH1,

EVENTOUT

LCD_SEG37,

FMC_NBL1,

TIM17_CH1,

EVENTOUT

62 J1 142

63 63 A8 A8 99 D3 143 143

64 64 A9 A9 100 C4 144 144

VDD12

VSS

VDD

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current

(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF

- These GPIOs must not be used as current sources (e.g. to drive an LED).

2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0351 reference manual.

3. OPAMPx_VINM pins are not available as additional functions on pins PA1 and PA7 on UFBGA packages. On UFBGA packages, use the OPAMPx_VINM dedicated pins available on M3 and M4 balls.

4. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated.

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105

AF0 AF1

Table 17. Alternate function AF0 to AF7 (1)

AF2 AF3 AF4 AF5

Port

SYS_AF

TIM1/TIM2/

TIM5/TIM8/

LPTIM1

TIM1/TIM2/

TIM3/TIM4/

TIM5

TIM8

PA6

Port A

PA7

PA8

PA9

PA10

PA11

PA0

PA1

PA2

PA3

PA4

PA5

MCO

PA12 -

PA13 JTMS-SWDIO

PA14 JTCK-SWCLK

PA15 JTDI

TIM2_CH1

TIM2_CH2

TIM2_CH3

TIM2_CH4

TIM2_CH1

TIM1_BKIN

TIM1_CH1N

TIM1_CH1

TIM1_CH2

TIM1_CH3

TIM1_CH4

TIM1_ETR

IR_OUT

TIM2_CH1

TIM5_CH1

TIM5_CH2

TIM5_CH3

TIM5_CH4

TIM2_ETR

TIM3_CH1

TIM3_CH2

TIM1_BKIN2

TIM2_ETR

TIM8_ETR

TIM8_CH1N

TIM8_BKIN

TIM8_CH1N

I2C1/I2C2/I2C3 SPI1/SPI2

SPI1_NSS

SPI1_SCK

SPI1_MISO

SPI1_MOSI

SPI1_NSS

AF6 AF7

SPI3_NSS

SPI3/DFSDM

USART1/

USART2/

USART3

USART2_CTS

USART2_RTS_

USART2_TX

USART2_RX

USART2_CK

USART3_CTS

USART1_CK

USART1_TX

USART1_RX

USART1_CTS

USART1_RTS_

AF0

Port

SYS_AF

TIM1/TIM2/

TIM5/TIM8/

LPTIM1

Port B

PB7

PB8

PB9

PB10

PB11

PB12

PB13

PB14

PB0

PB1

PB2

PB3

PB4

PB5

PB6

RTC_OUT

JTDO-

TRACESWO

NJTRST

TIM1_CH2N

TIM1_CH3N

LPTIM1_OUT

TIM2_CH2

LPTIM1_IN1

LPTIM1_ETR

LPTIM1_IN2

IR_OUT

TIM2_CH3

TIM2_CH4

TIM1_BKIN

TIM1_CH1N

TIM1_CH2N

PB15 RTC_REFIN TIM1_CH3N

TIM1/TIM2/

TIM3/TIM4/

TIM5

TIM3_CH3

TIM3_CH4

TIM3_CH1

TIM3_CH2

TIM4_CH1

TIM4_CH2

TIM4_CH3

TIM4_CH4

AF1

Table 17. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5 AF6 AF7

TIM8

TIM8_CH2N

TIM8_CH3N

TIM8_BKIN2

TIM8_BKIN

TIM1_BKIN_

COMP2

TIM8_CH2N

TIM8_CH3N

I2C3_SMBA

I2C1_SMBA

I2C1_SCL

I2C1_SDA

I2C1_SCL

I2C1_SDA

I2C2_SCL

I2C2_SDA

I2C2_SMBA

I2C2_SCL

I2C2_SDA

I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM

USART1/

USART2/

USART3

SPI2_NSS

SPI2_SCK

SPI2_NSS

SPI2_SCK

SPI2_MISO

SPI1_SCK

SPI1_MISO

SPI1_MOSI

SPI3_SCK

SPI3_MISO

USART3_CK

DFSDM1_

DATIN0

DFSDM1_CKIN0

USART3_RTS_

USART1_RTS_

USART1_CTS

USART1_CK SPI3_MOSI

DFSDM1_

DATIN5

USART1_TX

DFSDM1_CKIN5 USART1_RX

DFSDM1_

DATIN6

DFSDM1_CKIN6

DFSDM1_

DATIN7

USART3_TX

DFSDM1_CKIN7 USART3_RX

DFSDM1_

DATIN1

USART3_CK

DFSDM1_CKIN1 USART3_CTS

DFSDM1_

DATIN2

USART3_RTS_

SPI2_MOSI DFSDM1_CKIN2 -

Port

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

Port C

PC8

PC9

PC10

PC11

PC12

PC13

PC14

PC15

AF0

SYS_AF

AF1

Table 17. Alternate function AF0 to AF7 (1) (continued)

TIM1/TIM2/

TIM5/TIM8/

LPTIM1

AF2

TIM1/TIM2/

TIM3/TIM4/

TIM5

LPTIM1_IN1

LPTIM1_OUT

LPTIM1_IN2

LPTIM1_ETR

TIM8_BKIN2

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

AF3 AF4 AF5 AF6 AF7

TIM8

TIM8_CH1

TIM8_CH2

TIM8_CH3

TIM8_CH4

I2C3_SCL

I2C3_SDA

I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM

USART1/

USART2/

USART3

SPI2_MISO

SPI2_MOSI

DFSDM1_

DATIN4

DFSDM1_CKIN4

DFSDM1_

CKOUT

DFSDM1_CKIN3

DFSDM1_

DATIN3

USART3_TX

USART3_RX

SPI3_SCK USART3_TX

SPI3_MISO

SPI3_MOSI

USART3_RX

USART3_CK

Port

PD0

PD1

PD2

PD3

PD4

PD5

PD6

Port D

PD7

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

AF0

SYS_AF

AF1

Table 17. Alternate function AF0 to AF7 (1) (continued)

TIM1/TIM2/

TIM5/TIM8/

LPTIM1

AF2

TIM1/TIM2/

TIM3/TIM4/

TIM5

TIM3_ETR

TIM4_CH1

TIM4_CH2

TIM4_CH3

TIM4_CH4

AF3

TIM8

AF4 AF5 AF6 AF7

I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM

USART1/

USART2/

USART3

SPI2_NSS

SPI2_SCK

DFSDM1_

DATIN7

DFSDM1_CKIN7

USART3_RTS_

SPI2_MISO

DFSDM1_

DATIN0

USART2_CTS

SPI2_MOSI DFSDM1_CKIN0

USART2_RTS_

USART2_TX

DFSDM1_

DATIN1

USART2_RX

DFSDM1_CKIN1 USART2_CK

USART3_TX

USART3_RX

USART3_CK

USART3_CTS

USART3_RTS_

Port

AF0

SYS_AF

PE0

PE1

PE2

PE3

PE4

PE5

PE6

PE7

PE8

Port E

PE9

PE10

PE11

PE12

PE13

PE14

PE15

TRACECK

TRACED0

TRACED1

TRACED2

TRACED3

AF1

Table 17. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5 AF6 AF7

TIM1/TIM2/

TIM5/TIM8/

LPTIM1

TIM1/TIM2/

TIM3/TIM4/

TIM5

TIM8

TIM1_ETR

TIM1_CH1N

TIM1_CH1

TIM1_CH2N

TIM1_CH2

TIM1_CH3N

TIM1_CH3

TIM1_CH4

TIM1_BKIN

TIM4_ETR

TIM3_ETR

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

TIM1_BKIN2

TIM1_BKIN2_

COMP2

TIM1_BKIN_

COMP1

I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM

SPI1_NSS

SPI1_SCK

SPI1_MISO

DFSDM1_

DATIN3

DFSDM1_CKIN3

DFSDM1_

DATIN2

DFSDM1_CKIN2

DFSDM1_

CKOUT

DFSDM1_

DATIN4

DFSDM1_

CKIN4

DFSDM1_

DATIN5

DFSDM1_CKIN5

SPI1_MOSI -

USART1/

USART2/

USART3

Port

Port F

PF0

PF1

PF2

PF3

PF4

PF5

PF6

PF7

PF8

PF9

PF10

PF11

PF12

PF13

PF14

PF15 -

AF0

SYS_AF

AF1

Table 17. Alternate function AF0 to AF7 (1) (continued)

TIM1/TIM2/

TIM5/TIM8/

LPTIM1

TIM5_ETR

AF2

TIM1/TIM2/

TIM3/TIM4/

TIM5

TIM5_CH1

TIM5_CH2

TIM5_CH3

TIM5_CH4

AF3

TIM8

AF4 AF5 AF6 AF7

I2C1/I2C2/I2C3 SPI1/SPI2

I2C2_SDA

I2C2_SCL

I2C2_SMBA

SPI3/DFSDM

DFSDM1_

DATIN6

DFSDM1_CKIN6

USART1/

USART2/

USART3

AF0 AF1

Table 17. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5

Port

SYS_AF

Port G

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

PG8

PG9

PG10 LPTIM1_IN1

PG11

PG12

LPTIM1_IN2

LPTIM1_ETR

Port H

PG13

PG14

PG15

PH0

PH1

1. Please refer to

Table 18

for AF8 to AF15.

LPTIM1_OUT

TIM1/TIM2/

TIM5/TIM8/

LPTIM1

TIM1/TIM2/

TIM3/TIM4/

TIM5

TIM8

I2C3_SMBA

I2C3_SCL

I2C3_SDA

I2C1_SDA

I2C1_SCL

I2C1_SMBA

I2C1/I2C2/I2C3 SPI1/SPI2

SPI1_SCK

SPI1_MISO

SPI1_MOSI

SPI1_NSS

AF6 AF7

SPI3_SCK

SPI3/DFSDM

USART1/

USART2/

USART3

USART1_TX

SPI3_MISO

SPI3_MOSI

SPI3_NSS

USART1_RX

USART1_CTS

USART1_RTS_

USART1_CK

Port

PA0

PA1

PA2

PA3

PA4

PA5

PA6

Port A

PA7

PA8

PA9

PA10

PA11

AF8

UART4,

UART5,

LPUART1

UART4_TX

UART4_RX

PA12

PA13

PA14

PA15

UART4_RTS

_DE

AF9

CAN1_RX

CAN1_TX

TSC_G3_IO1

Table 18. Alternate function AF8 to AF15 (1)

AF10

CAN1, TSC OTG_FS, QUADSPI

OTG_FS_DM

OTG_FS_DP

OTG_FS_NOE

AF11

LCD

LCD_SEG0

LCD_SEG1

LCD_SEG2

QUADSPI_BK1_IO3 LCD_SEG3

QUADSPI_BK1_IO2 LCD_SEG4

OTG_FS_SOF LCD_COM0

OTG_FS_ID

LCD_COM1

LCD_COM2

LCD_SEG17

AF12

SDMMC1, COMP1,

COMP2, FMC,

SWPMI1

TIM1_BKIN_

COMP2

TIM1_BKIN2_

COMP1

SAI1, SAI2

TIM2, TIM15,

TIM16, TIM17,

LPTIM2

EVENTOUT

SAI1_EXTCLK TIM2_ETR

TIM15_CH1N

EVENTOUT

SAI2_EXTCLK TIM15_CH1 EVENTOUT

TIM15_CH2 EVENTOUT

SAI1_FS_B LPTIM2_OUT EVENTOUT

LPTIM2_ETR EVENTOUT

TIM8_BKIN_

COMP2

TIM16_CH1

TIM17_CH1

LPTIM2_OUT

TIM15_BKIN

TIM17_BKIN

EVENTOUT

AF13

SAI2_FS_B

AF14

AF15

EVENTOUT

AF8 AF9

Table 18. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11

Port UART4,

UART5,

LPUART1

CAN1, TSC

PB0

PB1

PB2

PB3

PB4

UART5_RTS

_DE

TSC_G2_IO1

PB5 UART5_CTS TSC_G2_IO2

OTG_FS, QUADSPI LCD

QUADSPI_BK1_IO1 LCD_SEG5

QUADSPI_BK1_IO0 LCD_SEG6

LCD_SEG7

LCD_SEG8

LCD_SEG9

Port B

PB6

PB7 UART4_CTS TSC_G2_IO4

PB8

TSC_G2_IO3

CAN1_RX

LCD_SEG21

LCD_SEG16

LCD_COM3

AF12 AF13 AF14 AF15

SDMMC1, COMP1,

COMP2, FMC,

SWPMI1

COMP1_OUT

SAI1, SAI2

TIM2, TIM15,

TIM16, TIM17,

LPTIM2

EVENTOUT

SAI1_SCK_B

EVENTOUT

LPTIM2_IN1 EVENTOUT

EVENTOUT

SAI1_MCLK_

TIM17_BKIN EVENTOUT

SAI1_SD_B TIM16_BKIN EVENTOUT COMP2_OUT

TIM8_BKIN2_

COMP2

SAI1_FS_B TIM16_CH1N EVENTOUT

FMC_NL

SDMMC1_D4

SDMMC1_D5

TIM8_BKIN_

COMP1

SAI1_MCLK_

SAI1_FS_A

TIM17_CH1N

TIM16_CH1

TIM17_CH1

EVENTOUT

EVENTOUT PB9

PB10

LPUART1_

PB11 LPUART1_TX

PB12

PB13

LPUART1_

RTS_DE

LPUART1_

CTS

CAN1_TX

TSC_G1_IO1

TSC_G1_IO2

QUADSPI_CLK

QUADSPI_NCS

LCD_SEG10

LCD_SEG11

LCD_SEG12

LCD_SEG13

COMP1_OUT

COMP2_OUT

SWPMI1_IO

SWPMI1_TX

SAI1_SCK_A

SAI2_FS_A

EVENTOUT

TIM15_BKIN EVENTOUT

SAI2_SCK_A TIM15_CH1N EVENTOUT

PB14 TSC_G1_IO3 LCD_SEG14 SWPMI1_RX

SAI2_MCLK_

TIM15_CH1 EVENTOUT

PB15 TSC_G1_IO4 LCD_SEG15 SWPMI1_SUSPEND SAI2_SD_A TIM15_CH2 EVENTOUT

AF8

Port UART4,

UART5,

LPUART1

PC0

LPUART1_

PC1 LPUART1_TX

PC2 -

PC3

PC4

PC5

PC6 -

AF9

CAN1, TSC

TSC_G4_IO1

Table 18. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12

OTG_FS, QUADSPI

LCD

LCD_SEG18

LCD_SEG19

LCD_SEG20

LCD_VLCD

LCD_SEG22

LCD_SEG23

LCD_SEG24

SDMMC1, COMP1,

COMP2, FMC,

SWPMI1

SDMMC1_D6

AF13

SAI1, SAI2

PC7

PC8

Port C

PC9

TSC_G4_IO2

TSC_G4_IO3

TSC_G4_IO4

OTG_FS_NOE

LCD_SEG25

LCD_SEG26

LCD_SEG27

SDMMC1_D7

SDMMC1_D0

SDMMC1_D1

AF14 AF15

TIM2, TIM15,

TIM16, TIM17,

LPTIM2

EVENTOUT

LPTIM2_IN1 EVENTOUT

EVENTOUT

SAI1_SD_A LPTIM2_ETR EVENTOUT

EVENTOUT

EVENTOUT -

SAI2_MCLK_

EVENTOUT

SAI2_EXTCLK

TIM8_BKIN2_

COMP1

EVENTOUT

PC10 UART4_TX TSC_G3_IO2

PC11 UART4_RX TSC_G3_IO3

PC12 UART5_TX TSC_G3_IO4

PC13

PC14

PC15

LCD_COM4/

LCD_SEG28/

LCD_SEG40

LCD_COM5/

LCD_SEG29/

LCD_SEG41

LCD_COM6/

LCD_SEG30/

LCD_SEG42

SDMMC1_D2

SDMMC1_D3

SDMMC1_CK

SAI2_SCK_B

SAI2_MCLK_

SAI2_SD_B

EVENTOUT

Port

PD0

PD1

PD2

PD3

PD4

PD5

PD6

Port D

PD7

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

AF8

UART4,

UART5,

LPUART1

UART5_RX

AF9

Table 18. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12

CAN1, TSC OTG_FS, QUADSPI

CAN1_RX

CAN1_TX

TSC_SYNC

LCD

LCD_COM7/

LCD_SEG31/

LCD_SEG43

SDMMC1, COMP1,

COMP2, FMC,

SWPMI1

FMC_D2

FMC_D3

SDMMC1_CMD

FMC_CLK

FMC_NOE

FMC_NWE

FMC_NWAIT

AF13

SAI1, SAI2

SAI1_SD_A

AF14 AF15

TIM2, TIM15,

TIM16, TIM17,

LPTIM2

EVENTOUT

EVENTOUT

TSC_G6_IO1

TSC_G6_IO2

TSC_G6_IO3

TSC_G6_IO4

LCD_SEG28

LCD_SEG29

LCD_SEG30

LCD_SEG31

LCD_SEG32

LCD_SEG33

LCD_SEG34

LCD_SEG35

FMC_NE1

FMC_D13

FMC_D14

FMC_D15

FMC_A16

FMC_A17

FMC_A18

FMC_D0

FMC_D1

EVENTOUT

SAI2_MCLK_

EVENTOUT

SAI2_SCK_A EVENTOUT

SAI2_SD_A LPTIM2_ETR EVENTOUT

SAI2_FS_A

LPTIM2_IN1 EVENTOUT

LPTIM2_OUT EVENTOUT

EVENTOUT

Port

PE0

PE1

PE2

Port E

PE3

PE4

PE5

PE6

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

AF8

UART4,

UART5,

LPUART1

AF9

TSC_G7_IO1

TSC_G7_IO2

TSC_G7_IO3

TSC_G7_IO4

TSC_G5_IO1

Table 18. Alternate function AF8 to AF15 (1) (continued)

AF10

CAN1, TSC OTG_FS, QUADSPI

QUADSPI_CLK

TSC_G5_IO2 QUADSPI_NCS

TSC_G5_IO3 QUADSPI_BK1_IO0

TSC_G5_IO4 QUADSPI_BK1_IO1

QUADSPI_BK1_IO2

QUADSPI_BK1_IO3

AF11

LCD

LCD_SEG36

LCD_SEG37

LCD_SEG38

LCD_SEG39

AF12 AF13 AF14 AF15

SDMMC1, COMP1,

COMP2, FMC,

SWPMI1

FMC_NBL0

FMC_NBL1

FMC_A23

FMC_A19

FMC_A20

FMC_A21

FMC_A22

FMC_D4

FMC_D5

FMC_D6

FMC_D7

FMC_D8

FMC_D9

FMC_D10

FMC_D11

FMC_D12

SAI1, SAI2

SAI1_MCLK_

SAI1_SD_B

SAI1_FS_A

SAI1_SCK_A

SAI1_SD_A

SAI1_SD_B

SAI1_SCK_B

SAI1_FS_B

SAI1_MCLK_

TIM2, TIM15,

TIM16, TIM17,

LPTIM2

EVENTOUT

TIM16_CH1 EVENTOUT

TIM17_CH1 EVENTOUT

EVENTOUT

Port

Port F

PF7

PF8

PF9

PF10

PF11

PF12

PF13

PF14

PF15

PF0

PF1

PF2

PF3

PF4

PF5

PF6

AF8

UART4,

UART5,

LPUART1

AF9

Table 18. Alternate function AF8 to AF15 (1) (continued)

AF10

CAN1, TSC OTG_FS, QUADSPI

TSC_G8_IO1

TSC_G8_IO2

AF11

LCD

AF12 AF13 AF14 AF15

SDMMC1, COMP1,

COMP2, FMC,

SWPMI1

FMC_A0

FMC_A1

FMC_A2

FMC_A3

FMC_A4

FMC_A5

FMC_A6

FMC_A7

FMC_A8

FMC_A9

SAI1, SAI2

SAI1_SD_B

SAI1_MCLK_

SAI1_SCK_B

SAI1_FS_B

TIM2, TIM15,

TIM16, TIM17,

LPTIM2

TIM15_CH1

TIM15_CH2

EVENTOUT

EVENTOUT

Port

PG0

PG1

PG2

PG3

PG4

AF8

UART4,

UART5,

LPUART1

Port G

PG5

PG6

LPUART1_

CTS

LPUART1_

RTS_DE

PG7 LPUART1_TX

PG8

LPUART1_

AF9

TSC_G8_IO3

TSC_G8_IO4

Table 18. Alternate function AF8 to AF15 (1) (continued)

AF10

CAN1, TSC OTG_FS, QUADSPI

AF11

LCD

AF12 AF13 AF14 AF15

SDMMC1, COMP1,

COMP2, FMC,

SWPMI1

FMC_A10

FMC_A11

FMC_A12

FMC_A13

FMC_A14

SAI1, SAI2

SAI2_SCK_B

SAI2_FS_B

SAI2_MCLK_

TIM2, TIM15,

TIM16, TIM17,

LPTIM2

EVENTOUT

EVENTOUT

FMC_A15

FMC_INT

SAI2_SD_B

EVENTOUT

PG9 -

FMC_NCE/

FMC_NE2

SAI2_SCK_A TIM15_CH1N EVENTOUT

PG10 FMC_NE3

PG11

PG12

PG13

PG14

PG15 -

FMC_NE4

FMC_A24

FMC_A25

SAI2_FS_A

SAI2_MCLK_

SAI2_SD_A

TIM15_CH1 EVENTOUT

TIM15_CH2 EVENTOUT

EVENTOUT

AF8 AF9

Table 18. Alternate function AF8 to AF15 (1) (continued)

AF10

Port UART4,

UART5,

LPUART1

CAN1, TSC

Port H

PH0

PH1

1. Please refer to

Table 17

for AF0 to AF7.

OTG_FS, QUADSPI

AF11

LCD

AF12

SDMMC1, COMP1,

COMP2, FMC,

SWPMI1

AF13

SAI1, SAI2

AF14 AF15

TIM2, TIM15,

TIM16, TIM17,

LPTIM2

EVENTOUT

EVENTOUT

STM32L486xx Memory mapping

Figure 14. STM32L486xx memory map

0xFFFF FFFF

Cortex™-M4 with FPU

Internal

Peripherals

0xE000 0000

0xC000 0000

FMC and

QUADSPI registers

0xA000 0000

4 0x9000 0000

QUADSPI Flash bank

FMC bank 3

0x8000 0000

FMC bank 1 & bank 2

0x6000 0000

0x4000 0000

Peripherals

0x2000 0000

0x0000 0000

SRAM1

CODE

Reserved

0xBFFF FFFF

0xA000 1400

0xA000 1000

0xA000 0000

0x5FFF FFFF

0x5006 0C00

0x4800 0000

0x4002 4400

0x4002 0000

Reserved

QUADSPI registers

FMC registers

Reserved

AHB2

Reserved

AHB1

Reserved

0x4001 6400

0x4001 0000

0x4000 9800

0x4000 0000

0x1FFF FFFF

0x1FFF F810

0x1FFF F800

0x1FFF F000

0x1FFF 8000

0x1FFF 7810

0x1FFF 7800

0x1FFF 7400

0x1FFF 7000

0x1FFF 0000

0x1000 8000

0x1000 0000

0x0810 0000

0x0800 0000

0x0010 0000

0x0000 0000

APB2

Reserved

APB1

Reserved

Option Bytes

Reserved

System memory

Reserved

Options Bytes

Reserved

OTP area

System memory

Reserved

SRAM2

Reserved

Flash memory

Reserved

Flash, system memory or SRAM, depending on

BOOT configuration

MS34100V3

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Memory mapping STM32L486xx

Table 19. STM32L486xx memory map and peripheral register boundary addresses (1)

Bus Boundary address

Size

(bytes)

Peripheral

AHB3

AHB2

AHB1

0xA000 1000 - 0xA000 13FF

0xA000 0000 - 0xA000 0FFF

0x5006 0800 - 0x5006 0BFF

0x5006 0400 - 0x5006 07FF

0x5006 0000 - 0x5006 03FF

0x5004 0400 - 0x5005 FFFF

0x5004 0000 - 0x5004 03FF

0x5000 0000 - 0x5003 FFFF

0x4800 2000 - 0x4FFF FFFF

0x4800 1C00 - 0x4800 1FFF

0x4800 1800 - 0x4800 1BFF

0x4800 1400 - 0x4800 17FF

0x4800 1000 - 0x4800 13FF

0x4800 0C00 - 0x4800 0FFF

0x4800 0800 - 0x4800 0BFF

0x4800 0400 - 0x4800 07FF

0x4800 0000 - 0x4800 03FF

0x4002 4400 - 0x47FF FFFF

0x4002 4000 - 0x4002 43FF

0x4002 3400 - 0x4002 3FFF

0x4002 3000 - 0x4002 33FF

0x4002 2400 - 0x4002 2FFF

0x4002 2000 - 0x4002 23FF

0x4002 1400 - 0x4002 1FFF

0x4002 1000 - 0x4002 13FF

0x4002 0800 - 0x4002 0FFF

0x4002 0400 - 0x4002 07FF

0x4002 0000 - 0x4002 03FF

1 KB

4 KB

1 KB

127 KB

1 KB

QUADSPI

FMC

RNG

Reserved

AES

Reserved

ADC

16 KB OTG_FS

~127 MB Reserved

1 KB GPIOH

1 KB

GPIOG

GPIOF

GPIOE

1 KB

3 KB

1 KB

3 KB

1 KB

GPIOD

GPIOC

GPIOB

1 KB GPIOA

~127 MB Reserved

1 KB TSC

2 KB

1 KB

Reserved

CRC

Reserved

FLASH registers

Reserved

RCC

Reserved

DMA2

DMA1

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DS10199 Rev 7

STM32L486xx Memory mapping

Table 19. STM32L486xx memory map and peripheral register boundary addresses (1)

(continued)

Bus Boundary address

Size

(bytes)

Peripheral

APB2

0x4001 6400 - 0x4001 FFFF

0x4001 6000 - 0x4000 63FF

0x4001 5C00 - 0x4000 5FFF

0x4001 5800 - 0x4000 5BFF

0x4001 5400 - 0x4000 57FF

0x4001 4C00 - 0x4000 53FF

0x4001 4800 - 0x4001 4BFF

0x4001 4400 - 0x4001 47FF

0x4001 4000 - 0x4001 43FF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2C00 - 0x4001 2FFF

0x4001 2800 - 0x4001 2BFF

0x4001 2000 - 0x4001 27FF

0x4001 1C00 - 0x4001 1FFF

0x4001 0800- 0x4001 1BFF

0x4001 0400 - 0x4001 07FF

0x4001 0200 - 0x4001 03FF

0x4001 0030 - 0x4001 01FF

0x4001 0000 - 0x4001 002F

Reserved

DFSDM1

Reserved

SAI2

SAI1

Reserved

TIM17

TIM16

TIM15

Reserved

USART1

TIM8

SPI1

TIM1

SDMMC1

Reserved

FIREWALL

Reserved

EXTI

COMP

VREFBUF

SYSCFG

1 KB

2 KB

1 KB

5 KB

1 KB

39 KB

1 KB

2 KB

1 KB

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105

Memory mapping STM32L486xx

Table 19. STM32L486xx memory map and peripheral register boundary addresses (1)

(continued)

Bus Boundary address

Size

(bytes)

Peripheral

APB1

0x4000 9800 - 0x4000 FFFF

0x4000 9400 - 0x4000 97FF

0x4000 8C00 - 0x4000 93FF

0x4000 8800 - 0x4000 8BFF

0x4000 8400 - 0x4000 87FF

0x4000 8000 - 0x4000 83FF

0x4000 7C00 - 0x4000 7FFF

0x4000 7800 - 0x4000 7BFF

0x4000 7400 - 0x4000 77FF

0x4000 7000 - 0x4000 73FF

0x4000 6800 - 0x4000 6FFF

0x4000 6400 - 0x4000 67FF

0x4000 6000 - 0x4000 63FF

0x4000 5C00- 0x4000 5FFF

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 5000 - 0x4000 53FF

0x4000 4C00 - 0x4000 4FFF

Reserved

LPTIM2

Reserved

SWPMI1

Reserved

LPUART1

LPTIM1

OPAMP

DAC1

PWR

Reserved

CAN1

Reserved

I2C3

I2C2

I2C1

UART5

UART4

1 KB

26 KB

1 KB

2 KB

1 KB

104/259

DS10199 Rev 7

STM32L486xx Memory mapping

Table 19. STM32L486xx memory map and peripheral register boundary addresses (1)

(continued)

Bus Boundary address

Size

(bytes)

Peripheral

APB1

0x4000 4800 - 0x4000 4BFF

0x4000 4400 - 0x4000 47FF

0x4000 4000 - 0x4000 43FF

0x4000 3C00 - 0x4000 3FFF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 2400 - 0x4000 27FF

0x4000 1800 - 0x4000 23FF

0x4000 1400 - 0x4000 17FF

0x4000 1000 - 0x4000 13FF

0x4000 0C00- 0x4000 0FFF

0x4000 0800 - 0x4000 0BFF

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 03FF

1. The gray color is used for reserved boundary addresses.

USART3

USART2

Reserved

SPI3

SPI2

Reserved

IWDG

WWDG

RTC

LCD

Reserved

TIM7

TIM6

TIM5

TIM4

TIM3

TIM2

1 KB

3 KB

1 KB

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Electrical characteristics STM32L486xx

6.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3 σ ).

Unless otherwise specified, typical data are based on T

A are given only as design guidelines and are not tested.

= 25 °C, V

= V

DDA

= 3 V. They

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2 σ )

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.5

The loading conditions used for pin parameter measurement are shown in

Figure 15

Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 16 .

Figure 15. Pin loading conditions Figure 16. Pin input voltage

MCU pin MCU pin

C = 50 pF

MS19210V1

MS19211V1

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STM32L486xx

6.1.6 Power supply scheme

Figure 17. Power supply scheme

Electrical characteristics

VBAT

BAT

VBAT 1.55 – 3.6 V

1.55 – 3.6 V

Backup circuitry

(LSE, RTC,

Backup circuitry

(LSE, RTC,

V CORE n x VDD

2 x VDD12

Power switch

V V

DDIO1

1.05 – 1.32 V

Kernel logic

(CPU, Digital

CORE

DD n x VDD

Regulator

DDIO1

OUT n x 100 nF

+1 x 4.7 μF

DDIO2 m x V

DDIO2

GPIOs

+4.7 μF

+4.7 μF GPIOs n x VSS m x V

SS m x VSS

DDIO2 m x100 nF

+4.7 μF

+1 μF

DDA

DDA m x VDDIO2

DDA

VDDA

REF

GPIOs m x VSS

SSA

DDIO2

OUT

REF+

REF-

V REF-

DDIO2

OUT

ADCs/

VREF

10 nF

+1 μF

DDA

REF

VSSA

VDDA

100 nF

+1 μF

REF+

REF-

ADCs/

DACs/

OPAMPs/

COMPs/

VREFBUF

VSSA

IO logic

IO logic logic

Kernel logic

(CPU, Digital

& Memories)

IO logic

MS35001V1

MS35001V2

MSv45701V1

Caution: Each power supply pair (V

, V

DDA

SSA

etc.) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or

DS10199 Rev 7

107/259

232

Electrical characteristics STM32L486xx below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

108/259

DS10199 Rev 7

STM32L486xx Electrical characteristics

Figure 18. Current consumption measurement scheme with and without external

SMPS power supply

DD_USB

DDUSB

DD_USB

DDUSB

DD_VBAT

BAT

DD_VBAT

BAT

DDIO2

SMPS

DD12

DDIO2

DDA

MSv45730V1

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 20: Voltage characteristics

Table 21: Current characteristics

and

Table 22: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Symbol

DDX

- V

DD12

- V

(2)

Table 20. Voltage characteristics

(1)

Ratings Min

External main supply voltage (including

, V

DDA

, V

DDIO2

, V

DDUSB

, V

LCD

, V

BAT

)

Range 1

External SMPS supply voltage

Range 2

-0.3

Input voltage on FT_xxx pins

Input voltage on TT_xx pins

Input voltage on BOOT0 pin

Input voltage on any other pins

-0.3

Max

4.0

1.4

min (V

, V

DDA

, V

LCD

) + 4.0

4.0

9.0

4.0

, V

DDUSB

Unit

DS10199 Rev 7

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232

Electrical characteristics STM32L486xx

Symbol

Table 20. Voltage characteristics (1) (continued)

Ratings Min Max Unit

| ∆ V

SSx

DDx

-V

Variations between different V

DDX pins of the same domain

power

Variations between all the different ground pins

(5)

50 mV mV

1. All main power (V , V

DDA

, V , V

DDUSB

, V

LCD

, V

BAT

) and ground (V

, V

SSA

) pins must always be connected to the

2. V

maximum must always be respected. Refer to

Table 21: Current characteristics for the maximum allowed injected

current values.

3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.

4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

5. Include VREF- pin.

Symbol

∑ IV

DD(PIN)

SS(PIN)

Table 21. Current characteristics

Ratings

Total current into sum of all V

power lines (source)

(1)(2)

Total current out of sum of all V

ground lines (sink)

(1)

Maximum current into each V

power pin (source)

(1)(2)

Maximum current out of each V

ground pin (sink)

(1)

Output current sunk by any I/O and control pin except FT_f

Max

150

100

Unit

100

20 I

∑

IO(PIN)

Output current sunk by any FT_f pin

Output current sourced by any I/O and control pin

Total output current sunk by sum of all I/Os and control pins

(3)

Total output current sourced by sum of all I/Os and control pins

(3)

100

100 mA

INJ(PIN)

(4)

Injected current on FT_xxx, TT_xx, RST and B pins, except PA4,

PA5

-5/+0

(5)

∑ |I

INJ(PIN)

Injected current on PA4, PA5

Total injected current (sum of all I/Os and control pins)

(6)

-5/0

1. All main power (V

, V

DDA

, V

DDIO2

, V

DDUSB

, V

LCD

, V

BAT

) and ground (V

, V

SSA

) pins must always be connected to the

2. Valid also for V

DD12

on SMPS packages.

3. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.

4. Positive injection (when V specified maximum value.

> V

DDIOx

) is not possible on these I/Os and does not occur for input voltages lower than the

5. A negative injection is induced by V

< V

. I

INJ(PIN)

must never be exceeded. Refer also to

Table 20: Voltage characteristics

for the minimum allowed input voltage values.

6. When several inputs are submitted to a current injection, the maximum ∑ |I injected currents (instantaneous values).

INJ(PIN)

| is the absolute sum of the negative

110/259

DS10199 Rev 7

STM32L486xx

Symbol

STG

Electrical characteristics

Table 22. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

Unit

°C

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Electrical characteristics STM32L486xx

6.3.1 General operating conditions

Table 23. General operating conditions

Symbol f

HCLK f

PCLK1 f

PCLK2

Parameter

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Conditions

Min

Standard operating voltage -

1.71

(1)

DD12

Standard operating voltage

DDIO2

PG[15:2] I/Os supply voltage

DDA

BAT

Analog supply voltage

Backup operating voltage

DDUSB

USB supply voltage

Full frequency range

Up to 26 MHz

At least one I/O in PG[15:2] used

PG[15:2] not used

ADC or COMP used

DAC or OPAMP used

VREFBUF used

ADC, DAC, OPAMP, COMP,

VREFBUF not used

USB used

USB not used

TT_xx I/O

BOOT0

1.55

3.0

-0.3

1.08

1.05

1.08

1.62

1.8

2.4

I/O input voltage

All I/O except BOOT0 and TT_xx -0.3

Power dissipation at

= 85 °C for suffix 6 or

= 105 °C for suffix 7

(4)

Power dissipation at T

125 °C for suffix 3

(4)

LQFP144

LQFP100

LQFP64

UFBGA132

WLCSP72

LQFP144

LQFP100

LQFP64

UFBGA132

WLCSP72

Max

3.6

1.32

3.6

Unit

MHz

3.6

DDIOx

+0.3

Min(Min(V

, V

DDA

DDIO2

, V

DDUSB

LCD

)+3.6 V,

5.5 V)

(2)(3)

625

476

444

363

434

156

119

111

108

V mW mW

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STM32L486xx Electrical characteristics

Symbol

Table 23. General operating conditions (continued)

Parameter Conditions Min Max Unit

Ambient temperature for the suffix 6 version

Ambient temperature for the suffix 7 version

Ambient temperature for the suffix 3 version

Junction temperature range

Maximum power dissipation

Low-power dissipation (5)

Maximum power dissipation

Low-power dissipation

(5)

Maximum power dissipation

Low-power dissipation

(5)

Suffix 6 version

Suffix 7 version

Suffix 3 version

–40

105

125

130

105

125

130

1. When RESET is released functionality is guaranteed down to V

BOR0

Min.

2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.

Maximum I/O input voltage is the smallest value between Min(V

, V

DDA

, V

DDIO2

, V

DDUSB

, V

LCD

)+3.6 V and 5.5V.

3. For operation with voltage higher than Min (V resistors must be disabled.

, V

DDA

, V

DDIO2

, V

DDUSB

, V

LCD

) +0.3 V, the internal Pull-up and Pull-Down

4. If T

is lower, higher P

values are allowed as long as T

does not exceed T

Jmax

(see

Section 7.6: Thermal characteristics

5. In low-power dissipation state, T

Thermal characteristics

can be extended to this range as long as T

does not exceed T

Jmax

(see

Section 7.6:

°C

The parameters given in

Table 24 are derived from tests performed under the ambient

temperature condition summarized in

Table 23 .

Symbol

Table 24. Operating conditions at power-up / power-down

(1)

Parameter Conditions t t t t

VDD

VDDA

VDDUSB

VDDIO2

rise time rate

fall time rate

DDA

rise time rate

DDA

fall time rate

DDUSB

rise time rate

DDUSB

fall time rate

DDIO2

rise time rate

DDIO2

fall time rate

1. At power-up, the V

DD12

voltage should not be forced externally.

Min

Max

∞

Unit

µs/V

The requirements for power-up/down sequence specified in Section 3.9.1: Power supply schemes must be respected.

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Electrical characteristics

6.3.3 Embedded reset and power control block characteristics

STM32L486xx

The parameters given in

Table 25 are derived from tests performed under the ambient

temperature conditions summarized in Table 23: General operating conditions

Table 25. Embedded reset and power control block characteristics

Symbol Parameter Conditions

(1)

Min Typ Max t

RSTTEMPO

(2)

Reset temporization after

BOR0 is detected

DD rising 250 400

BOR0

(2)

BOR1

BOR2

BOR3

BOR4

PVD0

PVD1

PVD2

PVD3

PVD4

PVD5

PVD6

V hyst_BORH0

Brown-out reset threshold 0

Brown-out reset threshold 1

Brown-out reset threshold 2

Brown-out reset threshold 3

Brown-out reset threshold 4

Programmable voltage detector threshold 0

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

PVD threshold 6

Hysteresis voltage of BORH0

2.59

2.85

2.75

2.92

2.84

2.15

2.41

2.31

2.56

2.47

2.69

2.47

2.85

2.76

2.1

2.26

1.62

1.6

2.06

1.96

2.26

2.16

2.56

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Hysteresis in continuous mode

Hysteresis in other mode

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

2.64

2.91

2.81

2.98

2.90

2.20

2.46

2.36

2.61

2.52

2.74

2.52

2.90

2.81

2.15

2.05

2.31

1.66

1.64

2.1

2.31

2.20

2.61

2.69

2.96

2.86

3.04

2.96

2.25

2.51

2.41

2.66

2.57

2.79

2.57

2.95

2.86

2.19

2.1

2.36

1.7

1.69

2.14

2.04

2.35

2.24

2.66

V hyst_BOR_PVD

Hysteresis voltage of BORH

(except BORH0) and PVD

100 -

Unit

μ s

V mV mV

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STM32L486xx Electrical characteristics

Table 25. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions (1) Min Typ Max Unit

(BOR_PVD) (2)

PVM1

PVM2

BOR

(3)

(except BOR0) and

PVD consumption from V

DDUSB

peripheral voltage monitoring

DDIO2

peripheral voltage monitoring

1.18

0.92

1.1

1.22

0.96

1.6

1.26

µA

PVM3

PVM4

V hyst_PVM3

V hyst_PVM4

(PVM1/PVM2)

(2)

DDA

peripheral voltage monitoring

DDA

peripheral voltage monitoring

PVM3 hysteresis

PVM4 hysteresis

PVM1 and PVM2 consumption from V

Rising edge

Falling edge

Rising edge

Falling edge

1.61

1.6

1.78

1.77

1.65

1.64

1.82

1.81

0.2

1.69

1.68

1.86

1.85

V mV mV

µA

(PVM3/PVM4)

(2)

PVM3 and PVM4 consumption from V

2 µA

1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

2. Guaranteed by design.

3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current characteristics tables.

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Electrical characteristics STM32L486xx

The parameters given in

Table 26 are derived from tests performed under the ambient

temperature and supply voltage conditions summarized in Table 23: General operating conditions

Symbol

Table 26. Embedded internal voltage reference

Parameter Conditions Min Typ Max t t

REFINT

S_vrefint

(1) start_vrefint

REFINTBUF

)

Internal reference voltage

ADC sampling time when reading the internal reference voltage

Start time of reference voltage buffer when ADC is enable

REFINT

buffer consumption from V

ADC

when converted by

–40 °C < T

< +130 °C

∆ V

REFINT

Internal reference voltage spread over the temperature range

= 3 V

Coeff

Average temperature coefficient

–40°C < T

< +130°C

Coeff

DDCoeff

REFINT_DIV1

REFINT_DIV2

REFINT_DIV3

Long term stability

Average voltage coefficient

1/4 reference voltage

1/2 reference voltage

3/4 reference voltage

1000 hours, T = 25°C

3.0 V < V

< 3.6 V

1. The shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design.

1.182

1.212

1.232

(2)

12.5

7.5

(2)

300 1000

(2)

250 1200

(2)

Unit

µs

µA mV ppm/°C ppm ppm/V

REFINT

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1.235

1.23

1.225

1.22

1.215

1.21

1.205

1.2

1.195

1.19

1.185

-40 -20

Electrical characteristics

Figure 19. V

REFINT

versus temperature

0 20

Mean

Min

Max

80 100 120 °C

MSv40169V1

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232

Electrical characteristics

6.3.5 Supply current characteristics

STM32L486xx

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 18: Current consumption measurement scheme with and without external SMPS power supply .

The I

DD_ALL

parameters given in

Table 27 to

Table 49 represent the total MCU consumption

including the current supplying V

, V

DD12

, V

DDIO2

, V

DDA

, V

LCD

, V

DDUSB

and V

BAT

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in analog input mode

• All peripherals are disabled except when explicitly mentioned

• The Flash memory access time is adjusted with the minimum wait states number, depending on the f

HCLK

frequency (refer to the table “Number of wait states according to CPU clock (HCLK) frequency” available in the RM0351 reference manual).

• When the peripherals are enabled f

PCLK

= f

HCLK

The parameters given in

Table 27 to

Table 50 are derived from tests performed under

ambient temperature and supply voltage conditions summarized in

Table 23: General operating conditions

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DS10199 Rev 7

Table 27. Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF)

Conditions TYP MAX

(1)

Symbol Parameter

Voltage scaling f

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

26 MHz 2.88

2.93

3.05

3.23

3.58

3.20

3.37

3.51

3.93

4.76

16 MHz 1.83

1.87

1.98

2.16

2.49

2.01

2.16

2.30

2.72

3.34

Unit

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

Range 2

8 MHz 0.98

1.02

1.12

4 MHz 0.55

0.59

0.69

2 MHz 0.34

0.37

0.47

1 MHz 0.23

0.26

0.36

100 kHz 0.14

0.17

0.27

80 MHz 10.2

10.3

10.5

72 MHz 9.24

9.31

9.47

64 MHz 8.25

8.32

8.46

Supply current in

Low-power run mode f

HCLK

= f

MSI all peripherals disable

Range 1 48 MHz 6.28

6.35

6.5

32 MHz 4.24

4.30

4.44

24 MHz 3.21

3.27

3.4

16 MHz 2.19

2.24

2.36

2 MHz 272

1 MHz 154

400 kHz 78

100 kHz 42

303

184

108

413

293

217

182

592

473

396

360

6.72

4.65

3.61

2.56

0.43

10.7

9.69

8.68

1.29

0.85

0.64

0.53

958

835

758

723

7.11

5.04

3.98

2.94

1.62

1.18

0.96

0.85

1.10

1.17

0.61

0.70

0.37

0.46

0.27

0.33

0.75

0.17

0.21

11.1

11.22

11.8

10.1

10.16

10.7

9.09

9.08

9.6

6.91

4.66

3.53

2.41

330

195

110

7.3

4.97

3.76

2.66

393

265

180

138

954

822

755

706

8.0

5.67

4.46

3.16

0.74

12.5

11.4

10.3

1.73

1.24

0.98

0.86

579

457

380

331

7.6

5.26

4.05

2.95

0.38

12.1

11.0

9.9

1.31

0.89

0.64

0.50

µA

8.8

6.51

5.30

3.99

1704

1572

1505

1456

1.44

13.3

12.2

11.1

2.56

1.95

1.71

1.57

1. Guaranteed by characterization results, unless otherwise specified.

Symbol

DD_ALL

(Run)

Table 28. Current consumption in Run modes, code with data processing running from Flash,

ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS

DD12

= 1.10 V)

Conditions

(1)

Parameter

TYP

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C

Unit

Supply current in Run mode f

HCLK

= f

HSE

up to 48MHz included, bypass mode

PLL ON above 48 MHz all peripherals disable

80 MHz 3.67

3.70

72 MHz 3.32

3.35

64 MHz 2.97

2.99

48 MHz 2.26

2.28

32 MHz 1.52

1.55

24 MHz 1.15

1.18

16 MHz 0.79

0.81

8 MHz 0.42

0.44

4 MHz 0.24

0.25

2 MHz 0.15

0.16

1 MHz 0.10

0.11

100 kHz 0.06

0.07

1.60

1.22

0.85

0.48

3.77

3.40

3.04

2.34

0.30

0.20

0.16

0.12

1.67

1.30

0.92

0.56

3.85

3.48

3.12

2.42

0.37

0.28

0.23

0.19

1.81

1.43

1.06

0.70

3.99

3.63

3.27

2.56

0.51

0.41

0.37

0.32

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,

DD12

= 1.10 V

Table 29. Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART disable

Conditions TYP MAX

(1)

Symbol Parameter

Voltage scaling f

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

Supply current in

Low-power run f

HCLK

= f

MSI all peripherals disable

Range 2

Range 1

26 MHz 3.15

3.19

3.31

16 MHz 2.24

2.28

2.39

8 MHz 1.26

1.29

1.40

4 MHz 0.71

0.75

0.85

2 MHz 0.42

0.45

0.55

1 MHz 0.27

0.30

0.40

100 kHz 0.14

0.17

0.27

80 MHz 10.0

10.1

10.3

72 MHz 9.06

9.13

9.28

64 MHz 8.96

9.04

9.22

48 MHz 7.64

7.72

7.91

32 MHz 5.49

5.57

5.74

24 MHz 4.16

4.22

4.36

16 MHz 2.93

2.99

3.13

2 MHz 358 392 503

1 MHz 197 230 340

400 kHz 97

100 kHz 47

126

235

186

1. Guaranteed by characterization results, unless otherwise specified.

10.6

9.51

9.48

8.17

5.98

4.57

3.35

683

3.50

2.57

1.57

1.02

0.72

0.57

0.43

519

414

365

3.85

2.90

1.89

1.34

1.04

0.89

0.75

3.47

2.46

1.40

0.79

0.46

0.30

0.17

3.70

2.60

1.50

0.88

0.55

0.38

0.22

3.84

2.74

1.64

1.06

0.73

0.57

0.40

4.26

3.16

2.06

1.38

1.09

0.90

0.74

11.0

11.00

11.35

11.64

12.26

13.10

9.92

9.97

10.36

10.65

11.06

11.69

9.92

9.86

10.25

10.54

10.95

11.79

8.62

6.40

4.96

3.75

8.40

6.04

4.60

3.22

1050 435

8.76

6.40

4.86

3.43

501

8.90

6.69

5.15

3.72

694

9.52

10.36

7.10

5.56

4.13

1069

7.94

6.19

4.97

1819

4.88

3.78

2.68

2.21

1.88

1.61

1.44

880 245 312 512 887 1637

778

726

130

202

147

402

347

777 1527

711 1472 mA

µA

Symbol

DD_ALL

(Run)

Table 30. Current consumption in Run modes, code with data processing running from Flash,

ART disable and power supplied by external SMPS (V

DD12

= 1.10 V)

Conditions

(1)

Parameter

TYP

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C

Supply current in Run mode f

HCLK

= f

HSE

up to 48MHz included, bypass mode

PLL ON above 48 MHz all peripherals disable

80 MHz 3.59

72 MHz 3.26

64 MHz 3.22

48 MHz 2.75

32 MHz 1.97

24 MHz 1.50

16 MHz 1.05

8 MHz 0.54

4 MHz

2 MHz

0.31

0.18

1 MHz 0.12

100 kHz 0.06

2.06

1.57

1.13

0.60

3.70

3.34

3.31

2.84

0.37

0.24

0.17

0.12

2.00

1.52

1.07

0.56

3.63

3.28

3.25

2.78

0.32

0.19

0.13

0.07

2.15

1.64

1.20

0.68

3.81

3.42

3.41

2.94

0.44

0.31

0.25

0.19

2.30

1.78

1.35

0.82

3.95

3.57

3.10

0.58

0.45

0.38

0.32

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,

DD12

= 1.10 V

Unit mA

Table 31. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1

Conditions TYP MAX

(1)

Symbol Parameter

Voltage scaling f

HCLK

25 °C 55 °C 85 °C

105

°C

125

°C

25 °C 55 °C 85 °C

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode

Supply current in low-power run mode f

HCLK

48MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable f

HCLK

= f

HSE

= f

MSI

up to

Range 2

Range 1 all peripherals disable

FLASH in power-down

26 MHz 2.88

2.94

3.05

3.23

3.58

3.18

3.26

3.40

4.02

4.65

16 MHz 1.83

1.87

1.98

2.15

2.50

2.01

2.16

2.30

2.72

3.34

8 MHz 0.97

1.00

1.11

1.27

1.62

1.07

1.16

1.32

1.73

2.36

4 MHz 0.54

0.57

0.67

0.84

1.18

0.59

0.69

0.88

1.23

1.96

2 MHz 0.33

0.36

0.46

0.62

0.96

0.37

0.45

0.63

0.98

1.70

1 MHz 0.22

0.25

0.35

0.51

0.85

0.25

0.33

0.50

0.86

1.57

100 kHz 0.12

0.15

0.25

0.41

0.75

0.15

0.21

0.39

0.74

1.45

80 MHz 10.2

10.3

10.5

10.7

11.1

11.22

11.57

11.86

12.07

13.11

72 MHz 9.25

9.31

9.46

9.68

10.1

10.18

10.41

10.55

10.76

11.80

64 MHz 8.25

8.31

8.46

8.67

9.08

9.37

9.66

9.87

10.91

48 MHz 6.26

6.33

6.48

6.69

7.11

6.89

7.11

7.25

7.67

8.50

32 MHz 4.22

4.28

4.42

4.63

5.03

4.64

4.86

5.15

5.56

6.19

24 MHz 3.20

3.25

3.38

3.59

3.99

3.52

3.70

3.84

4.26

5.09

16 MHz 2.18

2.22

2.35

2.55

2.94

2.40

2.55

2.84

3.25

4.09

2 MHz 242 275 384 562 924 300 380 573 927 1677

1 MHz 130 162 269 445 809 180 243 435 810 1560

400 kHz 61

100 kHz 26

197

163

374

339

734

702

160

122

353

314

728 1478

679 1429

1. Guaranteed by characterization results, unless otherwise specified.

105

°C

125

°C

Unit mA

µA

Symbol

Table 32. Current consumption in Run, code with data processing running from

SRAM1 and power supplied by external SMPS (V

DD12

= 1.10 V)

Conditions

(1)

Parameter

HCLK

TYP

25 °C 55 °C 85 °C 105 °C 125 °C

Unit

DD_ALL

(Run) Supply current in Run mode f

HCLK

= f

HSE

up to 48MHz included, bypass mode

PLL ON above 48 MHz all peripherals disable

80 MHz 3.67

3.70

3.77

72 MHz 3.33

3.35

3.40

64 MHz 2.97

2.99

3.04

48 MHz 2.25

2.28

2.33

32 MHz 1.52

1.54

1.59

24 MHz 1.15

1.17

1.22

16 MHz 0.78

0.80

0.84

8 MHz 0.42

0.43

0.48

4 MHz 0.23

0.25

0.29

2 MHz 0.14

0.16

0.20

1 MHz 0.09

0.11

0.15

100 kHz 0.05

0.06

0.11

1.66

1.29

0.92

0.55

3.85

3.48

3.12

2.40

0.36

0.27

0.22

0.18

1.81

1.43

1.06

0.70

3.99

3.63

3.26

2.56

0.51

0.41

0.37

0.32

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,

DD12

= 1.10 V

STM32L486xx Electrical characteristics

Table 33. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF)

Conditions TYP TYP

Symbol Parameter Unit Unit

Voltage scaling

Code 25 °C 25 °C

Reduced code

(1)

2.9

Coremark 3.1

111

118 mA µA/MHz

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode f

HCLK

= f

HSE

up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable

Supply current in

Low-power run f

HCLK

= f

MSI

= 2 MHz all peripherals disable

Dhrystone 2.1

Fibonacci

3.1

2.9

While(1) 2.8

Reduced code

(1)

10.2

Coremark

Dhrystone 2.1

Fibonacci

While(1)

Reduced code

(1)

Coremark

10.9

11.0

10.5

9.9

Dhrystone 2.1

Fibonacci

While(1)

272

291

302

269

269 mA

µA

136

137

131

124

119

112

108

127

136

145

151

135

µA/MHz

1. Reduced code used for characterization results provided in Table 27 ,

Table 29 ,

Table 31

Table 34. Typical current consumption in Run, with different codes running from Flash,

ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS

DD12

= 1.10 V)

Conditions

(1)

TYP TYP

Symbol Parameter Unit Unit

Voltage scaling

Code 25 °C 25 °C

DD_ALL

(Run)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48 MHz included, bypass mode PLL

ON above

48 MHz all peripherals disable

Reduced code

(2)

1.25

Coremark 1.34

Dhrystone 2.1

Fibonacci

1.34

1.25

While(1) 1.21

Reduced code

(2)

3.67

Coremark

Dhrystone 2.1

Fibonacci

While(1)

3.92

3.95

3.77

3.56

µA/MHz

DS10199 Rev 7

125/259

232

Electrical characteristics STM32L486xx

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters:

SMPS input = 3.3 V, SMPS efficiency = 85%, V

DD12

= 1.10 V

2. Reduced code used for characterization results provided in

Table 27 ,

Table 29 ,

Table 31

Table 35. Typical current consumption in Run, with different codes running from Flash,

ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS

DD12

= 1.05 V)

Conditions

(1)

TYP TYP

Symbol Parameter Unit Unit

Voltage scaling

Code 25 °C 25 °C

DD_ALL

(Run)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48 MHz included, bypass mode PLL

ON above

48 MHz all peripherals disable

Reduced code

(2)

1.14

Coremark 1.22

Dhrystone 2.1

Fibonacci

1.22

1.14

While(1) 1.10

µA/MHz

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters:

SMPS input = 3.3 V, SMPS efficiency = 85%, V

DD12

= 1.05 V

2. Reduced code used for characterization results provided in

Table 27 ,

Table 29 ,

Table 31

Table 36. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART disable

TYP Conditions TYP

Symbol Parameter

Voltage scaling

Code 25 °C

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode

Supply current in

Low-power run f f

HCLK HSE

48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

HCLK

= f

MSI

up to

= 2 MHz all peripherals disable

Reduced code

(1)

3.1

Coremark

Dhrystone 2.1

Fibonacci

While(1)

Reduced code

(1)

Coremark

Dhrystone 2.1

Fibonacci

2.9

2.8

2.7

2.6

10.0

9.4

9.1

9.0

While(1)

Reduced code

(1)

Coremark

Dhrystone 2.1

Fibonacci

While(1)

9.3

358

392

390

385

1. Reduced code used for characterization results provided in Table 27 ,

Table 29 ,

Table 31

Unit mA mA

µA

25 °C

Unit

µA/MHz

116

179

196

195

125

117

114

112

192

119

111

104

100

126/259

DS10199 Rev 7

STM32L486xx Electrical characteristics

Table 37. Typical current consumption in Run modes, with different codes running from

Flash, ART disable and power supplied by external SMPS (V

DD12

= 1.10 V)

Conditions (1) TYP TYP

Symbol Parameter Unit Unit

Voltage scaling

Code 25 °C 25 °C

DD_ALL

(Run)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

Reduced code

(2)

1.34

Coremark 1.25

Dhrystone 2.1

Fibonacci

1.21

1.16

While(1) 1.12

Reduced code

(2)

3.59

Coremark 3.38

Dhrystone 2.1

Fibonacci

While(1)

3.27

3.24

3.34

µA/MHz

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, V

DD12

= 1.10 V

2. Reduced code used for characterization results provided in Table 27 ,

Table 29 ,

Table 31

Table 38. Typical current consumption in Run modes, with different codes running from Flash, ART disable and power supplied by external SMPS (V

DD12

= 1.05 V)

Conditions

(1)

TYP TYP

Symbol Parameter Unit

Voltage scaling

Code 25 °C 25 °C

Unit

DD_ALL

(Run)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals

Reduced code

(2)

1.22

Coremark

Dhrystone 2.1

Fibonacci

1.14

1.10

1.06

While(1) 1.02

µA/MHz

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, V

DD12

= 1.05 V

2. Reduced code used for characterization results provided in Table 27 ,

Table 29 ,

Table 31

DS10199 Rev 7

127/259

232

Electrical characteristics STM32L486xx

Table 39. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1

TYP Conditions TYP

Symbol Parameter

Voltage scaling

Code 25 °C

DD_ALL

(Run)

DD_ALL

(LPRun)

Supply current in

Run mode

Supply current in

Low-power run f f

HCLK

48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

HCLK

= f

HSE

up to

= f

MSI

= 2 MHz all peripherals disable

Reduced code

(1)

2.9

Coremark

Dhrystone 2.1

Fibonacci

2.9

2.6

While(1)

Reduced code

(1)

Coremark

2.6

10.2

10.4

Dhrystone 2.1

Fibonacci

While(1)

Reduced code

(1)

Coremark

Dhrystone 2.1

Fibonacci

While(1)

10.3

9.6

9.3

242

225

242

1. Reduced code used for characterization results provided in Table 27 ,

Table 29 ,

Table 31

Unit mA mA

µA

25 °C

Unit

µA/MHz

121

112

121

129

120

116

121

111

100

127

130

Table 40. Typical current consumption in Run mode, with different codes running from

SRAM1 and power supplied by external SMPS (V

DD12

= 1.10 V)

Conditions

(1)

TYP TYP

Symbol Parameter Unit Unit

Voltage scaling

Code 25 °C 25 °C

DD_ALL

(Run)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

Reduced code

(2)

1.25

Coremark 1.25

Dhrystone 2.1

Fibonacci

1.25

1.12

While(1) 1.12

Reduced code

(2)

3.67

Coremark

Dhrystone 2.1

Fibonacci

While(1)

3.74

3.70

3.45

3.34

µA/MHz

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, V

DD12

= 1.10 V

2. Reduced code used for characterization results provided in Table 27 ,

Table 29 ,

Table 31

128/259

DS10199 Rev 7

STM32L486xx Electrical characteristics

Table 41. Typical current consumption in Run mode, with different codes running from

SRAM1 and power supplied by external SMPS (V

DD12

= 1.05 V)

Conditions

(1)

TYP TYP

Symbol Parameter Unit Unit

Voltage scaling

Code 25 °C 25 °C

DD_ALL

(Run)

Supply current in

Run mode f

HCLK

= f

HSE

up to

48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

Reduced code

(2)

1.14

Coremark

Dhrystone 2.1

1.14

Fibonacci

While(1)

1.02

µA/MHz

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, V

DD12

= 1.05 V

2. Reduced code used for characterization results provided in Table 27 ,

Table 29 ,

Table 31

DS10199 Rev 7

129/259

232

Symbol Parameter

Table 42. Current consumption in Sleep and Low-power sleep modes, Flash ON

Conditions

Voltage scaling f

HCLK

TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

DD_ALL

(Sleep)

DD_ALL

(LPSleep)

Supply current in sleep mode, f

HCLK

= f

HSE

up to 48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

Range 2

Range 1

Supply current in low-power sleep mode f

HCLK

= f

MSI all peripherals disable

26 MHz 0.92

0.96

1.07

16 MHz 0.61

0.65

0.75

8 MHz 0.36

0.40

0.50

4 MHz 0.24

0.27

0.37

2 MHz 0.18

0.20

0.30

1 MHz 0.15

0.17

0.27

100 kHz 0.12

0.14

0.24

80 MHz 2.96

3.00

3.13

72 MHz 2.69

2.73

2.85

64 MHz 2.41

2.45

2.58

48 MHz 1.88

1.93

2.07

32 MHz 1.30

1.35

1.48

24 MHz 1.01

1.05

1.17

16 MHz 0.71

0.75

0.87

2 MHz 96 126 233

1 MHz 65 94 202

400 kHz 43

100 kHz 33

181

171

1. Guaranteed by characterization results, unless otherwise specified.

0.41

3.33

3.05

2.77

2.27

1.68

1.37

1.07

412

1.25

0.92

0.66

0.53

0.47

0.43

381

359

348

0.74

3.73

3.45

3.17

2.67

2.08

1.76

1.45

775

1.59

1.012

1.14

1.27

0.69

0.78

1.01

0.87

0.42

0.28

0.50

0.36

0.81

0.215

0.29

0.77

0.18

0.25

0.15

3.26

2.96

2.65

2.10

1.43

1.11

0.80

130

0.21

3.43

3.21

2.88

2.27

1.56

1.23

0.90

202

742 95 166

718

708

138

128

1.44

4.97

4.54

4.21

3.66

3.10

2.77

2.44

1527

2.40

2.04

1.75

1.60

1.53

1.49

1483

1456

1441

0.74

4.13

3.71

3.58

2.83

2.26

1.93

1.60

777

1.77

1.32

1.03

0.89

0.82

0.78

733

706

691

0.39

3.72

3.50

3.17

2.41

1.85

1.52

1.19

402

1.36

0.97

0.68

0.54

0.46

0.44

358

331

322 mA

µA

Symbol

Table 43. Current consumption in Sleep, Flash ON and power supplied by external SMPS

DD12

= 1.10 V)

Conditions

(1)

Parameter

TYP

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C

DD_ALL

(Sleep) Supply current in sleep mode, f

HCLK

= f

HSE

up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable

80 MHz 1.06

1.08

72 MHz 0.97

0.98

64 MHz 0.87

0.88

48 MHz 0.68

0.69

32 MHz 0.47

0.49

24 MHz

16 MHz

0.36

0.26

0.38

0.27

1.13

1.02

0.93

0.74

0.53

0.42

0.31

1.20

1.10

1.00

0.82

0.60

0.49

0.38

8 MHz

4 MHz

2 MHz

1 MHz

0.16

0.17

0.10

0.12

0.08

0.09

0.06

0.07

0.22

0.16

0.13

0.12

0.28

0.23

0.20

0.19

0.44

0.38

0.35

0.33

100 kHz 0.05

0.06

0.10

0.18

0.32

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,

DD12

= 1.10 V

1.34

1.24

1.14

0.96

0.75

0.63

0.52

Unit mA

Symbol Parameter

Table 44. Current consumption in Low-power sleep modes, Flash in power-down

Conditions TYP MAX

(1)

Voltage scaling f

HCLK

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

DD_ALL

(LPSleep)

Supply current in low-power sleep mode f

HCLK

= f

MSI all peripherals disable

2 MHz

1 MHz

400 kHz 28

100 kHz 18

1. Guaranteed by characterization results, unless otherwise specified.

110

217

185

163

155

395

362

340

332

754

720

698

686

115

182

149

122

114

375

342

314

313

750

717

689

688

1500

1456

1429

1438

µA

Symbol

DD_ALL

(Stop 2)

DD_ALL

(Stop 2 with

RTC)

Parameter

Supply current in

Stop 2 mode,

RTC disabled

Conditions

LCD disabled

LCD enabled

(3) clocked by LSI

Table 45. Current consumption in Stop 2 mode

RTC clocked by LSI,

LCD disabled

RTC clocked by LSI,

LCD enabled

(3)

Supply current in

Stop 2 mode,

RTC enabled

RTC clocked by LSE bypassed at

32768Hz,LCD disabled

RTC clocked by LSE quartz

(4) in low drive mode,

LCD disabled

TYP MAX

(1)

25 °C 55 °C 85 °C

1.8 V 1.14

3.77

14.7

2.4 V 1.15

3.86

105 °C 125 °C 25 °C

34.7

35.5

79.1

2.7

55 °C

85 °C 105 °C 125 °C

193

198

3 V 1.18

3.97

15.4

3.6 V 1.26

4.11

1.8 V 1.43

3.98

2.4 V 1.49

4.07

15.3

36.4

35.8

81.3

85.1

77.3

79.4

2.8

3.0

3.2

(2)

203

213

193

199

3 V 1.54

4.24

15.7

3.6 V 1.75

4.47

16.1

1.8 V 1.42

4.04

2.4 V 1.5

4.22

15.4

3 V 1.64

4.37

15.8

3.6 V 1.79

4.65

16.6

1.8 V 1.53

4.07

15.1

2.4 V 1.62

4.32

15.5

36.7

38.3

34.9

35.7

36.7

38.4

35.1

35.9

81.6

85.4

77.2

79.2

81.4

85.4

77.4

79.5

3.3

3.5

3.1

3.2

3.4

3.6

3.3

3.4

204

214

194

199

204

214

193

198

3 V 1.69

4.43

15.9

3.6 V 1.86

4.65

16.7

1.8 V 1.5

4.13

15.2

2.4 V 1.63

4.33

15.6

3 V 1.79

4.55

16.1

3.6 V 2.04

4.9

16.8

1.8 V 1.43

3.99

14.7

2.4 V 1.54

4.11

3 V 1.67

4.29

15.5

3.6 V 1.87

4.57

16.2

36.8

38.5

35.3

38.7

35.8

36.7

38.3

81.7

85.5

77.6

79.6

81.8

85.6

3.6

3.9

3.2

3.3

3.5

3.7

3.2

3.4

3.7

205

214

204

214

194

199

Unit

µA

Symbol Parameter

DD_ALL

(wakeup from

Stop 2)

Supply current during wakeup from Stop 2 mode

Table 45. Current consumption in Stop 2 mode (continued)

Conditions

TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

Wakeup clock is

MSI = 48 MHz, voltage Range 1.

See

(5)

Wakeup clock is

MSI = 4 MHz, voltage Range 2.

See

(5)

Wakeup clock is

HSI16 = 16 MHz, voltage Range 1.

See

(5)

3 V 1.9

3 V 2.24

3 V 2.1

1. Guaranteed by characterization results, unless otherwise specified.

2. Guaranteed by test in production.

3. LCD enabled with external voltage source. Consumption from VLCD excluded. Refer to LCD controller characteristics for I

VLCD.

4. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

5. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings .

Symbol

DD_ALL

(Stop 1)

Parameter

Supply current in Stop 1 mode,

RTC disabled

Conditions

RTC clocked by

LSI

DD_ALL

(Stop 1 with

RTC)

Supply current in stop 1 mode,

RTC enabled RTC clocked by

LSE bypassed at 32768 Hz

Table 46. Current consumption in Stop 1 mode

LCD disabled

LCD enabled

(2) clocked by

LSI

LCD disabled

LCD enabled

(2)

LCD disabled

RTC clocked by

LSE quartz

(3)

in low drive mode

LCD disabled

TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

1.8 V 6.59

24.7

92.7

2.4 V 6.65

24.8

92.9

3 V 6.65

24.9

93.3

3.6 V 6.70

25.1

93.8

1.8 V 7.00

25.2

97.2

2.4 V 7.14

25.4

97.5

3 V 7.24

25.7

97.7

3.6 V 7.36

26.1

98.7

1.8 V 6.88

25.0

93.1

2.4 V 7.02

25.2

93.7

3 V 7.12

25.4

94.2

3.6 V 7.25

25.7

95.2

1.8 V 7.01

26.1

99.0

214

223

2.4 V 7.14

26.3

99.6

3 V 7.31

26.6

100.0

225

226

223

209

210

212

208

209

210

212

219

220

221

3.6 V 7.41

26.9

102.0

229

1.8 V 6.91

25.2

93.4

210

2.4 V 7.04

25.3

94.2

3 V 7.19

25.7

95.0

211

212

3.6 V 7.97

26.0

96.1

215

1.8 V 6.85

25.0

93.0

208.3

2.4 V 6.94

25.1

93.2

209.3

3 V 7.10

25.2

93.6

210.3

3.6 V 7.34

25.4

94.1

212.3

437

439

442

447

461

463

465

471

439

441

444

449

467

470

474

480

440

443

446

451

247

233

234

236

238

248

249

250

232

233

235

243

244

240

233

234

255

234

236

238

235

535

558

563

565

558

523

525

530

520

523

525

530

548

550

553

538

521

523

526

573 1200

525 1100

528

530

1108

1115

531

1128

1178

1098

1103

1110

1123

1168

1175

1185

1093

1098

1105

1118

1153

1158

1163

Unit

µA

Symbol

DD_ALL

(wakeup from Stop1)

Parameter

Table 46. Current consumption in Stop 1 mode (continued)

Conditions

TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

Supply current during wakeup from

Stop 1

Wakeup clock MSI = 48 MHz, voltage Range 1.

See

(4)

Wakeup clock MSI = 4 MHz, voltage Range 2.

See

(4)

Wakeup clock

HSI16 = 16 MHz, voltage Range 1.

See

(4)

3 V

1.47

1.7

1.62

1. Guaranteed by characterization results, unless otherwise specified.

2. LCD enabled with external voltage source. Consumption from VLCD excluded. Refer to LCD controller characteristics for I

VLCD.

3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings .

Symbol

DD_ALL

(Stop 0)

Parameter

Supply current in

Stop 0 mode,

RTC disabled

Table 47. Current consumption in Stop 0 mode

Conditions TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

1.8 V

2.4 V

3 V

3.6 V

108 132

110 134

111 135

113 137

217

219

220

222

356

358

360

363

631

634

637

642

153

158

161

166

213

218

221

226

426

431

773

778

433 783

438 791

(2)

1461

1468

1476

1488

µA

1. Guaranteed by characterization results, unless otherwise specified.

2. Guaranteed by test in production.

Symbol

DD_ALL

(Standby)

DD_ALL

(Standby with RTC)

Parameter

Supply current in Standby mode (backup registers retained),

RTC disabled

Supply current in Standby mode (backup registers retained),

RTC enabled

Conditions

Table 48. Current consumption in Standby mode no independent watchdog

TYP MAX

(1)

1.8 V 114 355 1540 4146 10735 176

2.4 V 138 407 1795 4828 12451 223

888

1018

3850

4488

10365 26838

12070 31128

3 V 150

3.6 V

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C

198

486

618

2074

2608

5589

6928

14291

17499

263

383

55 °C

1215

1545

85 °C 105 °C 125 °C

5185

6520

13973 35728

17320

(2)

43748

Unit nA with independent watchdog

RTC clocked by LSI, no independent watchdog

RTC clocked by LSI, with independent watchdog

RTC clocked by LSE bypassed at 32768Hz

RTC clocked by LSE quartz

(3)

in low drive mode

1.8 V 317

2.4 V 391

3 V 438

3.6 V 566

1.8 V 377

2.4 V 464

3 V 572

621 1873 4564 11318 491 1207 4250 10867 27537

756 2210 5348 13166 614 1436 4986 12694 31986

913 2599 6219 15197 770 1727 5815 14729 36815

3.6 V 722 1144 3253 7724 18696 1012 2176 7294 18275 45184

1.8 V 456 -

2.4 V 557

3 V 663

3.6 V 885

1.8 V 289

2.4 V 396

3 V 528

527

671

853

1747

2108

2531

4402

5202

6095

11009

12869

14915

3.6 V 710 1111 3115 7470 18221

1.8 V 416 640 1862 4479 11908

2.4 V 514

3 V 652

796

961

2193

2589

5236

6103

13689

15598

3.6 V 821 1226 3235 7551 17947

nA nA

Symbol

DD_ALL

(SRAM2)

(4)

DD_ALL

(wakeup from

Standby)

Parameter

Supply current to be added in

Standby mode when SRAM2 is retained

Supply current during wakeup from Standby mode

See

(5)

Table 48. Current consumption in Standby mode (continued)

Conditions

MSI = 4 MHz.

Wakeup clock is

TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C

1.8 V 235

2.4 V 237

3 V 236

3.6 V 235

55 °C 85 °C 105 °C 125 °C

641 2293 5192 11213 588 1603 5733 12980 28033

645 2303 5213 11246 593 1613 5758 13033 28115

647

646

2306

2308

5221

5200

11333

11327

593

595

1618

1620

5765

5770

13053 28333

13075 28350

Unit nA

3 V 1.7

1. Guaranteed by characterization results, unless otherwise specified.

2. Guaranteed by test in production.

3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

4. The supply current in Standby with SRAM2 mode is: I

+ RTC) + I

DD_ALL

(SRAM2).

DD_ALL

(Standby) + I

DD_ALL

(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: I

DD_ALL

(Standby

5. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings .

Symbol

DD_ALL

(Shutdown)

Parameter

Supply current in Shutdown mode

(backup registers retained) RTC disabled

Table 49. Current consumption in Shutdown mode

Conditions TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C

1.8 V 29.8

194 1110 3250 9093 75

2.4 V 44.3

237 1310 3798 10473 111

3 V 64.1

293 1554 4461 12082 160

55 °C

485

593

733

85 °C 105 °C 125 °C

2775

3275

3885

8125

9495

11153

22733

26183

30205

Unit nA

3.6 V 112 420 2041 5689 15186 280 1050 5103 14223 37965

Symbol

DD_ALL

(Shutdown with RTC)

Parameter

Supply current in Shutdown mode

(backup registers retained) RTC enabled

Table 49. Current consumption in Shutdown mode (continued)

Conditions

RTC clocked by LSE bypassed at 32768 Hz

RTC clocked by LSE quartz

(2)

in low drive mode

TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C

1.8 V 210 378 1299 3437 9357

2.4 V 303 499 1577 4056 10825

55 °C

85 °C 105 °C 125 °C

3 V 422 655 1925 4820 12569

3.6 V 584 888 2511 6158 15706

1.8 V 329 499 1408 3460

2.4 V 431 634 1688 4064

3 V 554 791 2025 4795

3.6 V 729 1040 2619 6129 -

Unit nA

DD_ALL

(wakeup from

Shutdown)

Supply current during wakeup from Shutdown mode

Wakeup clock is

MSI = 4 MHz.

See

(3)

3 V 0.6

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 52: Low-power mode wakeup timings .

Symbol

DD_VBAT

Parameter

Table 50. Current consumption in VBAT mode

Conditions TYP MAX

(1)

25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C

Unit

RTC disabled

Backup domain supply current

RTC enabled and clocked by LSE bypassed at 32768 Hz

RTC enabled and clocked by LSE quartz

(2)

3 V

3.6 V

1.8 V

2.4 V

3 V

3.6 V

BAT

1.8 V

2.4 V

3 V

3.6 V

1.8 V

2.4 V

5.27

183 201

268 295

376 412

508 558

302 344

388 436

494 549

630 692

367

486

602

752

196

226

264

323

521

639

784

971

587

673

775

919

729

901

1075

1299

915 1978

1091 2289

1301 2656

1571 3115

1663 10.8

1884 13.2

2147 15.5

2488 25.8

490

565

660

808

106

144

1468 4158

1683 4710

1938 5368

2298 6220

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

STM32L486xx Electrical characteristics

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

Table 70: I/O static characteristics

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see

Table 51: Peripheral current consumption ), the I/Os used by an application also contribute

to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load

(internal or external) connected to the pin:

= V

DDIOx

×

C where

is the current sunk by a switching I/O to charge/discharge the capacitive load

DDIOx

is the I/O supply voltage f

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

+ C

is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

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Electrical characteristics STM32L486xx

AHB

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in

Table 51 . The MCU is placed

under the following conditions:

• All I/O pins are in Analog mode

• The given value is calculated by measuring the difference of the current consumptions:

– when the peripheral is clocked on

– when the peripheral is clocked off

•

Ambient operating temperature and supply voltage conditions summarized in Table 20:

Voltage characteristics

• The power consumption of the digital part of the on-chip peripherals is given in

Table 51 . The power consumption of the analog part of the peripherals (where

applicable) is indicated in each related section of the datasheet.

Table 51. Peripheral current consumption

Range 1 Range 2 Peripheral

Bus Matrix

(1)

ADC independent clock domain

ADC AHB clock domain

AES

CRC

DMA1

DMA2

FLASH

FMC

GPIOA

(2)

GPIOB

(2)

GPIOC

(2)

GPIOD

(2)

GPIOE

(2)

GPIOF (2)

GPIOG

(2)

GPIOH

(2)

OTG_FS independent clock domain

OTG_FS AHB clock domain

QUADSPI

RNG independent clock domain

RNG AHB clock domain

SRAM1

4.8

4.5

4.6

5.2

5.9

6.2

8.9

4.8

4.3

0.7

4.5

0.4

5.5

1.7

0.4

1.4

1.5

23.2

16.4

7.8

2.2

0.6

0.9

4.0

3.8

3.9

4.5

4.9

5.2

7.5

3.8

0.6

3.7

0.1

4.7

1.5

0.2

1.3

N/A

6.7

N/A

0.8

Low-power run and sleep

4.6

4.3

4.4

4.9

5.7

5.8

8.4

4.4

4.2

0.8

4.1

0.2

5.5

1.6

0.3

1.4

Unit

µA/MHz

N/A

7.3

N/A

0.9

142/259

DS10199 Rev 7

STM32L486xx

AHB

APB1

Electrical characteristics

Table 51. Peripheral current consumption (continued)

Peripheral Range 1 Range 2

Low-power run and sleep

SRAM2

TSC

All AHB Peripherals

AHB to APB1 bridge

(3)

CAN1

DAC1

I2C1 independent clock domain

I2C1 APB clock domain

I2C2 independent clock domain

I2C2 APB clock domain

I2C3 independent clock domain

I2C3 APB clock domain

LCD

LPUART1 independent clock domain

LPUART1 APB clock domain

LPTIM1 independent clock domain

LPTIM1 APB clock domain

LPTIM2 independent clock domain

LPTIM2 APB clock domain

OPAMP

TIM2

TIM3

TIM4

TIM5

TIM6

TIM7

PWR

SPI2

SPI3

SWPMI1 independent clock domain

SWPMI1 APB clock domain

1.3

3.7

1.4

2.9

0.9

1.0

1.6

1.8

118.5

0.9

4.6

2.4

3.7

2.1

0.6

3.3

0.9

3.1

0.8

0.4

0.5

1.8

2.1

2.3

1.1

6.8

5.4

5.2

6.5

1.1

3.0

1.1

2.3

0.9

0.8

1.4

77.3

0.7

4.0

1.9

3.1

1.6

0.6

2.6

0.8

2.7

1.8

1.1

5.7

4.6

4.4

5.5

1.0

0.9

0.6

0.4

0.5

1.6

1.7

1.0

6.3

5.0

4.9

6.1

1.0

0.7

0.3

0.4

1.6

1.8

1.5

3.2

1.5

2.5

1.1

0.9

1.6

87.6

0.9

4.4

2.2

3.2

2.0

0.6

2.9

1.0

2.9

2.2

Unit

µA/MHz

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232

Electrical characteristics

APB1

APB2

STM32L486xx

Table 51. Peripheral current consumption (continued)

Peripheral Range 1 Range 2

Low-power run and sleep

USART2 independent clock domain

USART2 APB clock domain

USART3 independent clock domain

USART3 APB clock domain

UART4 independent clock domain

UART4 APB clock domain

UART5 independent clock domain

UART5 APB clock domain

WWDG

All APB1 on

AHB to APB2 bridge

(4)

DFSDM1

SAI1 independent clock domain

SAI1 APB clock domain

SAI2 independent clock domain

SAI2 APB clock domain

SDMMC1 independent clock domain

SDMMC1 APB clock domain

SPI1

SYSCFG/VREFBUF/COMP

TIM1

TIM8

TIM15

TIM16

TIM17

USART1 independent clock domain

USART1 APB clock domain

All APB2 on

ALL

4.1

1.4

4.7

1.5

3.9

1.5

3.9

1.3

0.5

84.2

1.0

5.6

0.7

2.6

2.1

3.3

2.4

4.7

8.3

8.6

4.1

3.0

2.5

2.0

0.6

4.9

1.5

56.8

256.8

3.6

1.1

4.1

1.3

3.2

1.3

3.2

3.9

6.9

7.1

3.4

2.5

2.4

1.9

1.6

0.4

1.2

0.5

70.7

0.9

4.6

0.5

2.1

1.8

2.7

2.1

4.0

1.3

43.3

189.6

3.8

1.5

4.2

1.7

3.5

1.6

3.5

7.9

8.1

3.9

2.9

2.1

1.9

0.5

1.4

0.5

80.2

0.9

5.3

0.7

2.3

2.0

3.0

2.2

4.2

4.4

1.7

48.2

215.5

Unit

µA/MHz

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DS10199 Rev 7

STM32L486xx Electrical characteristics

1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).

2. The GPIOx (x= A…H) dynamic current consumption is approximately divided by a factor two versus this table values when the GPIO port is locked thanks to LCKK and LCKy bits in the GPIOx_LCKR register. In order to save the full GPIOx current consumption, the GPIOx clock should be disabled in the RCC when all port I/Os are used in alternate function or analog mode (clock is only required to read or write into GPIO registers, and is not used in AF or analog modes).

3. The AHB to APB1 Bridge is automatically active when at least one peripheral is ON on the APB1.

4. The AHB to APB2 Bridge is automatically active when at least one peripheral is ON on the APB2.

The consumption for the peripherals when using SMPS can be found using STM32CubeMX

PCC tool.

6.3.6

Symbol

Wakeup time from low-power modes and voltage scaling transition times

The wakeup times given in

Table 52 are the latency between the event and the execution of

the first user instruction.

The device goes in low-power mode after the WFE (Wait For Event) instruction.

Table 52. Low-power mode wakeup timings

(1)

Parameter Conditions Typ Max Unit t

WUSLEEP

Wakeup time from Sleep mode to Run mode

6 6 t

WULPSLEEP t

WUSTOP0

Wakeup time from Lowpower sleep mode to Lowpower run mode

Wake up time from Stop 0 mode to Run mode in Flash

Wake up time from Stop 0 mode to Run mode in

SRAM1

Wakeup in Flash with Flash in power-down during low-power sleep mode (SLEEP_PD=1 in

FLASH_ACR) and with clock MSI = 2 MHz

Range 1

Range 2

Range 1

Range 2

6 9.3

Wakeup clock MSI = 48 MHz 5.6

10.9

Wakeup clock HSI16 = 16 MHz 4.7

10.4

Wakeup clock MSI = 24 MHz 5.7

11.1

Wakeup clock HSI16 = 16 MHz 4.5

10.5

Wakeup clock MSI = 4 MHz 6.6

14.2

Wakeup clock MSI = 48 MHz 0.7

2.05

Wakeup clock HSI16 = 16 MHz 1.7

2.8

Wakeup clock MSI = 24 MHz 0.8

2.72

Wakeup clock HSI16 = 16 MHz 1.7

2.8

Wakeup clock MSI = 4 MHz 2.4 11.32

Nb of

CPU cycles

µs

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232

Electrical characteristics STM32L486xx

Symbol t

WUSTOP1 t

WUSTOP2 t

WUSTBY

Table 52. Low-power mode wakeup timings (1) (continued)

Parameter

Wake up time from Stop 1 mode to Run mode in Flash

Range 2

Wake up time from Stop 1 mode to Run mode in

SRAM1

Range 1

Range 2

Conditions Typ Max Unit

Wakeup clock MSI = 48 MHz 6.2

10.2

Wakeup clock HSI16 = 16 MHz 6.3

8.99

Wakeup clock MSI = 24 MHz 6.3 10.46

Wakeup clock HSI16 = 16 MHz 6.3

8.87

Wakeup clock MSI = 4 MHz

Wakeup clock MSI = 48 MHz

8.0 13.23

4.5

5.78

Wakeup clock HSI16 = 16 MHz 5.5

7.1

Wakeup clock MSI = 24 MHz 5.0

6.5

Wakeup clock HSI16 = 16 MHz 5.5

7.1

Wakeup clock MSI = 4 MHz 8.2

13.5

µs

Wake up time from Stop 1 mode to Low-power run mode in Flash

Wake up time from Stop 1 mode to Low-power run mode in SRAM1

Regulator in low-power mode (LPR=1 in

PWR_CR1)

Wakeup clock MSI = 2 MHz

12.7

10.7 21.5

Range 1

Wake up time from Stop 2 mode to Run mode in Flash

Range 2

Wake up time from Stop 2 mode to Run mode in

SRAM1

Range 1

Range 2

Wakeup time from Standby mode to Run mode

Range 1 t

WUSTBY

SRAM2

Wakeup time from Standby with SRAM2 to Run mode t

WUSHDN

Wakeup time from

Shutdown mode to Run mode

1. Guaranteed by characterization results.

Range 1

Wakeup clock MSI = 48 MHz 8.0

9.4

Wakeup clock HSI16 = 16 MHz 7.3

9.3

Wakeup clock MSI = 24 MHz 8.2

9.9

Wakeup clock HSI16 = 16 MHz 7.3

9.3

Wakeup clock MSI = 4 MHz 10.6 15.8

Wakeup clock MSI = 48 MHz 5.1

6.7

Wakeup clock HSI16 = 16 MHz 5.7

Wakeup clock MSI = 24 MHz 5.5

6.65

Wakeup clock HSI16 = 16 MHz 5.7

7.53

Wakeup clock MSI = 4 MHz

Wakeup clock MSI = 8 MHz

8.2

16.6

14.3 20.8

Wakeup clock MSI = 4 MHz

Wakeup clock MSI = 8 MHz

Wakeup clock MSI = 4 MHz

20.1 35.5

14.3 24.3

20.1 38.5

Wakeup clock MSI = 4 MHz

µs

256 330.6

µs

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DS10199 Rev 7

STM32L486xx

Symbol

Table 53. Regulator modes transition times (1)

Parameter Conditions t

WULPRUN t

VOST

Wakeup time from Low-power run mode to

Run mode (2)

Code run with MSI 2 MHz

Regulator transition time from Range 2 to

Range 1 or Range 1 to Range 2

(3)

Code run with MSI 24 MHz

1. Guaranteed by characterization results.

2. Time until REGLPF flag is cleared in PWR_SR2.

3. Time until VOSF flag is cleared in PWR_SR2.

Electrical characteristics

Typ

Max

Unit

µs

Symbol

Table 54. Wakeup time using USART/LPUART

(1)

Parameter t t

WUUSART

WULPUART

Wakeup time needed to calculate the maximum USART/LPUART baudrate allowing to wakeup up from stop mode when USART/LPUART clock source is

HSI16

1. Guaranteed by design.

Conditions

Stop 0 mode

Stop 1 mode and Stop 2 mode

Typ

Max

1.7

8.5

Unit

µs

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.14

. However,

Symbol f

HSE_ext

HSEH

HSEL

Table 55. High-speed external user clock characteristics

(1)

Parameter Conditions Min Typ

User external clock source frequency

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage t w(HSEH) t w(HSEL)

OSC_IN high or low time

Voltage scaling

Range 1

Voltage scaling

Range 2

Voltage scaling

Range 1

Voltage scaling

Range 2

0.7 V

DDIOx

1. Guaranteed by design.

Max

DDIOx

0.3 V

DDIOx

Unit

MHz

V ns

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232

Electrical characteristics STM32L486xx

Figure 20. High-speed external clock source AC timing diagram tw(HSEH)

VHSEH

VHSEL

90%

10% tr(HSE)

THSE tf(HSE) tw(HSEL) t

MS19214V2

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.14

. However,

Symbol

Table 56. Low-speed external user clock characteristics (1)

Parameter f

LSE_ext

LSEH

LSEL t w(LSEH) t w(LSEL)

User external clock source frequency

OSC32_IN input pin high level voltage

OSC32_IN input pin low level voltage

OSC32_IN high or low time

1. Guaranteed by design.

Conditions

Min

0.7 V

DDIOx

250

Typ

32.768

Max

1000

DDIOx

0.3 V

DDIOx

Unit kHz

V ns

Figure 21. Low-speed external clock source AC timing diagram tw(LSEH)

VLSEH

VLSEL

90%

10% tr(LSE)

TLSE tf(LSE) tw(LSEL) t

MS19215V2

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DS10199 Rev 7

STM32L486xx Electrical characteristics

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 57 . In the

application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics

(frequency, package, accuracy).

Symbol

Table 57. HSE oscillator characteristics (1)

Parameter Conditions

(2)

Min Typ Max Unit

I f

OSC_IN

DD(HSE)

Oscillator frequency

Feedback resistor

HSE current consumption

During startup

(3)

= 3 V,

Rm = 30 Ω ,

CL = 10 pF@8 MHz

= 3 V,

Rm = 45 Ω ,

CL = 10 pF@8 MHz

= 3 V,

Rm = 30 Ω ,

CL = 5 pF@48 MHz

= 3 V,

Rm = 30 Ω ,

CL = 10 pF@48 MHz

200

0.44

0.45

0.68

0.94

5.5

MHz k Ω mA

= 3 V,

Rm = 30 Ω ,

CL = 20 pF@48 MHz

1.77

G m

Maximum critical crystal transconductance

Startup 1.5

mA/V t

SU(HSE)

(4)

Startup time V

is stabilized 2 ms

1. Guaranteed by design.

2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

3. This consumption level occurs during the first 2/3 of the t

SU(HSE) startup time

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see Figure 22

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

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232

Electrical characteristics

Note:

STM32L486xx

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 22. Typical application with an 8 MHz crystal

Resonator with integrated capacitors

OSC_IN f

HSE

8 MHz resonator

EXT

(1) OSC_OUT

Bias controlled gain

MS19876V1

1. R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 58 . In the application, the

resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 58. LSE oscillator characteristics (f

LSE

= 32.768 kHz)

(1)

Parameter Conditions

(2)

DD(LSE)

Gm critmax t

SU(LSE)

(3)

LSE current consumption

Maximum critical crystal gm

Startup time

LSEDRV[1:0] = 00

Low drive capability

LSEDRV[1:0] = 01

Medium low drive capability

LSEDRV[1:0] = 10

Medium high drive capability

LSEDRV[1:0] = 11

High drive capability

LSEDRV[1:0] = 00

Low drive capability

LSEDRV[1:0] = 01

Medium low drive capability

LSEDRV[1:0] = 10

Medium high drive capability

LSEDRV[1:0] = 11

High drive capability

is stabilized

Min Typ Max Unit

250

315

500

630

0.5

0.75

1.7

2.7

µA/V s

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1. Guaranteed by design.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

3. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 23. Typical application with a 32.768 kHz crystal

Resonator with integrated capacitors

OSC32_IN f

LSE

32.768 kHz resonator

Drive programmable amplifier

OSC32_OUT

Note:

MS30253V2

An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

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Electrical characteristics STM32L486xx

6.3.8 Internal clock source characteristics

The parameters given in

Table 59 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 23: General operating conditions

. The provided curves are characterization results, not tested in production.

High-speed internal (HSI16) RC oscillator

Symbol

Table 59. HSI16 oscillator characteristics (1)

Parameter Conditions

DuCy(HSI16)

(2)

∆

∆ t

Temp

VDD su t stab

DD f

HSI16

TRIM

(HSI16)

(2)

HSI16 Frequency

HSI16 user trimming step

=3.0 V, T

=30 °C

Trimming code is not a multiple of 64

Trimming code is a multiple of 64

Duty Cycle

HSI16 oscillator frequency drift over temperature

= 0 to 85 °C

= -40 to 125 °C

HSI16 oscillator frequency drift over V

HSI16 oscillator start-up time

=1.62 V to 3.6 V

HSI16 oscillator stabilization time

HSI16 oscillator power consumption

1. Guaranteed by characterization results.

2. Guaranteed by design.

Min

15.88

0.2

-4

-1

-2

-0.1

Typ

0.3

-6

0.8

155

Max Unit

16.08

MHz

0.4

-8

1.5

0.05

1.2

190

μ s

μ A

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MHz

16.4

16.3

16.2

16.1

15.9

15.8

15.7

15.6

-40 -20

Electrical characteristics

Figure 24. HSI16 frequency versus temperature

+2 %

+1.5 %

+1 %

Mean

-1 %

-1.5 %

-2 %

40 min

60 80 max

100 120 °C

MSv39299V2

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Electrical characteristics STM32L486xx

Symbol f

MSI

Multi-speed internal (MSI) RC oscillator

∆

TEMP

(MSI) (2)

Parameter

Table 60. MSI oscillator characteristics

(1)

Conditions

MSI frequency after factory calibration, done at V

=3 V and

=30 °C

MSI oscillator frequency drift over temperature

MSI mode

PLL mode

XTAL=

32.768 kHz

MSI mode

Range 0

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

Range 0

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

= -0 to 85 °C

= -40 to 125 °C

Min

0.99

1.98

3.96

7.92

15.8

198

396

792

23.8

31.7

47.5

-3.5

-8

Max Unit

24.4

32.32

48.48

101

202

404

808 kHz

1.01

2.02

4.04

8.08

16.16

MHz kHz

MHz

Typ

98.304

196.608

393.216

786.432

1.016

1.999

100

200

400

800

3.998

7.995

15.991

23.986

32.014

48.005

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Symbol

VDD

(MSI)

P_USB

(2)

(6)

MT_USB

(6)

CC jitter(MSI)

(6)

P jitter(MSI) t

∆

∆ t

(MSI)

Jitter(MSI)

(MSI)

STAB

(6)

(MSI)

(6)

Table 60. MSI oscillator characteristics (1) (continued)

Parameter Conditions Min

MSI oscillator frequency drift over V

(reference is 3 V)

MSI mode

Range 0 to 3

Range 4 to 7

=1.62 V to 3.6 V

=2.4 V to 3.6 V

=1.62 V to 3.6 V

=2.4 V to 3.6 V

Range 8 to 11

=1.62 V to 3.6 V

=2.4 V to 3.6 V

= -40 to 85 °C Frequency variation in sampling mode

(3)

MSI mode

= -40 to 125 °C

Period jitter for

USB clock

(4)

Medium term jitter for USB clock

MSI oscillator

(5) stabilization time

PLL mode

Range 11

PLL mode

Range 11

PLL mode

Range 11

RMS cycle-tocycle jitter

PLL mode Range 11

RMS Period jitter PLL mode Range 11

MSI oscillator start-up time

Range 0

Range 1

Range 2

Range 3

Range 4 to 7

Range 8 to 11 for next transition for paired transition for next transition for paired transition

10 % of final frequency

5 % of final frequency

1 % of final frequency

-1.2

-0.5

-2.5

-0.8

-5

-1.6

Electrical characteristics

Max Unit

0.5

0.7

3.458

3.916

1 ns

0.5

ps ps us

1.25

2.5

Typ

2.5

0.25

0.5

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Electrical characteristics STM32L486xx

Symbol

Table 60. MSI oscillator characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit

(MSI)

(6)

MSI oscillator power consumption

MSI and

PLL mode

Range 0

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

0.6

0.8

1.2

1.9

4.7

6.5

18.5

110

155

µA

1. Guaranteed by characterization results.

2. This is a deviation for an individual part once the initial frequency has been measured.

3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.

4. Average period of MSI @48 MHz is compared to a real 48 MHz clock over 28 cycles. It includes frequency tolerance + jitter of MSI @48 MHz clock.

5. Only accumulated jitter of MSI @48 MHz is extracted over 28 cycles.

For next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of the MSI @48 MHz, for 1000 captures over 28 cycles.

For paired transitions: min. and max. jitter of 2 consecutive frame of 56 cycles of the MSI @48 MHz, for 1000 captures over

56 cycles.

6. Guaranteed by design.

2.5

1.2

1.7

110

130

190

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Figure 25. Typical current consumption versus MSI frequency

Low-speed internal (LSI) RC oscillator

Symbol Parameter

Table 61. LSI oscillator characteristics

(1)

Conditions Min f

LSI

LSI Frequency

= 3.0 V, T

= 30 °C

= 1.62 to 3.6 V, T

= -40 to 125 °C t t

STAB

(LSI)

(2)

LSI oscillator startup time

LSI oscillator stabilization time

LSI oscillator power consumption

1. Guaranteed by characterization results.

2. Guaranteed by design.

5% of final frequency

31.04

29.5

Typ

125

110

Max Unit

32.96

34 kHz

130 μ s

180 μ s

180 nA

The parameters given in

Table 62 are derived from tests performed under temperature and

supply voltage conditions summarized in

Table 23: General operating conditions .

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Electrical characteristics STM32L486xx

Symbol f

PLL_IN f

PLL_P_OUT

Table 62. PLL, PLLSAI1, PLLSAI2 characteristics (1)

Parameter

PLL input clock

(2)

PLL input clock duty cycle

PLL multiplier output clock P f

PLL_Q_OUT

PLL multiplier output clock Q f

PLL_R_OUT

PLL multiplier output clock R f

VCO_OUT t

LOCK

Jitter

(PLL)

PLL VCO output

PLL lock time

RMS cycle-to-cycle jitter

RMS period jitter

PLL power consumption on

(1)

Conditions

Voltage scaling Range 1

Voltage scaling Range 2

Voltage scaling Range 1

Voltage scaling Range 2

Voltage scaling Range 1

Voltage scaling Range 2

Voltage scaling Range 1

Voltage scaling Range 2

System clock 80 MHz

VCO freq = 64 MHz

VCO freq = 96 MHz

VCO freq = 192 MHz

VCO freq = 344 MHz

Min

2.0645

Typ Max Unit

150 200

200 260

300 380

520 650

128

344

16 MHz

55 %

MHz

μ s

±ps

μ A

1. Guaranteed by design.

2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between the 3 PLLs.

Symbol t prog_page t t prog prog_row

ERASE

Table 63. Flash memory characteristics (1)

Parameter

64-bit programming time one row (32 double word) programming time one page (2 Kbyte) programming time

Page (2 KB) erase time t prog_bank t

ME one bank (512 Kbyte) programming time

Mass erase time

(one or two banks)

Conditions

normal programming fast programming normal programming fast programming

normal programming fast programming

Typ

22.13

81.69

2.61

1.91

20.91

15.29

22.02

5.35

3.91

Max Unit

90.76

µs

2.90

2.12

ms 23.24

16.98

24.47

5.95

4.35

24.59

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Symbol

Table 63. Flash memory characteristics (1) (continued)

Parameter Conditions

Average consumption from V

Maximum current (peak)

Write mode

Erase mode

Write mode

Erase mode

1. Guaranteed by design.

Typ

3.4

7 (for 2 μ s)

7 (for 41 μ s)

Max Unit

Symbol

Table 64. Flash memory endurance and data retention

Parameter Conditions

N t

END

RET

Endurance

Data retention

= –40 to +105 °C

1 kcycle

(2)

at T

= 85 °C

1 kcycle

(2)

at T

= 105 °C

1 kcycle

(2)

at T

= 125 °C

10 kcycles (2) at T

= 55 °C

10 kcycles

(2)

at T

= 85 °C

10 kcycles (2) at T

= 105 °C

1. Guaranteed by characterization results.

2. Cycling performed over the whole temperature range.

Min

(1)

Unit kcycles

Years

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Electrical characteristics STM32L486xx

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

and

A device reset allows normal operations to be resumed.

The test results are given in Table 65

. They are based on the EMS levels and classes defined in application note AN1709.

Symbol

Table 65. EMS characteristics

Parameter Conditions

Level/

Class

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

and V pins to induce a functional disturbance

SS f

= 3.3 V, T

HCLK

= +25 °C,

= 80 MHz, conforming to IEC 61000-4-2 f

= 3.3 V, T

HCLK

= +25 °C,

= 80 MHz, conforming to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (control registers...)

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Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

EMI

Symbol Parameter

Table 66. EMI characteristics

Conditions

Monitored frequency band

Peak level

= 3.6 V, T compliant with

IEC 61967-2

= 25 °C,

LQFP144 package

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1 GHz

EMI Level

Max vs. [f

HSE

HCLK

] f

MSI

= 24 MHz 8 MHz / 80 MHz

-9

-8

-10

1.5

3.5

Unit dBµV

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard.

Symbol

Table 67. ESD absolute maximum ratings

Ratings Conditions Class

Maximum value

(1)

Unit

ESD(HBM)

Electrostatic discharge voltage (human body model)

ESD(CDM)

Electrostatic discharge voltage (charge device model)

= +25 °C, conforming to ANSI/ESDA/JEDEC

JS-001

= +25 °C, conforming to ANSI/ESD

STM5.3.1

1. Guaranteed by characterization results.

2000

250

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Electrical characteristics STM32L486xx

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin.

• A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Symbol Parameter

Table 68. Electrical sensitivities

Conditions

LU Static latch-up class T

= +105 °C conforming to JESD78A

1. Negative injection is limited to -30 mA for PF0, PF1, PG6, PG7, PG8, PG12, PG13, PG14.

Class

II level A

(1)

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

DDIOx product operation. However, in order to give an indication of the robustness of the

(for standard, 3.3 V-capable I/O pins) should be avoided during normal microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation).

The characterization results are given in

Table 69 .

Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection.

Symbol

Table 69. I/O current injection susceptibility

Functional susceptibility

Description

Negative injection

Positive injection

Unit

INJ

Injected current on BOOT0 pin

Injected current on pins except PA4, PA5, BOOT0

Injected current on PA4, PA5 pins

1. Injection is not possible.

-0

-5

N/A (1)

0 mA

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General input/output characteristics

Unless otherwise specified, the parameters given in

Table 70 are derived from tests

performed under the conditions summarized in Table 23: General operating conditions

. All

I/Os are designed as CMOS- and TTL-compliant (except BOOT0).

Symbol

(1)

V hys

(3)

Parameter

Table 70. I/O static characteristics

Conditions Min Typ Max

I/O input low level voltage except

BOOT0

I/O input low level voltage except

BOOT0

I/O input low level voltage except

BOOT0

BOOT0 I/O input low level voltage

I/O input high level voltage except

BOOT0

I/O input high level voltage except

BOOT0

I/O input high level voltage except

BOOT0

1.62 V<V

1.08 V<V

1.62 V<V

1.08 V<V

DDIOx

<3.6 V

<1.62 V

<3.6 V

<3.6 V 0.7xV

DDIOx

(2)

<3.6 V 0.49xV

DDIOX

<1.62 V 0.61xV

DDIOX

BOOT0 I/O input high level voltage

1.62 V<V

DDIOx

<3.6 V

TT_xx, FT_xxx and

NRST I/O input hysteresis

FT_sx

BOOT0 I/O input hysteresis

1.62 V<V

1.08 V<V

1.62 V<V

DDIOx

<3.6 V

<1.62 V

<3.6 V

0.77xV

+0.26

(3)

+0.05

(3)

DDIOX

(3)

200

150

200

0.3xV

0.39xV

0.43xV

DDIOx

0.17xV

DDIOx

(2)

-0.06

(3)

-0.1

DDIOx

(3)

Unit

V mV

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Electrical characteristics STM32L486xx

Symbol Parameter

FT_xx input leakage current

(3)(5)

Table 70. I/O static characteristics (continued)

Conditions Min Typ

≤

Max(V

DDXXX

) (6)(7)

Max(V

DDXXX

Max(V

DDXXX

) ≤ V

)+1 V

≤

Max(V

≤ 5.5 V

)+1 V <

≤ Max(V

DDXXX

)

Max

±100

650

200

±150

I lkg

(4)

FT_lu, FT_u and PC3

I/Os

TT_xx input leakage current

Max(V

DDXXX

Max(V

DDXXX

) ≤ V

)+1 V

≤

Max(V

≤ 5.5 V

)+1 V <

≤ Max(V

DDXXX

)

(6)

Max(V

3.6 V

) ≤ V

OPAMPx_VINM

(x=1,2) dedicated input leakage current

(UFBGA132 only)

Weak pull-up equivalent resistor

(9)

= V

2500

250

±150

2000

(8)

(3)

Weak pull-down equivalent resistor

(9)

= V

DDIOx

25 40 55

I/O pin capacitance 5 -

1. Refer to Figure 26: I/O input characteristics .

2. Guaranteed by test in production.

3. Guaranteed by design.

4. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula:

Total_Ileak_max

= 10 µA + [number of IOs where V

is applied on the pad] ₓ I lkg

(Max).

5. All FT_xx GPIOs except FT_lu, FT_u and PC3 I/Os.

6. Max(V

DDXXX

) is the maximum value of all the I/O supplies.

7. To sustain a voltage higher than Min(V resistors must be disabled.

, V

DDA

, V

DDIO2

, V

DDUSB

, V

LCD

) +0.3 V, the internal Pull-up and Pull-Down

8. Refer to I bias

in Table 86: OPAMP characteristics

for the values of the OPAMP dedicated input leakage current.

9. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

Unit nA k Ω k Ω pF

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All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements is shown in Figure 26

for standard I/Os, and in

Figure 26

for

5 V tolerant I/Os.

Figure 26. I/O input characteristics

TTL requirement Vih min = 2V

min = 0

.7xV

DDIO x

DDIOx

+0.2

6 for V

DDIOx

>1.62

DDIOx

<1.62 or

0.49xV

Teste d in production CMOS requirement Vih on Vi h min = 0.

lation V il max

61xV

DDIOx

=0.43xV

DDIOx

+0.05

for 1.08<V

-0.1 for 1.08

<V DDIOx

<1.62 or 0.39xV

ax = 0.3xVdd

DDIOx

-0.06 for

DDIO x

>1.62

TTL requirement Vil max = 0.8V

Based on simu ction CMOS req uirement Vil m

Tested in produ

MSv37613V1

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ± 20 mA (with a relaxed V

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2

• The sum of the currents sourced by all the I/Os on V

DDIOx, consumption of the MCU sourced on V

DD,

Σ I

VDD

(see Table 20: Voltage characteristics ).

plus the maximum cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

, plus the maximum consumption of the MCU sunk on V

, cannot exceed the absolute maximum rating

Table 20: Voltage characteristics

Σ I

VSS

(see

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Electrical characteristics STM32L486xx

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 23: General operating conditions . All I/Os are CMOS- and TTL-compliant (FT OR TT

unless otherwise specified).

Symbol

Table 71. Output voltage characteristics (1)

Parameter Conditions Min Max Unit

(3)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

CMOS port

DDIOx

(2)

= 8 mA

≥ 2.7 V

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

TTL port

DDIOx

(2)

= 8 mA

≥ 2.7 V

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

DDIOx

= 20 mA

≥ 2.7 V

= 4 mA

≥ 1.62 V

= 2 mA

1.62 V ≥ V

DDIOx

≥ 1.08 V

DDIOx

2.4

DDIOx

-0.4

-1.3

-0.45

0.65

ₓ V

DDIOx

0.35

0.4

0.45

ₓ

1.3

DDIOx

Output low level voltage for an FT I/O pin in FM+ mode (FT I/O with "f" option)

| = 20 mA

DDIOx

≥ 2.7 V

| = 10 mA

DDIOx

≥ 1.62 V

| = 2 mA

1.62 V ≥ V

DDIOx

≥ 1.08 V

0.4

1. The I

current sourced or sunk by the device must always respect the absolute maximum rating specified in

Table 20:

Voltage characteristics

, and the sum of respect the absolute maximum ratings the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always

Σ I

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. Guaranteed by design.

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 27

and

Table 72 , respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 23: General operating conditions

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Speed Symbol

Table 72. I/O AC characteristics (1)(2)

Parameter Conditions

Fmax Maximum frequency

Tr/Tf Output rise and fall time

Fmax Maximum frequency

Tr/Tf Output rise and fall time

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

Electrical characteristics

Min

Max

140

110

1.5

0.1

4.5

Unit

MHz ns

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Speed Symbol

Table 72. I/O AC characteristics (1)(2) (continued)

Parameter Conditions Min Max Unit

Fmax

Tr/Tf

Fmax

Tr/Tf

Maximum frequency

Output rise and fall time

Maximum frequency

Output rise and fall time

C=50 pF, 2.7 V ≤ V

C=10 pF, 2.7 V ≤ V

C=50 pF, 2.7 V ≤ V

C=10 pF, 2.7 V ≤ V

C=30 pF, 2.7 V ≤ V

C=10 pF, 2.7 V ≤ V

C=30 pF, 2.7 V ≤ V

C=30 pF, 1.08 V ≤

DDIOx

C=50 pF, 1.62 V ≤ V

C=50 pF, 1.08 V ≤ V

DDIOx

C=10 pF, 1.62 V ≤ V

C=10 pF, 1.08 V ≤ V

DDIOx

C=50 pF, 1.62 V ≤ V

C=50 pF, 1.08 V ≤ V

DDIOx

C=10 pF, 1.62 V ≤ V

C=10 pF, 1.08 V ≤ V

DDIOx

C=30 pF, 1.62 V ≤ V

C=30 pF, 1.08 V ≤ V

DDIOx

C=10 pF, 1.62 V ≤ V

C=10 pF, 1.08 V ≤ V

DDIOx

C=30 pF, 1.62 V ≤ V

≤

DDIOx

≤

DDIOx

≤

DDIOx

≤

DDIOx

≤

DDIOx

≤

DDIOx

≤

DDIOx

3.6 V

≤

3.6 V

≤

3.6 V

≤

3.6 V

≤

3.6 V

≤

3.6 V

≤

3.6 V

≤

2.7 V

1.62 V

2.7 V

1.62 V

2.7 V

1.62 V

2.7 V

1.62 V

2.7 V

1.62 V

2.7 V

1.62 V

2.7 V

1.62 V

100

(3)

37.5

5.8

2.5

120

(3)

180

(3)

3.3

MHz ns

Fm+

Fmax Maximum frequency

Tf Output fall time

(4)

C=50 pF, 1.6 V ≤ V

DDIOx

≤ 3.6 V

MHz ns

1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.

Refer to the RM0351 reference manual for a description of GPIO Port configuration register.

2. Guaranteed by design.

3. This value represents the I/O capability but the maximum system frequency is limited to 80 MHz.

4. The fall time is defined between 70% and 30% of the output waveform accordingly to I 2 C specification.

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Figure 27. I/O AC characteristics definition

(1)

90% 10%

50% 50%

10% 90% t r(IO)out t f(IO)out

T when loaded by the specified capacitance.

MS32132V2

1. Refer to Table 72: I/O AC characteristics .

6.3.15 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, R

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 23: General operating conditions .

Symbol Parameter

Table 73. NRST pin characteristics (1)

Conditions Min Typ Max Unit

IL(NRST)

IH(NRST)

V hys(NRST)

F(NRST)

NF(NRST)

NRST input low level voltage

NRST input high level voltage

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(2)

NRST input filtered pulse

NRST input not filtered pulse

= V

1.71 V ≤ V

≤ 3.6 V

0.7

ₓ V

DDIOx

350

200

0.3

ₓ V

DDIOx

1. Guaranteed by design.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order)

V mV k Ω ns ns

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Figure 28. Recommended NRST pin protection

External reset circuit

(1)

0.1 μF

NRST

(2)

Filter

Internal reset

MS19878V3

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

IL(NRST)

max level specified in

Table 73: NRST pin characteristics

. Otherwise the reset will not be taken into account by the device.

3. The external capacitor on NRST must be placed as close as possible to the device.

6.3.16 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length in order to guarantee that it is detected by the event controller.

Symbol

Table 74. EXTI input characteristics (1)

Parameter

PLEC

Pulse length to event controller

1. Guaranteed by design.

Conditions

Min

Typ

Max

Unit ns

6.3.17 Analog switches booster

Symbol

Table 75. Analog switches booster characteristics

(1)

Parameter

DD t

SU(BOOST)

Supply voltage

Booster startup time

DD(BOOST)

Booster consumption for

1.62 V ≤ V

≤ 2.0 V

Booster consumption for

2.0 V ≤ V

≤ 2.7 V

Booster consumption for

2.7 V ≤ V

≤ 3 .6 V

1. Guaranteed by design.

Min

1.62

Typ

Max

3.6

240

250

500

900

Unit

µs

µA

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Note:

Symbol

DDA

REF+

REFf

ADC f s f

TRIG

AIN

(3)

AIN

ADC

Unless otherwise specified, the parameters given in Table 76

are preliminary values derived from tests performed under ambient temperature, f

PCLK frequency and V

conditions summarized in Table 23: General operating conditions

DDA

supply voltage

It is recommended to perform a calibration after each power-up.

Parameter

Table 76. ADC characteristics

(1) (2)

Conditions Min

Analog supply voltage

Positive reference voltage

DDA

≥ 2 V

DDA

< 2 V

Negative reference voltage

Range 1

ADC clock frequency

Sampling rate for FAST channels

Range 2

Resolution = 12 bits

Resolution = 10 bits

Resolution = 8 bits

Resolution = 6 bits

Resolution = 12 bits

Resolution = 10 bits

Sampling rate for SLOW channels

Resolution = 8 bits

Resolution = 6 bits

External trigger frequency f

ADC

= 80 MHz

Resolution = 12 bits

Conversion voltage range(2)

External input impedance

Internal sample and hold capacitor

1.62

0.14

Typ

DDA

SSA

Max

3.6

DDA

7.27

8.88

4.21

4.71

5.33

6.15

5.33

6.15

5.33

REF+

Unit

MHz

Msps

MHz

1/f

ADC

V k Ω pF t

STAB t

CAL t

LATR

Power-up time -

Calibration time f

ADC

= 80 MHz

Trigger conversion latency Regular and injected channels without conversion abort

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11 -

1.5

1.45

116

2.5

2.0

2.25

2.125

conversion cycle

µs

1/f

ADC

1/f

ADC

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Symbol

Table 76. ADC characteristics (1) (2) (continued)

Parameter Conditions Min Typ Max Unit t

LATRINJ

Trigger conversion latency Injected channels aborting a regular conversion

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11

Sampling time f

ADC

= 80 MHz

2.5

3.5

3.0

3.25

3.125

1/f

ADC t s

0.03125

2.5

8.00625

640.5

µs

1/f

ADC t

ADCVREG_STUP

ADC voltage regulator start-up time

20 µs f

ADC

= 80 MHz

Resolution = 12 bits

0.1875

8.1625

µs

I t

CONV

DDA

(ADC)

DDV_S

(ADC)

Total conversion time the V

REF+ mode

(including sampling time)

ADC consumption from the V

DDA

supply

ADC consumption from

single ended

Resolution = 12 bits fs = 5 Msps fs = 1 Msps fs = 10 ksps fs = 5 Msps fs = 1 Msps fs = 10 ksps fs = 5 Msps

ts + 12.5 cycles for successive approximation

= 15 to 653

730 830

160

130

0.6

260

220

160

310

1/f

ADC

µA

DDV_D

(ADC)

ADC consumption from the V mode

REF+

differential fs = 1 Msps fs = 10 ksps

1.3

µA

1. Guaranteed by design

2. The I/O analog switch voltage booster is enable when V

DDA

< 2.4V). It is disable when V

DDA

≥ 2.4 V.

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

REF+

can be internally connected to V

DDA

and V

Section 4: Pinouts and pin description

REF-

can be internally connected to V

for further details.

SSA

, depending on the package.

The maximum value of R

AIN

can be found in Table 77: Maximum ADC RAIN .

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Resolution

12 bits

10 bits

8 bits

6 bits

1. Guaranteed by design.

Electrical characteristics

Table 77. Maximum ADC R

AIN

(1)(2)

Sampling cycle

@80 MHz

Sampling time [ns]

@80 MHz

AIN

max ( Ω )

Fast channels

(3) channels

(4)

92.5

247.5

640.5

2.5

6.5

12.5

640.5

2.5

6.5

12.5

24.5

47.5

24.5

47.5

92.5

247.5

640.5

2.5

6.5

12.5

24.5

47.5

92.5

247.5

2.5

6.5

12.5

24.5

47.5

92.5

247.5

8006.75

31.25

81.25

156.25

306.25

593.75

1156.25

3093.75

8006.75

31.25

81.25

156.25

8006.75

31.25

81.25

156.25

306.25

593.75

1156.25

3093.75

31.25

81.25

156.25

306.25

593.75

1156.25

3093.75

306.25

593.75

1156.25

3093.75

8006.75

6800

15000

50000

220

560

1200

47000

180

470

1000

1800

2700

39000

120

390

820

1500

2200

5600

12000

100

330

680

1500

2200

4700

12000

2700

3900

8200

18000

50000

5600

12000

50000

N/A

330

1000

39000

N/A

270

680

1500

2200

33000

N/A

180

560

1200

1800

4700

10000

N/A

100

470

1200

1800

3900

10000

2200

3300

6800

15000

50000

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Electrical characteristics STM32L486xx

2. The I/O analog switch voltage booster is enable when V

DDA

< 2.4V). It is disable when V

DDA

≥ 2.4 V.

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

3. Fast channels are: PC0, PC1, PC2, PC3, PA0.

4. Slow channels are: all ADC inputs except the fast channels.

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Table 78. ADC accuracy - limited test conditions 1 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Differential linearity error

Integral linearity error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

DDA

= VREF+ = 3 V,

TA = 25 °C

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

1 1.5

1 1.2

1.5

2.5

1.5

2.5

1 2

Slow channel (max speed) 1 2

Fast channel (max speed) 10.4 10.5

Slow channel (max speed) 10.4 10.5

Fast channel (max speed) 10.8 10.9

Slow channel (max speed) 10.8 10.9

Fast channel (max speed) 64.4 65 -

Slow channel (max speed) 64.4 65

Fast channel (max speed) 66.8 67.4

Slow channel (max speed) 66.8 67.4

Fast channel (max speed) 65 66

Slow channel (max speed) 65 66

Fast channel (max speed) 67 68

Slow channel (max speed) 67 68

4 5

3.5

4.5

3.5

4.5

1 2.5

1.5

2.5

1.5

2.5

4.5

2.5

4.5

2.5

3.5

2.5

3.5

1 1.5

LSB bits dB

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Table 78. ADC accuracy - limited test conditions 1 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

DDA

= V

REF+

= 3 V,

TA = 25 °C

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-74 -73

-79 -76

-79 -76 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

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Table 79. ADC accuracy - limited test conditions 2 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Differential linearity error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

2 V ≤ V

DDA Integral linearity error

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

1 1.5

1 1.2

1.5

3.5

1.5

3.5

1 3

Slow channel (max speed) 1 2.5

Fast channel (max speed) 10 10.5

Slow channel (max speed) 10 10.5

Fast channel (max speed) 10.7 10.9

Slow channel (max speed) 10.7 10.9

Fast channel (max speed) 62 65 -

Slow channel (max speed) 62 65

Fast channel (max speed) 66 67.4

Slow channel (max speed) 66 67.4

Fast channel (max speed) 64 66

Slow channel (max speed) 64 66

Fast channel (max speed) 66.5 68

Slow channel (max speed) 66.5 68

4 6.5

3.5

5.5

3.5

5.5

1 4.5

1 5

1.5

2.5

3.5

2.5

3.5

1 1.5

LSB bits dB

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Table 79. ADC accuracy - limited test conditions 2 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

2 V ≤ V

DDA

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-74 -65

-74 -67

-79 -70

-79 -71 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

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Table 80. ADC accuracy - limited test conditions 3 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Differential linearity error

Integral linearity error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

1.65 V ≤ V

DDA

3.6 V,

= V

REF+

≤

Voltage scaling Range 1

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

1.2

1.5

1 1.2

3 3.5

2.5

3.5

2 2.5

Slow channel (max speed) 2 2.5

Fast channel (max speed) 10 10.4

Slow channel (max speed) 10 10.4

Fast channel (max speed) 10.6 10.7

Slow channel (max speed) 10.6 10.7

Fast channel (max speed) 62 64 -

Slow channel (max speed) 62 64

Fast channel (max speed) 65 66

Slow channel (max speed) 65 66

Fast channel (max speed) 63 65

Slow channel (max speed) 63 65

Fast channel (max speed) 66 67

Slow channel (max speed) 66 67

5.5

7.5

4.5

6.5

4.5

7.5

4.5

5.5

2 5

2.5

2 3.5

2.5

4.5

3.5

1.2

1.5

LSB bits dB

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Table 80. ADC accuracy - limited test conditions 3 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

1.65 V ≤ V

DDA

3.6 V,

= V

REF+

≤

Voltage scaling Range 1

Single ended

Differential

Fast channel (max speed)

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-69 -67

-71 -67

-72 -71

-72 -71 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

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Table 81. ADC accuracy - limited test conditions 4 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

ADC clock frequency ≤

26 MHz,

1.65 V ≤ V

DDA

3.6 V,

= VREF+ ≤

Voltage scaling Range 2

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

1 1.5

1 1.2

2.5

2 2.5

Slow channel (max speed) 2 2.5

Fast channel (max speed) 10.2 10.5

Slow channel (max speed) 10.2 10.5

Fast channel (max speed) 10.6 10.7

Slow channel (max speed) 10.6 10.7

Fast channel (max speed) 63 65 -

Slow channel (max speed) 63 65

Fast channel (max speed) 65 66

Slow channel (max speed) 65 66

Fast channel (max speed) 64 65

Slow channel (max speed) 64 65

Fast channel (max speed) 66 67

Slow channel (max speed) 66 67

5 5.4

3.5

4.5

2 4

2 3.5

4 4.5

1 1.5

LSB bits dB

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Electrical characteristics STM32L486xx

Table 81. ADC accuracy - limited test conditions 4 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency

26 MHz,

1.65 V ≤ V

DDA

3.6 V,

≤

= VREF+ ≤

Voltage scaling Range 2

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-71 -69

-73 -72

-73 -72 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

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Figure 29. ADC accuracy characteristics

SSA

4095

4094

4093

E O

1 LSB

IDEAL

1 2 3 4 5 6 7

(2)

E D

(3)

(1)

E G

4093 4094 4095 4096

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

= total unajusted error : maximum deviation

between the actual and ideal transfer curves.

= offset error : maximum deviation

between the first actual transition and

the first ideal one.

= gain error : deviation between the last

ideal transition and the last actual one.

= differential linearity error : maximum

deviation between actual steps and the ideal ones.

= integral linearity error : maximum deviation

between any actual transition and the end point

correlation line.

DDA

MS19880V2

Figure 30. Typical connection diagram using the ADC

DDA

AIN

(1)

AINx

C parasitic

(2)

I lkg

(3)

Sample and hold ADC converter

ADC

12-bit converter

ADC

MS33900V5

1. Refer to Table 76: ADC characteristics

for the values of R

AIN

and C

ADC

2. C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

Table 70: I/O static characteristics for the value of the pad capacitance). A high

C parasitic

value will downgrade conversion accuracy. To remedy this, f

ADC

should be reduced.

3. Refer to Table 70: I/O static characteristics for the values of I

lkg

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 17: Power supply scheme

. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

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Electrical characteristics STM32L486xx

Symbol

DDA

REF+

Parameter

Table 82. DAC characteristics (1)

Analog supply voltage for

DAC ON

Conditions Min

DAC output buffer OFF (no resistive load on DAC1_OUTx pin or internal connection)

1.71

Other modes 1.80

Positive reference voltage

DAC output buffer OFF (no resistive load on DAC1_OUTx pin or internal connection)

1.71

Other modes 1.80

REF-

BON

BOFF

Negative reference voltage -

Resistive load

Output Impedance

Output impedance sample and hold mode, output buffer ON

Output impedance sample and hold mode, output buffer OFF

Capacitive load

DAC output buffer ON connected to V

SSA connected to V

DDA

DAC output buffer OFF

= 2.7 V

= 2.0 V

= 2.7 V

= 2.0 V

DAC output buffer ON

Sample and hold mode

DAC_OUT t

SETTLING t

WAKEUP

(2)

PSRR

Voltage on DAC1_OUTx output

DAC output buffer ON

DAC output buffer OFF

±0.5 LSB

Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes when

DAC1_OUTx reaches final value ±0.5LSB, ±1 LSB,

±2 LSB, ±4 LSB, ±8 LSB)

Normal mode

DAC output buffer ON

CL ≤ 50 pF,

RL ≥ 5 k Ω

±1 LSB

±2 LSB

±4 LSB

±8 LSB

Normal mode DAC output buffer

OFF, ±1LSB, CL = 10 pF

Wakeup time from off state

(setting the ENx bit in the

DAC Control register) until final value ±1 LSB

DDA

supply rejection ratio

Normal mode DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

Normal mode DAC output buffer

OFF, CL ≤ 10 pF

Normal mode DAC output buffer ON

CL ≤ 50 pF, RL = 5 k Ω , DC

0.2

9.6

Typ Max Unit

3.6

DDA

1.7

1.6

1.55

1.48

1.4

SSA

11.7

0.1

13.8

3.5

16.5

18.0

REF+

– 0.2

REF+

2.9

2.85

2.8

2.75

2 2.5

V k Ω k Ω k Ω k Ω pF

µF

µs

4.2

-80

7.5

-28

µs dB

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STM32L486xx Electrical characteristics

Symbol

W_to_W t

SAMP

I leak

CI int t

TRIM

V offset

DDA

(DAC)

Table 82. DAC characteristics (1) (continued)

Parameter Conditions Min

Minimal time between two consecutive writes into the

DAC_DORx register to guarantee a correct

DAC1_OUTx for a small variation of the input code

(1 LSB)

DAC_MCR:MODEx[2:0] =

000 or 001

DAC_MCR:MODEx[2:0] =

010 or 011

Sampling time in sample and hold mode (code transition between the lowest input code and the highest input code when

DAC1_OUTx reaches final value ±1LSB)

Output leakage current

CL ≤ 50 pF, RL ≥ 5 k Ω

CL ≤ 10 pF

DAC1_OUTx pin connected

DAC output buffer

ON, C

= 100 nF

DAC output buffer

OFF, C

= 100 nF

DAC1_OUTx pin not connected

(internal connection only)

DAC output buffer

OFF

Sample and hold mode,

DAC1_OUTx pin connected

Internal sample and hold capacitor

Middle code offset trim time DAC output buffer ON

Middle code offset for 1 trim code step

REF+

= 3.6 V

REF+

= 1.8 V

DAC output buffer ON

No load, middle code (0x800)

No load, worst code

(0xF1C)

DAC consumption from

DDA

DAC output buffer OFF

No load, middle code (0x800)

1.4

5.2

Sample and hold mode, C

100 nF

Typ

0.7

10.5

1500

750

315

450

Max

3.5

(3)

670

0.2

315 ₓ

Ton/(Ton

+Toff)

(4)

670 ₓ

Ton/(Ton

+Toff)

(4)

8.8

500

Unit

µs ms

µs nA pF

µs

µV

µA

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Electrical characteristics STM32L486xx

Symbol

DDV

(DAC)

Table 82. DAC characteristics (1) (continued)

Parameter Conditions Min

DAC output buffer ON

DAC output buffer OFF

No load, middle code (0x800)

No load, worst code

(0xF1C)

No load, middle code (0x800)

DAC consumption from

REF+

Sample and hold mode, buffer ON,

= 100 nF, worst case

Typ

185

340

155

Max

240

400

205

185 ₓ

Ton/(Ton

+Toff)

(4)

400 ₓ

Ton/(Ton

+Toff)

(4)

Unit

µA

Sample and hold mode, buffer OFF,

= 100 nF, worst case

155 ₓ

Ton/(Ton

+Toff)

(4)

205 ₓ

Ton/(Ton

+Toff)

(4)

1. Guaranteed by design.

2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

3. Refer to Table 70: I/O static characteristics .

4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0351 reference manual for more details.

Figure 31. 12-bit buffered / non-buffered DAC

Buffered/non-buffered DAC

Buffer

(1)

LOAD

12-bit digital to analog converter

DACx_OUT

LOAD ai17157d

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the

DAC_CR register.

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STM32L486xx

Symbol

DNL

INL

Parameter

Table 83. DAC accuracy (1)

Conditions

Differential non linearity

(2) monotonicity

Integral non linearity

(3)

DAC output buffer ON

DAC output buffer OFF

10 bits

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

DAC output buffer OFF

CL ≤ 50 pF, no RL

Offset

Offset1

Offset error at code 0x800

(3)

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

Offset error at code 0x001

(4)

DAC output buffer OFF

CL ≤ 50 pF, no RL

DAC output buffer OFF

CL ≤ 50 pF, no RL

REF+

= 3.6 V

= 1.8 V

OffsetCal

Gain

TUE

TUECal

SNR

THD

Offset Error at code 0x800 after calibration

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

REF+

= 3.6 V

REF+

= 1.8 V

Gain error

Total unadjusted error

(5)

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

DAC output buffer OFF

CL ≤ 50 pF, no RL

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

DAC output buffer OFF

CL ≤ 50 pF, no RL

Total unadjusted error after calibration

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

Signal-to-noise ratio

Total harmonic distortion

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

1 kHz, BW 500 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

BW 500 kHz

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω , 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

Electrical characteristics

Min

Typ

guaranteed

Max

±2

±4

±5

±7

±0.5

±30

±12

±25

±8

±5

Unit

LSB

71.2

71.6

-78

-79

±23 LSB

dB dB

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Electrical characteristics STM32L486xx

Symbol Parameter

Table 83. DAC accuracy (1) (continued)

Conditions Min Typ Max Unit

SINAD

ENOB

Signal-to-noise and distortion ratio

Effective number of bits

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω , 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω , 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

70.4

11.4

11.5

dB bits

1. Guaranteed by design.

2. Difference between two consecutive codes - 1 LSB.

3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.

4. Difference between the value measured at Code (0x001) and the ideal value.

5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (V

REF+

– 0.2) V when buffer is ON.

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STM32L486xx Electrical characteristics

Symbol

DDA

REFBUF_

OUT

TRIM

CL esr

I load

I line_reg

I load_reg

Parameter

Table 84. VREFBUF characteristics (1)

Conditions

Analog supply voltage

Voltage reference output

Normal mode

Degraded mode

(2)

Normal mode

Degraded mode

(2)

= 0

= 1

= 0

= 1

= 0

= 1

= 0

= 1

Trim step resolution

Load capacitor

Equivalent

Serial Resistor of Cload

Static load current

Line regulation 2.8 V ≤ V

DDA

≤ 3.6 V

I load

= 500 µA

I load

= 4 mA

Load regulation

500 μ A ≤ I load

≤ 4 mA Normal mode

Min

0.5

2.4

2.8

1.65

2.046

(3)

2.498

(3)

DDA

-150 mV

DDA

-150 mV

200

100

Typ Max

3.6

2.4

2.8

2.048

2.5

DDA

±0.05

±0.1

1 1.5

Coeff

PSRR t

START

INRUSH

Temperature coefficient

-40 °C < TJ < +125 °C

0 °C < TJ < +50 °C

Power supply rejection

Start-up time

100 kHz

CL = 0.5 µF

(4)

CL = 1.1 µF

(4)

CL = 1.5 µF

(4)

Control of maximum DC current drive on VREFBUF_

OUT during start-up phase

(5)

300

500

650

µF

4 mA

1000

500

500 ppm/V ppm/mA

T coeff_ vrefint +

T coeff_ vrefint

350

650

800 ppm/ °C dB

µs

Unit

Ω mA

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Electrical characteristics STM32L486xx

Symbol Parameter

Table 84. VREFBUF characteristics (1) (continued)

Conditions Min Typ Max Unit

DDA

(VREF

BUF)

VREFBUF consumption from V

DDA

I load

= 0 µA

I load

= 500 µA

I load

= 4 mA -

µA

1. Guaranteed by design, unless otherwise specified.

2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (V drop voltage).

DDA

3. Guaranteed by test in production.

4. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise.

5. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the V the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for V

= 0 and V

= 1.

DDA

voltage should be in

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STM32L486xx Electrical characteristics

Symbol Parameter

Table 85. COMP characteristics (1)

Conditions

DDA

Analog supply voltage

Comparator input voltage range

Scaler input voltage

(2)

Scaler offset voltage

BRG_EN=0 (bridge disable)

DDA

(SCALER)

Scaler static consumption from V

DDA t

START_SCALER

Scaler startup time t

START

V t

(3) offset

BRG_EN=1 (bridge enable)

Comparator startup time to reach propagation delay specification

High-speed mode

DDA

≥ 2.7 V

DDA

< 2.7 V

Medium mode

DDA

≥ 2.7 V

DDA

< 2.7 V

Ultra-low-power mode

Propagation delay for

200 mV step with 100 mV overdrive

Comparator offset error

High-speed mode

DDA

≥ 2.7 V

DDA

< 2.7 V

DDA

≥ 2.7 V

Medium mode

DDA

< 2.7 V

Ultra-low-power mode

Full common mode range

V hys

Comparator hysteresis

No hysteresis

Low hysteresis

Medium hysteresis

High hysteresis -

Min Typ Max Unit

1.62

3.6

V 0 V

DDA

0.55

0.65

0.8

100

REFINT

±5

200

±10

300

200

100

0.9

±5 ±20

µs ns

µs mV mV nA

µA

µs

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Electrical characteristics STM32L486xx

Symbol

DDA

(COMP)

Table 85. COMP characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit

400 600

Ultra-lowpower mode

Comparator consumption from V

DDA

Medium mode

High-speed mode

Static -

With 50 kHz

±100 mV overdrive square signal

Static -

With 50 kHz

±100 mV overdrive square signal

Static -

With 50 kHz

±100 mV overdrive square signal

1200

100 nA

µA

I bias

Comparator input bias current

1. Guaranteed by design, unless otherwise specified.

2. Refer to Table 26: Embedded internal voltage reference

3. Guaranteed by characterization results.

4. Mostly I/O leakage when used in analog mode. Refer to I lkg

parameter in Table 70: I/O static characteristics .

(4) nA

Symbol

DDA

CMIR

OFFSET

∆ VI

OFFSET

Parameter

Table 86. OPAMP characteristics (1)

Conditions

Analog supply voltage

(2)

Common mode input range

Input offset voltage

Input offset voltage drift

25 °C, No Load on output.

All voltage/Temp.

Normal mode

Low-power mode

TRIMOFFSETP

TRIMLPOFFSETP

TRIMOFFSETN

TRIMLPOFFSETN

Offset trim step at low common input voltage

(0.1 ₓ V

DDA

)

Offset trim step at high common input voltage

(0.9 ₓ V

DDA

)

Min

1.8

Typ

Max

3.6

Unit

±5

±10

DDA

±1.5

±3

V mV

μ V/°C

0.8

1.1

1.35

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DS10199 Rev 7

STM32L486xx

Symbol

LOAD

LOAD_PGA

LOAD

LOAD_PGA

LOAD

CMRR

PSRR

GBW

(3)

OHSAT

(3)

OLSAT

(3)

φ m

Electrical characteristics

Table 86. OPAMP characteristics (1) (continued)

Parameter Conditions Min

Drive current

Drive current in

PGA mode

Normal mode

Low-power mode

Normal mode

Low-power mode

DDA

≥ 2 V

DDA

≥ 2 V

Resistive load

(connected to

VSSA or to

VDDA)

Normal mode

Low-power mode

DDA

< 2 V

Typ

Max

500

100

450

Unit

µA

Resistive load in PGA mode

(connected to

VSSA or to

DDA

)

Capacitive load

Power supply rejection ratio

Low saturation voltage

Phase margin

Normal mode

Low-power mode

Common mode rejection ratio

Normal mode

Low-power mode

Normal mode

Low-power mode

Normal mode

Gain Bandwidth

Product

Low-power mode

Normal mode

Low-power mode

Slew rate

(from 10 and

90% of output voltage)

Open loop gain

Normal mode

Low-power mode

Normal mode

Low-power mode

Normal mode

Low-power mode

High saturation voltage

Normal mode

Low-power mode

Normal mode

Low-power mode

Normal mode

Low-power mode

DDA

< 2 V

4.5

40 -

-85

-90

LOAD

≤ 50 pf,

≥ 4 k Ω DC

LOAD

≤ 50 pf,

≥ 20 k Ω DC

DDA

≥ 2.4 V

(OPA_RANGE = 1)

DDA

< 2.4 V

(OPA_RANGE = 0)

≥ 2.4 V

< 2.4 V

I load

= max or R load min Input at V

DDA

100

DDA

load

= max or R load min Input at 0.

90 -

550 1600 2200

100 420 600

250

700

180

950

280

700

180

300

80 -

110

110 -

100

k Ω pF dB dB kHz

V/ms dB mV

DS10199 Rev 7

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Electrical characteristics STM32L486xx

Symbol

GM t

WAKEUP

I bias

PGA gain

(3)

Table 86. OPAMP characteristics (1) (continued)

Parameter Conditions Min

Gain margin

Wake up time from OFF state.

OPAMP input bias current

Normal mode

Low-power mode

Normal mode

Low-power mode

LOAD

≤

≥ follower

50 pf,

4 k Ω configuration

LOAD

≤

≥ follower

50 pf,

20 k Ω configuration

Dedicated input

(UFBGA132 only)

≤ 75 °C

≤ 85 °C

≤ 105 °C

≤ 125 °C

General purpose input (all packages except UFBGA132)

Non inverting gain value

PGA Gain = 2

R network

R2/R1 internal resistance values in PGA mode

(5)

PGA Gain = 4

PGA Gain = 8

PGA Gain = 16

Delta R

Resistance variation (R1 or

R2)

PGA gain error PGA gain error

Gain = 2

-15

-1

PGA BW

PGA bandwidth for different non inverting gain

Gain = 4

Gain = 8

Gain = 16 -

Typ

GBW/

80/80

120/

140/

150/

Max

(4)

Unit dB

µs nA

k Ω /k Ω

MHz

194/259

DS10199 Rev 7

STM32L486xx Electrical characteristics

Symbol

Table 86. OPAMP characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit en

Voltage noise density

Normal mode

Low-power mode

Normal mode

Low-power mode at 1 kHz, Output loaded with 4 k Ω at 1 kHz, Output loaded with 20 k Ω at 10 kHz, Output loaded with 4 k Ω at 10 kHz, Output loaded with 20 k Ω

500

600

180

290 -

nV/ √

DDA

(OPAMP)

(3)

OPAMP consumption from V

DDA

Normal mode

Low-power mode no Load, quiescent mode

120

260

100

1. Guaranteed by design, unless otherwise specified.

2. The temperature range is limited to 0 °C-125 °C when V

DDA

is below 2 V

3. Guaranteed by characterization results.

4. Mostly I/O leakage, when used in analog mode. Refer to I lkg

parameter in

Table 70: I/O static characteristics

5. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between

OPAMP inverting input and ground. The PGA gain =1+R2/R1

µA

DS10199 Rev 7

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Electrical characteristics STM32L486xx

6.3.23 Temperature sensor characteristics

Symbol

(1)

Avg_Slope

(2)

30 t

START

(TS_BUF)

(1)

START

(1)

Average slope

Voltage at 30°C (±5 °C)

Table 87. TS characteristics

Parameter

linearity with temperature

(3)

Sensor Buffer Start-up time in continuous mode

Start-up time when entering in continuous mode

(4)

Min

2.3

0.742

Typ

±1

2.5

0.76

Max

±2

2.7

0.785

120

Unit

°C mV/°C

µs

µs t

S_temp

(1)

ADC sampling time when reading the temperature 5 µs

(TS) (1)

Temperature sensor consumption from V

DD selected by ADC

, when

4.7

7 µA

1. Guaranteed by design.

2. Guaranteed by characterization results.

3. Measured at V = 3.0 V ±10 mV. The V

Temperature sensor calibration values

ADC conversion result is stored in the TS_CAL1 byte. Refer to

Table 8:

4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

6.3.24 V

BAT monitoring characteristics

Symbol

Table 88. V

BAT

monitoring characteristics

Parameter

(1)

Resistor bridge for V

BAT

Ratio on V

BAT

measurement

Error on Q t

S_vbat

(1)

ADC sampling time when reading the VBAT

1. Guaranteed by design.

Min

-10

Typ

Symbol

Table 89. V

BAT

charging characteristics

Parameter Conditions Min Typ

Battery charging resistor

VBRS = 0

VBRS = 1 -

1.5

Max

Unit k Ω

µs

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DS10199 Rev 7

STM32L486xx Electrical characteristics

Symbol

LCD

LCD0

LCD1

LCD2

LCD3

LCD4

LCD5

LCD6

LCD7

C ext

LCD

(2)

VLCD

The devices embed a built-in step-up converter to provide a constant LCD reference voltage independently from the V

voltage. An external capacitor C ext

must be connected to the

VLCD pin to decouple this converter.

Table 90. LCD controller characteristics

(1)

Parameter Conditions Min Typ Max Unit

LCD external voltage

LCD internal reference voltage 0

LCD internal reference voltage 1

LCD internal reference voltage 2

LCD internal reference voltage 3

LCD internal reference voltage 4

LCD internal reference voltage 5

LCD internal reference voltage 6

LCD internal reference voltage 7

LCD

external capacitance

Buffer OFF

(BUFEN=0 is LCD_CR register)

Buffer ON

(BUFEN=1 is LCD_CR register)

Supply current from V

= 2.2 V

Supply current from V

= 3.0 V

Buffer OFF

(BUFEN=0 is LCD_CR register)

Buffer OFF

(BUFEN=0 is LCD_CR register)

Buffer OFF

(BUFFEN = 0, PON = 0)

Supply current from V

LCD

= 3 V)

LCD

Buffer ON

(BUFFEN = 1, 1/2 Bias)

Buffer ON

(BUFFEN = 1, 1/3 Bias)

Buffer ON

(BUFFEN = 1, 1/4 Bias)

Total High Resistor value for Low drive resistive network

Total Low Resistor value for High drive resistive network

Segment/Common highest level voltage

Segment/Common 3/4 level voltage

Segment/Common 2/3 level voltage

Segment/Common 1/2 level voltage

Segment/Common 1/3 level voltage

Segment/Common 1/4 level voltage

Segment/Common lowest level voltage

0.2

1.5

0.5

0.6

0.8

5.5

240

LCD

3/4 V

LCD

2/3 V

LCD

1/2 V

LCD

1/3 V

LCD

1/4 V

LCD

2.62

2.76

2.89

3.04

3.19

3.32

3.46

3.62

3.6

μ F

μ A

M Ω k Ω

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Electrical characteristics STM32L486xx

1. Guaranteed by design.

2. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD connected.

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STM32L486xx Electrical characteristics

Unless otherwise specified, the parameters given in

Table 91

for DFSDM are derived from tests performed under the ambient temperature, f

APB2

frequency and V

conditions summarized in Table 23: General operating conditions

supply voltage

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5 ₓ V

Refer to Section 6.3.14: I/O port characteristics

for more details on the input/output alternate function characteristics (DFSDM1_CKINy, DFSDM1_DATINy, DFSDM1_CKOUT for

DFSDM).

Symbol Parameter

Table 91. DFSDM characteristics (1)

Conditions Min Typ f

DFSDMCLK f

CKIN

(1/T

CKIN

) f

CKOUT

DuCy

CKOUT t wh(CKIN) t wl(CKIN) t su t h

Manchester

DFSDM clock

Input clock frequency

SPI mode (SITP[1:0] = 01)

Output clock frequency

Output clock frequency duty cycle

Input clock high and low time

Data input setup time

Data input hold time

Manchester data period

(recovered clock period)

SPI mode (SITP[1:0] = 01),

External clock mode

(SPICKSEL[1:0] = 0)

SPI mode (SITP[1:0]=01),

External clock mode

(SPICKSEL[1:0] = 0)

SPI mode (SITP[1:0]=01),

External clock mode

(SPICKSEL[1:0] = 0)

Manchester mode (SITP[1:0]

= 10 or 11),

Internal clock mode

(SPICKSEL[1:0] ≠ 0)

CKIN

/2-0.5

CKIN

(CKOUT

DIV+1) ₓ

DFSDMCLK

1. Guaranteed by characterization results.

Max f

SYSCLK

DFSDMCLK

/4)

(2 ₓ CKOUTDIV) ₓ T

DFSDMCLK

Unit

MHz

% ns

DS10199 Rev 7

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232

Electrical characteristics

Figure 16: DFSDM timing diagram

63,&.6(/

6,73

63,&.6(/

6,73

5HFRYHUHGFORFN

5HFRYHUHGGDWD

STM32L486xx

06Y9

The parameters given in the following tables are guaranteed by design.

Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

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Symbol

Table 92. TIMx (1) characteristics

Parameter Conditions Min Max Unit t res(TIM)

Timer resolution time

TIMxCLK

= 80 MHz

12.5

TIMxCLK ns f

EXT

Res

TIM

Timer external clock frequency on CH1 to CH4

Timer resolution f

TIMxCLK

= 80 MHz

TIMx (except TIM2 and TIM5)

TIMxCLK

/2 MHz

MHz bit

TIM2 and TIM5 32 t

COUNTER

16-bit counter clock period

1 f

TIMxCLK

= 80 MHz 0.0125

MAX_COUNT

Maximum possible count with 32-bit counter f

TIMxCLK

= 80 MHz -

1. TIMx

, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.

65536

819.2

TIMxCLK

µs

65536 × 65536 t

TIMxCLK

53.68

Table 93. IWDG min/max timeout period at 32 kHz (LSI) (1)

Prescaler divider PR[2:0] bits

Min timeout RL[11:0]=

0x000

Max timeout RL[11:0]=

0xFFF

Unit

/16

/32

/64

/128

/256

6 or 7

0.125

0.250

0.500

1.0

2.0

4.0

8.0

512

1024

2048

4096

8192

16384

32768 ms

1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.

Prescaler

Table 94. WWDG min/max timeout value at 80 MHz (PCLK)

WDGTB Min timeout value Max timeout value

0.0512

0.1024

0.2048

0.4096

3.2768

6.5536

13.1072

26.2144

Unit ms

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6.3.28 Communication interfaces characteristics

I

C interface characteristics

The I2C interface meets the timings requirements of the I 2 C-bus specification and user manual rev. 03 for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s

• Fast-mode (Fm): with a bit rate up to 400 kbit/s

• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0351 reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and

SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V

DDIOx

is disabled, but is still present. Only FT_f I/O pins support Fm+ low level output current maximum requirement. Refer to

Section 6.3.14: I/O port characteristics for the I2C I/Os characteristics.

All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics:

Symbol

Table 95. I2C analog filter characteristics

(1)

Parameter t

Maximum pulse width of spikes that are suppressed by the analog filter

1. Guaranteed by design.

2. Spikes with widths below t

AF(min) are filtered.

3. Spikes with widths above t

AF(max)

are not filtered

Min

(2)

Max

260

(3)

Unit ns

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SPI characteristics

Unless otherwise specified, the parameters given in

Table 96

for SPI are derived from tests performed under the ambient temperature, f

PCLKx frequency and supply voltage conditions summarized in

Table 23: General operating conditions .

• Output speed is set to OSPEEDRy[1:0] = 11

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5 ₓ V

Refer to Section 6.3.14: I/O port characteristics

for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI).

Symbol Parameter

Table 96. SPI characteristics

(1)

Conditions

1/t

SCK c(SCK)

SPI clock frequency

Master mode receiver/full duplex

2.7 < V

< 3.6 V

Voltage Range 1

Master mode receiver/full duplex

1.71 < V

< 3.6 V

Voltage Range 1

Master mode transmitter

1.71 < V

< 3.6 V

Voltage Range 1

Slave mode receiver

1.71 < V

< 3.6 V

Voltage Range 1

Slave mode transmitter/full duplex

2.7 < V

< 3.6 V

Voltage Range 1

Slave mode transmitter/full duplex

1.71 < V

< 3.6 V

Voltage Range 1 t su(NSS) t h(NSS) t w(SCKH) t w(SCKL) t su(MI) t su(SI) t h(MI) t h(SI) t a(SO) t dis(SO)

NSS setup time

NSS hold time

Voltage Range 2

1.08 < V

DDIO2

< 1.32 V

(3)

Slave mode, SPI prescaler = 2

SCK high and low time Master mode

Data input setup time

Data input hold time

Master mode

Slave mode

Master mode

Slave mode

Data output access time Slave mode

Data output disable time Slave mode

Min

4 ₓ T

PCLK

2 ₓ T

PCLK

3.5

6.5

Typ

PCLK

-2 T

PCLK

Max

(2)

Unit

MHz ns ns

PCLK

+2 ns

ns ns ns ns

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Symbol Parameter

Table 96. SPI characteristics (1) (continued)

Conditions Min Typ Max Unit

Slave mode 2.7 < V

Voltage Range 1

< 3.6 V

12.5

19 t v(SO)

Slave mode 1.71 < V

Voltage Range 1

< 3.6 V

12.5

Data output valid time

Slave mode 1.71 < V

Voltage Range 2

< 3.6 V

12.5

33 ns t

t v(MO) h(SO)

Data output hold time

Slave mode 1.08 < V

DDIO2

< 1.32 V

(3)

Master mode

Slave mode

Slave mode 1.08 < V

DDIO2

< 1.32 V

(3)

Master mode

2.5

62.5

12.5

ns t h(MO)

0 -

1. Guaranteed by characterization results.

2. Maximum frequency in Slave transmitter mode is determined by the sum of t having t su(MI)

= 0 while Duty(SCK) = 50 %.

v(SO)

and t su(MI)

which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master

3. SPI mapped on Port G.

Figure 32. SPI timing diagram - slave mode and CPHA = 0

NSS input t su(NSS) t w(SCKH) t c(SCK) t r(SCK) t h(NSS)

CPHA=0

CPOL=0

CPHA=0

CPOL=1 t a(SO)

MISO output t w(SCKL)

First bit OUT t h(SI) t v(SO) t h(SO)

Next bits OUT t f(SCK)

Last bit OUT t dis(SO) t su(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V1

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Figure 33. SPI timing diagram - slave mode and CPHA = 1

NSS input t w(SCKH) t c(SCK)

CPHA=1

CPOL=0

CPHA=1

CPOL=1 t su(NSS) t a(SO)

MISO output t w(SCKL) t v(SO) t su(SI)

First bit OUT t h(SI)

First bit IN t h(SO)

Next bits OUT

MOSI input Next bits IN

1. Measurement points are done at CMOS levels: 0.3 V

and 0.7 V

Figure 34. SPI timing diagram - master mode

High

NSS input tc(SCK)

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1 t f(SCK) t h(NSS) t r(SCK) t dis(SO)

Last bit OUT

Last bit IN

MSv41659V1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTPUT tsu(MI) tw(SCKH) tw(SCKL)

MSB IN th(MI)

MSB OUT tv(MO)

BIT6 IN

B I T1 OUT th(MO)

1. Measurement points are done at CMOS levels: 0.3 V

and 0.7 V

tr(SCK) tf(SCK)

LSB IN

LSB OUT ai14136c

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Quad SPI characteristics

Unless otherwise specified, the parameters given in

Table 97

and Table 98 for Quad SPI

are derived from tests performed under the ambient temperature, f

AHB

frequency and V

supply voltage conditions summarized in Table 23: General operating conditions

, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11

• Capacitive load C = 15 or 20 pF

• Measurement points are done at CMOS levels: 0.5 ₓ V

Refer to Section 6.3.14: I/O port characteristics

for more details on the input/output alternate function characteristics.

Symbol

1/t

(CK) t w(CKH) t w(CKL) t s(IN) t h(IN) t v(OUT) t h(OUT)

Table 97. Quad SPI characteristics in SDR mode (1)

Parameter Conditions Min

Quad SPI clock frequency

1.71 < V

< 3.6 V, C

LOAD

= 20 pF

Voltage Range 1

1.71 < V

< 3.6 V, C

LOAD

= 15 pF

Voltage Range 1

2.7 < V

< 3.6 V, C

LOAD

= 15 pF

Voltage Range 1

1.71 < V

< 3.6 V C

LOAD

= 20 pF

Voltage Range 2

Quad SPI clock high and low time

Data input setup time

Data input hold time

Data output valid time

Data output hold time f

AHBCLK

= 48 MHz, presc=0

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2

6.5

1.5

2 t

(CK)

/2-2 t

(CK)

3.5

5.5

1. Guaranteed by characterization results.

Typ

2.5

Max

(CK)

/2 t

(CK)

/2+2

Unit

MHz ns

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Symbol

Table 98. QUADSPI characteristics in DDR mode (1)

Parameter Conditions

1/t

(CK)

Quad SPI clock frequency

1.71 < V

< 3.6 V, C

LOAD

= 20 pF

Voltage Range 1

2 < V

< 3.6 V, C

LOAD

Voltage Range 1

= 20 pF

1.71 < V

< 3.6 V, C

LOAD

= 15 pF

Voltage Range 1

1.71 < V

< 3.6 V C

Voltage Range 2

LOAD

= 20 pF t t t t t w(CKH) t w(CKL) sf(IN) hf(IN) vf(OUT) hf(OUT)

; t

; t sr(IN) hr(IN) vr(OUT) hr(OUT)

Quad SPI clock high and low time f

AHBCLK

= 48 MHz, presc=0

Data input setup time

Data input hold time

Voltage Range 1 and 2

Data output valid time

Voltage Range 1

Data output hold time

Voltage Range 2

Voltage Range 1

Voltage Range 2

1. Guaranteed by characterization results.

Min

Typ

Max

26 t

(CK)

/2-2 t

(CK)

/2 t

(CK)

/2+2

3.5

6.5

Unit

MHz ns t r(CK)

Figure 35. Quad SPI timing diagram - SDR mode t

(CK) t w(CKH) t w(CKL) t f(CK)

Clock

Data output

Data input t v(OUT) t h(OUT)

D0 t s(IN)

D1 t h(IN)

D1 D0 t r(CK)

Figure 36. Quad SPI timing diagram - DDR mode t

(CK) t w(CKH) t w(CKL)

D2 t f(CK)

MSv36878V1

Clock

Data output

Data input t vf(OUT) t hr(OUT)

D0 t vr(OUT)

D1 t sf(IN) t hf(IN)

D1 D2

D3 t hf(OUT)

D4 t sr(IN) t hr(IN)

D4 D5

MSv36879V1

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SAI characteristics

Unless otherwise specified, the parameters given in

Table 99

for SAI are derived from tests performed under the ambient temperature, f

PCLKx

frequency and V

DD supply voltage conditions summarized in

Table 23: General operating conditions , with

the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5 ₓ V

Refer to Section 6.3.14: I/O port characteristics

for more details on the input/output alternate function characteristics (CK,SD,FS).

Symbol

Table 99. SAI characteristics (1)

Parameter Conditions Max Unit f

MCLK

SAI Main clock output t f

CK v(FS) t h(FS) t su(FS) t h(FS) t su(SD_A_MR) t su(SD_B_SR) t h(SD_A_MR) t h(SD_B_SR)

SAI clock frequency

(2)

FS valid time

FS hold time

FS setup time

FS hold time

Data input setup time

Data input hold time

Master transmitter

2.7 ≤ V

≤ 3.6

Voltage Range 1

Master transmitter

1.71 ≤ V

≤ 3.6

Voltage Range 1

Master receiver

Voltage Range 1

Slave transmitter

2.7 ≤ V

≤ 3.6

Voltage Range 1

Slave transmitter

1.71 ≤ V

≤ 3.6

Voltage Range 1

Slave receiver

Voltage Range 1

Voltage Range 2

Master mode

2.7 ≤ V

≤ 3.6

Master mode

1.71 ≤ V

≤ 3.6

Master mode

Slave mode

Master receiver

Slave receiver

Master receiver

Slave receiver

2.5

50 MHz

18.5

12.5

22.5

14.5

12.5

MHz ns ns ns ns ns ns

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Symbol

Table 99. SAI characteristics (1) (continued)

Parameter Conditions Max Unit t v(SD_B_ST)

Data output valid time

Slave transmitter (after enable edge)

2.7 ≤ V

≤ 3.6

Slave transmitter (after enable edge)

1.71 ≤ V

≤ 3.6

Data output hold time Slave transmitter (after enable edge) t h(SD_B_ST) t v(SD_A_MT)

Data output valid time

Master transmitter (after enable edge)

2.7 ≤ V

≤ 3.6

Master transmitter (after enable edge)

1.71 ≤ V

≤ 3.6

Data output hold time Master transmitter (after enable edge) t h(SD_A_MT)

1. Guaranteed by characterization results.

2. APB clock frequency must be at least twice SAI clock frequency.

ns ns ns ns

Figure 37. SAI master timing waveforms

1/fSCK

SAI_SCK_X th(FS)

SAI_FS_X

(output)

SAI_SD_X

(transmit) tv(FS)

SAI_SD_X

(receive) tsu(SD_MR) tv(SD_MT)

Slot n th(SD_MR)

Slot n+2

Slot n th(SD_MT)

MS32771V1

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Figure 38. SAI slave timing waveforms

1/fSCK

SAI_SCK_X tw(CKH_X) tw(CKL_X) th(FS)

SAI_FS_X

(input)

SAI_SD_X

(transmit) tsu(FS) tsu(SD_SR) tv(SD_ST)

Slot n th(SD_SR)

Slot n

Slot n+2 th(SD_ST)

SAI_SD_X

(receive)

MS32772V1

SDMMC characteristics

Unless otherwise specified, the parameters given in

Table 100 for SDIO are derived from

tests performed under the ambient temperature, f

PCLKx

frequency and V

supply voltage

conditions summarized in Table 23: General operating conditions

, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5 ₓ V

Refer to Section 6.3.14: I/O port characteristics

for more details on the input/output characteristics.

Symbol

Table 100. SD / MMC dynamic characteristics, V

=2.7 V to 3.6 V (1)

Parameter Conditions Min Typ Max Unit f

Clock frequency in data transfer mode

SDIO_CK/fPCLK2 frequency ratio -

W(CKL) t

W(CKH)

Clock low time

Clock high time f f

= 50 MHz

CMD, D inputs (referenced to CK) in MMC and SD HS mode

8 t

ISU

Input setup time HS f

= 50 MHz 2 t

Input hold time HS f

= 50 MHz

CMD, D outputs (referenced to CK) in MMC and SD HS mode

4.5

OV t

Output valid time HS

Output hold time HS

CMD, D inputs (referenced to CK) in SD default mode f

= 50 MHz f

= 50 MHz 9 t

ISUD t

IHD

Input setup time SD

Input hold time SD f

= 50 MHz 2 f

= 50 MHz 4.5

50 MHz

4/3 ns ns

ns ns ns ns ns ns

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Table 100. SD / MMC dynamic characteristics, V

=2.7 V to 3.6 V (1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

CMD, D outputs (referenced to CK) in SD default mode t

OVD t

OHD

Output valid default time SD

Output hold default time SD

1. Guaranteed by characterization results.

= 50 MHz f

= 50 MHz 0

4.5

ns ns

Table 101. eMMC dynamic characteristics, V

= 1.71 V to 1.9 V (1)(2)

Symbol Parameter Conditions Min Typ Max Unit f

W(CKL)

Clock frequency in data transfer mode

SDIO_CK/f

PCLK2

frequency ratio

Clock low time t

W(CKH)

Clock high time

CMD, D inputs (referenced to CK) in eMMC mode t

ISU t

Input setup time HS

Input hold time HS

CMD, D outputs (referenced to CK) in eMMC mode t

OV t

Output valid time HS

Output hold time HS

1. Guaranteed by characterization results.

2. C

LOAD

= 20pF.

= 50 MHz f

= 50 MHz

50 MHz

4/3

ns ns

13.5

15.5

ns ns ns ns

Figure 39. SDIO high-speed mode

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Figure 40. SD default mode

D, CMD

(output) tOVD tOHD

Note: ai14888

USB OTG full speed (FS) characteristics

The STM32L486xx USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation).

Symbol

Table 102. USB OTG DC electrical characteristics

Parameter Conditions Min

(1)

Typ Max

(1)

Unit

DDUSB

(3)

USB OTG full speed transceiver operating voltage

Differential input sensitivity

Differential input common mode range

Single ended receiver input threshold

Static output level low

Over VCM range

Includes V

DI range

of 1.5

Ω to 3.6 V

of 15 k Ω to V

(4)

Static output level high

Pull down resistor on PA11,

PA12 (USB_FS_DP/DM)

Pull Up Resistor on PA12

(USB_FS_DP)

Pull Up Resistor on PA12

(USB_FS_DP)

Pull Up Resistor on PA10

(OTG_FS_ID)

= V

, during idle

= V

during reception

3.0

(2)

0.2

0.8

2.8

14.25

0.3

3.6

0.9

1.25

1.575

k Ω

1.425

2.25

3.09

3.6

2.5

2.0

24.8

14.5

1. All the voltages are measured from the local ground potential.

2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed electrical characteristics which are degraded in the 2.7-to-3.0 V V

voltage range.

3. Guaranteed by design.

4. R

is the load connected on the USB OTG full speed drivers.

V k Ω k Ω k Ω

When VBUS sensing feature is enabled, PA9 should be left at its default state (floating input), not as alternate function. A typical 200 µA current consumption of the sensing block

(current to voltage conversion to determine the different sessions) can be observed on PA9 when the feature is enabled.

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Figure 41. USB OTG timings – definition of data signal rise and fall time

Cross over points

Differential data lines

CRS

SS t f t r

Table 103. USB OTG electrical characteristics (1)

Driver characteristics

Symbol Parameter Conditions Min Max Unit t rLS t fLS t rfmLS t rFS t fFS t rfmFS

CRS

DRV

Rise time in LS

Fall time in LS

Rise time in FS

Fall time in FS

(2)

Rise/ fall time matching in LS

(2)

Rise/ fall time matching in FS

Output signal crossover voltage (LS/FS)

Output driver impedance

(3)

L t r

/t f f

= 200 to 600 pF

= 50 pF

Driving high or low

1.3

300

125

111

2.0

1. Guaranteed by design.

2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching impedance is included in the embedded driver.

ns ns

% ns ns

Ω ai14137b

Symbol

DD(USBBCD)

RDAT_LKG

VDAT_LKG

RDCP_DAT

VLGC_HI

VLGC_LOW

VLGC

Table 104. USB BCD DC electrical characteristics

(1)

Parameter Conditions Min.

Typ.

Max.

Unit

Primary detection mode consumption

Secondary detection mode consumption

Data line leakage resistance

Data line leakage voltage

Dedicated charging port resistance across D+/D-

Logic high

Logic low

Logic threshold -

300

0.0

2.0

0.8

300

3.6

200

3.6

0.8

2.0

μ k

Ω

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Electrical characteristics STM32L486xx

Symbol

VDAT_REF

VDP_SRC

VDM_SRC

IDP_SINK

IDM_SINK

Table 104. USB BCD DC electrical characteristics (1) (continued)

Parameter Conditions Min.

Typ.

Max.

Unit

Data detect voltage

D+ source voltage

D- source voltage

D+ sink current

D- sink current

1. Guaranteed by design.

0.25

0.5

25 -

0.4

0.7

175

μ A

CAN (controller area network) interface

Refer to Section 6.3.14: I/O port characteristics

for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX).

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Unless otherwise specified, the parameters given in

Table 105 to

Table 118

for the FMC interface are derived from tests performed under the ambient temperature, f

HCLK and V

frequency

supply voltage conditions summarized in

Table 23 , with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5V

Refer to Section 6.3.14: I/O port characteristics for more details on the input/output

characteristics.

Asynchronous waveforms and timings

Figure 42

through Figure 45 represent asynchronous waveforms and

Table 105

through

Table 112

provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration:

• AddressSetupTime = 0x1

• AddressHoldTime = 0x1

• DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)

• BusTurnAroundDuration = 0x0

In all timing tables, the THCLK is the HCLK clock period.

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Figure 42. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms t w(NE)

FMC_NE t v(NOE_NE) t w(NOE) t h(NE_NOE)

FMC_NOE

FMC_NWE

FMC_A[25:0] t v(A_NE) t v(BL_NE)

Address t h(A_NOE) t h(BL_NOE)

FMC_NBL[1:0] t h(Data_NE) t h(Data_NOE)

FMC_D[15:0] t su(Data_NOE) t su(Data_NE)

Data t v(NADV_NE) t w(NADV)

FMC_NADV (1)

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32753V1

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Table 105. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings (1)(2)

Symbol Parameter Min Max Unit t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t v(A_NE) t h(A_NOE) t v(BL_NE) t h(BL_NOE) t su(Data_NE) t su(Data_NOE) t h(Data_NOE) t h(Data_NE) t v(NADV_NE) t w(NADV)

FMC_NE low time

FMC_NEx low to FMC_NOE low

FMC_NOE low time

FMC_NOE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

Address hold time after FMC_NOE high

FMC_NEx low to FMC_BL valid

FMC_BL hold time after FMC_NOE high

Data to FMC_NEx high setup time

Data to FMC_NOEx high setup time

Data hold time after FMC_NOE high

Data hold time after FMC_NEx high

FMC_NEx low to FMC_NADV low

FMC_NADV low time

1. CL = 30 pF.

2. Guaranteed by characterization results.

HCLK

-0.5

HCLK

+0.5

0 1

HCLK

-0.5

HCLK

-1

HCLK

-0.5

3.5

HCLK

+0.5

Table 106. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings (1)(2)

Symbol Parameter Min Max Unit t w(NE)

FMC_NE low time t w(NOE) t w(NWAIT) t su(NWAIT_NE) t h(NE_NWAIT)

FMC_NWE low time

FMC_NWAIT low time

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

1. CL = 30 pF.

2. Guaranteed by characterization results.

HCLK

-0.5

HCLK

+0.5

HCLK

-0.5

HCLK

+0.5

HCLK

-0.5

HCLK

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Figure 43. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE)

FMC_NEx

FMC_NOE

FMC_NWE

FMC_A[25:0]

FMC_NBL[1:0]

FMC_D[15:0] tv(NWE_NE) tw(NWE) tv(A_NE) tv(BL_NE) tv(Data_NE) th(A_NWE)

Address th(BL_NWE)

NBL th(Data_NWE)

Data t v(NADV_NE) tw(NADV) t h(NE_NWE)

FMC_NADV (1)

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32754V1

Table 107. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings

(1)(2)

Symbol Parameter Min Max Unit t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t h(A_NWE) t v(BL_NE) t h(BL_NWE) t v(Data_NE) t h(Data_NWE) t v(NADV_NE) t w(NADV)

FMC_NE low time

FMC_NEx low to FMC_NWE low

FMC_NWE low time

FMC_NWE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

Address hold time after FMC_NWE high

FMC_NEx low to FMC_BL valid

FMC_BL hold time after FMC_NWE high

Data to FMC_NEx low to Data valid

Data hold time after FMC_NWE high

FMC_NEx low to FMC_NADV low

FMC_NADV low time

1. CL = 30 pF.

2. Guaranteed by characterization results.

HCLK

-1

HCLK

-0.5

HCLK

-1

HCLK

-0.5

HCLK

-1

HCLK

-0.5

HCLK

+1.5

HCLK

1.5

HCLK

+0.5 ns

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Table 108. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings (1)(2)

Symbol Parameter Min Max Unit t w(NE) t w(NWE) t su(NWAIT_NE) t h(NE_NWAIT)

FMC_NE low time

FMC_NWE low time

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

1. CL = 30 pF.

2. Guaranteed by characterization results.

HCLK

+0.5 8T

HCLK

+0.5

HCLK

-0.5

HCLK

+0.5

HCLK

+2 -

HCLK

+2 ns

Figure 44. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE)

FMC_ NE tv(NOE_NE) t h(NE_NOE)

FMC_NOE tw(NOE)

FMC_NWE tv(A_NE) th(A_NOE)

FMC_ A[25:16]

Address tv(BL_NE) th(BL_NOE)

FMC_ NBL[1:0] NBL th(Data_NE)

FMC_ AD[15:0] t v(NADV_NE) t v(A_NE)

Address th(AD_NADV) tw(NADV) tsu(Data_NE) tsu(Data_NOE)

Data th(Data_NOE)

FMC_NADV

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32755V1

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Table 109. Asynchronous multiplexed PSRAM/NOR read timings (1)(2)

Symbol Parameter Min Max t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t v(A_NE) t v(NADV_NE) t w(NADV)

FMC_NE low time

FMC_NEx low to FMC_NOE low

FMC_NOE low time

FMC_NOE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

FMC_NEx low to FMC_NADV low t h(AD_NADV)

FMC_NADV low time

FMC_AD(address) valid hold time after

FMC_NADV high t h(A_NOE) t h(BL_NOE) t v(BL_NE) t su(Data_NE) t su(Data_NOE) t h(Data_NE) t h(Data_NOE)

Address hold time after FMC_NOE high

FMC_BL time after FMC_NOE high

FMC_NEx low to FMC_BL valid

Data to FMC_NEx high setup time

Data to FMC_NOE high setup time

Data hold time after FMC_NEx high

Data hold time after FMC_NOE high

1. CL = 30 pF.

2. Guaranteed by characterization results.

HCLK

-0.5 3T

HCLK

-0.5

HCLK

+0.5

HCLK

+0.5

HCLK

-0.5

HCLK

-0.5

HCLK

-2

HCLK

-1

Unit ns

Table 110. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings (1)(2)

Symbol Parameter Min Max Unit t w(NE) t w(NOE) t su(NWAIT_NE)

FMC_NE low time

FMC_NWE low time

FMC_NWAIT valid before FMC_NEx high

HCLK

+2 8T

HCLK

-1 5T

HCLK

+1.5

HCLK

+1.5

t h(NE_NWAIT)

FMC_NEx hold time after FMC_NWAIT invalid 4T

HCLK

1. CL = 30 pF.

2. Guaranteed by characterization results.

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Figure 45. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE)

FMC_ NEx

FMC_NOE

FMC_NWE

FMC_ A[25:16]

FMC_ NBL[1:0]

FMC_ AD[15:0] t v(NADV_NE) tv(NWE_NE) tw(NWE) tv(A_NE) tv(BL_NE) t v(A_NE)

Address th(A_NWE)

Address th(BL_NWE)

NBL tv(Data_NADV)

Data th(AD_NADV) tw(NADV) t h(NE_NWE) th(Data_NWE)

FMC_NADV

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

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Table 111. Asynchronous multiplexed PSRAM/NOR write timings (1)(2)

Symbol Parameter Min Max t w(NE) t v(NWE_NE) t w(NWE)

FMC_NE low time

FMC_NEx low to FMC_NWE low

FMC_NWE low time t h(NE_NWE) t v(A_NE) t v(NADV_NE) t w(NADV)

FMC_NWE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

FMC_NEx low to FMC_NADV low t h(AD_NADV)

FMC_NADV low time

FMC_AD(adress) valid hold time after

FMC_NADV high t h(A_NWE) t h(BL_NWE) t v(BL_NE) t v(Data_NADV) t h(Data_NWE)

Address hold time after FMC_NWE high

FMC_BL hold time after FMC_NWE high

FMC_NEx low to FMC_BL valid

FMC_NADV high to Data valid

Data hold time after FMC_NWE high

1. CL = 30 pF.

2. Guaranteed by characterization results.

HCLK

-0.5

HCLK

-0.5

HCLK

2xT

HCLK

-1.5

2xT

HCLK

+1.

HCLK

-0.5

HCLK

-0.5

HCLK

-2

HCLK

-1

HCLK

+0.5

HCLK

+0.5

1.5

HCLK

Unit ns

Table 112. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings (1)(2)

Symbol Parameter Min Max Unit t w(NE)

FMC_NE low time t w(NWE)

FMC_NWE low time t su(NWAIT_NE) t h(NE_NWAIT)

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

1. CL = 30 pF.

2. Guaranteed by characterization results.

HCLK

-0.5

HCLK

-1.5

HCLK

+1.5

HCLK

-3

Synchronous waveforms and timings

Table 116

provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration:

• BurstAccessMode = FMC_BurstAccessMode_Enable

• MemoryType = FMC_MemoryType_CRAM

• WriteBurst = FMC_WriteBurst_Enable

• CLKDivision = 1

• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

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In all timing tables, the T

HCLK

is the HCLK clock period.

Figure 46. Synchronous multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK)

BUSTURN = 0

FMC_CLK

Data latency = 0 td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx t d(CLKL-NADVL)

FMC_NADV td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16] td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE td(CLKL-ADV)

FMC_AD[15:0] td(CLKL-ADIV) tsu(ADV-CLKH)

AD[15:0] tsu(NWAITV-CLKH)

D1 th(CLKH-ADV) tsu(ADV-CLKH)

D2 th(CLKH-NWAITV) th(CLKH-ADV)

FMC_NWAIT

(WAITCFG = 1b,

WAITPOL + 0b)

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) tsu(NWAITV-CLKH) tsu(NWAITV-CLKH) th(CLKH-NWAITV) th(CLKH-NWAITV)

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Table 113. Synchronous multiplexed NOR/PSRAM read timings (1)(2)

Symbol Parameter Min Max t w(CLK) t d(CLKL-NExL) t d(CLKH_NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NOEL) t d(CLKH-NOEH) t d(CLKL-ADV) t d(CLKL-ADIV) t su(ADV-CLKH) t h(CLKH-ADV) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NOE low

FMC_CLK high to FMC_NOE high

FMC_CLK low to FMC_AD[15:0] valid

FMC_CLK low to FMC_AD[15:0] invalid

FMC_A/D[15:0] valid data before FMC_CLK high

FMC_A/D[15:0] valid data after FMC_CLK high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. CL = 30 pF.

2. Guaranteed by characterization results.

HCLK

-1

HCLK

+0.5

HCLK

2.5

3.5

1.5

2.5

Unit ns

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Figure 47. Synchronous multiplexed PSRAM write timings t w(CLK) t w(CLK)

BUSTURN = 0

FMC_CLK t d(CLKL-NExL)

Data latency = 0 t d(CLKH-NExH)

FMC_NEx t d(CLKL-NADVL)

FMC_NADV t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV)

FMC_A[25:16] t d(CLKL-NWEL) t d(CLKH-NWEH)

FMC_NWE t d(CLKL-ADV)

FMC_AD[15:0] t d(CLKL-ADIV) t d(CLKL-Data)

AD[15:0] t d(CLKL-Data)

D1 D2

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b)

FMC_NBL t su(NWAITV-CLKH) t h(CLKH-NWAITV) t d(CLKH-NBLH)

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Symbol

Table 114. Synchronous multiplexed PSRAM write timings (1)(2)

Parameter Min Max Unit t w(CLK) t d(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NWEL) t d(CLKH-NWEH) t d(CLKL-ADV) t d(CLKL-ADIV) t d(CLKL-DATA) t d(CLKL-NBLL) t d(CLKH-NBLH) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NWE low

FMC_CLK high to FMC_NWE high

FMC_CLK low to FMC_AD[15:0] valid

FMC_CLK low to FMC_AD[15:0] invalid

FMC_A/D[15:0] valid data after FMC_CLK low

FMC_CLK low to FMC_NBL low

FMC_CLK high to FMC_NBL high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. CL = 30 pF.

2. Guaranteed by characterization results.

HCLK

-1

HCLK

+0.5

HCLK

4 ns

5.5

2.5

3.5

2.5

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Figure 48. Synchronous non-multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK)

FMC_CLK td(CLKL-NExL)

FMC_NEx td(CLKL-NADVL)

Data latency = 0 td(CLKL-NADVH) td(CLKH-NExH)

FMC_NADV td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0] td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE

FMC_D[15:0] tsu(DV-CLKH) tsu(NWAITV-CLKH)

D1 th(CLKH-DV) tsu(DV-CLKH)

D2 th(CLKH-NWAITV) th(CLKH-DV)

FMC_NWAIT

(WAITCFG = 1b,

WAITPOL + 0b)

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) tsu(NWAITV-CLKH) t h(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32759V1

Table 115. Synchronous non-multiplexed NOR/PSRAM read timings

(1)(2)

Symbol Parameter Min Max Unit t w(CLK) t d(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NOEL) t d(CLKH-NOEH) t su(DV-CLKH) t h(CLKH-DV) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NOE low

FMC_CLK high to FMC_NOE high

FMC_D[15:0] valid data before FMC_CLK high

FMC_D[15:0] valid data after FMC_CLK high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

HCLK

-0.5

0.5

HCLK

-0.5

3.5

2.5

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1. CL = 30 pF.

2. Guaranteed by characterization results.

Figure 49. Synchronous non-multiplexed PSRAM write timings t w(CLK) t w(CLK)

FMC_CLK t d(CLKL-NExL)

FMC_NEx

Data latency = 0 t d(CLKH-NExH) t d(CLKL-NADVL)

FMC_NADV t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV)

FMC_A[25:0] t d(CLKL-NWEL) t d(CLKH-NWEH)

FMC_NWE

FMC_D[15:0] t d(CLKL-Data)

D1 t d(CLKL-Data)

FMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

FMC_NBL t su(NWAITV-CLKH) t d(CLKH-NBLH) t h(CLKH-NWAITV)

MSv38002V1

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Table 116. Synchronous non-multiplexed PSRAM write timings (1)(2)

Symbol Parameter Min Max Unit t w(CLK) t d(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NWEL) t d(CLKH-NWEH) t d(CLKL-Data) t d(CLKL-NBLL) t d(CLKH-NBLH) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NWE low

FMC_CLK high to FMC_NWE high

FMC_D[15:0] valid data after FMC_CLK low

FMC_CLK low to FMC_NBL low

FMC_CLK high to FMC_NBL high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. CL = 30 pF.

2. Guaranteed by characterization results.

HCLK

-0.5

HCLK

+0.5

2.5

HCLK

-1

HCLK

-1

1.5

HCLK

4 ns

4.5

NAND controller waveforms and timings

Figure 50

through

Figure 53

represent synchronous waveforms, and

Table 117

and

Table 118

provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration:

• COM.FMC_SetupTime = 0x02

• COM.FMC_WaitSetupTime = 0x03

• COM.FMC_HoldSetupTime = 0x02

• COM.FMC_HiZSetupTime = 0x03

• ATT.FMC_SetupTime = 0x01

• ATT.FMC_WaitSetupTime = 0x03

• ATT.FMC_HoldSetupTime = 0x02

• ATT.FMC_HiZSetupTime = 0x03

• Bank = FMC_Bank_NAND

• MemoryDataWidth = FMC_MemoryDataWidth_16b

• ECC = FMC_ECC_Enable

• ECCPageSize = FMC_ECCPageSize_512Bytes

• TCLRSetupTime = 0

• TARSetupTime = 0

In all timing tables, the T

HCLK

is the HCLK clock period.

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Electrical characteristics

Figure 50. NAND controller waveforms for read access

FMC_NCEx

STM32L486xx

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NWE t d(NCE-NOE) t h(NOE-ALE)

FMC_NOE (NRE) t su(D-NOE) t h(NOE-D)

FMC_D[15:0]

MSv38003V1

FMC_NCEx

Figure 51. NAND controller waveforms for write access

ALE (FMC_A17)

CLE (FMC_A16) t d(NCE-NWE)

FMC_NWE t h(NWE-ALE)

FMC_NOE (NRE) t v(NWE-D) t h(NWE-D)

FMC_D[15:0]

MSv38004V1

Figure 52. NAND controller waveforms for common memory read access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NWE

FMC_NOE t d(NCE-NOE) t w(NOE) t h(NOE-ALE) t su(D-NOE) t h(NOE-D)

FMC_D[15:0]

MSv38005V1

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Figure 53. NAND controller waveforms for common memory write access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16) t d(NCE-NWE)

FMC_NWE t w(NWE) t h(NOE-ALE)

FMC_NOE t d(D-NWE) t v(NWE-D) t h(NWE-D)

FMC_D[15:0]

MSv38006V1

Table 117. Switching characteristics for NAND Flash read cycles (1)(2)

Symbol Parameter Min Max

T w(N0E)

T su(D-NOE)

T h(NOE-D)

T d(NCE-NOE)

T h(NOE-ALE)

FMC_NOE low width

FMC_D[15-0] valid data before FMC_NOE high

FMC_D[15-0] valid data after FMC_NOE high

FMC_NCE valid before FMC_NOE low

FMC_NOE high to FMC_ALE invalid

1. CL = 30 pF.

2. Guaranteed by characterization results.

HCLK

-1 4T

HCLK

16 -

6 -

HCLK

-2

HCLK

Unit ns

Table 118. Switching characteristics for NAND Flash write cycles

(1)(2)

Symbol Parameter Min Max

T w(NWE)

T v(NWE-D)

T h(NWE-D)

T d(D-NWE)

T d(NCE_NWE)

T h(NWE-ALE)

FMC_NWE low width

FMC_NWE low to FMC_D[15-0] valid

FMC_NWE high to FMC_D[15-0] invalid

FMC_D[15-0] valid before FMC_NWE high

FMC_NCE valid before FMC_NWE low

FMC_NWE high to FMC_ALE invalid

1. CL = 30 pF.

2. Guaranteed by characterization results.

HCLK

-1

HCLK

-4

HCLK

-3

HCLK

-2

HCLK

2.5

HCLK

Unit ns

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The Single Wire Protocol Master Interface (SWPMI) and the associated SWPMI_IO transceiver are compliant with the ETSI TS 102 613 technical specification.

Symbol t

SWPSTART t

SWPBIT

Table 119. SWPMI electrical characteristics

(1)

Parameter Conditions Min Typ Max Unit

SWPMI regulator startup time

SWP bit duration

SWP Class B

2.7 V ≤ V

≤ 3,3V

CORE

voltage range 1

CORE voltage range 2

500 -

620 -

300 μ s

1. Guaranteed by design.

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STM32L486xx Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

ECOPACK ® is an ST trademark.

Figure 54. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline

SEATING

PLANE

C c ccc C

0.25 mm

GAUGE PLANE

109

108 73

144

PIN 1

IDENTIFICATION

1. Drawing is not to scale. e

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Table 120. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max e

E3 k ccc

D1 b c

0.050

1.350

0.170

0.090

21.800

19.800

21.800

19.800

0.450

0°

1.400

0.220

22.000

20.000

17.500

22.000

20.000

17.500

0.500

0.600

1.000

3.5°

1.600

0.150

1.450

0.270

0.200

22.200

20.200

22.200

20.200

0.750

7°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.8583

0.7795

0.0177

0°

0.0020

0.0531

0.0067

0.0035

0.8583

0.7795

0.6890

0.8661

0.7874

0.6890

0.0197

0.0236

0.0394

3.5°

0.0551

0.0087

0.8661

0.7874

0.8740

0.7953

0.0295

7°

0.0031

0.0630

0.0059

0.0571

0.0106

0.0079

0.8740

0.7953

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Figure 55. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint

108 73

1.35

109 0.35

0.5

19.9

17.85

22.6

144

1. Dimensions are expressed in millimeters.

19.9

22.6

36 ai14905e

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Package information STM32L486xx

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 56. LQFP144 marking (package top view)

Optional gate mark

Product identification(1)

Revision code

STM32L486ZGT6

Date code

Y WW

Pin 1 identifier

MSv36849V2

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

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7.2

Package information

UFBGA132 package information

Figure 57. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package outline

A1 ball identifier

E1 B A e

D1 D e

BOTTOM VIEW

Øb (132 balls)

Ø eee M C A B

Ø fff M C

TOP VIEW

A4 ddd C

A2 A3 b A1 A

SEATING

PLANE

UFBGA132_A0G8_ME_V2

1. Drawing is not to scale.

Table 121. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

A2 -

A3 -

A4 b 0.240

6.850

0.450

0.130

0.320

0.290

7.000

5.500

7.000

5.500

0.600

0.110

0.340

7.150

0.0094

0.2697

0.0177

0.0051

0.0114

0.2756

0.2165

0.2756

0.2165

0.0236

0.0043

0.0134

0.2815

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Table 121. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min Typ Max e

Z ddd eee fff -

0.500

0.750

0.080

0.150

0.050

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0197

0.0295

0.0031

0.0059

0.0020

Figure 58. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package recommended footprint

Dpad

Dsm

238/259

UFBGA132_A0G8_FP_V1

Pitch

Dpad

Dsm

Table 122. UFBGA132 recommended PCB design rules (0.5 mm pitch BGA)

Dimension Recommended values

Stencil opening

Stencil thickness

Pad trace width

Ball diameter

0.5 mm

0.280 mm

0.370 mm typ. (depends on the soldermask registration tolerance)

0.280 mm

Between 0.100 mm and 0.125 mm

0.100 mm

0.280 mm

DS10199 Rev 7

STM32L486xx Package information

Device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 59. UFBGA132 marking (package top view)

Product identification

(1)

STM32L

486QGI6

Y WW

Date code

Ball A1 indentifier 3

Revision code

MSv36852V3

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Package information STM32L486xx

Figure 60. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline

SEATING PLANE

C c

0.25 mm

GAUGE PLANE ccc C

L K

75 51

240/259

100

PIN 1

IDENTIFICATION

1 25

26 e

1L_ME_V5

1. Drawing is not to scale.

Table 123. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max b c

0.050

1.350

0.170

0.090

15.800

13.800

15.800

1.400

0.220

16.000

14.000

12.000

16.000

1.600

0.150

1.450

0.270

0.200

16.200

14.200

16.200

0.0020

0.0531

0.0067

0.0035

0.6220

0.5433

0.6220

0.0551

0.0087

0.6299

0.5512

0.4724

0.6299

0.0630

0.0059

0.0571

0.0106

0.0079

0.6378

0.5591

0.6378

DS10199 Rev 7

STM32L486xx Package information

Table 123. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min Typ Max

L1 k ccc

E3 e

13.800

0.450

0.0°

14.000

12.000

0.500

0.600

1.000

3.5°

14.200

0.750

7.0°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.5433

0.0177

0.0°

0.5512

0.4724

0.0197

0.0236

0.0394

3.5°

0.5591

0.0295

7.0°

0.0031

Figure 61. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint

75 51

76 50

0.5

0.3

16.7

14.3

100 26

1.2

1 25

12.3

16.7

ai14906c

1. Dimensions are expressed in millimeters.

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

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Package information STM32L486xx

Figure 62. LQFP100 marking (package top view)

Product identification

(1)

STM32L486

VGT6 3

Date code

Y WW

Optional gate mark

Revision code

Pin 1 indentifier

MSv36846V2

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7.4

Package information

WLCSP72 package information

Figure 63. WLCSP72 - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package outline e1 bbb Z e

Bottom view

Bump side

Bump

G e e2

Side view

Detail A

A1 ball location

Top view

Wafer back side

E aaa eee Z

A1 b (72X)

Ø ccc M

Ø ddd M

X Y

Detail A rotated by 90°

Seating plane

A02R_ME_V1

1. Drawing is not to scale.

e1 e2

E e

(2) b

(3)

Table 124. WLCSP72 - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches

(1)

Symbol millimeters

Min Typ Max Min Typ Max

0.525

0.220

4.3734

3.7244

0.555

0.175

0.380

0.025

0.250

4.4084

3.7594

0.400

3.200

0.6042

0.2797

0.585

0.280

4.4434

3.7944

0.0207

0.0087

0.1722

0.1466

0.0219

0.0069

0.0150

0.0010

0.0098

0.1736

0.1480

0.0157

0.1260

0.0238

0.0110

0.0230

0.0110

0.1749

0.1494

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Package information STM32L486xx

Table 124. WLCSP72 - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package mechanical data (continued) inches (1)

Symbol millimeters

Min Typ Max Min Typ Max aaa bbb ccc ddd eee

0.100

0.050

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Back side coating

3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

0.0039

0.0020

Figure 64. WLCSP72 - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package recommended footprint

Dpad

Dsm

244/259

WLCSP72_A02R_FP_V1

Pitch

Dpad

Dsm

Table 125. WLCSP72 recommended PCB design rules (0.4 mm pitch BGA)

Dimension Recommended values

Stencil opening

Stencil thickness

0.4 mm

0.225 mm

0.290 mm typ. (depends on the solder mask registration tolerance)

0.250 mm

0.100 mm

Device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

DS10199 Rev 7

STM32L486xx Package information

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 65. WLCSP72 marking (package top view)

Ball A1 identifier

L486JGY6

Product identification

(1)

Revision code

Date code

Y WW 3

MSv36871V3

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251

Package information

7.5 LQFP64 package information

STM32L486xx

Figure 66. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline

SEATING PLANE

0.25 mm

GAUGE PLANE ccc C

D3 L1

48 33

32 b

246/259

64 17

PIN 1

IDENTIFICATION

1 e

5W_ME_V3

D1 b c

1. Drawing is not to scale.

Table 126. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min

0.050

1.350

0.170

0.090

Typ

1.400

0.220

12.000

10.000

7.500

12.000

10.000

Max

1.600

0.150

1.450

0.270

0.200

Min

0.0020

0.0531

0.0067

0.0035

Typ

0.0551

0.0087

0.4724

0.3937

0.2953

0.4724

0.3937

Max

0.0630

0.0059

0.0571

0.0106

0.0079

DS10199 Rev 7

STM32L486xx Package information

Table 126. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min

L1 ccc

E3 e

0°

0.450

7.500

0.500

3.5°

0.600

1.000

7°

0.750

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0°

0.0177

Typ

0.2953

0.0197

3.5°

0.0236

0.0394

Max

7°

0.0295

0.0031

Figure 67. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint

0.5

0.3

12.7

10.3

64 17

1.2

1 16

7.8

12.7

ai14909c

1. Dimensions are expressed in millimeters.

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

DS10199 Rev 7

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251

Package information

Figure 68. LQFP64 marking (package top view)

Product identification(1)

Revision code

STM32L486

RGT6

STM32L486xx

Y WW

Date code

Pin 1 identifier

MSv36855V3

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DS10199 Rev 7

STM32L486xx Package information

The maximum chip junction temperature (T

Table 22: General operating conditions .

max) must never exceed the values given in

The maximum chip-junction temperature, T

J using the following equation:

max, in degrees Celsius, may be calculated

max = T

max + (P

max x Θ

)

Where:

• T

max is the maximum ambient temperature in °C,

• Θ

is the package junction-to-ambient thermal resistance, in °C/W,

• P

max is the sum of P

INT

max and P

I/O max (P

max = P

INT

max + P

I/O max),

• P

INT

max is the product of all I

DDXXX and maximum chip internal power.

DDXXX

, expressed in Watts. This is the

I/O

max represents the maximum power dissipation on output pins where:

I/O

max = Σ (V

× I

) + Σ ((V

DDIOx

– V

) × I

), taking into account the actual V

OL application.

/ I

and V

/ I

OH of the I/Os at low and high level in the

Symbol

Table 127. Package thermal characteristics

Parameter Value

Thermal resistance junction-ambient

LQFP64 - 10 × 10 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP100 - 14 × 14mm

Thermal resistance junction-ambient

LQFP144 - 20 × 20 mm

Thermal resistance junction-ambient

UFBGA132 - 7 × 7 mm

Thermal resistance junction-ambient

WLCSP72

Unit

°C/W

7.6.2

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org

Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering

information scheme shown in Section 8: Ordering information .

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.

As applications do not commonly use the STM32L486xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application.

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251

Package information

Note:

STM32L486xx

The following examples show how to calculate the temperature range needed for a given application.

Example 1: High-performance application

Assuming the following application conditions:

Maximum ambient temperature T

Amax

DDmax

= 50 mA, V

= 82 °C (measured according to JESD51-2),

= 3.5 V, maximum 20 I/Os used at the same time in output at low level with I

= 8 mA, V

= 0.4 V and maximum 8 I/Os used at the same time in output at low level with I

= 20 mA, V

= 1.3 V

INTmax

= 50 mA × 3.5 V= 175 mW

IOmax

= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW

This gives: P

INTmax

= 175 mW and P

IOmax

= 272 mW:

Dmax

= 175 + 272 = 447 mW

Using the values obtained in Table 127 T

Jmax

is calculated as follows:

– For LQFP64, 45 °C/W

Jmax

= 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.115 °C = 102.115 °C

This is within the range of the suffix 6 version parts (–40 < T

Ordering information .

< 105 °C) see Section 8:

In this case, parts must be ordered at least with the temperature range suffix 6 (see Part numbering).

With this given P

Dmax

we can find the T

Amax

allowed for a given device temperature range

(order code suffix 6 or 7).

Suffix 6: T

Amax

= T

Jmax

- (45°C/W × 447 mW) = 105-20.115 = 84.885 °C

Suffix 7: T

Amax

= T

Jmax

- (45°C/W × 447 mW) = 125-20.115 = 104.885 °C

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature T

J specified range.

remains within the

Assuming the following application conditions:

Maximum ambient temperature T

Amax

DDmax

= 20 mA, V

= 100 °C (measured according to JESD51-2),

= 3.5 V, maximum 20 I/Os used at the same time in output at low level with I

= 8 mA, V

= 0.4 V

INTmax

= 20 mA × 3.5 V= 70 mW

IOmax

= 20 × 8 mA × 0.4 V = 64 mW

This gives: P

INTmax

= 70 mW and P

IOmax

= 64 mW:

Dmax

= 70 + 64 = 134 mW

Thus: P

Dmax

= 134 mW

Using the values obtained in Table 127 T

Jmax

is calculated as follows:

– For LQFP64, 45 °C/W

Jmax

= 100 °C + (45 °C/W × 134 mW) = 100 °C + 6.03 °C = 106.03 °C

This is above the range of the suffix 6 version parts (–40 < T

< 105 °C).

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DS10199 Rev 7

STM32L486xx Package information

In this case, parts must be ordered at least with the temperature range suffix 7 (see

Section 8: Ordering information

) unless we reduce the power dissipation in order to be able to use suffix 6 parts.

Refer to Figure 69 to select the required temperature range (suffix 6 or 7) according to your

ambient temperature or power requirements.

Figure 69. LQFP64 P

max vs. T

700

600

500

400

300

200

100

65 75 85 95 105 115 125 135

(°C)

Suffix 6

Suffix 7

MSv32143V1

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Ordering information STM32L486xx

252/259

Table 128. STM32L486xx ordering information scheme

Example:

Device family

STM32 = Arm

® based 32-bit microcontroller

STM32 L 486 R G T 6 P I TR

Product type

L = ultra-low-power

Device subfamily

486: STM32L486xx

Pin count

R = 64 pins

J = 72 pins

V = 100 pins

Q = 132 pins

Z = 144 pins

Flash memory size

G = 1 MB of Flash memory

Package

T = LQFP ECOPACK

I = UFBGA ECOPACK

Y = CSP ECOPACK

Temperature range

6 = Industrial temperature range, -40 to 85 °C (105 °C junction)

7 = Industrial temperature range, -40 to 105 °C (125 °C junction)

3 = Industrial temperature range, -40 to 125 °C (130 °C junction)

Option

Blank = Standard production with integrated LDO

P = Dedicated pinout supporting external SMPS

OptionSpecific package

I = Specific material used

(1)

Blank = Standard

Packing

TR = tape and reel xxx = programmed parts

1. This option is available only on STM32L486RGT6ITR part number under specific ordering conditions.

Contact your nearest ST sales office for availability.

For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.

DS10199 Rev 7

STM32L486xx Revision history

Date

29-May-2015

12-Jun-2015

18-Sep-2015

Table 129. Document revision history

Revision Changes

Initial release.

Updated Table 16: STM32L486xx pin definitions

and

Table 85: COMP characteristics .

Changed alternate function pin name “SWDAT” into

“SWDIO” in all the document.

Updated Section 3.9.1: Power supply schemes

Updated Section 3.15.1: Temperature sensor

In all Section 6: Electrical characteristics , renamed table footnotes related to test and characterization.

Added Note 2.

Updated Table 51: Low-power mode wakeup timings .

Updated Table 52: Regulator modes transition times .

Updated Table 58: HSI16 oscillator characteristics .

Added Table 27: HSI16 frequency versus temperature .

Updated Table 59: MSI oscillator characteristics .

Updated Table 61: LSI oscillator characteristics .

Updated Table 69: I/O current injection susceptibility .

Removed first Note in Table 70: I/O static characteristics .

Removed second Note in Table 71: Output voltage characteristics .

Updated Table 76: ADC characteristics .

Updated Table 78: ADC accuracy - limited test conditions 1 .

Added Table 79: ADC accuracy - limited test conditions

2 .

Added Table 80: ADC accuracy - limited test conditions

3 .

Added Table 81: ADC accuracy - limited test conditions

4 .

Updated Table 83: DAC accuracy .

Updated Table 84: VREFBUF characteristics .

Added Section 6.3.26: DFSDM characteristics .

Updated Section : Quad SPI characteristics .

Updated Table 97: Quad SPI characteristics in SDR mode .

Updated Table 98: QUADSPI characteristics in DDR mode .

Updated Table 101: USB electrical characteristics .

Updated Section 7.2: UFBGA132 package information

Updated Section 7.4: WLCSP72 package information

Updated Table 68: LQFP64 marking (package top view) .

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258

Revision history STM32L486xx

Date

04-Dec-2015

17-Jun-2016

Table 129. Document revision history (continued)

Revision Changes

In all the document:

– Stop 1 with main regulator becomes Stop 0

– Stop 1 with low-power regulator remains as Stop 1.

Section 4: Pinouts and pin description

– PC14/OSC32_IN becomes PC14-OSC32_IN (PC14)

– PC15/OSC32_OUT becomes PC15-OSC32_OUT

(PC15)

– PH0/OSC_IN becomes PH0-OSC_IN (PH0)

– PH1/OSC_OUT becomes PH1-OSC_OUT (PH1)

– PA13 becomes PA13 (JTMS-SWDIO)

– PA14 becomes PA14 (JTCK-SWCLK)

– PA15 becomes PA15 (JTDI)

– PB3 becomes PB3 (JTDO-TRACESWO)

– PB4 becomes PB4 (NJTRST).

Added Table 13: STM32L486xx USART/UART/LPUART features

Added Note 5.

Updated Table 25: Embedded internal voltage reference .

Updated Table 34: Current consumption in Stop 2 mode .

Updated Table 35: Current consumption in Stop 1 mode .

Updated Table 47: Current consumption in Stop 0 mode .

Updated Table 48: Current consumption in Standby mode

Updated Table 49: Current consumption in Shutdown mode

Updated Table 51: Low-power mode wakeup timings .

Added Figure 22: VREFINT versus temperature .

Updated Figure 27: HSI16 frequency versus temperature .

Updated Table 70: I/O static characteristics .

Updated Table 82: DAC characteristics .

Updated Figure 57: UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package outline .

Updated Table 121: UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package mechanical data .

Replaced DFSDM by DFSDM1 in many places within the document.

Added –: IRTIM (Infrared interface)

and updated number of maskable interrupts on cover page.

Added IRTIM in

Table 6: STM32L486xx peripherals interconnect matrix

Updated number of maskable interrupts and edge detector lines in

Section 3.14: Interrupts and events .

Added Figure 5: Voltage reference buffer

Added Section 3.25.5: Infrared interface (IRTIM)

254/259

DS10199 Rev 7

STM32L486xx Revision history

Date

17-Jun-2016

06-Jul-2017

Table 129. Document revision history (continued)

Revision Changes

(continued)

Updated Section 3.28: Universal synchronous/asynchronous receiver transmitter

(USART)

Updated footnotes of Table 21: Current characteristics

Added Table 33: Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) .

Updated Table 52: Low-power mode wakeup timings

Added Table 54: Wakeup time using USART/LPUART

Updated OPAMPx_VINM in

Table 70: I/O static characteristics .

Added footnote to

Figure 28: Recommended NRST pin protection .

Updated Table 75: Analog switches booster characteristics .

Updated footnotes of Figure 30: Typical connection diagram using the ADC

Updated footnotes of Table 84: VREFBUF characteristics .

Updated Table 86: OPAMP characteristics

Added Section 6.3.30: SWPMI characteristics .

Updated Table 128: STM32L486xx ordering information scheme .

Added:

–

Table 10: DFSDM1 implementation

–

Figure 7: STM32L486Zx, external SMPS device,

LQFP144 pinout

(1)

–

Figure 11: STM32L486Jx, external SMPS device,

WLCSP72 ballout

(1)

–

Figure 13: STM32L486Rx, external SMPS device,

LQFP64 pinout

(1)

–

Table 28: Current consumption in Run modes, code with data processing running from Flash, ART enable

(Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.10 V)

–

Table 30: Current consumption in Run modes, code with data processing running from Flash, ART disable and power supplied by external SMPS (VDD12 =

1.10 V)

–

Table 32: Current consumption in Run, code with data processing running from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V)

–

Table 34: Typical current consumption in Run, with different codes running from Flash, ART enable

(Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.10 V)

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258

Revision history STM32L486xx

Date

06-Jul-2017

Table 129. Document revision history (continued)

Revision Changes

(continued)

–

Table 35: Typical current consumption in Run, with different codes running from Flash, ART enable

(Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.05 V)

–

Table 37: Typical current consumption in Run modes, with different codes running from Flash, ART disable and power supplied by external SMPS (VDD12 =

1.10 V)

–

Table 38: Typical current consumption in Run modes, with different codes running from Flash, ART disable and power supplied by external SMPS (VDD12 =

1.05 V)

–

Table 40: Typical current consumption in Run mode, with different codes running from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V)

–

Table 41: Typical current consumption in Run mode, with different codes running from SRAM1 and power supplied by external SMPS (VDD12 = 1.05 V)

–

Table 43: Current consumption in Sleep, Flash ON and power supplied by external SMPS (VDD12 =

1.10 V)

–

Table 54: Wakeup time using USART/LPUART

–

Section 6.3.16: Extended interrupt and event controller input (EXTI) characteristics

–

Section 6.3.30: SWPMI characteristics

–

Table 104: USB BCD DC electrical characteristics

–

Figure 41: USB OTG timings – definition of data signal rise and fall time

Sections updated:

–

Section : Features

–

Section 2: Description

–

Section 3.9.1: Power supply schemes

–

Section 3.9.3: Voltage regulator

–

Section 3.14.2: Extended interrupt/event controller

(EXTI)

–

Section 3.25.6: Independent watchdog (IWDG)

–

Section 3.28: Universal synchronous/asynchronous

receiver transmitter (USART)Section 3.29: Low-power universal asynchronous receiver transmitter

(LPUART)

–

Section 3.35: Universal serial bus on-the-go full-speed

(OTG_FS)

–

Section 6.2: Absolute maximum ratings

–

Section 6.3.5: Supply current characteristics

–

Section 6.3.18: Analog-to-Digital converter characteristics

–

Section : USB OTG full speed (FS) characteristics

–

Section 7: Package information

–

Section 8: Ordering information

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DS10199 Rev 7

STM32L486xx Revision history

Date

06-Jul-2017

Table 129. Document revision history (continued)

Revision Changes

(continued)

Tables updated:

–

Table 2: STM32L486xx family device features and peripheral counts

–

Table 4: STM32L486xx modes overview

–

Table 16: STM32L486xx pin definitions

–

Table 17: Alternate function AF0 to AF7

to update

FMC_INT3 to FMC_INT and FMC_NCE3 to

FMC_NCE

–

Table 20: Voltage characteristics

–

Table 23: General operating conditions

–

Table 70: I/O static characteristics

–

Table 76: ADC characteristics

–

Table 82: DAC characteristics

–

Table 85: COMP characteristics

–

Table 102: USB OTG DC electrical characteristics

–

Table 103: USB OTG electrical characteristics

–

Table 121: UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package mechanical data

–

Table 128: STM32L486xx ordering information scheme

Figure updated:

–

Figure 1: STM32L486xx block diagram

–

Figure 6: STM32L486Zx LQFP144 pinout

(1)

–

Figure 12: STM32L486Rx LQFP64 pinout

(1)

–

Figure 18: Current consumption measurement scheme with and without external SMPS power supply

–

Figure 57: UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package outline

Footnotes updated for:

–

Table 2: STM32L486xx family device features and peripheral counts

–

Table 4: STM32L486xx modes overview

–

Table 16: STM32L486xx pin definitions

–

Table 21: Current characteristics

–

Table 24: Operating conditions at power-up / powerdown

–

Table 69: I/O current injection susceptibility

–

Table 70: I/O static characteristics

–

Table 77: Maximum ADC RAIN

–

Figure 30: Typical connection diagram using the ADC

–

Table 85: COMP characteristics

–

Table 91: DFSDM characteristics

–

Table 102: USB OTG DC electrical characteristics

–

Table 119: SWPMI electrical characteristics

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Revision history STM32L486xx

Date

25-May-2018

Table 129. Document revision history (continued)

Revision Changes

Updated Energy benchmark

Updated DAC terminology in all the document for clarification: single DAC instance (= DAC1) with 2 output channels.

Updated clock-out capability in Section 3.11: Clocks and startup .

Updated Section 3.14.1: Nested vectored interrupt controller (NVIC) .

Updated V

DD12

characteristics .

-V

in Table 20: Voltage

Updated Table 82: DAC characteristics

Added power up/down sequence requirements in

Section 3.9.1: Power supply schemes

Added Figure 3: Power-up/down sequence .

Updated Section 6.3.2: Operating conditions at powerup / power-down .

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