STMicroelectronics STM32F103RD Datasheet

STM32F103xC, STM32F103xD,

STM32F103xE

High-density performance line Arm

®

-based 32-bit MCU with 256 to 512KB

Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces

Datasheet

−

production data

Features

• Core: Arm ® 32-bit Cortex ® -M3 CPU

– 72 MHz maximum frequency, 1.25 DMIPS/MHz

(Dhrystone 2.1) performance at 0 wait state memory access

– Single-cycle multiplication and hardware division

• Memories

– 256 to 512 Kbytes of Flash memory

– up to 64 Kbytes of SRAM

– Flexible static memory controller with 4 Chip

Select. Supports Compact Flash, SRAM,

PSRAM, NOR and NAND memories

– LCD parallel interface, 8080/6800 modes

• Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR, and programmable voltage detector

(PVD)

– 4-to-16 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC with calibration

– 32 kHz oscillator for RTC with calibration

• Low power

– Sleep, Stop and Standby modes

– V

BAT

supply for RTC and backup registers

• 3 × 12-bit, 1 µs A/D converters (up to 21 channels)

– Conversion range: 0 to 3.6 V

– Triple-sample and hold capability

– Temperature sensor

• 2 × 12-bit D/A converters

• DMA: 12-channel DMA controller

– Supported peripherals: timers, ADCs, DAC,

SDIO, I

2

Ss, SPIs, I

2

Cs and USARTs

• Debug mode

– Serial wire debug (SWD) & JTAG interfaces

– Cortex

®

-M3 Embedded Trace Macrocell™

• Up to 112 fast I/O ports

– 51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant

LQFP64 10 × 10 mm,

LQFP100 14 × 14 mm,

LQFP144 20 × 20 mm

WLCSP64

LFBGA100 10 × 10 mm

LFBGA144 10 × 10 mm

• Up to 11 timers

– Up to four 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter and quadrature

(incremental) encoder input

– 2 × 16-bit motor control PWM timers with deadtime generation and emergency stop

– 2 × watchdog timers (Independent and Window)

– SysTick timer: a 24-bit downcounter

– 2 × 16-bit basic timers to drive the DAC

• Up to 13 communication interfaces

– Up to 2 × I

2

C interfaces (SMBus/PMBus)

– Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)

– Up to 3 SPIs (18 Mbit/s), 2 with I

2

S interface multiplexed

– CAN interface (2.0B Active)

– USB 2.0 full speed interface

– SDIO interface

• CRC calculation unit, 96-bit unique ID

• ECOPACK ® packages

Reference

STM32F103xC

STM32F103xD

STM32F103xE

Table 1.Device summary

Part number

STM32F103RC STM32F103VC

STM32F103ZC

STM32F103RD STM32F103VD

STM32F103ZD

STM32F103RE STM32F103ZE

STM32F103VE

July 2018 DS5792 Rev 13

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Contents

Contents

STM32F103xC, STM32F103xD, STM32F103xE

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1

Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2

Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.1

Arm

®

Cortex

®

-M3 core with embedded Flash and SRAM . . . . . . . . . . 15

2.3.2

2.3.3

2.3.4

2.3.5

2.3.6

2.3.7

2.3.8

2.3.9

Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15

Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 15

LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16

External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16

Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.10

Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.11

Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.12

Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.13

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.14

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.15

DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.16

RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18

2.3.17

Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.18

I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.19

Universal synchronous/asynchronous receiver transmitters (USARTs) 21

2.3.20

Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.21

Inter-integrated sound (I

2

S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.22

SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.23

Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.24

Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.25

GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.26

ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.27

DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.3.28

Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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2.3.29

Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.3.30

Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.2

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.3

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 45

Embedded reset and power control block characteristics . . . . . . . . . . . 45

Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.3.9

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.3.10

FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.3.11

EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

5.3.12

Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 87

5.3.13

I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

5.3.14

I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.3.15

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

5.3.16

TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

5.3.17

Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

5.3.18

CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . 106

5.3.19

12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

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5.3.20

DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

5.3.21

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

6.1

LFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

6.2

LFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

6.3

WLCSP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

6.4

LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.5

LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

6.6

LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

6.7

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

6.7.1

6.7.2

Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 133

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

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List of tables

List of tables

Table 1.

Table 2.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

STM32F103xC, STM32F103xD and STM32F103xE features

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

High-density timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

High-density STM32F103xC/D/E pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 10.

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 11.

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 12.

Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 13.

Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 14.

Maximum current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 15.

Maximum current consumption in Run mode, code with data processing

running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 16.

Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 49

Table 17.

Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 50

Table 18.

Typical current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 19.

Typical current consumption in Sleep mode, code running from Flash or

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 20.

Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 21.

High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 22.

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 23.

HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 24.

LSE oscillator characteristics (f

LSE

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 25.

HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 26.

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 27.

Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 28.

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 29.

Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 30.

Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 31.

Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 67

Table 32.

Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 68

Table 33.

Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 34.

Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 35.

Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 36.

Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 37.

Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 38.

Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 39.

Switching characteristics for PC Card/CF read and write cycles . . . . . . . . . . . . . . . . . . . . 81

Table 40.

Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 85

Table 41.

EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 42.

EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 43.

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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Table 44.

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 45.

I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 46.

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 47.

Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 48.

I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 49.

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 50.

TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 51.

I

2

C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 52.

SCL frequency (f

PCLK1

= 36 MHz.,V

DD_I2C

= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 53.

SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 54.

I

2

S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 55.

SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 56.

USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 57.

USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 58.

USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 59.

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 60.

R

AIN

max for f

ADC

= 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 61.

ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 62.

ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 63.

DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 64.

TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 65.

LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 66.

LFBGA144 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 115

Table 67.

LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 68.

LFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 118

Table 69.

WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 70.

WLCSP64 recommended PCB design rules (0.5 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 121

Table 71.

LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 72.

LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 73.

LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 129

Table 74.

Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 75.

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

6/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE

List of figures

List of figures

Figure 1.

STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram . . . 12

Figure 2.

Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3.

STM32F103xC/D/E BGA144 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 4.

STM32F103xC/D/E performance line BGA100 ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 5.

STM32F103xC/D/E performance line LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 6.

STM32F103xC/D/E performance line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 7.

STM32F103xC/D/E performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 8.

STM32F103xC/D/E performance line

WLCSP64 ballout, ball side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 9.

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 10.

Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 11.

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 12.

Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 13.

Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 14.

Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled . . . . . . . . . . . . . . . . . 48

Figure 15.

Typical current consumption in Run mode versus frequency (at 3.6 V)code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . 48

Figure 16.

Typical current consumption on V

BAT

with RTC on vs. temperature at different V

BAT values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 17.

Typical current consumption in Stop mode with regulator in run mode versus temperature at different V

DD

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 18.

Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different V

DD

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 19.

Typical current consumption in Standby mode versus temperature at different V

DD

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 20.

High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 21.

Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 22.

Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 23.

Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 24.

Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 66

Figure 25.

Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 67

Figure 26.

Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 27.

Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 28.

Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 29.

Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 30.

Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 31.

Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 32.

PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 77

Figure 33.

PC Card/CompactFlash controller waveforms for common memory write access . . . . . . . 78

Figure 34.

PC Card/CompactFlash controller waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 35.

PC Card/CompactFlash controller waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 36.

PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 80

Figure 37.

PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 81

Figure 38.

NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 39.

NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

DS5792 Rev 13

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8

List of figures STM32F103xC, STM32F103xD, STM32F103xE

Figure 40.

NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 84

Figure 41.

NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . . 85

Figure 42.

Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 43.

Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 44.

5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 45.

5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 46.

I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 47.

Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 48.

I

2

C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 49.

SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 50.

SPI timing diagram - slave mode and CPHA = 1

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 51.

Figure 52.

I

SPI timing diagram - master mode

2

Figure 53.

I

2

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

S slave timing diagram (Philips protocol)

(1)

S master timing diagram (Philips protocol)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 54.

SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 55.

SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 56.

USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 57.

ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 58.

Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 59.

Power supply and reference decoupling (V

REF+

Figure 60.

Power supply and reference decoupling (V

REF+ not connected to V connected to V

DDA

DDA

). . . . . . . . . . . . . 109

). . . . . . . . . . . . . . . . 110

Figure 61.

12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 62.

LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 63.

LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 64.

LFBGA144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 65.

LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 66.

LFBGA100 – 100-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package recommended footprintoutline . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 67.

LFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 68.

WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 69.

WLCSP64 - 64-ball, 4.4757 x 4.4049 mm, 0.5 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 70.

LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 122

Figure 71.

LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 72.

LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 73.

LQFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline . . . . . . . . . . . . . . 126

Figure 74.

LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 75.

LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 76.

LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 129

Figure 77.

LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . 130

Figure 78.

LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 79.

LQFP100 P

D

max vs. T

A

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

8/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE

1 Introduction

Introduction

This datasheet provides the ordering information and mechanical device characteristics of the STM32F103xC, STM32F103xD and STM32F103xE high-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xC/D/E

family, please refer to Section 2.2: Full compatibility throughout the family

.

The high-density STM32F103xC/D/E datasheet should be read in conjunction with the

STM32F10xxx reference manual.

For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual.

The reference and Flash programming manuals are both available from the

STMicroelectronics website www.st.com

.

For information on the Arm ®(a) Cortex ® -M3 core please refer to the Cortex ® -M3 Technical

Reference Manual, available from the www.arm.com

website at the following address: http://infocenter.arm.com

.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS5792 Rev 13

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135

Description

2 Description

STM32F103xC, STM32F103xD, STM32F103xE

The STM32F103xC, STM32F103xD and STM32F103xE performance line family incorporates the high-performance Arm ® Cortex ® -M3 32-bit RISC core operating at a

72 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and

SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer three 12-bit ADCs, four general-purpose 16bit timers plus two PWM timers, as well as standard and advanced communication interfaces: up to two I 2 Cs, three SPIs, two I 2 Ss, one SDIO, five USARTs, an USB and a

CAN.

The STM32F103xC/D/E high-density performance line family operates in the –40 to

+105 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications.

These features make the STM32F103xC/D/E high-density performance line microcontroller family suitable for a wide range of applications such as motor drives, application control, medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems video intercom, and HVAC.

10/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Description

The STM32F103xC/D/E high-density performance line family offers devices in six different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.

Figure 1 shows the general block diagram of the device family.

Table 2. STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts

Peripherals STM32F103Rx STM32F103Vx STM32F103Zx

Flash memory in Kbytes

SRAM in Kbytes

FSMC

Timers

General-purpose

Advanced-control

Basic

SPI(I

2

S)

(2)

I

2

C

USART

Comm

USB

CAN

SDIO

GPIOs

12-bit ADC

Number of channels

12-bit DAC

Number of channels

CPU frequency

Operating voltage

Operating temperatures

256

48

384

No

64

512 256 384 512 256 384 512

48

Yes

(1)

64 48

Yes

64

4

2

2

3(2)

2

5

51

3

16

1

1

1

2

2

72 MHz

80

3

16

112

3

21

2.0 to 3.6 V

Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Table 10

)

Junction temperature: –40 to + 125 °C (see

Table 10

)

LQFP64, WLCSP64 LQFP100, BGA100 LQFP144, BGA144 Package

1. For the LQFP100 and BGA100 packages, only FSMC Bank1 and Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or

8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package.

2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the

I 2 S audio mode.

DS5792 Rev 13

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135

Description STM32F103xC, STM32F103xD, STM32F103xE

Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram

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53"?$0#!.?48

53"?$-#!.?28

$!#?/54AS!&

$!#?/54AS!&

AIG

1. T

A

= –40 °C to +85 °C (suffix 6, see

Table 75 ) or –40 °C to +105 °C (suffix 7, see Table 75

), junction temperature up to 105 °C or 125 °C, respectively.

2. AF = alternate function on I/O port pin.9

12/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Description

Figure 2. Clock tree

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DLE

1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is

64 MHz.

2. For the USB function to be available, both HSE and PLL must be enabled, with the USBCLK at 48 MHz.

3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.

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135

Description STM32F103xC, STM32F103xD, STM32F103xE

The STM32F103xC/D/E is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices.

Low-density and high-density devices are an extension of the STM32F103x8/B mediumdensity devices, they are specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively. Low-density devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I

2

S and DAC while remaining fully compatible with the other members of the family.

The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE are a drop-in replacement for the STM32F103x8/B devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle.

Moreover, the STM32F103xx performance line family is fully compatible with all existing

STM32F101xx access line and STM32F102xx USB access line devices.

Pinout

Low-density devices

16 KB Flash

32 KB

Flash

(1)

Table 3. STM32F103xx family

Medium-density devices

64 KB Flash

128 KB

Flash

256 KB

Flash

High-density devices

384 KB Flash 512 KB Flash

6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 48 RAM 64 KB RAM 64 KB RAM

144

100

64

2 × USARTs

2 × 16-bit timers

1 × SPI, 1 × I

2

C, USB, CAN,

1 × PWM timer

2 × ADCs

3 × USARTs

3 × 16-bit timers

2 × SPIs, 2 × I

2

Cs, USB,

CAN, 1 × PWM timer

2 × ADCs

5 × USARTs

4 × 16-bit timers, 2 × basic timers

3 × SPIs, 2 × I

2

Ss, 2 × I2Cs

USB, CAN, 2 × PWM timers

3 × ADCs, 2 × DACs, 1 × SDIO

FSMC (100- and 144-pin packages (2) )

48

36

1. For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7), the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density devices.

2. Ports F and G are not available in devices delivered in 100-pin packages.

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STM32F103xC, STM32F103xD, STM32F103xE Description

2.3 Overview

2.3.1 Arm

®

Cortex

®

-M3 core with embedded Flash and SRAM

The Arm Cortex ® -M3 processor is the latest generation of Arm processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The Arm Cortex ® -M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices.

With its embedded Arm core, STM32F103xC, STM32F103xD and STM32F103xE performance line family is compatible with all Arm tools and software.

Figure 1 shows the general block diagram of the device family.

2.3.3

Up to 512 Kbytes of embedded Flash is available for storing programs and data.

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

2.3.5

Up to 64 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.

FSMC (flexible static memory controller)

The FSMC is embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line family. It has four Chip Select outputs supporting the following modes: PC

Card/Compact Flash, SRAM, PSRAM, NOR and NAND.

Functionality overview:

• The three FSMC interrupt lines are ORed in order to be connected to the NVIC

• Write FIFO

• Code execution from external memory except for NAND Flash and PC Card

• The targeted frequency, f

CLK

, is HCLK/2, so external access is at 36 MHz when HCLK is at 72 MHz and external access is at 24 MHz when HCLK is at 48 MHz

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135

Description

2.3.6

2.3.7

STM32F103xC, STM32F103xD, STM32F103xE

LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration.

Nested vectored interrupt controller (NVIC)

The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of Cortex ® -M3) and 16 priority levels.

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail-chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

2.3.9

The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected to the 16 external interrupt lines.

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator).

Several prescalers allow the configuration of the AHB frequency, the high speed APB

(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed

APB domain is 36 MHz. See Figure 2

for details on the clock tree.

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DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Description

At startup, boot pins are used to select one of three boot options:

• Boot from user Flash: you have an option to boot from any of two memory banks. By default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash memory bank 2 by setting a bit in the option bytes.

• Boot from system memory

• Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1.

2.3.11 Power supply schemes

• V

DD

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

Provided externally through V

DD

pins.

• V

SSA

, V

DDA

= 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC is used). V

DDA

and V

SSA

must be connected to V

DD

and V

SS

, respectively.

• V

BAT

= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V

DD

is not present.

For more details on how to connect power pins, refer to

Figure 12: Power supply scheme .

2.3.12 Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when V

DD external reset circuit.

is below a specified threshold, V

POR/PDR

, without the need for an

The device features an embedded programmable voltage detector (PVD) that monitors the

V

DD

/V

DDA

power supply and compares it to the V

PVD

threshold. An interrupt can be generated when V higher than the V

DD

PVD

/V

DDA

drops below the V

PVD

threshold and/or when V

DD

/V

DDA

is

threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to

Table 12: Embedded reset and power control block characteristics for the values of

V

POR/PDR

and V

PVD

.

The regulator has three operation modes: main (MR), low-power (LPR) and power down.

• MR is used in the nominal regulation mode (Run)

• LPR is used in the Stop modes.

• Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode.

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135

Description STM32F103xC, STM32F103xD, STM32F103xE

Note:

The STM32F103xC, STM32F103xD and STM32F103xE performance line supports three low-power modes to achieve the best compromise between low-power consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB wakeup.

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.

2.3.15 DMA

The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for

DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-toperipheral transfers. The two DMA controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I

2

C, USART, general-purpose, basic and advanced-control timers TIMx, DAC, I

2

S, SDIO and ADC.

2.3.16 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

V

DD

supply when present or through the V

BAT

pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when V

DD

power is not present.

They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode.

The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a

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DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Description periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.3.17 Timers and watchdogs

The high-density STM32F103xC/D/E performance line devices include up to two advancedcontrol timers, up to four general-purpose timers, two basic timers, two watchdog timers and a SysTick timer.

Table 4 compares the features of the advanced-control, general-purpose and basic timers.

Timer

TIM1,

TIM8

Counter resolution

Table 4. High-density timer feature comparison

Counter type

Prescaler factor

DMA request generation

Capture/compare channels

Complementary outputs

16-bit

Up, down, up/down

Any integer between 1 and 65536

Yes 4 Yes

TIM2,

TIM3,

TIM4,

TIM5

16-bit

Up, down, up/down

Any integer between 1 and 65536

Yes 4 No

TIM6,

TIM7

16-bit Up

Any integer between 1 and 65536

Yes 0 No

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Description STM32F103xC, STM32F103xD, STM32F103xE

Advanced-control timers (TIM1 and TIM8)

The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase

PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as a complete general-purpose timer. The 4 independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge or center-aligned modes)

• One-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switch driven by these outputs.

Many features are shared with those of the general-purpose TIM timers which have the same architecture. The advanced-control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining.

General-purpose timers (TIMx)

There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or onepulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages.

The general-purpose timers can work together with the advanced-control timer via the Timer

Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from

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DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Description the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

• A 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0.

• Programmable clock source

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes.

They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and

USART3) and two universal asynchronous receiver transmitters (UART4 and UART5).

These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability.

The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s.

USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5.

2.3.20 Serial peripheral interface (SPI)

Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes.

All SPIs can be served by the DMA controller.

Two standard I 2 S interfaces (multiplexed with SPI2 and SPI3) are available, that can be operated in master or slave mode. These interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to

48 kHz are supported. When either or both of the I 2 S interfaces is/are configured in master

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135

Description STM32F103xC, STM32F103xD, STM32F103xE mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency.

2.3.22 SDIO

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System

Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with SD

Memory Card Specifications Version 2.0.

The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous.

In addition to SD/SDIO/MMC, this interface is also fully compliant with the CE-ATA digital protocol Rev1.1.

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and

14 scalable filter banks.

The STM32F103xC, STM32F103xD and STM32F103xE performance line embed a USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator).

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

22/143

Three 12-bit analog-to-digital converters are embedded into STM32F103xC, STM32F103xD and STM32F103xE performance line devices and each ADC shares up to 21 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

• Simultaneous sample and hold

• Interleaved sample and hold

• Single shunt

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Description

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) and the advanced-control timers (TIM1 and TIM8) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers.

The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.

This dual digital Interface supports the following features:

• two DAC converters: one for each output channel

• 8-bit or 12-bit monotonic output

• left or right data alignment in 12-bit mode

• synchronized update capability

• noise-wave generation

• triangular-wave generation

• dual DAC channel independent or simultaneous conversions

• DMA capability for each channel

• external triggers for conversion

• input voltage reference V

REF+

Eight DAC trigger inputs are used in the STM32F103xC, STM32F103xD and

STM32F103xE performance line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.

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135

Description STM32F103xC, STM32F103xD, STM32F103xE

The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < V

DDA

< 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The Arm SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

The Arm

®

Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the

STM32F10xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.

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DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE

3 Pinouts and pin descriptions

Pinouts and pin descriptions

Figure 3. STM32F103xC/D/E BGA144 ballout

1 2 3 4 5 6 7 8 9 10 11 12

A

PC1 3 -

TAMPER-RTC

PE 3 PE2

B

PC14-

O S C 3 2_IN

PE4

C

PC15-

O S C 3 2_OUT

VBAT

PE5

PF0

PE1

PE6

PF1

PE0

PB4

JTR S T

PB 3

JTDO

PD6 PD7

PA15

JTDI

PB 8 PB6 PG14 PG11 PD4 PC12

PA14

JTCK

PB9 PB5 PG15 PG12 PD5 PC11 PC10 PA12

NC

PA1 3

JTM S

PA11

D O S C_IN V

SS _5

VDD_5 PF2 BOOT0 PB7 PG1 3 PG10 PD 3 PD1 PA10 PA9

E O S C_OUT PF 3 PF4 PF5 V

SS _ 3

V

SS _11

V

SS _10

PG9 PD2 PD0 PC9 PA 8

F NR S T PF7 PF6 VDD_4 VDD_

3

VDD_11 VDD_10 VDD_

8

VDD_2 VDD_9 PC 8 PC7

G PF10 PF9 PF 8 V

SS _4

VDD_6 VDD_7 VDD_1 V

SS _ 8

V

SS _2

V

SS _9

PG 8 PC6

H PC0 PC1 PC2 PC 3

V

SS _6

V

SS _7

V

SS _1

PE11 PD11 PG7 PG6 PG5

J V

SS A

PA0-WKUP PA4 PC4

PB2/

BOOT1

PG1 PE10 PE12 PD10 PG4 PG 3 PG2

K VREF– PA1 PA5 PC5 PF1 3 PG0 PE9 PE1 3 PD9 PD1 3 PD14 PD15

L VREF+ PA2 PA6 PB0 PF12 PF15 PE 8 PE14 PD 8 PD12 PB14 PB15

M VDDA PA 3 PA7 PB1 PF11 PF14 PE7 PE15 PB10 PB11 PB12 PB1 3

AI1479 8b

1. The above figure shows the package top view.

DS5792 Rev 13

25/143

135

Pinouts and pin descriptions

1

STM32F103xC, STM32F103xD, STM32F103xE

2

Figure 4. STM32F103xC/D/E performance line BGA100 ballout

3 4 5 6 7 8 9 10

A

PC14-

OSC32_IN

PC13-

TAMPER-

RTC

B

PC15-

OSC32_OUT

VBAT

PE2

PE3

PB9

PB8

PB7

PB6

PB4

PD5

PB3

PD2

PA15

PC11

PA14

PC10

PA13

PA12

C OSC_IN VSS_5 PE4 PE1 PB5 PD6 PD3 PC12 PA9 PA11

D OSC_OUT VDD_5 PE5 PE0 BOOT0 PD7 PD4 PD0

E NRST PC2

PA8 PA10

PC9 PC7

F PC0 PC1

PE6 VSS_4 VSS_3 VSS_2 VSS_1 PD1

PC3 VDD_4 VDD_3 VDD_2 VDD_1 NC PC8 PC6

G VSSA PA0-WKUP PA4 PC4 PB2 PE10 PE14 PB15 PD11 PD15

H VREF– PA1 PA5 PC5 PE7 PE11 PE15 PB14 PD10 PD14

J VREF+ PA2 PA6 PB0 PE8 PE12 PB10 PB13 PD9 PD13

K VDDA PA3 PA7 PB1 PE9 PE13 PB11 PB12 PD8 PD12

AI14601c

1. The above figure shows the package top view.

26/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions

Figure 5. STM32F103xC/D/E performance line LQFP144 pinout

0%

0%

0%

0%

0%

6"!4

0#4!-0%224#

0#/3#?).

0#/3#?/54

0&

0&

0&

0&

0&

0&

6

33?

6

$$?

0&

0&

0&

0&

0&

/3#?).

/3#?/54

.234

0#

0#

0#

0#

6

33!

6

2%&

6

2%&

6

$$!

0! 7+50

0!

0!

,1&0

1. The above figure shows the package top view.

6

$$?

6

33?

0'

0'

0'

0'

0'

0'

0'

0$

0$

6

$$?

6

33?

0$

0$

0$

0$

0$

0$

0"

0"

0"

0"

0!

0!

0#

0#

0#

0#

6

$$?

6

33?

.#

0!

0!

0!

0!

AI

DS5792 Rev 13

27/143

135

Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE

Figure 6. STM32F103xC/D/E performance line LQFP100 pinout

0%

0%

0%

0%

0%

6"!4

0#4!-0%224#

0#/3#?).

0#/3#?/54

633?

6$$?

/3#?).

/3#?/54

.234

0#

0#

0#

0#

633!

62%&

62%&

6$$!

0!7+50

0!

0!

,1&0

0#

0#

0$

0$

0$

0$

0$

0$

0$

0$

0"

0"

0"

0"

6$$?

633?

.#

0!

0!

0!

0!

0!

0!

0#

0#

AI

1. The above figure shows the package top view.

28/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions

Figure 7. STM32F103xC/D/E performance line LQFP64 pinout s d

WϭϯͲdDWZͲZd

W ϭϰͲK ^ ϯϮͺ/E

W ϭϱͲK ^ ϯϮͺKh d

W ϬͲK^ ͺ/E

W ϭͲK^ ͺKhd

EZ^d

WϬ

Wϭ

WϮ

Wϯ s ^^ s

W ϬͲt< hW

W ϭ

W Ϯ ϭϬ ϭϭ ϭϮ ϱ ϲ ϳ

Ϯ ϯ ϭ ϲϰ ϲϯ ϲϮ ϲϭ ϲϬ ϱϵ ϱϴ ϱϳ ϱϲ ϱϱ ϱϰ ϱϯ ϱϮ ϱϭ ϱϬ ϰϵ ϰϴ ϰϳ ϰϲ ϰ ϰϱ ϰϰ ϰϯ

ϴ ϵ

>Y&Wϲϰ ϰϮ ϰϭ ϰϬ ϯϵ ϯϴ ϯϳ ϭϯ ϭϰ ϯϲ ϯϱ ϯϰ ϭϱ ϭϲ ϭϳ ϭϴ ϭϵ ϮϬ Ϯϭ ϮϮ Ϯϯ Ϯϰ Ϯϱ Ϯϲ Ϯϳ Ϯϴ ϯϯ

Ϯϵ ϯϬ ϯϭ ϯϮ

W ϵ

W ϴ

Wϵ

Wϴ

Wϳ

Wϲ s ͺϮ s

^^ͺϮ

W ϭϯ

W ϭϮ

W ϭϭ

W ϭϬ

W ϭϱ

W ϭϰ

W ϭϯ

W ϭϮ

DL

1. The above figure shows the package top view.

DS5792 Rev 13

29/143

135

Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE

8

Figure 8. STM32F103xC/D/E performance line

WLCSP64 ballout, ball side

7 6 5 4 3 2 1

E

F

G

H

A

B

C

D

VDD_3

VSS_3 BOOT0 PB5 PB3 PD2 PC10

VDD_2

PC14 PC15 PB9 PB6

PC13 NRST VBAT PB7

PB4 PC11 PA14

BYPASS/

VSS_2

PC12 PA15 PA12 PA11

OSC_IN OSC_OUT PC2 PB8 PA13 PA10 PA9 PC9

PC0 VSSA PA1 PA5

PC1 VREF+

PA0-

WKUP

VSS_4

PA8 PC8 PC7

PB1 PB11 PB14

VDDA

PA3

VDD_4

PA6 PA7 PB10 PB12

PC6

PB15

PB13

PA2

PA4 PC4 PC5 PB0 PB2 VSS_1 VDD_1 ai15460b

30/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE

Pins

Pinouts and pin descriptions

Table 5. High-density STM32F103xC/D/E pin definitions

Alternate functions

(4)

Pin name

Main function

(3)

(after reset) Default Remap

A3 A3

A2 B3

B2 C3

B3 D3

-

-

-

-

-

-

-

-

B4 E3 5

C2 B2 C6 1 6

A1

B1

A2

A1

C8

B8

2

3

3

4

1

2

7

8

3

4

1

2

5

6

7

8

C1 B1 B7 4 9 9

C3

C4

D4

E2

E3

E4

D2 C2

D3 D2

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

14

15

10 16

11 17

10

11

12

13

F3

F2

G3

G2

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

G1 22

D1 C1 D8 5 12 23

E1 D1 D7 6 13 24

F1 E1 C7 7 14 25

18

19

20

21

H1

H2

F1

F2

E8

F8

8

9

15

16

26

27

H3 E2 D6 10 17 28

PF7

PF8

PF9

PF10

OSC_IN

OSC_OUT

NRST

PC0

PC1

PC2

PF0

PF1

PF2

PF3

PF4

PF5

V

SS_5

V

DD_5

PF6

PE2

PE3

PE4

PE5

PE6

V

BAT

PC13-TAMPER-

RTC

(5)

PC14-

OSC32_IN

(5)

PC15-

OSC32_OUT

(5)

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

S -

I/O

I/O

I/O

-

-

-

I/O

I

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

S

S

-

-

-

-

-

-

-

-

-

-

-

-

-

PE2

PE3

PE4

PE5

PE6

V

BAT

PC13

PC14

(6)

(6)

PC15

(6)

PF7

PF8

PF9

PF10

OSC_IN

OSC_OUT

NRST

PC0

PC1

PC2

PF0

PF1

PF2

PF3

PF4

PF5

V

SS_5

V

DD_5

PF6

TRACECK/ FSMC_A23

TRACED0/FSMC_A19

TRACED1/FSMC_A20

TRACED2/FSMC_A21

TRACED3/FSMC_A22

-

TAMPER-RTC

OSC32_IN

OSC32_OUT

FSMC_A0

FSMC_A1

FSMC_A2

FSMC_A3

FSMC_A4

FSMC_A5

-

-

ADC3_IN4/FSMC_NIORD

ADC3_IN5/FSMC_NREG

ADC3_IN6/FSMC_NIOWR

ADC3_IN7/FSMC_CD

ADC3_IN8/FSMC_INTR

-

-

-

ADC123_IN10

ADC123_IN11

ADC123_IN12

DS5792 Rev 13

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

31/143

135

Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE

Pins

Table 5. High-density STM32F103xC/D/E pin definitions (continued)

Alternate functions (4)

Pin name

Main function

(3)

(after reset) Default Remap

H4

J1

F3

K1 H1

11 18 29

G1 E7 12 19 30

20 31

L1 J1

-

F7

(8)

21 32

M1 K1 G8 13 22 33

J2 G2 F6 14 23 34

PC3

(7)

V

SSA

V

REF-

V

REF+

V

DDA

PA0-WKUP

I/O

S

S

S

S

-

-

-

-

-

I/O -

K2

L2

H2 E6 15 24 35

M2 K2 G7 17 26 37

G4 E4 F5 18 27 38

F4 F4 G6 19 28 39

J3

K3

L3

M3

J2

G3 H7 20 29 40

H3

J3

K3

H8 16

E5 21

G5 22

G4 23

25

30

31

32

36

41

42

43

J4 G4 H6 24 33 44

K4 H4 H5 25 34 45

L4

M4

J4 H4 26 35 46

K4 F4 27 36 47

PA1

PA2

PA3

V

SS_4

V

DD_4

PA4

PA5

PA6

PA7

PC4

PC5

PB0

PB1

I/O -

I/O -

I/O

I/O

I/O

-

-

-

I/O -

I/O -

I/O

S

S

-

-

-

I/O -

I/O -

I/O -

PA7

PC4

PC5

PB0

PB1

PA2

PA3

V

SS_4

V

DD_4

PA4

PA5

PA6

PC3

V

SSA

V

REF-

V

REF+

V

DDA

PA0

PA1

ADC123_IN13

-

-

-

-

-

-

-

-

WKUP/USART2_CTS

(9)

ADC123_IN0

TIM2_CH1_ETR

TIM5_CH1/TIM8_ETR

USART2_RTS

(9)

ADC123_IN1/

TIM5_CH2/TIM2_CH2

(9)

USART2_TX

(9)

/TIM5_CH3

ADC123_IN2/

TIM2_CH3

(9)

USART2_RX

(9)

/TIM5_CH4

ADC123_IN3/TIM2_CH4

(9)

-

-

SPI1_NSS

(9)

USART2_CK

/

(9)

DAC_OUT1/ADC12_IN4

SPI1_SCK

(9)

DAC_OUT2 ADC12_IN5

SPI1_MISO

(9)

TIM8_BKIN/ADC12_IN6

TIM3_CH1

(9)

SPI1_MOSI

(9)

/

TIM8_CH1N/ADC12_IN7

TIM3_CH2

(9)

-

-

-

-

-

-

-

-

-

TIM1_BKIN

TIM1_CH1N

ADC12_IN14 -

ADC12_IN15 -

ADC12_IN8/TIM3_CH3

TIM8_CH2N

ADC12_IN9/TIM3_CH4

(9)

TIM8_CH3N

TIM1_CH2N

TIM1_CH3N

32/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions

Pins

Table 5. High-density STM32F103xC/D/E pin definitions (continued)

Alternate functions (4)

Pin name

Main function

(3)

(after reset) Default Remap

G5

K5

M6

L6

J5

M5

L5

H5

K6

J6

M7 H5

L7 J5

-

-

K7 K5

H6 -

G6

J7

-

G6 -

-

-

-

-

-

-

-

-

-

-

-

-

G5 H3 28 37 48

49

-

-

-

-

-

-

50

51

-

-

-

-

-

-

-

-

-

-

-

-

52

53

54

55

-

-

-

-

-

-

-

-

-

38

39

40

-

-

56

57

58

59

60

61

62

41 63

H8 H6

J8 J6

K8 K6

L8 G7

-

-

-

-

42 64

43 65

44 66

45 67

M8 H7 46 68

M9 J7 G3 29 47 69

M10 K7 F3 30 48 70

H7 E7 H2 31 49 71

G7 F7 H1 32 50 72

M11 K8 G2 33 51 73

M12 J8 G1 34 52 74

PE11

PE12

PE13

PE14

PE15

PB10

PB11

V

SS_1

V

DD_1

PE7

PE8

PE9

V

SS_7

V

DD_7

PE10

PB2

PF11

PF12

V

SS_6

V

DD_6

PF13

PF14

PF15

PG0

PG1

PB12

PB13

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

S -

S -

I/O FT

I/O FT

I/O FT

S -

S -

I/O FT

I/O FT

I/O FT

I/O FT PB2/BOOT1

I/O FT PF11

I/O FT

S -

S

I/O

-

FT

PF12

V

SS_6

V

DD_6

PF13

I/O FT

I/O FT

I/O FT

I/O FT

PF14

PF15

PG0

PG1

PE7

PE8

PE9

V

SS_7

V

DD_7

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

V

SS_1

V

DD_1

I/O

I/O

FT

FT

PB12

PB13

-

FSMC_NIOS16

FSMC_A6

-

-

FSMC_A7

FSMC_A8

FSMC_A9

FSMC_A10

FSMC_A11

FSMC_D4

FSMC_D5

FSMC_D6

-

-

FSMC_D7

FSMC_D8

FSMC_D9

FSMC_D10

FSMC_D11

FSMC_D12

I2C2_SCL/USART3_TX

(9)

I2C2_SDA/USART3_RX

(9)

-

-

SPI2_NSS/I2S2_WS/

I2C2_SMBA/

USART3_CK

(9)

/

TIM1_BKIN

(9)

SPI2_SCK/I2S2_CK

USART3_CTS

(9)

/

TIM1_CH1N

-

-

TIM1_ETR

TIM1_CH1N

TIM1_CH1

-

-

TIM1_CH2N

-

-

-

-

-

-

-

-

TIM1_CH2

TIM1_CH3N

TIM1_CH3

TIM1_CH4

TIM1_BKIN

TIM2_CH3

TIM2_CH4

-

-

-

-

DS5792 Rev 13

33/143

135

Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE

Pins

Table 5. High-density STM32F103xC/D/E pin definitions (continued)

Alternate functions (4)

Pin name

Main function

(3)

(after reset) Default Remap

L11 H8 F2 35 53 75

L12 G8 F1 36 54 76

L9

K9

K9

J9

J9 H9 -

H9 G9 -

-

-

L10 K10 -

55 77

56 78

57 79

58 80

59 81

H12

H11

H10

G11

G10

F10

K10 J10 -

G8 -

F8 -

K11 H10 -

K12 G10 -

J12 -

J11

J10

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

G12 F10 E1 37 63 96

-

-

-

-

-

-

60 82

83

84

61 85

-

-

62 86

87

-

-

88

89

-

-

-

-

-

-

90

91

92

93

94

95

F12 E10 E2 38 64 97

F11 F9 E3 39 65 98

E11 E9 D1 40 66 99

E12 D9 E4 41 67 100

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

S -

S -

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

S

S

-

-

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

PB14

PB15

PD8

PD9

PD10

PD11

PD12

PD13

V

SS_8

V

DD_8

PD14

PD15

PG2

PG3

PG4

PG5

PG6

PG7

PG8

V

SS_9

V

DD_9

PC6

PC7

PC8

PC9

PA8

PB14

PB15

PD8

PD9

PD10

PD11

PD12

PD13

V

SS_8

V

DD_8

PD14

PD15

PG2

PG3

PG4

PG5

PG6

PG7

PG8

V

SS_9

V

DD_9

PC6

PC7

PC8

PC9

PA8

SPI2_MISO/TIM1_CH2N

USART3_RTS

(9)

/

SPI2_MOSI/I2S2_SD

TIM1_CH3N

(9)

/

FSMC_D13

FSMC_D14

FSMC_D15

FSMC_A16

FSMC_A17

FSMC_A18

-

-

FSMC_D0

FSMC_D1

FSMC_A12

FSMC_A13

FSMC_A14

FSMC_A15

FSMC_INT2

FSMC_INT3

-

-

-

I2S2_MCK/

TIM8_CH1/SDIO_D6

I2S3_MCK/

TIM8_CH2/SDIO_D7

TIM8_CH3/SDIO_D0

TIM8_CH4/SDIO_D1

USART1_CK/

TIM1_CH1

(9)

/MCO

-

-

USART3_TX

USART3_RX

USART3_CK

USART3_CTS

TIM4_CH1 /

USART3_RTS

TIM4_CH2

-

-

TIM4_CH3

TIM4_CH4

-

-

-

-

-

-

-

-

-

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

-

34/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions

Pins

Table 5. High-density STM32F103xC/D/E pin definitions (continued)

Alternate functions (4)

Pin name

Main function

(3)

(after reset) Default Remap

D12 C9 D2 42 68 101

D11 D10 D3 43 69 102

C12 C10 C1 44 70 103

B12 B10 C2 45 71 104

A12 A10 D4 46 72 105

C11 F8 73 106

G9 E6 B1 47 74 107

F9 F6 A1 48 75 108

A11 A9 B2 49 76 109

A10 A8 C3 50 77 110

B11 B9 A2 51 78 111

B10 B8 B3 52 79 112

C10 C8 C4 53 80 113

E10 D8 D8 5 81 114

D10 E8 D7 6 82 115

E9 B7 A3 54 83 116

D9 C7

C9 D7

B9 B6

E7 -

F7 -

A8 C6

A9 D6

E8 -

D8 -

-

-

-

-

-

-

-

-

-

84 117

85 118

86 119

120

121

87 122

88 123

124

125

PA9

PA10

PA11

PA12

PA13

V

SS_2

V

DD_2

PA14

PA15

PD3

PD4

PD5

V

SS_10

V

DD_10

PD6

PD7

PG9

PG10

PC10

PC11

PC12

PD0

PD1

PD2

I/O FT

I/O FT

I/O FT

S -

S -

I/O FT

I/O FT

I/O FT

I/O FT

I/O

I/O

I/O

I/O

I/O

I/O

FT

FT

FT

FT

FT

I/O FT

I/O FT

FT

PA9

PA10

PA11

PA12

I/O FT JTMS-SWDIO

Not connected

S

S

-

-

V

SS_2

V

DD_2

I/O FT JTCK-SWCLK

JTDI

PC10

PC11

I/O FT

I/O FT

PC12

OSC_IN

(10)

I/O FT

OSC_OUT

(10)

PD2

PD3

PD4

PD5

V

SS_10

V

DD_10

PD6

PD7

PG9

PG10

USART1_TX

(9)

/

TIM1_CH2

(9)

USART1_RX

(9)

/

TIM1_CH3

(9)

USART1_CTS/USBDM

CAN_RX

(9)

/TIM1_CH4

(9)

USART1_RTS/USBDP/

CAN_TX

(9)

/TIM1_ETR

(9)

-

-

-

-

SPI3_NSS/

I2S3_WS

UART4_TX/SDIO_D2

UART4_RX/SDIO_D3

UART5_TX/SDIO_CK

FSMC_D2

(11)

FSMC_D3

(11)

TIM3_ETR/UART5_RX

SDIO_CMD

FSMC_CLK

FSMC_NOE

FSMC_NWE

-

-

FSMC_NWAIT

FSMC_NE1/FSMC_NCE2

FSMC_NE2/FSMC_NCE3

FSMC_NCE4_1/

FSMC_NE3

-

-

-

-

PA13

-

-

-

PA14

TIM2_CH1_ET

R PA15 /

SPI1_NSS

USART3_TX

USART3_RX

USART3_CK

CAN_RX

CAN_TX

-

USART2_CTS

USART2_RTS

USART2_TX

-

-

USART2_RX

USART2_CK

-

-

DS5792 Rev 13

35/143

135

Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE

Pins

Table 5. High-density STM32F103xC/D/E pin definitions (continued)

Alternate functions (4)

Pin name

Main function

(3)

(after reset) Default Remap

E6

F6

B7

C8

B8

D7

C7

A7

A6

-

-

-

-

-

-

-

A7

A6

-

-

-

-

-

-

-

-

-

-

-

-

-

-

A4 55

B4 56

-

-

-

-

-

-

-

89

90

126

127

128

129

130

131

132

133

134

PG11

PG12

PG13

PG14

V

V

SS_11

DD_11

PG15

PB3

PB4

I/O

I/O

I/O

I/O

S

S

I/O

I/O

I/O

FT

FT

FT

FT

-

-

FT

FT

FT

PG11

PG12

PG13

PG14

V

V

SS_11

DD_11

PG15

JTDO

NJTRST

FSMC_NCE4_2

FSMC_NE4

FSMC_A24

FSMC_A25

-

-

-

SPI3_SCK / I2S3_CK/

SPI3_MISO

B6

C6

D6

C5

B5

A5

A5 57

B5 58

C5 59

91

92

93

135

136

137

PB5

PB6

PB7

I/O

I/O

I/O

-

FT

FT

PB5

PB6

PB7

I2C1_SMBA/ SPI3_MOSI

I2S3_SD

I2C1_SCL

(9)

/ TIM4_CH1

(9)

I2C1_SDA

(9)

/ FSMC_NADV

/ TIM4_CH2

(9)

-

USART1_RX

D5

C5

B5

D5

B4

A4

A6 60

D5 61

B6 62

94

95

96

138

139

140

A5 D4

A4 C4

-

-

97 141

98 142

E5 E5 A7 63 99 143

F5 F5 A8 64

10

0

144

BOOT0

V

V

PB8

PB9

PE0

PE1

SS_3

DD_3

I

I/O

I/O

I/O

I/O

S

S

-

FT

FT

FT

FT

-

-

BOOT0

V

V

PB8

PB9

PE0

PE1

SS_3

DD_3

TIM4_CH3

TIM4_CH4

(9)

(9)

/SDIO_D4

/SDIO_D5

TIM4_ETR / FSMC_NBL0

FSMC_NBL1

-

-

-

I2C1_SCL/

CAN_RX

I2C1_SDA /

CAN_TX

-

-

-

-

1. I = input, O = output, S = supply.

2. FT = 5 V tolerant.

3. Function availability depends on the chosen device.

4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).

-

-

-

-

-

-

-

PB3/TRACES

WO

TIM2_CH2 /

SPI1_SCK

PB4 /

TIM3_CH1

SPI1_MISO

TIM3_CH2 /

SPI1_MOSI

USART1_TX

36/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions

5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of

30 pF and these IOs must not be used as a current source (e.g. to drive an LED).

6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the

STMicroelectronics website: www.st.com.

7. In the WCLSP64 package, the PC3 I/O pin is not bonded and it must be configured by software to output mode (Push-pull) and writing 0 to the data register in order to avoid an extra consumption during low-power modes.

8. Unlike in the LQFP64 package, there is no PC3 in the WLCSP package. The V

REF+

functionality is provided instead.

9. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.

10. For the WCLSP64/LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100/BGA100 and

LQFP144/BGA144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.

11. For devices delivered in LQFP64 packages, the FSMC function is not available.

DS5792 Rev 13

37/143

135

Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE

Pins

PG1

PE7

PE8

PE9

PE10

PE11

PF11

PF12

PF13

PF14

PF15

PG0

PE12

PE13

PE14

PE15

PD8

PF3

PF4

PF5

PF6

PF7

PF8

PF9

PF10

PE6

PF0

PF1

PF2

PE2

PE3

PE4

PE5

CF CF/IDE

-

A0

A1

A2

-

-

-

-

A3

A4

A5

NIORD

NREG

-

-

-

NIORD

NREG

NIOWR NIOWR

CD CD

INTR INTR

-

A0

A1

A2

-

-

-

-

-

D4

D5

D6

D7

D8

NIOS16 NIOS16

A6 -

A7 -

A8

A9

A10

-

-

-

-

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D9

D10

D11

D12

D13

Table 6. FSMC pin definition

FSMC

NOR/PSRAM/

SRAM

NOR/PSRAM Mux NAND 16 bit

A11

D4

D5

D6

D7

D8

-

A6

A7

A8

A9

A10

D9

D10

D11

D12

D13

A3

A4

A5

-

-

-

-

-

A22

A0

A1

A2

A23

A19

A20

A21

-

DA4

DA5

DA6

DA7

DA8

-

-

-

-

-

-

DA9

DA10

DA11

DA12

DA13

-

-

-

-

-

-

-

-

A22

-

-

-

A23

A19

A20

A21

-

D4

D5

D6

D7

D8

-

-

-

-

-

-

D9

D10

D11

D12

D13

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

LQFP100

BGA100

(1)

-

Yes

Yes

Yes

Yes

Yes

-

-

-

-

-

-

Yes

Yes

Yes

Yes

Yes

-

-

-

-

-

-

-

-

Yes

-

-

-

Yes

Yes

Yes

Yes

38/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions

Table 6. FSMC pin definition (continued)

FSMC

Pins

CF CF/IDE

-

-

-

-

-

D2

-

D0

D1

-

D14

D15

-

-

D3

-

NOE

NWE

NWAIT

-

D3

-

NOE

NWE

NWAIT

-

-

NCE4_1 NCE4_1

NCE4_2 NCE4_2

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

D2

-

D0

D1

-

D14

D15

-

-

PG9

PG10

PG11

PG12

PG13

PG14

PD1

PD3

PD4

PD5

PD6

PD7

PB7

PE0

PE1

PG3

PG4

PG5

PG6

PG7

PD0

PD9

PD10

PD11

PD12

PD13

PD14

PD15

PG2

1. Ports F and G are not available in devices delivered in 100-pin packages.

NE2

NE3

-

NE4

A24

A25

D3

CLK

NOE

NWE

NWAIT

NE1

NADV

NBL0

NBL1

A13

A14

A15

-

-

D2

A18

D0

D1

A12

D14

D15

A16

A17

NE2

NE3

-

NE4

A24

A25

DA3

CLK

NOE

NWE

NWAIT

NE1

NADV

NBL0

NBL1

-

-

-

-

-

DA2

DA14

DA15

A16

A17

A18

DA0

DA1

-

NOR/PSRAM/

SRAM

NOR/PSRAM Mux NAND 16 bit

NCE3

-

-

-

-

-

D3

-

NOE

NWE

NWAIT

NCE2

-

-

-

-

-

-

INT2

INT3

D2

-

D0

D1

-

D14

D15

CLE

ALE

LQFP100

BGA100

(1)

-

-

-

-

-

-

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

-

-

-

-

-

Yes

Yes

Yes

Yes

-

Yes

Yes

Yes

Yes

DS5792 Rev 13

39/143

135

Memory mapping STM32F103xC, STM32F103xD, STM32F103xE

40/143

The memory map is shown in

Figure 9 .

0xFFFF FFFF

512-Mbyte

block 7

Cortex-M3's internal peripherals 0xE000 0000

0xDFFF FFFF

512-Mbyte

block 6

Not used

0xC000 0000

0xBFFF FFFF

512-Mbyte

block 5

FSMC register

0xA000 0000

0x9FFF FFFF

512-Mbyte

block 4

FSMC bank 3

& bank4

0x8000 0000

0x7FFF FFFF

512-Mbyte

block 3

FSMC bank1

& bank2

0x6000 0000

0x5FFF FFFF

512-Mbyte

block 2

Peripherals

0x4000 0000

0x3FFF FFFF

512-Mbyte

block 1

SRAM

0x2000 0000

0x1FFF FFFF

512-Mbyte

block 0

Code

0x0000 0000

Figure 9. Memory map

Reserved

SRAM (64 KB aliased by bit-banding)

Option Bytes

System memory

Reserved

Flash

Reserved

Aliased to Flash or system memory depending on

BOOT pins

Reserved

FSMC register

FSMC bank4 PCCARD

FSMC bank3 NAND (NAND2)

FSMC bank2 NAND (NAND1)

FSMC bank1 NOR/PSRAM 4

FSMC bank1 NOR/PSRAM 3

FSMC bank1 NOR/PSRAM 2

FSMC bank1 NOR/PSRAM 1

Reserved

CRC

Reserved

Flash interface

Reserved

RCC

Reserved

DMA2

DMA1

Reserved

SDIO

Reserved

ADC3

USART1

TIM8

SPI1

TIM1

ADC2

ADC1

Port G

Port F

Port E

Port D

Port C

Port B

Port A

EXTI

AFIO

Reserved

DAC

PWR

BKP

Reserved

BxCAN

Shared USB/CAN SRAM 512 bytes

USB registers

I2C2

I2C1

UART5

UART4

USART3

USART2

Reserved

SPI3/I 2 S3

SPI2/I 2 S2

Reserved

IWDG

WWDG

RTC

Reserved

TIM7

TIM6

TIM5

TIM4

TIM3

TIM2

0x3FFF FFFF

0x2001 0000

0x2000 FFFF

0xA000 1000 - 0xBFFF FFFF

0xA000 0000 - 0xA000 0FFF

0x9000 0000 - 0x9FFF FFFF

0x8000 0000 - 0x8FFF FFFF

0x7000 0000 - 0x7FFF FFFF

0x6C00 0000 - 0x6FFF FFFF

0x6800 0000 - 0x6BFF FFFF

0x6400 0000 - 0x67FF FFFF

0x6000 0000 - 0x63FF FFFF

0x4002 4400 - 0x5FFF FFFF

0x4002 3000 - 0x4002 33FF

0x4002 2400 - 0x4002 2FFF

0x4002 2000 - 0x4002 23FF

0x4002 1400 - 0x4002 1FFF

0x4002 1000 - 0x4002 13FF

0x4002 0400 - 0x4002 0FFF

0x4002 0400 - 0x4002 07FF

0x4002 0000 - 0x4002 03FF

0x4001 8400 - 0x4001 FFFF

0x4001 8000 - 0x4001 83FF

0x4001 400 - 0x4001 7FFF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2C00 - 0x4001 2FFF

0x4001 2800 - 0x4001 2BFF

0x4001 2400 - 0x4001 27FF

0x4001 2000 - 0x4001 23FF

0x4001 1C00 - 0x4001 1FFF

0x4001 1800 - 0x4001 1BFF

0x4001 1400 - 0x4001 17FF

0x4001 1000 - 0x4001 13FF

0x4001 0C00 - 0x4001 0FFF

0x4001 0800 - 0x4001 0BFF

0x4001 0400 - 0x4001 07FF

0x4001 0000 - 0x4001 03FF

0x4000 7800 - 0x4000 FFFF

0x4000 7400 - 0x4000 77FF

0x4000 7000 - 0x4000 73FF

0x4000 6C00 - 0x4000 6FFF

0x4000 6800 - 0x4000 6BFF

0x4000 6400 - 0x4000 67FF

0x4000 6000 - 0x4000 63FF

0x4000 5C00 - 0x4000 5FFF

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 5000 - 0x4000 53FF

0x4000 4C00 - 0x4000 4FFF

0x4000 4800 - 0x4000 4BFF

0x4000 4400 - 0x4000 47FF

0x4000 4000 - 0x4000 43FF

0x4000 3C00 - 0x4000 3FFF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 1800 - 0x4000 27FF

0x4000 1400 - 0x4000 17FF

0x4000 1000 - 0x4000 13FF

0x4000 0C00 - 0x4000 0FFF

0x4000 0800 - 0x4000 0BFF

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 03FF

0x2000 0000

0x1FFF F800 - 0x1FFF F80F

0x1FFF F000- 0x1FFF F7FF

0x1FFF EFFF

0x0808 0000

0x0807 FFFF

0x0800 0000

0x07FF FFFF

0x0008 0000

0x0007 FFFF

0x0000 0000 ai14753d

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

5.1.1

Unless otherwise specified, all voltages are referenced to V

SS

.

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

A

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 Σ ).

Unless otherwise specified, typical data are based on T

A

2 V ≤ V tested.

DD

= 25 °C, V

DD

= 3.3 V (for the

≤ 3.6 V voltage range). They are given only as design guidelines and are not

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2 Σ )

.

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.5

The loading conditions used for pin parameter measurement are shown in

Figure 10

.

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 11 .

Figure 10. Pin loading conditions Figure 11. Pin input voltage

-#5PIN

-#5PIN

#P& 6).

-36

-36

DS5792 Rev 13

41/143

135

Electrical characteristics

5.1.6 Power supply scheme

ϭ͘ϴͲϯ͘ϲs

STM32F103xC, STM32F103xD, STM32F103xE

Figure 12. Power supply scheme sd

WŽ ǁĞƌƐǁŝ ƚĐŚ

ĂĐŬƵƉĐŝƌĐƵŝƚƌLJ

;K^ϯϮ<͕Zd͕ tĂŬĞͲƵƉůŽŐŝĐ

ĂĐŬƵƉƌĞŐŝƐƚĞƌƐͿ

' W /ͬK Ɛ

K hd

/E

/K

>ŽŐŝĐ ϭϭп ϭ ϬϬŶ& нϭп ϰ͘ϳђ& s sϭͬϮͬͬ͘͘͘ϭϭ s^^ϭͬϮͬͬ͘͘͘ϭϭ s s sZ& sZ&н ϭϬŶ& нϭђ& ϭϬŶ& нϭђ& sZ&Ͳ s^^

Z ĞŐ ƵůĂƚŽƌ

ͬ ŶĂůŽŐ͗

ZƐ͕W>>͕

͘͘͘

Caution: In

Figure 12 , the 4.7 µF capacitor must be connected to V

DD3

.

<ĞƌŶĞůůŽŐŝĐ

;Wh͕ ŝŐŝƚĂů

ΘDĞŵŽƌŝĞƐͿ

ĂŝϭϱϰϬϭ

Figure 13. Current consumption measurement scheme

,''B9%$7

9%$7

,''

9''

9''$

DL

42/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE

5.2 Absolute maximum ratings

Electrical characteristics

Stresses above the absolute maximum ratings listed in

Table 7: Voltage characteristics ,

Table 8: Current characteristics , and

Table 9: Thermal characteristics

may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 7. Voltage characteristics

Ratings Min Max Unit

V

|V

|

DD

V

Δ

IN

(2)

V

SSX

–V

SS

DDx

− V

|

SS

|

External main supply voltage (including V

DDA and V

DD

)

(1)

Input voltage on five volt tolerant pin

Input voltage on any other pin

Variations between different V

DD power pins

Variations between all the different ground pins (3)

V

–0.3

SS

V

SS

-

-

− 0.3

− 0.3

4.0

V

DD

+ 4.0

4.0

50

50

V mV

V

ESD(HBM)

Electrostatic discharge voltage (human body model) see

Section 5.3.12:

Absolute maximum ratings

(electrical sensitivity)

1. All main power (V , V

DDA

) and ground (V supply, in the permitted range.

SS

, V

SSA

) pins must always be connected to the external power

2. V

IN

maximum must always be respected. Refer to Table 8: Current characteristics for the maximum

allowed injected current values.

3. Include V

REF-

pin.

-

Symbol

Table 8. Current characteristics

Ratings Max.

Unit

I

I

VDD

VSS

Total current into V

DD

/V

DDA power lines (source)

(1)

Total current out of V

SS ground lines (sink)

(1)

Output current sunk by any I/O and control pin

150

150

I

IO

I

INJ(PIN)

(2)

Output current source by any I/Os and control pin

Injected current on five volt tolerant pins

(3)

Injected current on any other pin

(4)

Total injected current (sum of all I/O and control pins)

(5)

−

25

25

-5/+0

± 5 mA

Σ I

INJ(PIN)

± 25

1. All main power (V , V

DDA

) and ground (V supply, in the permitted range.

SS

, V

SSA

) pins must always be connected to the external power

2. Negative injection disturbs the analog performance of the device. See note 3 below Table 62 on page 108 .

3. Positive injection is not possible on these I/Os. A negative injection is induced by V values.

IN

<V

SS

. I

INJ(PIN)

must

never be exceeded. Refer to Table 7: Voltage characteristics

for the maximum allowed input voltage

4. A positive injection is induced by V

never be exceeded. Refer to

values.

>V

DD

while a negative injection is induced by V

Table 7: Voltage characteristics

IN

<V

SS

. I

for the maximum allowed input voltage

must

5. When several inputs are submitted to a current injection, the maximum Σ I positive and negative injected currents (instantaneous values).

INJ(PIN)

is the absolute sum of the

DS5792 Rev 13

43/143

135

Electrical characteristics

Symbol

T

STG

T

J

STM32F103xC, STM32F103xD, STM32F103xE

Table 9. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

Unit

°C

°C

5.3.1 General operating conditions

Symbol

Table 10. General operating conditions

Parameter Conditions Min Max Unit f f

V f

HCLK

PCLK1

PCLK2

V

V

DD

DDA

(1)

BAT

P

T

T

D

A

J

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Standard operating voltage

Analog operating voltage

(ADC not used)

Analog operating voltage

(ADC used)

Backup operating voltage

Power dissipation at T

85 °C for suffix 6 or T

A

105 °C for suffix 7

(3)

A

=

=

Ambient temperature for 6 suffix version

Ambient temperature for 7 suffix version

Junction temperature range

-

-

-

-

Must be the same potential as V

DD

(2)

2

2.4

-

LQFP144

LQFP100

LQFP64

LFBGA100

LFBGA144

WLCSP64

Maximum power dissipation -40

Low-power dissipation

(4)

-40

Maximum power dissipation -40

Low-power dissipation

(4)

-40

6 suffix version -40

7 suffix version -40

-

-

-

1.8

-

-

-

0

2

0

0

72

36

72

3.6

3.6

3.6

MHz

V

V

V mW

°C

°C

°C

1. When the ADC is used, refer to Table 59: ADC characteristics .

2. It is recommended to power V between V

DD

and V

DDA

DD

and V

DDA

from the same source. A maximum difference of 300 mV

can be tolerated during power-up and operation.

3. If T is lower, higher P

D

values are allowed as long as T

characteristics on page 132

).

J

does not exceed T

J

max (see Table 6.7: Thermal

4. In low-power dissipation state, T can be extended to this range as long as T

Table 6.7: Thermal characteristics on page 132

).

J

does not exceed T

J max (see

500

500

400

85

105

105

3.6

666

434

444

125

105

125

44/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

5.3.3

The parameters given in

Table 11

are derived from tests performed under the ambient temperature condition summarized in

Table 10 .

Symbol t

VDD

Table 11. Operating conditions at power-up / power-down

Parameter Conditions Min Max

V

DD

rise time rate

V

DD

fall time rate

-

0

20

∞

∞

Unit

µs/V

Embedded reset and power control block characteristics

The parameters given in

Table 12 are derived from tests performed under ambient

temperature and V

DD

supply voltage conditions summarized in

Table 10 .

Symbol

Table 12. Embedded reset and power control block characteristics

Parameter Conditions Min Typ Max Unit

V

PVD

PLS[2:0]=000 (rising edge)

PLS[2:0]=000 (falling edge)

PLS[2:0]=001 (rising edge)

PLS[2:0]=001 (falling edge)

PLS[2:0]=010 (rising edge)

PLS[2:0]=010 (falling edge)

PLS[2:0]=011 (rising edge)

PLS[2:0]=011 (falling edge)

Programmable voltage detector level selection

PLS[2:0]=100 (rising edge)

PLS[2:0]=100 (falling edge)

PLS[2:0]=101 (rising edge)

2.1

2

2.18

2.08

2.19 2.28

2.09 2.18

2.28 2.38

2.26

2.16

2.37

2.27

2.48

2.18 2.28

2.38

2.38 2.48

2.58

2.28 2.38

2.48

2.47 2.58

2.69

2.37 2.48

2.59

2.57 2.68

2.79

PLS[2:0]=101 (falling edge)

PLS[2:0]=110 (rising edge)

PLS[2:0]=110 (falling edge)

2.47 2.58

2.66 2.78

2.56 2.68

2.69

2.9

2.8

PLS[2:0]=111 (rising edge) 2.76 2.88

3

PLS[2:0]=111 (falling edge) 2.66 2.78

2.9

V

PVDhyst

(2)

V

POR/PDR

PVD hysteresis

Power on/power down reset threshold

-

Falling edge

Rising edge

-

1.8

(1)

100

1.88

-

1.96

1.84 1.92

2.0

V

PDRhyst

(2)

T

RSTTEMPO

(2)

PDR hysteresis

Reset temporization -

-

1

1. The product behavior is guaranteed by design down to the minimum V

POR/PDR

value.

2. Guaranteed by design.

40

2.5

-

4.5

V mV

V mV ms

DS5792 Rev 13

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135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

5.3.5

The parameters given in

Table 13 are derived from tests performed under ambient

temperature and V

DD

supply voltage conditions summarized in

Table 10 .

Symbol

Table 13. Embedded internal reference voltage

Parameter Conditions Min Typ Max Unit

V

REFINT

Internal reference voltage

–40 °C < T

A

< +105 °C 1.16 1.20

1.26

–40 °C < T

A

< +85 °C 1.16 1.20

1.24

T

S_vrefint

(1)

ADC sampling time when reading the internal reference voltage

-

V

RERINT

(2)

Internal reference voltage spread over the temperature range

V

DD

= 3 V ±10 mV -

T

Coeff

(2)

Temperature coefficient -

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design.

-

-

5.1

17.1

10

100

(2)

V

µs mV ppm/°C

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 13: Current consumption measurement scheme

.

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code.

Maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at V

DD

or V

SS

(no load)

• All peripherals are disabled except when explicitly mentioned

• The Flash memory access time is adjusted to the f

HCLK

frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above)

• Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)

• When the peripherals are enabled f

PCLK1

= f

HCLK

/2, f

PCLK2

= f

HCLK

The parameters given in

Table 14 , Table 15

and Table 16

are derived from tests performed under ambient temperature and V

DD

supply voltage conditions summarized in

Table 10 .

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DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Table 14. Maximum current consumption in Run mode, code with data processing running from Flash

Max

(1)

Symbol Parameter Conditions f

HCLK

Unit

T

A

= 85 °C T

A

= 105 °C

72 MHz 69 70

I

DD

External clock

(2)

, all peripherals enabled

48 MHz

36 MHz

24 MHz

16 MHz

Supply current in

Run mode

External clock

(2)

, all peripherals disabled

8 MHz

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

11

37

28

22

50

39

27

20

16.5

12.5

8

11.5

37.5

28.5

22.5

50.5

39.5

28

20.5

17

13

8 mA

1. Guaranteed by characterization results.

2. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

CIAO Table 15. Maximum current consumption in Run mode, code with data processing running from RAM

Max

(1)

Symbol Parameter Conditions f

HCLK

Unit

T

A

= 85 °C T

A

= 105 °C

I

DD

Supply current in Run mode

External clock (2) , all peripherals enabled

External clock

(2) , all

peripherals disabled

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

66

43.5

33

23

16

9

33

23

18

13

10

6

67

45.5

35

24.5

18

10.5

33.5

23.5

18.5

13.5

10.5

6.5

mA

1. Guaranteed by characterization results at V

DD max, f

HCLK

max.

2. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

DS5792 Rev 13

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135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled

-(Z

-(Z

-(Z

-(Z

-(Z

-(Z

4EMPERATURE #

AI

Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V)code with data processing running from RAM, peripherals disabled

-(Z

-(Z

-(Z

-(Z

-(Z

-(Z

4EMPERATURE #

AI

48/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Table 16. Maximum current consumption in Sleep mode, code running from Flash or

RAM

Max

(1)

Symbol Parameter Conditions f

HCLK

Unit

T

A

= 85 °C T

A

= 105 °C

72 MHz 45 46

I

DD

Supply current in Sleep mode

External clock

(2)

, all peripherals enabled

External clock

(2)

, all

peripherals disabled

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

8

8.5

7

6

31

24

17

12.5

5

4.5

4

8

9

7.5

6.5

32

25

17.5

13

5.5

5

4 mA

1. Guaranteed by characterization results at V

DD max, f

HCLK

max with peripherals enabled.

2. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

DS5792 Rev 13

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135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Table 17. Typical and maximum current consumptions in Stop and Standby modes

Typ

(1)

Max

Symbol Parameter Conditions

V

DD

/V

BAT

= 2.0 V

V

DD

/V

BAT

= 2.4 V

V

DD

/V

BAT

= 3.3 V

T

A

=

85 °C

T

A

=

105 °C

Unit

I

DD

Supply current in

Stop mode

Supply current in

Standby mode

Regulator in run mode, lowspeed and high-speed internal

RC oscillators and high-speed oscillator OFF (no independent watchdog)

Regulator in low-power mode, low-speed and high-speed internal RC oscillators and highspeed oscillator OFF (no independent watchdog)

Low-speed internal RC oscillator and independent watchdog ON

Low-speed internal RC oscillator

ON, independent watchdog OFF

Low-speed internal RC oscillator and independent watchdog OFF, low-speed oscillator and RTC

OFF

I

DD_VBAT

Backup domain supply current

Low-speed oscillator and RTC

ON

1. Typical values are measured at T

A

= 25 °C.

2. Guaranteed by characterization results.

-

-

-

-

-

1.05

34.5

24.5

3

2.8

1.9

1.1

35

25

3.8

3.6

2.1

1.4

379

365

-

-

5

(2)

2

(2)

1130

1110

-

-

6.5

(2)

2.3

(2)

µA

50/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Figure 16. Typical current consumption on V

BAT at different V

BAT

with RTC on vs. temperature values

9

9

9

9

9

±

7HPSHUDWXUHƒ&

DL

Figure 17. Typical current consumption in Stop mode with regulator in run mode versus temperature at different V

DD

values

6

6

6

6

6

6

6

6

6

6

#

#

# #

#

4EMPERATURE #

#

#

AI

AI

DS5792 Rev 13

51/143

135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Figure 18. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different V

DD

values

6

6

6

6

6

# # #

4EMPERATURE #

#

AI

Figure 19. Typical current consumption in Standby mode versus temperature at different V

DD

values

52/143

# #

4EMPERATURE #

#

6

6

6

6

6

#

AI

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Typical current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at V

DD

or V

SS

(no load).

• All peripherals are disabled except if it is explicitly mentioned.

• The Flash access time is adjusted to f

HCLK

frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHZ and 2 wait states above).

• Ambient temperature and V

DD

supply voltage conditions summarized in

Table 10 .

• Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling)

When the peripherals are enabled f

PCLK1

= f

HCLK

/4, f

PCLK

2 = f

HCLK

/2, f

ADCCLK

= f

PCLK2

/4

Table 18. Typical current consumption in Run mode, code with data processing running from Flash

Typ

(1)

Symbol Parameter Conditions f

HCLK All peripherals enabled

(2)

All peripherals disabled

Unit

I

DD

Supply current in

Run mode

External clock

Running on high speed internal RC

(HSI), AHB prescaler used to reduce the frequency

(3)

36 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

64 MHz

48 MHz

1. Typical values are measures at T

A

= 25 °C, V

DD

= 3.3 V.

15.6

10.8

7.6

4.4

2.5

1.5

1.1

0.8

0.6

2.1

1.7

1.4

1.2

27

20.1

30.5

20.7

16.2

11.4

8.2

5

3.1

26

17.9

12.2

6.6

3.6

2.1

1.4

1

0.7

2.7

2

1.6

1.3

45

34

51

34.6

26.6

18.5

12.8

7.2

4.2

mA mA

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135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

Table 19. Typical current consumption in Sleep mode, code running from Flash or

RAM

Typ

(1)

Symbol Parameter Conditions f

HCLK All peripherals enabled (2)

All peripherals disabled

Unit

External clock

(3)

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

64 MHz

7.2

3.9

2.6

1.85

1.5

29.5

20

15.1

10.4

1.3

1.2

25.6

I

DD

Supply current in

Sleep mode

48 MHz

36 MHz

24 MHz

Running on high speed internal RC

(HSI), AHB prescaler used to reduce the frequency

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

19.4

14.5

9.8

6.6

3.3

2

1.25

0.9

500 kHz

125 kHz

0.7

0.6

0.45

0.45

1. Typical values are measures at T

A

= 25 °C, V

DD

= 3.3 V.

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

1.4

0.7

0.6

0.55

0.5

4

3

2

2

1.3

1.2

1.15

1.1

6.4

4.6

3.6

2.6

1.05

1.05

5.1

mA

54/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in

Table 20 . The MCU is placed

under the following conditions:

• all I/O pins are in input mode with a static value at V

DD

or V

SS

(no load)

• all peripherals are disabled unless otherwise mentioned

• the given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

• ambient operating temperature and V

DD

Table 7

supply voltage conditions summarized in

Table 20. Peripheral current consumption

Peripheral

Current consumption

DMA1 20,42

AHB (up to 72 MHz)

DMA2

FSMC

CRC

SDIO

BusMatrix

(1)

19,03

52,36

2,36

33,33

9,72

Unit

μ A/MHz

DS5792 Rev 13

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135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Table 20. Peripheral current consumption (continued)

Peripheral

Current consumption

APB1-Bridge 7,78

APB1 (up to 36 MHz)

USART3

UART4

UART5

I2C1

I2C2

USB

CAN1

DAC

(3)

WWDG

PWR

BKP

IWDG

TIM2

TIM3

TIM4

TIM5

TIM6

TIM7

SPI2/I2S2

(2)

SPI3/I2S3 (2)

USART2

10,28

10,00

18,06

18,33

8,06

3,89

33,06

31,94

31,67

31,94

8,06

8,06

8,33

8,33

12,22

12,22

12,22

12,22

1,11

1,11

5,28

Unit

μ A/MHz

56/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Table 20. Peripheral current consumption (continued)

Peripheral

Current consumption

APB2-Bridge 4,17

APB2 (up to 72 MHz)

GPIOA 8,47

GPIOB 8,47

GPIOC

GPIOD

6,53

8,47

GPIOE

GPIOF

GPIOG

SPI1

USART1

TIM1

TIM8

ADC1

(4)

ADC2

(4)

ADC3 (4)

6,53

6,53

6,11

4,72

12,50

22,92

22,92

17,32

15,18

14,82

Unit

μ A/MHz

1. The BusMatrix is automatically active when at least one master is ON. (CPU, DMA1 or DMA2).

2. When the I2S is enabled, a current consumption equal to 0.02 mA must be added.

3. When DAC_OU1 or DAC_OUT2 is enabled, a current consumption equal to 0.36 mA must be added.

4. Specific conditions for measuring ADC current consumption: f f

HCLK

, f

ADCCLK

= f

HCLK

= 56 MHz, f

APB1

= f

HCLK

/2, f

APB2

=

/4. When ADON bit in the ADCx_CR2 register is set to 1, a current consumption of analog part equal to 0.54 mA must be added for each ADC.

DS5792 Rev 13

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135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

58/143

High-speed external user clock generated from an external source

The characteristics given in

Table 21 result from tests performed using an high-speed

external clock source, and under ambient temperature and supply voltage conditions summarized in

Table 10 .

Symbol

Table 21. High-speed external user clock characteristics

Parameter f

HSE_ext

User external clock source frequency

(1)

V

HSEH

V

HSEL t w(HSE) t w(HSE) t r(HSE) t f(HSE)

C in(HSE)

DuCy

(HSE)

I

L

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

OSC_IN rise or fall time

(1)

(1)

OSC_IN input capacitance

Duty cycle

(1)

OSC_IN Input leakage current

1. Guaranteed by design.

Conditions

-

-

-

V

SS

≤ V

IN

≤ V

DD

Min

1

0.7V

DD

V

SS

5

-

-

45

-

Typ Max Unit

8

-

-

5

-

-

-

-

25

V

DD

0.3V

DD

-

20

-

55

±1

MHz

V ns pF

%

µA

Low-speed external user clock generated from an external source

The characteristics given in

Table 22 result from tests performed using an low-speed

external clock source, and under ambient temperature and supply voltage conditions summarized in

Table 10 .

Symbol

Table 22. Low-speed external user clock characteristics

Parameter Conditions f

LSE_ext

V

LSEH

User External clock source frequency

(1)

OSC32_IN input pin high level voltage

V

LSEL

OSC32_IN input pin low level voltage

t w(LSE) t w(LSE) t r(LSE) t f(LSE)

C in(LSE)

DuCy

(LSE)

I

L

OSC32_IN high or low time

OSC32_IN rise or fall time

(1)

(1)

OSC32_IN input capacitance

Duty cycle

(1)

-

-

OSC32_IN Input leakage current V

SS

≤ V

IN

≤ V

DD

1. Guaranteed by design.

Min

-

0.7V

DD

V

SS

450

-

-

30

-

Typ

32.768

-

-

-

-

5

-

-

Max

1000

V

DD

0.3V

DD

-

50

-

70

±1

Unit kHz

V ns pF

%

µA

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Figure 20. High-speed external clock source AC timing diagram

6(3%(

6(3%,

TR(3%

4(3%

TF(3%

%XTERNAL

CLOCKSOURCE

F(3%?EXT

/3#?).

T7(3%

T7(3% T

),

34-&

AI

Figure 21. Low-speed external clock source AC timing diagram

9/6(+

9/6(/

WU/6(

7/6(

WI/6(

([WHUQDO

FORFNVRXUFH

I/6(BH[W

26&B,1

W:/6(

,/

670)

W:/6( W

DL

DS5792 Rev 13

59/143

135

Electrical characteristics

60/143

STM32F103xC, STM32F103xD, STM32F103xE

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 23

. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 23. HSE 4-16 MHz oscillator characteristics (1)(2)

Parameter Conditions Min Typ Max Unit f

OSC_IN

R

F

Oscillator frequency

Feedback resistor

-

-

4

-

8

200

16

-

MHz k Ω

C

Recommended load capacitance versus equivalent serial resistance of the crystal (R

S

)

(3)

R

S

= 30 Ω 30 pF i

2

HSE driving current

V

DD

= 3.3 V, V

IN

= V with 30 pF load

SS

1 mA g m t

SU(HSE)

(4)

Oscillator transconductance

Startup time

Startup

V

DD

is stabilized

25

-

-

2

-

mA/V ms

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Guaranteed by characterization results.

3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions.

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For C

L1

and C

L2

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see

Figure 22

). C

L1

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

L1

and C

L2

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

C

L1

and C

L2

. Refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

.

Figure 22. Typical application with an 8 MHz crystal

5HVRQDWRUZLWK

LQWHJUDWHGFDSDFLWRUV

&/

0+]

UHVRQDWRU

26&B,1

26&B28 7

5)

%LDV

FRQWUROOHG

JDLQ

&/

5(;7

1. R

EXT

value depends on the crystal characteristics.

I+6(

670)

DL

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 24

. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 24. LSE oscillator characteristics (f

LSE

= 32.768 kHz) (1)(2)

Parameter Conditions Min Typ Max Unit

R

F

Feedback resistor 5 M Ω

C

(2)

Recommended load capacitance versus equivalent serial resistance of the crystal (R

S

)

LSE driving current

R

S

= 30 k Ω 15 pF

I

2 g m

Oscillator transconductance

V

DD

= 3.3 V, V

IN

-

= V

SS

-

5 -

1.4

-

µA

µA/V t

SU(LSE)

(3)

Startup time

V

DD

is stabilized

T

A

= 50 °C

T

A

= 25 °C

T

A

= 10 °C

T

A

= 0 °C

T

A

= -10 °C

T

A

= -20 °C

T

A

= -30 °C

T

A

= -40 °C -

-

-

-

-

-

-

1.5

2.5

4

6

10

17

32

60 -

-

-

-

-

-

-

s

1. Guaranteed by characterization results.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

3. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) until a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer, PCB layout and humidity.

Note: For C

L1

and C

L2

, it is recommended to use high-quality ceramic capacitors in the 5 pF to

15 pF range selected to match the requirements of the crystal or resonator (see Figure 23 ).

C

L1

and C

L2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

L1

and C

L2

Load capacitance C

L

C stray

has the following formula: C between 2 pF and 7 pF.

L

= C

L1

.

x C

L2

/ ( C

L1

+ C

L2

) + C stray

where

is the pin capacitance and board or trace PCB-related capacitance. Typically, it is

Caution: To avoid exceeding the maximum value of C

L1 to use a resonator with a load capacitance C

L capacitance of 12.5 pF.

and C

≤

L2

(15 pF) it is strongly recommended

7 pF. Never use a resonator with a load

Example: if you choose a resonator with a load capacitance of C

L then C

L1

= C

L2

= 8 pF.

= 6 pF, and C stray

= 2 pF,

DS5792 Rev 13

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135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Figure 23. Typical application with a 32.768 kHz crystal

5.3.7

5HVRQDWRUZLWK

LQWHJUDWHGFDSDFLWRUV

&/

N+ ]

UHVRQDWRU

26&B,1

5)

%LDV

FRQWUROOHG

JDLQ

26&B28 7

&/

I/6(

670)

DL

Internal clock source characteristics

The parameters given in

Table 25 are derived from tests performed under ambient

temperature and V

DD

supply voltage conditions summarized in

Table 10 .

High-speed internal (HSI) RC oscillator

Symbol

Table 25. HSI oscillator characteristics

(1)

Parameter Conditions Min Typ Max Unit

I t f

HSI

DuCy

ACC

(HSI)

HSI

su(HSI)

(4)

DD(HSI)

(4)

Frequency

Duty cycle

Accuracy of the HSI oscillator

-

-

User-trimmed with the RCC_CR register

(2)

Factorycalibrated

(4)

T

A

= –40 to 105 °C

T

A

= –10 to 85 °C

T

A

= 0 to 70 °C

T

A

= 25 °C

HSI oscillator startup time

HSI oscillator power consumption

-

-

-

45

-

–2

–1.5

–1.3

–1.1

1

-

8

-

-

-

-

-

-

-

80

55

1

-

(3)

2.5

2.2

2

1.8

2

100

1. V

DD

= 3.3 V, T

A

= –40 to 105 °C unless otherwise specified.

2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the ST website www.st.com

.

3. Guaranteed by design.

4. Guaranteed by characterization results.

MHz

%

%

µs

µA

%

%

%

%

62/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Low-speed internal (LSI) RC oscillator

Table 26. LSI oscillator characteristics

(1)

Symbol Parameter Min f

LSI

(2) t su(LSI)

(3)

I

DD(LSI)

(3)

Frequency 30

LSI oscillator startup time

LSI oscillator power consumption

1. V

DD

= 3 V, T

A

= –40 to 105 °C unless otherwise specified.

2. Guaranteed by characterization results.

3. Guaranteed by design.

-

-

Typ

40

-

0.65

Max

60

85

1.2

Unit kHz

µs

µA

Wakeup time from low-power mode

The wakeup times given in

Table 27 is measured on a wakeup phase with a 8-MHz HSI RC

oscillator. The clock source used to wake up the device depends from the current operating mode:

• Stop or Standby mode: the clock source is the RC oscillator

• Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under ambient temperature and V

DD voltage conditions summarized in

Table 10 .

supply

Table 27. Low-power mode wakeup timings

Symbol Parameter Typ Unit t

WUSLEEP

(1)

Wakeup from Sleep mode 1.8

µs t

WUSTOP

(1)

Wakeup from Stop mode (regulator in run mode) 3.6

µs

Wakeup from Stop mode (regulator in low-power mode) 5.4

t

WUSTDBY

(1)

Wakeup from Standby mode 50

1. The wakeup times are measured from the wakeup event to the point in which the user application code reads the first instruction.

µs

DS5792 Rev 13

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135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

The parameters given in

Table 28 are derived from tests performed under ambient

temperature and V

DD

supply voltage conditions summarized in

Table 10 .

Table 28. PLL characteristics

Value

Symbol Parameter Unit

Min Typ Max (1) f

PLL_IN f

PLL_OUT t

LOCK

Jitter

PLL input clock

(2)

PLL input clock duty cycle

PLL multiplier output clock

PLL lock time

Cycle-to-cycle jitter

1

40

16

-

-

8.0

-

-

-

-

25

60

72

200

300

MHz

%

MHz

µs ps

1. Guaranteed by characterization results.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f

PLL_OUT

.

Flash memory

The characteristics are given at T

A

= –40 to 105 °C unless otherwise specified.

Symbol

Table 29. Flash memory characteristics

Parameter Conditions t

I prog t

ERASE t

ME

DD

V prog

16-bit programming time T

A

= –40 to +105 °C

Page (2 KB) erase time T

A

= –40 to +105 °C

Mass erase time T

A

= –40 to +105 °C

Supply current

Programming voltage

1. Guaranteed by design.

Read mode f

HCLK

= 72 MHz with 2 wait states, V

DD

= 3.3 V

Write mode f

HCLK

= 72 MHz, V

DD

= 3.3 V

Erase mode f

HCLK

= 72 MHz, V

DD

= 3.3 V

-

Power-down mode / Halt,

V

DD

= 3.0 to 3.6 V

Min

40

20

20

-

-

-

-

2

Typ Max

(1)

52.5

-

-

70

40

40

-

-

-

-

28

7

5

50

3.6

Unit

µs ms ms mA mA mA

µA

V

64/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Symbol

Table 30. Flash memory endurance and data retention

Value

Parameter Conditions

Min

(1)

N t

END

RET

Endurance

Data retention

T

A

= -40 to +85 °C (6 suffix versions)

T

A

= -40 to +105 °C (7 suffix versions)

1 kcycle (2) at T

A

= 85 °C

1 kcycle

(2)

at T

A

= 105 °C

10 kcycles

(2)

at T

A

= 55 °C

1. Guaranteed by characterization results.

2. Cycling performed over the whole temperature range.

10

30

10

20

Unit kcycles

Years

DS5792 Rev 13

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135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Asynchronous waveforms and timings

Figure 24

through Figure 27 represent asynchronous waveforms and

Table 31 through

Table 34 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

• AddressSetupTime = 0

• AddressHoldTime = 1

• DataSetupTime = 1

Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

W

Z1(

)60&B1(

W

Y12(B1(

W

Z12(

W

K1(B12(

)60&B12(

)60&B1:(

)60&B$>@

W

Y$B1(

W

Y%/B1(

$GGUHVV

W

K$B12(

W

K%/B12(

)60&B1%/>@

)60&B'>@

W

Y1$'9B1(

W

Z1$'9

)60&B1$'9

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

W

VX'DWDB12(

W

VX'DWDB1(

'DWD

W

K'DWDB1(

W

K'DWDB12(

069

66/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings (1)

Symbol Parameter Min Max Unit t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t v(A_NE) t h(A_NOE) t v(BL_NE) t h(BL_NOE) t su(Data_NE) t su(Data_NOE) t h(Data_NOE) t h(Data_NE) t v(NADV_NE) t w(NADV)

1. C

L

= 15 pF.

FSMC_NE low time

FSMC_NEx low to FSMC_NOE low

FSMC_NOE low time

FSMC_NOE high to FSMC_NE high hold time

FSMC_NEx low to FSMC_A valid

Address hold time after FSMC_NOE high

FSMC_NEx low to FSMC_BL valid

FSMC_BL hold time after FSMC_NOE high

Data to FSMC_NEx high setup time

Data to FSMC_NOEx high setup time

Data hold time after FSMC_NOE high

Data hold time after FSMC_NEx high

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time

5t

HCLK

5t

– 1.5

5t

0.5

HCLK

-

-

0

0

-

-

HCLK

– 1.5

5t

–1.5

0.1

2t

HCLK

+ 25

2t

HCLK

+ 25

0 t

+ 2

1.5

HCLK

HCLK

-

0

-

0

-

-

-

-

-

5 ns ns

+ 1.5 ns

+ 1.5

ns ns ns ns ns ns ns ns ns ns ns

Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

WZ1(

)60&B1([

)60&B12(

)60&B1:(

)60&B$>@

)60&B1%/>@

)60&B'>@

WY1:(B1( WZ1:(

WY$B1(

WY%/B1(

WY'DWDB1(

WK$B1:(

$GGUHVV

WK%/B1:(

1%/

WK'DWDB1:(

'DWD

W Y1$'9B1(

WZ1$'9

W K1(B1:(

)60&B1$'9

DL

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

DS5792 Rev 13

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135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings (1)(2)

Symbol Parameter Min Max Unit t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t h(A_NWE) t v(BL_NE) t h(BL_NWE) t v(Data_NE) t h(Data_NWE) t v(NADV_NE) t w(NADV)

FSMC_NE low time

FSMC_NEx low to FSMC_NWE low

FSMC_NWE low time

FSMC_NWE high to FSMC_NE high hold time

FSMC_NEx low to FSMC_A valid

Address hold time after FSMC_NWE high

FSMC_NEx low to FSMC_BL valid

FSMC_BL hold time after FSMC_NWE high

FSMC_NEx low to Data valid

Data hold time after FSMC_NWE high

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time

1. C

L

= 15 pF.

2. Guaranteed by characterization results.

3t

HCLK

– 1 t

HCLK

– 0.5

t

HCLK

– 0.5

t

HCLK

t

HCLK

t

HCLK

– 0.5

t

HCLK

-

-

3t

HCLK

+ 2 ns t

HCLK

+ 1.5

ns t

HCLK

+ 1.5

ns

ns

7.5

ns ns

0

ns ns t

HCLK

+ 7 ns

ns

5.5

ns t

HCLK

+ 1.5

ns

Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms

T

W.%

&3-#?.%

T

V./%?.%

T

H.%?./%

&3-#?./%

T

W./%

&3-#?.7%

T

V!?.%

T

H!?./%

&3-#?!;=

!DDRESS

T

V",?.% T

H",?./%

&3-#?.",;=

.",

T

H$ATA?.%

&3-#?!$;=

T

V!?.%

!DDRESS

T

V.!$6?.%

T

W.!$6

T

H!$?.!$6

T

SU$ATA?.%

T

SU$ATA?./%

$ATA

T

H$ATA?./%

&3-#?.!$6

AIB

68/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Table 33. Asynchronous multiplexed PSRAM/NOR read timings (1)(2)

Symbol Parameter t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t v(A_NE) t v(NADV_NE) t w(NADV)

FSMC_NE low time

FSMC_NEx low to FSMC_NOE low

FSMC_NOE low time

FSMC_NOE high to FSMC_NE high hold time

FSMC_NEx low to FSMC_A valid

FSMC_NEx low to FSMC_NADV low t h(AD_NADV)

FSMC_NADV low time

FSMC_AD (address) valid hold time after

FSMC_NADV high t h(A_NOE) t h(BL_NOE) t v(BL_NE) t su(Data_NE) t su(Data_NOE) t h(Data_NE) t h(Data_NOE)

Address hold time after FSMC_NOE high

FSMC_BL hold time after FSMC_NOE high

FSMC_NEx low to FSMC_BL valid

Data to FSMC_NEx high setup time

Data to FSMC_NOE high setup time

Data hold time after FSMC_NEx high

Data hold time after FSMC_NOE high

1. C

L

= 15 pF.

2. Guaranteed by characterization results.

Min

7t

HCLK

– 2 7t

HCLK

+ 2 ns

3t

HCLK

– 0.5

3t

HCLK

+ 1.5

ns

4t

HCLK

– 1

–1

4t

HCLK

+ 2 ns

ns

-

3 t

HCLK

–1.5

t

HCLK

0

5

+ 1.5

ns

ns

ns t

HCLK t

HCLK

-2

0

-

2t

HCLK

+ 24

2t

HCLK

+ 25

0

0

Max

-

0

-

-

-

-

-

-

Unit ns

ns

ns

ns

ns

ns

ns

ns

DS5792 Rev 13

69/143

135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms

WZ1(

)60&B1([

70/143

)60&B12(

WY1:(B1( WZ1:( W K1(B1:(

)60&B1:(

)60&B$>@

)60&B1%/>@

)60&B$'>@

WY$B1(

WY%/B1(

W Y$B1(

$GGUHVV

W Y1$'9B1(

WZ1$'9

WK$B1:(

$GGUHVV

WK%/B1:(

1%/

WY'DWDB1$'9

'DWD

WK$'B1$'9

WK'DWDB1:(

)60&B1$'9

DL%

Table 34. Asynchronous multiplexed PSRAM/NOR write timings (1)(2)

Symbol Parameter t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t v(NADV_NE) t w(NADV)

FSMC_NE low time

FSMC_NEx low to FSMC_NWE low

FSMC_NWE low time

FSMC_NWE high to FSMC_NE high hold time

FSMC_NEx low to FSMC_A valid

FSMC_NEx low to FSMC_NADV low t h(AD_NADV)

FSMC_NADV low time

FSMC_AD (address) valid hold time after

FSMC_NADV high t h(A_NWE) t v(BL_NE) t h(BL_NWE) t v(Data_NADV) t h(Data_NWE)

Address hold time after FSMC_NWE high

FSMC_NEx low to FSMC_BL valid

FSMC_BL hold time after FSMC_NWE high

FSMC_NADV high to Data valid

Data hold time after FSMC_NWE high

1. C

L

= 15 pF.

2. BGuaranteed by characterization results.

Min

5t

HCLK

– 1

2t

HCLK

2t

HCLK

– 1 t

HCLK

– 1

-

3 t

HCLK

– 1 t

HCLK

– 3

4t

HCLK

t

HCLK

– 1.5

t

HCLK

– 5

Max Unit

2t

5t

HCLK

+ 2 ns

HCLK

+ 1 ns

2t

HCLK

-

+ 2 ns ns

5

7 t

HCLK

+ 1 ns ns ns

ns

-

1.6

ns ns ns t

HCLK

+ 1.5

ns

ns

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Synchronous waveforms and timings

Figure 28

through Figure 31

represent synchronous waveforms and Table 36

through

Table 38 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

• BurstAccessMode = FSMC_BurstAccessMode_Enable;

• MemoryType = FSMC_MemoryType_CRAM;

• WriteBurst = FSMC_WriteBurst_Enable;

• CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual)

• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

Figure 28. Synchronous multiplexed NOR/PSRAM read timings

TW#,+ TW#,+ "53452.

&3-#?#,+

$ATALATENCY

TD#,+,.%X, TD#,+,.%X(

&3-#?.%X

TD#,+,.!$6,

&3-#?.!$6

TD#,+,.!$6(

TD#,+,!6 TD#,+,!)6

&3-#?!;=

TD#,+(./%, TD#,+,./%(

&3-#?./%

TD#,+,!$6

&3-#?!$;=

TD#,+,!$)6

TSU!$6#,+(

!$;=

TSU.7!)46#,+(

&3-#?.7!)4

7!)4#&'B7!)40/,B

$

TH#,+(!$6

TSU!$6#,+(

$

TH#,+(.7!)46

TH#,+(!$6

$

TSU.7!)46#,+( TH#,+(.7!)46

&3-#?.7!)4

7!)4#&'B7!)40/,B

TSU.7!)46#,+( TH#,+(.7!)46

AII

DS5792 Rev 13

71/143

135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Table 35. Synchronous multiplexed NOR/PSRAM read timings (1)(2)

Symbol Parameter Min Max t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NOEL) t d(CLKL-NOEH) t d(CLKL-ADV) t d(CLKL-ADIV)

FSMC_CLK period

FSMC_CLK low to FSMC_NEx low (x = 0...2)

FSMC_CLK low to FSMC_NEx high (x = 0...2)

FSMC_CLK low to FSMC_NADV low

FSMC_CLK low to FSMC_NADV high

FSMC_CLK low to FSMC_Ax valid (x = 16...25)

FSMC_CLK low to FSMC_Ax invalid (x = 16...25)

FSMC_CLK low to FSMC_NOE low

FSMC_CLK low to FSMC_NOE high

FSMC_CLK low to FSMC_AD[15:0] valid

FSMC_CLK low to FSMC_AD[15:0] invalid t su(ADV-CLKH)

FSMC_A/D[15:0] valid data before FSMC_CLK high t h(CLKH-ADV) t su(NWAITV-CLKH) t h(CLKH-NWAITV)

FSMC_A/D[15:0] valid data after FSMC_CLK high

FSMC_NWAIT valid before FSMC_CLK high

FSMC_NWAIT valid after FSMC_CLK high

1. C

L

= 15 pF.

2. Guaranteed by characterization results.

2

-

5

-

27.7

-

2

-

1.5

-

0

6

0

8

2 -

-

-

-

-

1

-

0

-

1.5

-

4

-

12

ns

ns

ns

ns

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

72/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Figure 29. Synchronous multiplexed PSRAM write timings

&3-#?#,+

TW#,+ TW#,+ "53452.

$ATALATENCY

TD#,+,.%X, TD#,+,.%X(

&3-#?.%X

TD#,+,.!$6,

&3-#?.!$6

TD#,+,.!$6(

TD#,+,!6 TD#,+,!)6

&3-#?!;=

TD#,+,.7%, TD#,+,.7%(

&3-#?.7%

TD#,+,!$6

&3-#?!$;=

TD#,+,!$)6

TD#,+,$ATA

!$;=

TD#,+,$ATA

$ $

&3-#?.7!)4

7!)4#&'B7!)40/,B

TSU.7!)46#,+(

&3-#?.",

TH#,+(.7!)46

TD#,+,.",(

AIG

DS5792 Rev 13

73/143

135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Symbol

Table 36. Synchronous multiplexed PSRAM write timings (1)(2)

Parameter Min Max Unit t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-ADV) t d(CLKL-ADIV) t d(CLKL-Data) t d(CLKL-NBLH) t su(NWAITV-CLKH) t h(CLKH-NWAITV)

FSMC_CLK period

FSMC_CLK low to FSMC_Nex low (x = 0...2)

FSMC_CLK low to FSMC_NEx high (x = 0...2)

FSMC_CLK low to FSMC_NADV low

FSMC_CLK low to FSMC_NADV high

FSMC_CLK low to FSMC_Ax valid (x = 16...25)

FSMC_CLK low to FSMC_Ax invalid (x = 16...25)

FSMC_CLK low to FSMC_NWE low

FSMC_CLK low to FSMC_NWE high

FSMC_CLK low to FSMC_AD[15:0] valid

FSMC_CLK low to FSMC_AD[15:0] invalid

FSMC_A/D[15:0] valid after FSMC_CLK low

FSMC_CLK low to FSMC_NBL high

FSMC_NWAIT valid before FSMC_CLK high

FSMC_NWAIT valid after FSMC_CLK high

1. C

L

= 15 pF.

2. Guaranteed by characterization results.

-

1

7

2

1

-

3

2

-

5

-

27.7

-

2

-

ns

12 ns

ns

6 ns

ns

ns

ns

ns

2 ns

ns

4 ns

ns

0 ns

ns

1 ns

74/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings

TW#,+ TW#,+

"53452.

&3-#?#,+

TD#,+,.%X,

&3-#?.%X

$ATALATENCY

TD#,+,.%X(

TD#,+,.!$6,

&3-#?.!$6

TD#,+,.!$6(

TD#,+,!6

TD#,+,!)6

&3-#?!;=

TD#,+(./%, TD#,+,./%(

&3-#?./%

TSU$6#,+(

&3-#?$;=

TSU.7!)46#,+(

$

TH#,+($6

TSU$6#,+(

$

TH#,+(.7!)46

TH#,+($6

$

&3-#?.7!)4

7!)4#&'B7!)40/,B

TSU.7!)46#,+( T H#,+(.7!)46

&3-#?.7!)4

7!)4#&'B7!)40/,B

TSU.7!)46#,+( TH#,+(.7!)46

AIH

Table 37. Synchronous non-multiplexed NOR/PSRAM read timings

(1)(2)

Symbol t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NOEL) t d(CLKL-NOEH)

FSMC_CLK period

Parameter

FSMC_CLK low to FSMC_NEx low (x = 0...2)

FSMC_CLK low to FSMC_NEx high (x = 0...2)

FSMC_CLK low to FSMC_NADV low

FSMC_CLK low to FSMC_NADV high

FSMC_CLK low to FSMC_Ax valid (x = 0...25)

FSMC_CLK low to FSMC_Ax invalid (x = 0...25)

FSMC_CLK low to FSMC_NOE low

FSMC_CLK low to FSMC_NOE high

Min

27.7

-

4

-

5

-

2

-

1.5

Max

-

1.5

-

0

-

4

-

1.5

t su(DV-CLKH)

FSMC_D[15:0] valid data before FSMC_CLK high

6.5

t h(CLKH-DV) t su(NWAITV-CLKH) t h(CLKH-NWAITV)

FSMC_D[15:0] valid data after FSMC_CLK high

FSMC_NWAIT valid before FSMC_SMCLK high

FSMC_NWAIT valid after FSMC_CLK high

1. C

L

= 15 pF.

2. Guaranteed by characterization results.

7

7

2

-

-

-

ns

ns

ns

ns

ns

ns

ns

ns

Unit

ns

ns

ns

ns

ns

DS5792 Rev 13

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135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Figure 31. Synchronous non-multiplexed PSRAM write timings

WZ&/.

WZ&/.

%867851

)60&B&/.

'DWDODWHQF\

WG&/./1([/ WG&/./1([+

)60&B1([

WG&/./1$'9/

)60&B1$'9

WG&/./1$'9+

WG&/./$9 WG&/./$,9

)60&B$>@

)60&B12(

WG&/./$'9

)60&B$'>@

WG&/./$',9

WVX$'9&/.+

$'>@

WVX1:$,79&/.+

)60&B1:$,7

:$,7&)* E:$,732/E

'

WVX$'9&/.+

WVX1:$,79&/.+

WK&/.+$'9

'

WK&/.+1:$,79

WK&/.+$'9

WK&/.+1:$,79

)60&B1:$,7

:$,7&)* E:$,732/E

WVX1:$,79&/.+

WG&/.+12(/ WG&/./12(+

WK&/.+1:$,79

DLK

Table 38. Synchronous non-multiplexed PSRAM write timings (1)(2)

Symbol Parameter Min Max Unit t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-Data) t d(CLKL-NBLH) t su(NWAITV-CLKH) t h(CLKH-NWAITV)

FSMC_CLK period

FSMC_CLK low to FSMC_NEx low (x = 0...2)

FSMC_CLK low to FSMC_NEx high (x = 0...2)

FSMC_CLK low to FSMC_NADV low

FSMC_CLK low to FSMC_NADV high

FSMC_CLK low to FSMC_Ax valid (x = 16...25)

FSMC_CLK low to FSMC_Ax invalid (x = 16...25)

FSMC_CLK low to FSMC_NWE low

FSMC_CLK low to FSMC_NWE high

FSMC_D[15:0] valid data after FSMC_CLK low

FSMC_CLK low to FSMC_NBL high

FSMC_NWAIT valid before FSMC_CLK high

FSMC_NWAIT valid after FSMC_CLK high

1. C

L

= 15 pF.

2. Guaranteed by characterization results.

2

-

5

-

27.7

-

2

-

1

7

1

-

2

ns

2 ns

ns

4 ns

ns

0 ns

ns

1 ns

-

-

ns

6 ns

-

ns

ns

ns

76/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE

WZ12(

Electrical characteristics

PC Card/CompactFlash controller waveforms and timings

Figure 32

through Figure 37 represent synchronous waveforms and Table 39

provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration:

• COM.FSMC_SetupTime = 0x04;

• COM.FSMC_WaitSetupTime = 0x07;

• COM.FSMC_HoldSetupTime = 0x04;

• COM.FSMC_HiZSetupTime = 0x00;

• ATT.FSMC_SetupTime = 0x04;

• ATT.FSMC_WaitSetupTime = 0x07;

• ATT.FSMC_HoldSetupTime = 0x04;

• ATT.FSMC_HiZSetupTime = 0x00;

• IO.FSMC_SetupTime = 0x04;

• IO.FSMC_WaitSetupTime = 0x07;

• IO.FSMC_HoldSetupTime = 0x04;

• IO.FSMC_HiZSetupTime = 0x00;

• TCLRSetupTime = 0;

• TARSetupTime = 0;

Figure 32. PC Card/CompactFlash controller waveforms for common memory read access

)60&B1&(B

)60&B1&(B

WY1&([$ WK1&([$,

)60&B$>@

WG15(*1&([

WG1,25'1&([

WK1&([15(*

WK1&([1,25'

WK1&([1,2:5

)60&B15(*

)60&B1,2:5

)60&B1,25'

)60&B1:(

WG1&(B12(

)60&B12(

WVX'12( WK12('

)60&B'>@

DLE

1. FSMC_NCE4_2 remains high (inactive during 8-bit access.

DS5792 Rev 13

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135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Figure 33. PC Card/CompactFlash controller waveforms for common memory write access

)60&B1&(B

)60&B1&(B +LJK

WY1&(B$

)60&B$>@

)60&B15(*

)60&B1,2:5

)60&B1,25'

WG1&(B1:(

)60&B1:(

WG15(*1&(B

WG1,25'1&(B

WZ1:(

)60&B12(

0(0[+,=

WG'1:(

WY1:('

WK1&(B$,

WK1&(B15(*

WK1&(B1,25'

WK1&(B1,2:5

WG1:(1&(B

WK1:('

)60&B'>@

DLE

78/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read access

)60&B1&(B

WY1&(B$ WK1&(B$,

)60&B1&(B

+LJK

)60&B$>@

)60&B1,2:5

)60&B1,25'

)60&B15(*

)60&B1:(

WG1&(B12(

)60&B12(

WG15(*1&(B

WZ12(

WVX'12(

)60&B'>@

WK1&(B15(*

WK12('

WG12(1&(B

DLE

1. Only data bits 0...7 are read (bits 8...15 are disregarded).

DS5792 Rev 13

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135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write access

)60&B1&(B

)60&B1&(B +LJK

WY1&(B$ WK1&(B$,

)60&B$>@

)60&B1,2:5

)60&B1,25'

WG15(*1&(B WK1&(B15(*

)60&B15(*

WG1&(B1:(

)60&B1:(

WZ1:(

WG1:(1&(B

)60&B12(

WY1:('

)60&B'>@

DLE

1. Only data bits 0...7 are driven (bits 8...15 remains HiZ).

Figure 36. PC Card/CompactFlash controller waveforms for I/O space read access

)60&B1&(B

)60&B1&(B

WY1&([$ WK1&(B$,

)60&B$>@

)60&B15(*

)60&B1:(

)60&B12(

)60&B1,2:5

WG1,25'1&(B

)60&B1,25'

WZ1,25'

WVX'1,25' WG1,25''

)60&B'>@

DL%

80/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access

)60&B1&(B

)60&B1&(B

WY1&([$ WK1&(B$,

)60&B$>@

)60&B15(*

)60&B1:(

)60&B12(

)60&B1,25'

WG1&(B1,2:5

)60&B1,2:5

WZ1,2:5

$77[+,=

WK1,2:5'

WY1,2:5'

)60&B'>@

DLF t d(NREG-NCEx) t d(NREG-NCE4_1) t h(NCEx-NREG) t h(NCE4_1-NREG) t d(NCE4_1-NOE) t w(NOE) t d(NOE-NCE4_1 t su(D-NOE) t h(NOE-D) t w(NWE) t d(NWE-NCE4_1) t d(NCE4_1-NWE) t v(NWE-D) t h(NWE-D) t d(D-NWE) t v(NCEx-A) t v(NCE4_1-A) t h(NCEx-AI) t h(NCE4_1-AI)

Table 39. Switching characteristics for PC Card/CF read and write cycles (1)(2)

Symbol Parameter Min Max Unit

FSMC_NCEx low (x = 4_1/4_2) to FSMC_Ay valid (y =

0...10) FSMC_NCE4_1 low (x = 4_1/4_2) to FSMC_Ay valid (y = 0...10)

FSMC_NCEx high (x = 4_1/4_2) to FSMC_Ax invalid (x =

0...10) FSMC_NCE4_1 high (x = 4_1/4_2) to FSMC_Ax invalid (x = 0...10)

FSMC_NCEx low to FSMC_NREG valid FSMC_NCE4_1 low to FSMC_NREG valid

FSMC_NCEx high to FSMC_NREG invalid FSMC_NCE4_1 high to FSMC_NREG invalid

FSMC_NCE4_1 low to FSMC_NOE low

FSMC_NOE low width

FSMC_NOE high to FSMC_NCE4_1 high

FSMC_D[15:0] valid data before FSMC_NOE high

FSMC_D[15:0] valid data after FSMC_NOE high

FSMC_NWE low width

FSMC_NWE high to FSMC_NCE4_1 high

FSMC_NCE4_1 low to FSMC_NWE low

FSMC_NWE low to FSMC_D[15:0] valid

FSMC_NWE high to FSMC_D[15:0] invalid

FSMC_D[15:0] valid before FSMC_NWE high t

-

2.5

-

HCLK

+ 3

0

5

-

ns

ns ns

ns

5t

HCLK

+ 2 ns

8t

HCLK

–1.5

8t

HCLK

+ 1 ns

5t

HCLK

25

+ 2

-

ns

ns

15 ns

8t

HCLK

– 1 8t

HCLK

+ 2 ns

5t

HCLK

-

+ 2

5t

-

HCLK

ns

+ 1.5 ns

0 ns

11t

HCLK

13t

HCLK

-

ns ns

DS5792 Rev 13

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135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Table 39. Switching characteristics for PC Card/CF read and write cycles (1)(2) (continued)

Symbol Parameter Min Max Unit t w(NIOWR) t v(NIOWR-D) t h(NIOWR-D) t d(NCE4_1-NIOWR) t h(NCEx-NIOWR) t h(NCE4_1-NIOWR) t d(NIORD-NCEx) t d(NIORD-NCE4_1) t h(NCEx-NIORD) t h(NCE4_1-NIORD) t su(D-NIORD) t d(NIORD-D) t w(NIORD)

FSMC_NIOWR low width

FSMC_NIOWR low to FSMC_D[15:0] valid

FSMC_NIOWR high to FSMC_D[15:0] invalid

FSMC_NCE4_1 low to FSMC_NIOWR valid

FSMC_NCEx high to FSMC_NIOWR invalid

FSMC_NCE4_1 high to FSMC_NIOWR invalid

FSMC_NCEx low to FSMC_NIORD valid FSMC_NCE4_1 low to FSMC_NIORD valid

FSMC_NCEx high to FSMC_NIORD invalid

FSMC_NCE4_1 high to FSMC_NIORD invalid

FSMC_D[15:0] valid before FSMC_NIORD high

FSMC_D[15:0] valid after FSMC_NIORD high

FSMC_NIORD low width

1. C

L

= 15 pF.

2. Guaranteed by characterization results.

8t

HCLK

+ 3

-

11t

HCLK

-

5t

HCLK

– 5

-

5t

HCLK

– 5

4.5

9

8t

HCLK

+ 2

ns

5t

HCLK

+1 ns

ns

5t

HCLK

+3ns ns

ns

5t

HCLK

+ 2.5 ns

-

-

-

ns

ns

ns

ns

82/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

NAND controller waveforms and timings

Figure 38

through Figure 41

represent synchronous waveforms and Table 39

provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration:

• COM.FSMC_SetupTime = 0x01;

• COM.FSMC_WaitSetupTime = 0x03;

• COM.FSMC_HoldSetupTime = 0x02;

• COM.FSMC_HiZSetupTime = 0x01;

• ATT.FSMC_SetupTime = 0x01;

• ATT.FSMC_WaitSetupTime = 0x03;

• ATT.FSMC_HoldSetupTime = 0x02;

• ATT.FSMC_HiZSetupTime = 0x01;

• Bank = FSMC_Bank_NAND;

• MemoryDataWidth = FSMC_MemoryDataWidth_16b;

• ECC = FSMC_ECC_Enable;

• ECCPageSize = FSMC_ECCPageSize_512Bytes;

• TCLRSetupTime = 0;

• TARSetupTime = 0;

Figure 38. NAND controller waveforms for read access

)60&B1&([ /RZ

$/()60&B$

&/()60&B$

)60&B1:(

WG$/(12( WK12($/(

)60&B12(15(

WVX'12( WK12('

)60&B'>@

DLE

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135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Figure 39. NAND controller waveforms for write access

)60&B1&([

$/()60&B$

&/()60&B$

WG$/(1:( WK1:($/(

)60&B1:(

)60&B12(15(

WY1:(' WK1:('

)60&B'>@

Figure 40. NAND controller waveforms for common memory read access

)60&B1&([ /RZ

AIC

$/()60&B$

&/()60&B$

)60&B1:(

WG$/(12( WK12($/(

WZ12(

)60&B12(

WVX'12( WK12('

)60&B'>@

DLE

84/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Figure 41. NAND controller waveforms for common memory write access

)60&B1&([ /RZ

$/()60&B$

&/()60&B$

WG$/(1:(

)60&B1:(

)60&B12(

WZ1:( WK1:($/(

WG'1:(

WY1:(' WK1:('

)60&B'>@

DLE

Table 40. Switching characteristics for NAND Flash read and write cycles (1)

Symbol Parameter Min Max Unit t d(D-NWE)

(2) t

w(NOE)

(2)

FSMC_D[15:0] valid before FSMC_NWE high

FSMC_NWE low width t

su(D-NOE)

(2)

FSMC_D[15:0] valid data before

FSMC_NOE high t h(NOE-D)

(2)

t w(NWE)

(2)

t v(NWE-D)

(2)

t h(NWE-D)

(2)

t d(ALE-NWE)

(3) t

h(NWE-ALE)

(3)

t

d(ALE-NOE)

(3)

t

h(NOE-ALE)

(3)

FSMC_D[15:0] valid data after FSMC_NOE high

FSMC_NWE low width

FSMC_NWE low to FSMC_D[15:0] valid

FSMC_NWE high to FSMC_D[15:0] invalid

FSMC_ALE valid before FSMC_NWE low

FSMC_NWE high to FSMC_ALE invalid

FSMC_ALE valid before FSMC_NOE low

FSMC_NWE high to FSMC_ALE invalid

1. C

L

= 15 pF.

2. Guaranteed by characterization results.

3. Guaranteed by design.

5t

HCLK

+ 12

4t

HCLK-1.5

25

7

4t

HCLK-1

-

2t

HCLK

+ 4

-

3t

HCLK

+ 4.5

-

3t

HCLK

+ 4.5

-

4t

HCLK+1.5

ns ns

ns

-

4t

HCLK+1

0

ns

3t

HCLK

+ 1.5 ns

ns

3t

HCLK

+ 2 ns

ns

-

ns

ns

DS5792 Rev 13

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135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

DD

V

SS compliant with the IEC 61000-4-4 standard.

and

through a 100 pF capacitor, until a functional disturbance occurs. This test is

A device reset allows normal operations to be resumed.

The test results are given in

Table 41

. They are based on the EMS levels and classes defined in application note AN1709.

Symbol

Table 41. EMS characteristics

Parameter Conditions

Level/

Class

V

FESD

V

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

DD

and V pins to induce a functional disturbance

SS

V

DD

= 3.3 V, LQFP144, T

A

= +25 °C, f

HCLK

= 72 MHz conforms to IEC 61000-4-2

V

DD

°C,

= 3.3 V, LQFP144, T

A

= +25 f

HCLK

= 72 MHz conforms to IEC 61000-4-4

2B

4A

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 42. EMI characteristics

Symbol Parameter

S

EMI

Peak level

Conditions

V

DD

= 3.3 V, T

A

= 25 °C,

LQFP144 package compliant with IEC

61967-2

Monitored frequency band

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI Level

Max vs. [f

HSE

/f

HCLK

]

8/48 MHz 8/72 MHz

8

31

28

4

12

21

33

4

Unit dBµV

-

5.3.12 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

Symbol Ratings

Table 43. ESD absolute maximum ratings

Conditions Class

Maximum value

(1)

Unit

V

ESD(HBM)

V

ESD(CDM)

Electrostatic discharge voltage

(human body model)

T

A

= +25 °C, conforming to

JESD22-A114

Electrostatic discharge voltage

(charge device model)

T

A

= +25 °C, conforming to

JESD22-C101

1. Guaranteed by characterization results.

2

III

2000

500

V

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

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135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Symbol

LU

Parameter

Table 44. Electrical sensitivities

Conditions

Static latch-up class T

A

= +105 °C conforming to JESD78A

Class

II level A

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

DD

or

(for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5

LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation).

The test results are given in

Table 45

Symbol

I

INJ

Table 45. I/O current injection susceptibility

Functional susceptibility

Description

Negative injection

Positive injection

Injected current on OSC_IN32,

OSC_OUT32, PA4, PA5, PC13

Injected current on all FT pins

Injected current on any other pin

-0

-5

-5

+0

+0

+5

Unit mA

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DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 46

are derived from tests

performed under the conditions summarized in Table 10

.

All I/Os are CMOS and TTL compliant.

Symbol Parameter

Table 46. I/O static characteristics

Conditions Min Typ Max Unit

V

IL

V

IH

V hys

I lkg

Standard IO input low level voltage

IO FT

(1)

input low level voltage

Standard IO input high level voltage

-

-

IO FT (1) input high level voltage

V

DD

> 2 V

V

DD

2 V

Standard IO Schmitt trigger voltage hysteresis

(2)

-

IO FT Schmitt trigger

voltage hysteresis

(2)

Input leakage current

(4)

V

SS

≤ V

IN

≤ V

DD

Standard I/Os

V

IN

= 5 V,

I/O FT

–0.3

–0.3

0.41*(V

DD

V

-2 V)+1.3

0.42*(V

DD

-2 V)+1 V

200

5% V

DD

(3)

-

-

-

-

-

-

-

-

-

0.28*(V

DD

-2 V)+0.8 V V

0.32*(V

DD

-2 V)+0.75 V V

V

DD

+0.3

5.5

5.2

-

-

± 1

3

V

V mV mV

µA

R

PU

R

PD

Weak pull-up equivalent resistor

(5)

Weak pull-down

equivalent resistor

(5)

V

IN

= V

SS

V

IN

= V

DD

30

30

40

40

50

50 k Ω k Ω

C

IO

I/O pin capacitance 5 -

1. FT = Five-volt tolerant. In order to sustain a voltage higher than V disabled.

DD

+0.3 the internal pull-up/pull-down resistors must be

2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.

3. With a minimum of 100 mV.

4. Leakage could be higher than max. if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

MOS/NMOS contribution to the series resistance is minimum (~10% order)

.

pF

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in

Figure 42

and

Figure 43 for standard I/Os, and

in

Figure 44

and Figure 45 for 5 V tolerant I/Os.

DS5792 Rev 13

89/143

135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Figure 42. Standard I/O input characteristics - CMOS port

6)(6),6

6)(6$$

7

)(MIN

7

),MAX

#-/3STANDARDREQUIREMENT

6 )(6

$$

#-/3STANDARDREQUIREMENT

6),6$$

6

),

6 $$

)NPUTRANGE

NOTGUARANTEED

6$$6

AIB

Figure 43. Standard I/O input characteristics - TTL port

7

)(MIN

6)(6),6

7

),MAX

44,REQUIREMENTS 6)(6

6)(6$$

6),6$$

44,REQUIREMENTS 6),6

)NPUTRANGE

NOTGUARANTEED

Figure 44. 5 V tolerant I/O input characteristics - CMOS port

6$$6

AI

6)(6),6

#-/3STANDARDREQUIREMENTS

6)(6

$$

6)(6$$

6),6$$

#-/3STANDARDREQUIR

MENT6),6$$

)NPUTRANGE

NOTGUARANTEED

6$$

6$$6

AIB

90/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Figure 45. 5 V tolerant I/O input characteristics - TTL port

6)(6),6

7

)(MIN

7

),MAX

44,REQUIREMENT6)(6

6)(6$$

6),6$$

)NPUTRANGE

NOTGUARANTEED

44,REQUIREMENTS6),6

6$$6

AI

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ± 20 mA (with a relaxed V

OL/

V

OH

) except PC13, PC14 and PC15 which can sink or source up to ±3 mA. When using the GPIOs PC13 to PC15 in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 5.2

:

• The sum of the currents sourced by all the I/Os on V

DD,

I consumption of the MCU sourced on V

DD,

VDD

(see

Table 8

). plus the maximum Run cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

SS

I consumption of the MCU sunk on V

SS

VSS

(see

Table 8

).

plus the maximum Run

cannot exceed the absolute maximum rating

Output voltage levels

Unless otherwise specified, the parameters given in Table 47

are derived from tests performed under ambient temperature and V

DD

supply voltage conditions summarized in

Table 10 . All I/Os are CMOS and TTL compliant.

Symbol

V

OL

(1)

V

OH

(2)

V

OL

(1)

V

OH

(2)

Table 47. Output voltage characteristics

Parameter Conditions

Output low level voltage for an I/O pin when 8 pins are sunk at same time

Output high level voltage for an I/O pin when 8 pins are sourced at same time

Output low level voltage for an I/O pin when 8 pins are sunk at same time

Output high level voltage for an I/O pin when 8 pins are sourced at same time

TTL port

(3)

I

IO

= +8 mA

2.7 V < V

DD

< 3.6 V

CMOS port

(3)

I

IO

=+ 8mA

2.7 V < V

DD

< 3.6 V

Min

V

DD

–0.4

-

-

2.4

Max Unit

0.4

-

-

0.4

V

V

DS5792 Rev 13

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135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Symbol

Table 47. Output voltage characteristics (continued)

Parameter Conditions Min Max Unit

V

OL

(1)(4)

Output low level voltage for an I/O pin when 8 pins are sunk at same time

V

OH

(2)(4)

Output high level voltage for an I/O pin when 8 pins are sourced at same time

V

OL

(1)(4)

Output low level voltage for an I/O pin when 8 pins are sunk at same time

V

OH

(2)(4)

Output high level voltage for an I/O pin when 8 pins are sourced at same time

I

2.7 V < V

I

IO

IO

= +20 mA

DD

< 3.6 V

= +6 mA

2 V < V

DD

< 2.7 V

V

V

DD

DD

-

-

–1.3

–0.4

1.3

-

-

0.4

1. The I

IO

current sunk by the device must always respect the absolute maximum rating specified in

Table 8

and the sum of I

IO

(I/O ports and control pins) must not exceed I

VSS

.

2. The I

Table 8

current sourced by the device must always respect the absolute maximum rating specified in

and the sum of I

IO

(I/O ports and control pins) must not exceed I

VDD

.

3. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

4. Guaranteed by characterization results.

V

V

92/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 46 and

Table 48 , respectively.

Unless otherwise specified, the parameters given in Table 48

are derived from tests performed under ambient temperature and V

DD

Table 10 .

supply voltage conditions summarized in

Table 48. I/O AC characteristics (1)

MODEx[1:0] bit value

(1)

Symbol Parameter Conditions Min Max Unit

10

01 f f max(IO)out t t t t f(IO)out r(IO)out max(IO)out f(IO)out r(IO)out

Maximum frequency

(2)

Output high to low level fall time

Output low to high level rise time

Maximum frequency

(2)

Output high to low level fall time

Output low to high level rise time

C

C

C

C

L

L

L

L

= 50 pF, V

= 50 pF, V

= 50 pF, V

= 50 pF, V

DD

DD

DD

DD

= 2 V to 3.6 V

= 2 V to 3.6 V

= 2 V to 3.6 V

= 2 V to 3.6 V

-

-

-

-

-

2

125

125

10

25

25

(3)

(3)

(3)

(3)

MHz ns

MHz ns

11

F max(IO)out t t f(IO)out r(IO)out

Maximum frequency

Output high to low level fall time

Output low to high level rise time

(2)

C

L

= 30 pF, V

DD

= 2.7 V to 3.6 V

C

L

= 50 pF, V

DD

= 2.7 V to 3.6 V

C

L

= 50 pF, V

DD

= 2 V to 2.7 V

C

L

= 30 pF, V

DD

= 2.7 V to 3.6 V

C

L

= 50 pF, V

DD

= 2.7 V to 3.6 V

C

L

= 50 pF, V

DD

= 2 V to 2.7 V

C

L

= 30 pF, V

DD

= 2.7 V to 3.6 V

C

L

= 50 pF, V

DD

= 2.7 V to 3.6 V

C

L

= 50 pF, V

DD

= 2 V to 2.7 V

-

-

-

-

-

-

-

-

-

50

30

20

5

(3)

8

(3)

12

(3)

5

(3)

8

(3)

12

(3)

MHz

MHz

MHz ns

t

EXTIpw

Pulse width of external signals detected by the

EXTI controller

10 -

1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of

GPIO Port configuration register.

2. The maximum frequency is defined in

Figure 46

.

3. Guaranteed by design.

ns

DS5792 Rev 13

93/143

135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Figure 46. I/O AC characteristics definition

(;7(51$/

287387

21&/

WU,2RXW WI,2RXW

7

0D[LPXPIUHTXHQF\LVDFKLHYHGLIWUWI”7DQGLIWKHGXW\F\FOHLV

ZKHQORDGHGE\& / VSHFLILHGLQWKHWDEOH³ ,2$&FKDUDFWHULVWLFV ´

DLG

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

PU

(see

Table 46 ).

Unless otherwise specified, the parameters given in Table 49

are derived from tests performed under ambient temperature and V

DD

Table 10 .

supply voltage conditions summarized in

Table 49. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

V

IL(NRST)

(1)

V

IH(NRST)

(1)

NRST Input low level voltage

NRST Input high level voltage -

–0.5

2 -

0.8

V

DD

+0.5

V

V hys(NRST)

R

PU

V

F(NRST)

(1)

V

NF(NRST)

(1)

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(2)

NRST Input filtered pulse

NRST Input not filtered pulse -

-

V

IN

= V

SS

-

-

30

-

300

200

40

-

-

-

50

100

mV

1. Guaranteed by design.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order)

.

k Ω ns ns

94/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

([WHUQDO

UHVHWFLUFXLW

Figure 47. Recommended NRST pin protection

1567

9''

538

,QWHUQDO5HVHW

)LOWHU

—)

670)

DLF

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

Table 49 . Otherwise the reset will not be taken into account by the device.

max level specified in

The parameters given in

Table 50 are guaranteed by design.

Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Symbol

Table 50. TIMx (1) characteristics

Parameter Conditions Min Max Unit t res(TIM) f

EXT

Res

TIM

Timer resolution time

Timer external clock frequency on CH1 to CH4

Timer resolution

-

-

f

TIMxCLK

= 72 MHz 13.9

0 f

TIMxCLK

= 72 MHz

1

0

-

-

f

TIMxCLK

/2

36

16 t

TIMxCLK ns

MHz

MHz bit t

COUNTER

16-bit counter clock period when internal clock is selected

1

f

TIMxCLK

= 72 MHz 0.0139

65536

910 t

TIMxCLK

µs t

MAX_COUNT

65536 × 65536 t

TIMxCLK

Maximum possible count

f

TIMxCLK

= 72 MHz -

1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.

59.6

s

DS5792 Rev 13

95/143

135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

I

2

C interface characteristics

The STM32F103xC, STM32F103xD and STM32F103xESTM32F103xF and STM32F103xG performance line I

2

C interface meets the requirements of the standard I

2

C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not

“true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V

DD is disabled, but is still present.

The I

2

C characteristics are described in

Table 51

. Refer also to

Section 5.3.14: I/O port characteristics

for more details on the input/output alternate function characteristics (SDA and SCL).

Symbol Parameter

Table 51. I 2 C characteristics

Standard mode

I

2

C

(1)

(2)

Min Max

Fast mode I

2

C

(1) (2)

Unit

Min Max t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time

4.7

4.0

250

-

-

-

-

-

-

3450

(3)

1000

300

1.3

0.6

100

-

-

-

-

-

-

900

(3)

300

300

µs ns t t t su(STA) su(STO) w(STO:STA)

C b

Start condition hold time

Repeated Start condition setup time

Stop condition setup time

Stop to Start condition time

(bus free)

Capacitive load for each bus line

4.0

4.7

4.0

4.7

-

-

-

-

-

400

0.6

0.6 -

0.6

1.3

-

-

-

-

400

µs

μ

μ s s pF t

SP

Pulse width of the spikes that are suppressed by the analog filter for standard and fast mode

0 50

(4)

0 50

(4)

1. Guaranteed by design.

2. f

PCLK1

must be at least 2 MHz to achieve standard mode I

2 achieve the fast mode I

2 mode maximum clock speed of 400 kHz.

C frequencies. It must be at least 4 MHz to

C frequencies and it must be a multiple of 10 MHz in order to reach the I2C fast

3. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region on the falling edge of SCL.

4. The minimum width of the spikes filtered by the analog filter is above t

SP

(max).

μ s

96/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Figure 48. I 2 C bus AC waveforms and measurement circuit

9''B,& 9''B,&

,ð&EXV

5

3

5

3

5

6

5

6

6'$

6&/

670

67$575(3($7('

67$57

WVX67$

67$57

6'$

WI6'$

WK67$

WU6'$

WZ6&//

WVX6'$

WK6'$

6 723

WZ67267$

6&/

WZ6&/+ WU6&/ WI6&/

WVX672

DLG

1. Measurement points are done at CMOS levels: 0.3V

DD

and 0.7V

DD.

2. Rs: Series protection resistors.

3. Rp: Pull-up resistors.

4. VDD_I2C : I2C bus supply

Table 52. SCL frequency (f

PCLK1

= 36 MHz.,V

DD_I2C

= 3.3 V)

(1)(2)

I2C_CCR value f

SCL

(kHz)

R

P

= 4.7 k Ω

400

300

200

0x801E

0x8028

0x803C

100

50

0x00B4

0x0168

20 0x0384

1. R

P

= External pull-up resistance, f

SCL

= I

2

C speed.

2. For speeds around 200 kHz, the tolerance on the achieved speed is of tolerance on the achieved speed 2%. These variations depend on the accuracy of the external components used to design the application.

± 5%. For other speed ranges, the

DS5792 Rev 13

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135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

I

2

S - SPI characteristics

Unless otherwise specified, the parameters given in Table 53

for SPI or in

Table 54 for I

2 S are derived from tests performed under ambient temperature, f

supply voltage conditions summarized in Table 10 .

PCLKx frequency and V

DD

Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I 2 S).

Symbol Parameter

Table 53. SPI characteristics

Conditions Min Max Unit

1/t f

SCK c(SCK)

SPI clock frequency

Master mode

Slave mode

-

-

18

18

MHz t r(SCK) t f(SCK)

SPI clock rise and fall time

Capacitive load: C = 30 pF 8 ns

DuCy(SCK)

SPI slave input clock duty cycle

Slave mode 30 70 % t su(NSS)

(1) t

h(NSS)

(1)

t t

w(SCKH)

(1) w(SCKL)

(1)

t t

su(MI)

(1)

su(SI)

(1)

NSS setup time

NSS hold time

SCK high and low time

Data input setup time

Slave mode

Slave mode

Master mode, f presc = 4

Master mode

PCLK

= 36 MHz,

4t

2t

PCLK

PCLK

50

5 -

-

-

60

Slave mode 5 t h(MI)

(1)

t

h(SI)

(1)

t

a(SO)

(1)(2)

t

dis(SO)

(1)(3)

t

v(SO)

(1)

t v(MO)

(1)

t

h(SO)

(1)

t

h(MO)

(1)

Data input hold time

Master mode

Slave mode

Data output access time Slave mode, f

Data output disable time

Data output valid time

Data output valid time

Data output hold time

Slave mode

PCLK

= 20 MHz

Slave mode (after enable edge)

Master mode (after enable edge)

Slave mode (after enable edge)

Master mode (after enable edge)

5

4

0

2

-

-

15

2

3t

PCLK

10

-

-

-

-

25

5

1. Guaranteed by characterization results.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z ns

98/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Figure 49. SPI timing diagram - slave mode and CPHA = 0

166LQSXW

W 68166

&3+$

&32/

&3+$

&32/

W Z6&.+

W Z6&./

W D62

0,62

287387

026,

,1387

W VX6,

Figure 50. SPI timing diagram - slave mode and CPHA = 1

(1)

W Y62

06%287

W K6,

06%,1

W F6&.

W K62

%,7287

%,7,1

W K166

W U6&.

W I6&.

W GLV62

/6%287

/6%,1

1. Measurement points are done at CMOS levels: 0.3V

DD

and 0.7V

DD.

DLE

DS5792 Rev 13

99/143

135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Figure 51. SPI timing diagram - master mode (1)

166LQSXW

+LJK

&3+$

&32/

&3+$

&32/

WF6&.

&3+$

&32/

&3+$

&32/

0,62

,13 87

026,

287387

WVX0,

WZ6&.+

WZ6&./

06%,1

WK0,

06%287

WY02

%,7,1

% , 7287

WK02

1. Measurement points are done at CMOS levels: 0.3V

DD

and 0.7V

DD.

WU6&.

WI6&.

/6%,1

/6%287

DLF

100/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Symbol Parameter

Table 54. I 2 S characteristics

Conditions f

DuCy(SCK)

CK

1/t c(CK)

I

I2S slave input clock duty cycle Slave mode

2

S clock frequency

Master mode (data: 16 bits,

Audio frequency = 48 kHz)

Slave mode t r(CK) t f(CK) t v(WS)

(1)

I

2

S clock rise and fall time

WS valid time

Capacitive load C

Master mode

L

= 50 pF t h(WS)

(1)

WS hold time Master mode

I2S2

I2S3 t su(WS)

(1)

t h(WS)

(1)

t w(CKH)

(1)

t

w(CKL)

(1)

WS setup time

WS hold time

CK high and low time

Slave mode

Slave mode

Master f

PCLK

= 16 MHz, audio frequency = 48 kHz t t t t t t t t

su(SD_MR)

(1)

su(SD_SR)

(1) h(SD_MR)

(1)(2) h(SD_SR)

(1)(2)

v(SD_ST)

(1)(2) h(SD_ST)

(1) v(SD_MT)

(1)(2)

h(SD_MT)

(1)

Data input setup time

Data input setup time

Data input hold time

Data output valid time

Data output hold time

Data output valid time

Data output hold time

Master receiver

I2S2

I2S3

Slave receiver

Master receiver

Slave receiver

Slave transmitter (after enable edge)

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

Master transmitter (after enable edge)

1. Guaranteed by design and/or characterization results.

2. Depends on f

PCLK

. For example, if f

PCLK

=8 MHz, then T

PCLK

= 1/f

PLCLK

=125 ns.

Min

30

1.522

0

11

-

-

0

312.5

345

2

6.5

1.5

0

4

3

2

0

0

0.5

-

Unit

%

MHz ns

Max

70

1.525

6.5

8

-

-

-

-

-

-

-

-

-

-

-

-

18

-

3

-

DS5792 Rev 13

101/143

135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Figure 52. I 2 S slave timing diagram (Philips protocol) (1)

1. Measurement points are done at CMOS levels: 0.3 × V

DD

and 0.7 × V

DD.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 53. I 2 S master timing diagram (Philips protocol) (1)

102/143

1. Guaranteed by characterization results.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

SD/SDIO MMC card host interface (SDIO) characteristics

Unless otherwise specified, the parameters given in Table 55

are derived from tests performed under ambient temperature, f

PCLKx summarized in

Table 10 .

frequency and V

DD

supply voltage conditions

Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate

function characteristics (D[7:0], CMD, CK).

Figure 54. SDIO high-speed mode

Figure 55. SD default mode

#+

$#-$

OUTPUT

T/6$ T/($

Symbol

Table 55. SD / MMC characteristics

Parameter f

PP

Clock frequency in data transfer mode tW(CKL) Clock low time, f

PP

= 16 MHz tW(CKH) Clock high time, f

PP

= 16 MHz t r t f

Clock rise time

Clock fall time

Conditions

C

L

≤ 30 pF

C

L

≤ 30 pF

C

L

≤ 30 pF

C

L

≤ 30 pF

C

L

≤ 30 pF

Min

0

-

-

32

30

DS5792 Rev 13

AI

Max

48

4

5

-

-

Unit

MHz ns

103/143

135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Symbol

Table 55. SD / MMC characteristics

Parameter Conditions Min t t

OV

OH

CMD, D inputs (referenced to CK) t

ISU

Input setup time C

L

≤ 30 pF t

IH

Input hold time C

L

≤ 30 pF

CMD, D outputs (referenced to CK) in MMC and SD HS mode

2

0

Output valid time C

L

≤ 30 pF -

Output hold time C

L

≤ 30 pF 0

CMD, D outputs (referenced to CK) i n SD default mode

(1) t t

OVD

OHD

Output valid default time

Output hold default time

C

L

≤ 30 pF

C

L

≤ 30 pF

1. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output.

-

0.5

USB characteristics

The USB interface is USB-IF certified (Full Speed).

Symbol

Table 56. USB startup time

Parameter t

STARTUP

(1)

USB transceiver startup time

1. Guaranteed by design.

Max

1

Max

7

-

-

-

6

-

Unit

µs

Unit ns ns ns

104/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Symbol

Table 57. USB DC electrical characteristics

Parameter Conditions Min.

(1)

Max.

(1)

Unit

Input levels

V

DD

V

DI

(4)

V

CM

(4)

V

SE

(4)

USB operating voltage (2)

Differential input sensitivity

Output levels

-

I(USB_DP, USB_DM)

Differential common mode range Includes V

Single ended receiver threshold

DI range

-

3.0

(3)

0.2

0.8

1.3

3.6

-

2.5

2.0

V

V

V

OL

V

OH

Static output level low

Static output level high

R

L

of 1.5 k Ω to 3.6 V

(5)

R

L

of 15 k Ω to V

SS

(5)

-

2.8

0.3

3.6

1. All the voltages are measured from the local ground potential.

2. To be compliant with the USB 2.0 full-speed electrical specification, the USB_DP (D+) pin should be pulled up with a 1.5 k Ω resistor to a 3.0-to-3.6 V voltage range.

3. The STM32F103xC/D/E USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V V

DD

voltage range.

4. Guaranteed by characterization results.

5. R

L

is the load connected on the USB drivers

V

Figure 56. USB timings: definition of data signal rise and fall time

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Table 58. USB: full-speed electrical characteristics

Driver characteristics

(1)

Symbol Parameter Conditions Min Max t r t f t rfm

V

CRS

Rise time

Fall Time

(2)

(2)

Rise/ fall time matching

Output signal crossover voltage

C

C

L

L

= 50 pF

= 50 pF t r

-

/t f

4

4

90

1.3

20

20

110

2.0

1. Guaranteed by design.

2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

Unit ns ns

%

V

DS5792 Rev 13

105/143

135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

5.3.18 CAN (controller area network) interface

Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate

function characteristics (CAN_TX and CAN_RX).

Note:

Unless otherwise specified, the parameters given in Table 59 are preliminary values derived

from tests performed under ambient temperature, f

PCLK2 voltage conditions summarized in

Table 10 .

frequency and V

DDA

supply

It is recommended to perform a calibration after each power-up.

Symbol

V

DDA

V

REF+

V

REF-

I

VREF f

ADC f

S

(2) f

TRIG

(2)

V

AIN

R

AIN

(2)

R

ADC

(2)

C

ADC

(2)

t

CAL

(2)

t lat

(2)

t latr

(2)

t

S

(2)

t

STAB

(2)

t

CONV

(2)

Parameter

Power supply

Positive reference voltage

Negative reference voltage

Current on the V

REF pin

input

ADC clock frequency

Sampling rate

External trigger frequency

Conversion voltage range

(3)

Table 59. ADC characteristics

Conditions Min

-

f

ADC

= 14 MHz

-

-

-

-

-

-

2.4

2.4

-

0.6

0.05

-

-

0 (V

SSA or V

REFtied to ground)

0

160

(1)

-

-

-

-

-

Typ

-

-

External input impedance

See

Equation 1

and

Table 60 for details

-

-

-

-

Sampling switch resistance

Internal sample and hold capacitor

-

Calibration time

Injection trigger conversion latency

Regular trigger conversion latency

Sampling time

Power-up time

Total conversion time

(including sampling time) f

ADC

= 14 MHz

f

ADC

= 14 MHz

f

ADC

= 14 MHz

f

ADC

= 14 MHz

-

f

ADC

= 14 MHz

-

Max

3.6

V

DDA

220

14

1

823

17

V

REF+

50

1

8

Unit

V

V

V

µA

MHz

MHz kHz

1/f

ADC

V

κΩ

κΩ pF

5.9

83

-

-

-

-

0.107

-

-

-

-

0.214

3

(4)

0.143

2 (4)

17.1

1.5

0

1

-

0

-

239.5

1/f

ADC

1 µs

18 µs

14 to 252 (t

S

for sampling +12.5 for successive approximation)

1/f

ADC

µs

1/f

ADC

µs

1/f

ADC

µs

1/f

ADC

µs

106/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

1. Guaranteed by characterization results.

2. Guaranteed by design.

3. V can be internally connected to V

Refer to

DDA

and V can be internally connected to V

for further details.

SSA

, depending on the package.

4. For external triggers, a delay of 1/f

PCLK2

must be added to the latency specified in Table 59

.

Equation 1: R

AIN

max formula

R

AIN

< f

ADC

× C

T

----------------------------------------------------------------

ADC

× ln ( 2 N + 2 )

– R

ADC

The formula above ( Equation 1 ) is used to determine the maximum external impedance

allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

T s

(cycles)

1.5

7.5

13.5

28.5

41.5

55.5

71.5

239.5

1. Guaranteed by design.

Table 60. R

AIN

max for f

ADC

= 14 MHz (1) t

S

(µs)

2.96

3.96

5.11

17.1

0.11

0.54

0.96

2.04

37.2

50

NA

NA

0.4

5.9

11.4

25.2

R

AIN

max (k Ω )

Symbol

Table 61. ADC accuracy - limited test conditions

(1)(2)

Parameter Test conditions Typ Max

(3)

Unit

ET

EO

EG

ED

EL

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f

PCLK2

= 56 MHz, f

ADC

= 14 MHz, R

AIN

< 10 k Ω ,

V

DDA

= 3 V to 3.6 V

T

A

= 25 °C

Measurements made after

ADC calibration

V

REF+

= V

DDA

±1.3

±1

±0.5

±0.7

±0.8

±2

±1.5

±1.5

±1

±1.5

LSB

1. ADC DC accuracy values are measured after internal calibration.

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I affect the ADC accuracy.

INJ(PIN)

and Σ I

INJ(PIN)

in Section 5.3.14

does not

3. Guaranteed by characterization results.

DS5792 Rev 13

107/143

135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Symbol Parameter

Table 62. ADC accuracy (1) (2)(3)

Test conditions Typ Max

(4)

Unit

ET

EO

EG

ED

EL

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f

PCLK2 f

ADC

= 56 MHz,

= 14 MHz, R

AIN

V

DDA

= 2.4 V to 3.6 V

Measurements made after

ADC calibration

< 10 k Ω ,

±2

±1.5

±1.5

±1

±1.5

±5

±2.5

±3

±2

±3

LSB

1. ADC DC accuracy values are measured after internal calibration.

2. Better performance could be achieved in restricted V

DD

, frequency, V

REF

and temperature ranges.

3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I affect the ADC accuracy.

INJ(PIN)

and Σ I

INJ(PIN)

in Section 5.3.14

does not

4. Guaranteed by characterization results.

Figure 57. ADC accuracy characteristics

%'

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1. Example of an actual transfer curve.

2. Ideal transfer curve.

3. End point correlation line.

4. E T = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.

EO = Offset Error: deviation between the first actual transition and the first ideal one.

EG = Gain Error: deviation between the last ideal transition and the last actual one.

ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.

EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.

108/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

9$,1

Figure 58. Typical connection diagram using the ADC

5$,1

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1. Refer to Table 59 for the values of R

AIN

, R

ADC

and C

ADC

.

2. C parasitic this, f

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

ADC

should be reduced.

parasitic

value will downgrade conversion accuracy. To remedy

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 59

or

Figure 60

, depending on whether V

REF+

is connected to V

DDA

or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 59. Power supply and reference decoupling (V

REF+ not connected to V

DDA

)

670)[[

9

5()

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—)Q)

—)Q)

9

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9

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5()±

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1. V

REF+

and V

REF–

inputs are available only on 100-pin packages.

DS5792 Rev 13

DLE

109/143

135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Figure 60. Power supply and reference decoupling (V

REF+ connected to V

DDA

)

670)[[

9

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9

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6HHQRWH

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1. V

REF+

and V

REF–

inputs are available only on 100-pin packages.

DL

110/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

Symbol

V

DDA

V

REF+

V

SSA

R

LOAD

(1)

R

O

(2)

Parameter

Analog supply voltage

Reference supply voltage

Ground

Resistive load with buffer

ON

Table 63. DAC characteristics

Min Typ

2.4

2.4

0 -

-

-

Max

3.6

3.6

0

Unit Comments

V -

V V

REF+

must always be below V

DDA

V -

5 -

Impedance output with buffer OFF

C

LOAD

(1)

load

DAC_OUT

min

(1)

Lower DAC_OUT voltage with buffer ON

I

DAC_OUT max

(1)

DAC_OUT

min

(1)

DAC_OUT max

(1)

DDVREF+

Higher DAC_OUT voltage with buffer ON

Lower DAC_OUT voltage with buffer OFF

Higher DAC_OUT voltage with buffer OFF

DAC DC current consumption in quiescent mode (Standby mode)

-

-

0.2 -

-

-

-

-

0.5

-

-

-

-

-

k Ω -

15

50

V

DDA

-

– 0.2 k Ω pF

V

V

When the buffer is OFF, the

Minimum resistive load between

DAC_OUT and V

SS

to have a 1% accuracy is 1.5 M Ω

Maximum capacitive load at

DAC_OUT pin (when the buffer is

ON).

It gives the maximum output excursion of the DAC.

It corresponds to 12-bit input code

(0x0E0) to (0xF1C) at V

REF+

= 3.6 V and (0x155) and (0xEAB) at V

REF+

= 2.4 V

-

V

REF+

1LSB

–

220 mV

It gives the maximum output excursion of the DAC.

V

I

DDA

DNL

(4)

INL

(3)

DAC DC current consumption in quiescent mode

(3)

Differential non linearity

Difference between two consecutive code-1LSB)

Integral non linearity

(difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023)

-

-

-

-

-

-

-

-

-

-

-

380

480

±0.5

±2

±1

±4

µA

µA

µA

With no load, worst code (0xF1C) at

V

REF+

= 3.6 V in terms of DC consumption on the inputs

With no load, middle code (0x800) on the inputs

With no load, worst code (0xF1C) at

V

REF+

= 3.6 V in terms of DC consumption on the inputs

LSB

Given for the DAC in 10-bit configuration

LSB

Given for the DAC in 12-bit configuration

LSB

Given for the DAC in 10-bit configuration

LSB

Given for the DAC in 12-bit configuration

DS5792 Rev 13

111/143

135

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE

Symbol Parameter

Table 63. DAC characteristics (continued)

Min Typ Max Unit Comments

Offset

(3)

Gain error

(3)

Offset error

(difference between measured value at Code

(0x800) and the ideal value

= V

REF+

/2)

Gain error -

-

-

-

-

-

-

±10

±3

±12

±0.5

mV

LSB

LSB

%

-

Given for the DAC in 10-bit at V

REF+

= 3.6 V

Given for the DAC in 12-bit at V

REF+

= 3.6 V

Given for the DAC in 12bit configuration t

SETTLING

(3)

Update rate

(3)

Settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when DAC_OUT reaches final value ±1LSB

Max frequency for a correct

DAC_OUT change when small variation in the input code (from code i to i+1LSB)

-

3

-

4

1

µs

MS/ s

C

C

LOAD

LOAD

≤ 50 pF, R

≤ 50 pF, R

LOAD

LOAD

≥

≥

5 k

5 k

Ω

Ω t

WAKEUP

(3)

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

6.5

10 µs

C

LOAD

≤ 50 pF, R

LOAD

≥ 5 k Ω input code between lowest and highest possible ones.

PSRR+

(1)

Power supply rejection ratio

(to V

DDA

) (static DC measurement

–67 –40 dB No , C

LOAD

= 50 pF

1. Guaranteed by design.

2. Guaranteed by characterization.

3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs.

4. Guaranteed by characterization results.

Figure 61. 12-bit buffered /non-buffered DAC

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1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

112/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics

5.3.21 Temperature sensor characteristics

Symbol

Table 64. TS characteristics

Parameter Min Typ t

T

L

Avg_Slope

V

T

25

START

(1)

S_temp

(2)(1)

V

SENSE

linearity with temperature

Average slope

Voltage at 25 °C

Startup time

ADC sampling time when reading the temperature

-

4.0

1.34

4

-

± 1

4.3

1.43

-

-

1. Guaranteed by design.

2. Shortest sampling time can be determined in the application by multiple iterations.

Max

± 2

4.6

1.52

10

17.1

Unit

°C mV/°C

V

µs

µs

DS5792 Rev 13

113/143

135

Package information STM32F103xC, STM32F103xD, STM32F103xE

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK ® is an ST trademark.

114/143

Figure 62. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package outline

& 6HDWLQJSODQH

GGG &

$

$ $

H

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$ $

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)

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H

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0

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HHH

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0

0

& $ %

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1. Drawing is not to scale.

Table 65. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Typ Min Max

A

(2)

A1

A2

A3

A4

-

0.250

0.810

0.225

0.585

-

0.300

0.910

0.26

0.650

1.700

0.350

1.010

0.295

0.715

-

0.098

0.0319

0.0089

0.0230

-

0.0118

0.0358

0.0102

0.0256

0.0669

0.0138

0.0398

0.0116

0.0281

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Package information

Table 65. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Typ Min Max

E

E1 e

F b

D

D1 ddd eee fff

0.350

9.900

-

9.900

-

-

-

-

-

-

0.400

10.000

8.800

10.000

8.800

0.800

0.600

-

-

-

0.450

10.100

-

10.100

-

-

-

0.100

0.150

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. STATSChipPAC package dimensions.

0.0138

0.3898

-

0.3898

-

-

-

-

-

-

0.0157

0.3937

0.3465

0.3937

0.3465

0.0315

0.0236

-

-

-

0.0177

0.3976

-

0.3976

-

-

-

0.0039

0.0059

0.0031

Figure 63. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package recommended footprint

'SDG

'VP

/)%*$B;B)3B9

Pitch

Dpad

Table 66. LFBGA144 recommended PCB design rules (0.8 mm pitch BGA)

Dimension Recommended values

0.8 mm

0.400 mm

DS5792 Rev 13

115/143

135

Package information STM32F103xC, STM32F103xD, STM32F103xE

Table 66. LFBGA144 recommended PCB design rules (0.8 mm pitch BGA) (continued)

Dimension Recommended values

UBM

Dsm

Stencil opening

Stencil thickness

Pad trace width

Ball Diameter

0.350 mm

0.470 mm typ. (depends on the solder mask registration tolerance)

0.400 mm

Between 0.100 mm to 0.125 mm

0.120 mm

0.400 mm

Device marking for LFBGA144 package

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

Figure 64. LFBGA144 marking example (package top view)

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670)

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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity

116/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Package information

Figure 65. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline

= 6HDWLQJSODQH

GGG =

$ $

H

(

)

$ $

$EDOO

LGHQWLILHU

$EDOO

LQGH[DUHD

;

(

$

)

H

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.

<

%277209,(:

‘EEDOOV

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HHH

III

0

0

= < ;

=

7239,(:

+B0(B9

1. Drawing is not to scale.

D

D1

E

E1 e

F ddd

A

A1

A2

A4 b

Table 67. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

-

-

-

-

9.850

-

9.850

-

0.270

-

-

0.450

-

-

0.300

-

0.500

10.000

7.200

10.000

7.200

0.800

1.400

-

1.700

-

-

0.800

0.550

10.150

-

10.150

-

-

-

0.120

-

0.0106

-

-

0.0177

0.3878

-

0.3878

-

-

-

-

-

-

0.0118

-

0.0197

0.3937

0.2835

0.3937

0.2835

0.0315

0.0551

-

0.0669

-

-

0.0315

0.0217

0.3996

-

0.3996

-

-

-

0.0047

DS5792 Rev 13

117/143

135

Package information STM32F103xC, STM32F103xD, STM32F103xE

Table 67. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data millimeters inches (1)

Symbol

Min Typ Max Min Typ Max eee fff

-

-

-

-

0.150

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

-

-

-

0.0059

0.0031

Figure 66. LFBGA100 – 100-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package recommended footprintoutline

'SDG

'VP

+B)3B9

Pitch

Dpad

Dsm

Table 68. LFBGA100 recommended PCB design rules (0.8 mm pitch BGA)

Dimension Recommended values

Stencil opening

Stencil thickness

Pad trace width

0.8

0.500 mm

0.570 mm typ. (depends on the soldermask registration tolerance)

0.500 mm

Between 0.100 mm and 0.125 mm

0.120 mm

118/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Package information

Device marking for LFBGA100 package

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

Figure 67. LFBGA100 marking example (package top view)

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670)

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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity

DS5792 Rev 13

119/143

135

Package information STM32F103xC, STM32F103xD, STM32F103xE

120/143

Figure 68. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline

H EEE =

)

*

$

'HWDLO$

H

H

+

*

H )

$

$

6LGHYLHZ %XPSVLGH

' ;

<

%XPS

$

$ 2ULHQWDWLRQ

UHIHUHQFH

(

HHH =

FFF

GGG

E

; < =

=

=

6HDWLQJSODQH

DDD

[

'HWDLO$

URWDWHGƒ

:DIHUEDFNVLGH

&5B0(B9

1. Drawing is not to scale.

2. Primary datum Z and seating plane are defined by the spherical crowns of the ball.

Table 69. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

A

A1

A2

0.535

0.205

0.330

0.585

0.230

0.355

0.635

0.255

0.380

0.0211

0.0081

0.0130

0.0230

0.0091

0.0140

0.0250

0.0100

0.0150

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Package information

Table 69. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data millimeters inches (1)

Symbol

Min Typ Max Min Typ Max b

(2)

0.290

0.320

0.350

0.0114

0.0126

0.0138

H

L

D

E

F

G e e1 eee aaa

Number of balls

4.446

4.375

-

-

-

-

-

-

-

0.500

3.500

0.447

0.483

4.466

4.395

0.250

0.200

0.05

0.10

4.486

4.415

-

-

-

-

-

-

-

-

64

0.1750

0.1722

-

-

-

-

-

-

-

0.0197

0.1378

0.0176

0.0190

0.1758

0.1730

0.0098

0.0079

0.0020

0.0039

0.1766

0.1738

-

-

-

-

-

-

-

-

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Dimension is measured at the maximum ball diameter parallel to primary datum Z.

Figure 69. WLCSP64 - 64-ball, 4.4757

x 4.4049 mm, 0.5 mm pitch wafer level chip scale package recommended footprint

'SDG

'VP

:/&63B&5B)3B9

Table 70. WLCSP64 recommended PCB design rules (0.5 mm pitch)

Dimension Recommended values

Pitch

Dpad

Dsm

Stencil Opening

0.5

250 µm

300 µm

320 µm

DS5792 Rev 13

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135

Package information STM32F103xC, STM32F103xD, STM32F103xE

Table 70. WLCSP64 recommended PCB design rules (0.5 mm pitch) (continued)

Dimension Recommended values

Stencil Thickness

Pad trace width

Ball Diameter

Between 100 µm to 125 µm

100 µm

320 µm

6.4 LQFP144 package information

Figure 70. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline

6($7,1*

3/$1(

&

F

FFF &

'

'

'

PP

*$8*(3/$1(

/

/

.

122/143

3,1

,'(17,),&$7,21

1. Drawing is not to scale.

H

DS5792 Rev 13

$B0(B9

STM32F103xC, STM32F103xD, STM32F103xE Package information

Table 71. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max e

L

L1

D3

E

E1

E3 k ccc

D

D1 b c

A

A1

A2

-

0.050

1.350

0.170

0.090

21.800

19.800

-

21.800

19.800

-

-

0.450

-

0°

-

-

-

1.400

0.220

-

22.000

20.000

17.500

22.000

20.000

17.500

0.500

0.600

1.000

3.5°

-

1.600

0.150

1.450

0.270

0.200

22.200

20.200

-

22.200

20.200

-

-

0.750

-

7°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

-

0.8583

0.7795

-

-

0.0177

-

0°

-

-

0.0020

0.0531

0.0067

0.0035

0.8583

0.7795

0.6890

0.8661

0.7874

0.6890

0.0197

0.0236

0.0394

3.5°

-

-

-

0.0551

0.0087

-

0.8661

0.7874

-

0.8740

0.7953

-

-

0.0295

-

7°

0.0031

0.0630

0.0059

0.0571

0.0106

0.0079

0.8740

0.7953

DS5792 Rev 13

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135

Package information STM32F103xC, STM32F103xD, STM32F103xE

Figure 71. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint

1. Dimensions are expressed in millimeters.

DLH

124/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Package information

Device marking for LQFP144 package

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Figure 72. LQFP144 marking example (package top view)

2SWLRQDOJDWHPDUN

3URGXFWLGHQWLILFDWLRQ

5HYLVLRQFRGH

;

670)=(7

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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity

DS5792 Rev 13

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135

Package information

6.5

STM32F103xC, STM32F103xD, STM32F103xE

LQFP100 package information

Figure 73. LQFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline

3%!4).'0,!.%

#

C

MM

'!5'%0,!.%

CCC #

$

$

$

,

, +

0).

)$%.4)&)#!4)/.

E

,?-%?6

1. Drawing is not to scale.

c

D

D1

D3

A

A1

A2 b

E

E1

Symbol

Table 72. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data millimeters inches

(1)

Min

-

0.050

1.350

0.170

0.090

15.800

13.800

-

15.800

13.800

Typ

-

-

1.400

0.220

-

16.000

14.000

12.000

16.000

14.000

Max

1.600

0.150

1.450

0.270

0.200

16.200

14.200

-

16.200

14.200

Min

-

0.0020

0.0531

0.0067

0.0035

0.6220

0.5433

-

0.6220

0.5433

Typ

-

-

0.0551

0.0087

-

0.6299

0.5512

0.4724

0.6299

0.5512

Max

0.0630

0.0059

0.0571

0.0106

0.0079

0.6378

0.5591

-

0.6378

0.5591

126/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Package information

Table 72. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min

L1 k ccc

E3 e

L

-

-

0.450

-

0°

-

12.000

0.500

0.600

1.000

3.5°

-

-

-

0.750

-

7°

0.08

1. Values in inches are converted from mm and rounded to 4 decimal digits.

-

-

0.0177

-

0°

-

Typ

0.4724

0.0197

0.0236

0.0394

3.5°

-

Max

-

-

0.0295

-

7°

0.0031

Figure 74. LQFP100 recommended footprint

1. Dimensions are in millimeters.

AIC

DS5792 Rev 13

127/143

135

Package information STM32F103xC, STM32F103xD, STM32F103xE

Device marking for LQFP100 package

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Figure 75. LQFP100 marking example (package top view)

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^dDϯϮ&ϭϬϯ sϴdϲ y z tt

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PDUN

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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity

128/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE

6.6 LQFP64 package information

Package information

Figure 76. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline

6($7,1*3/$1(

&

PP

*$8*(3/$1(

FFF &

.

'

'

' /

/

E

3,1

,'(17,),&$7,21

1. Drawing is not in scale.

H

:B0(B9

Table 73. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max c

D

D1

D3

A

A1

A2 b

E

E1

-

0.050

1.350

0.170

0.090

-

-

-

-

-

-

-

1.400

0.220

-

12.000

10.000

7.500

12.000

10.000

1.600

0.150

1.450

0.270

0.200

-

-

-

-

-

-

0.0020

0.0531

0.0067

0.0035

-

-

-

-

-

-

-

0.0551

0.0087

-

0.4724

0.3937

0.2953

0.4724

0.3937

0.0630

0.0059

0.0571

0.0106

0.0079

-

-

-

-

-

DS5792 Rev 13

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135

Package information STM32F103xC, STM32F103xD, STM32F103xE

Table 73. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min Typ Max

E3 e

θ

L

L1 ccc

-

-

0°

0.450

-

-

7.500

0.500

3.5°

0.600

1.000

-

-

-

7°

0.750

-

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

-

-

0°

0.0177

-

-

0.2953

0.0197

3.5°

0.0236

0.0394

-

-

-

7°

0.0295

-

0.0031

Figure 77. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint

1. Dimensions are in millimeters.

130/143

DS5792 Rev 13

AIC

STM32F103xC, STM32F103xD, STM32F103xE Package information

Device marking for LQFP64 package

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Figure 78. LQFP64 marking example (package top view)

5HYLVLRQFRGH

3URGXFWLGHQWLILFDWLRQ

^dDϯϮ&ϭϬϯ

Zdϲ

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z tt

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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity

DS5792 Rev 13

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135

Package information STM32F103xC, STM32F103xD, STM32F103xE

The maximum chip junction temperature (T

J max) must never exceed the values given in

Table 10: General operating conditions on page 44 .

The maximum chip-junction temperature, T

J using the following equation:

max, in degrees Celsius, may be calculated

T

J

max = T

A

max + (P

D

max x Θ

JA

)

Where:

• T

A

max is the maximum ambient temperature in °C,

• Θ

JA

is the package junction-to-ambient thermal resistance, in °C/W,

• P

D

max is the sum of P

INT

max and P

I/O max (P

D

max = P

INT

max + P

I/O max),

• P

INT

max is the product of I

DD and internal power.

V

DD

, expressed in Watts. This is the maximum chip

P

I/O

max represents the maximum power dissipation on output pins where:

P

I/O

max = Σ (V

OL

× I

OL

) + Σ ((V

DD

– V

OH

) × I

OH

), taking into account the actual V

OL application.

/ I

OL

and V

OH

/ I

OH of the I/Os at low and high level in the

Symbol

Θ

JA

Table 74. Package thermal characteristics

Parameter

Thermal resistance junction-ambient

LFBGA144 - 10 × 10 mm / 0.8 mm pitch

Thermal resistance junction-ambient

LQFP144 - 20 × 20 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LFBGA100 - 10 × 10 mm / 0.8 mm pitch

Thermal resistance junction-ambient

LQFP100 - 14 × 14 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP64 - 10 × 10 mm / 0.5 mm pitch

Thermal resistance junction-ambient

WLCSP64

Value

40

30

40

46

45

50

Unit

°C/W

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org

132/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE

6.7.2 Selecting the product temperature range

Package information

When ordering the microcontroller, the temperature range is specified in the ordering

information scheme shown in Table 75: Ordering information scheme .

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.

As applications do not commonly use the STM32F103xC, STM32F103xD and

STM32F103xE at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application.

The following examples show how to calculate the temperature range needed for a given application.

Example 1: High-performance application

Assuming the following application conditions:

Maximum ambient temperature T

Amax

I

DDmax

= 50 mA, V

DD

= 82 °C (measured according to JESD51-2),

= 3.5 V, maximum 20 I/Os used at the same time in output at low level with I

OL

= 8 mA, V

OL

= 0.4 V and maximum 8 I/Os used at the same time in output at low level with I

OL

= 20 mA, V

OL

= 1.3 V

P

INTmax =

50 mA × 3.5 V= 175 mW

P

IOmax = 20

× 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW

This gives: P

INTmax

= 175 mW and P

IOmax

= 272 mW:

P

Dmax =

175

+

272 = 447 mW

Thus: P

Dmax

= 447 mW

Using the values obtained in Table 74

T

Jmax

is calculated as follows:

– For LQFP100, 46 °C/W

T

Jmax

= 82 °C + (46 °C/W × 447 mW) = 82 °C + 20.6 °C = 102.6 °C

This is within the range of the suffix 6 version parts (–40 < T

J

< 105 °C).

In this case, parts must be ordered at least with the temperature range suffix 6 (see

Table 75: Ordering information scheme ).

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature T

J specified range.

remains within the

Assuming the following application conditions:

Maximum ambient temperature T

Amax

I

DDmax

= 20 mA, V

DD

= 115 °C (measured according to JESD51-2),

= 3.5 V, maximum 20 I/Os used at the same time in output at low level with I

OL

= 8 mA, V

OL

= 0.4 V

P

INTmax =

20 mA × 3.5 V= 70 mW

P

IOmax = 20

× 8 mA × 0.4 V = 64 mW

This gives: P

INTmax

= 70 mW and P

IOmax

= 64 mW:

P

Dmax =

70

+

64 = 134 mW

Thus: P

Dmax

= 134 mW

DS5792 Rev 13

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135

Package information STM32F103xC, STM32F103xD, STM32F103xE

Using the values obtained in Table 74

T

Jmax

is calculated as follows:

– For LQFP100, 46 °C/W

T

Jmax

= 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C

This is within the range of the suffix 7 version parts (–40 < T

J

< 125 °C).

In this case, parts must be ordered at least with the temperature range suffix 7 (see

Table 75: Ordering information scheme ).

Figure 79. LQFP100 P

D

max vs. T

A

700

600

500

400

300

200

100

0

65 75 85 95 105 115 125 135

T

A

(°C)

Suffix 6

Suffix 7

134/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Ordering information

Example:

Table 75. Ordering information scheme

STM32 F 103 R C T 6 xxx

Device family

STM32 = Arm-based 32-bit microcontroller

Product type

F = general-purpose

Device subfamily

103 = performance line

Pin count

R = 64 pins

V = 100 pins

Z = 144 pins

Flash memory size

C = 256 Kbytes of Flash memory

D = 384 Kbytes of Flash memory

E = 512 Kbytes of Flash memory

Package

H = BGA

T = LQFP

Y = WLCSP64

Temperature range

6 = Industrial temperature range, –40 to 85 °C.

7 = Industrial temperature range, –40 to 105 °C.

Options xxx = programmed parts

TR = tape and real

For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.

DS5792 Rev 13

135/143

135

Revision history STM32F103xC, STM32F103xD, STM32F103xE

Date

07-Apr-2008

22-May-2008

Revision

1

2

Table 76.Document revision history

Changes

Initial release.

Document status promoted from Target Specification to Preliminary

Data.

Section 1: Introduction and

Section 2.2: Full compatibility throughout the family

modified. Small text changes.

Note 2 added in

Table 2: STM32F103xC, STM32F103xD and

STM32F103xE features and peripheral counts on page 11

.

LQPF100/BGA100 column added to Table 6: FSMC pin definition on page 38

.

Values and Figures added to Maximum current consumption on page 62 (see Table 18 , Table 19 , Table 20 and Table 21 and see

Figure 14 , Figure 15 , Figure 17 , Figure 18 and Figure 19 ).

Values added to Typical current consumption on page 73 (see

Table 22 , Table 23 and Table 24 ). Table 19: Typical current consumption in Standby mode removed.

Note 4 and Note 1 added to Table 65: USB DC electrical characteristics and Table 66: USB: full-speed electrical characteristics on page 129 , respectively.

V

USB

added to Table 65: USB DC electrical characteristics on page 129 .

Figure 68: Recommended footprint(1) on page 143 corrected.

Equation 1 corrected. Figure 73: LQFP100 PD max vs. TA on page 149 modified.

Tolerance values corrected in Table 74: LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data on page 139 .

136/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Revision history

Date

21-Jul-2008

Revision

3

Table 76.Document revision history

Changes

Document status promoted from Preliminary Data to full datasheet.

FSMC (flexible static memory controller) on page 22 modified.

Number of complementary channels corrected in Figure 1:

STM32F103xF, STM32F103xD and STM32F103xGSTM32F103xF and

STM32F103xG performance line block diagram .

Power supply supervisor on page 23 modified and V

DDA

Table 14: General operating conditions on page 59 .

added to

Table notes revised in Section 5: Electrical characteristics .

Capacitance modified in Figure 12: Power supply scheme on page 57 .

Table 60: SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) updated.

Table 61: SPI characteristics modified, t h(NSS) modified in Figure 49:

SPI timing diagram - slave mode and CPHA = 0 on page 123 .

Minimum SDA and SCL fall time value for Fast mode removed from

Table 59: I2C characteristics on page 120 , note 1 modified.

I

DD_VBAT

values and some I

DD

values with regulator in run mode added to Table 21: Typical and maximum current consumptions in Stop and

Standby modes on page 68 .

Table 34: Flash memory endurance and data retention on page 87 updated.

t su(NSS)

modified in Table 61: SPI characteristics on page 122 .

EO corrected in Table 70: ADC accuracy on page 132 . Figure 58:

Typical connection diagram using the ADC on page 133 and note below corrected.

Typical T

S_temp page 137 .

value removed from Table 72: TS characteristics on

Section 6.1: Package mechanical data on page 138 updated.

Small text changes.

DS5792 Rev 13

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142

Revision history STM32F103xC, STM32F103xD, STM32F103xE

Date

12-Dec-2008

Revision

4

Table 76.Document revision history

Changes

Timers specified on page 1 (motor control capability mentioned).

Section 2.2: Full compatibility throughout the family updated.

Table 6: High-density timer feature comparison added.

General-purpose timers (TIMx) and Advanced-control timers (TIM1 and

TIM8) on page 27 updated.

Figure 1: STM32F103xF, STM32F103xD and

STM32F103xGSTM32F103xF and STM32F103xG performance line block diagram modified.

Note 10 added, main function after reset and Note 5 on page 44 updated in Table 8: High-density STM32F103xx pin definitions .

Note 2 modified below Table 11: Voltage characteristics on page 58 ,

|DV

DDx

| min and |DV

DDx

| min removed.

Note 2 and P

D

values for LQFP144 and LFBGA144 packages added to

Table 14: General operating conditions on page 59 .

Measurement conditions specified in Section 5.3.5: Supply current characteristics on page 62 .

Max values at T

A

= 85 °C and T

A

= 105 °C updated in Table 21: Typical and maximum current consumptions in Stop and Standby modes on page 68 .

Section 5.3.10: FSMC characteristics on page 87 updated.

Data added to Table 50: EMI characteristics on page 111 .

I

VREF

added to Table 67: ADC characteristics on page 130 .

Table 81: Package thermal characteristics on page 146 updated.

Small text changes.

138/143

DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Revision history

Date

30-Mar-2009

Revision

5

Table 76.Document revision history

Changes

I/O information clarified on page 1 . Figure 4: STM32F103xC and

STM32F103xE performance line BGA100 ballout corrected.

I/O information clarified on page 1 .

In Table 5: High-density STM32F103xx pin definitions :

– I/O level of pins PF11, PF12, PF13, PF14, PF15, G0, G1 and G15 updated

– PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column

PG14 pin description modified in Table 6: FSMC pin definition .

Figure 9: Memory map on page 54 modified.

Note modified in Table 18: Maximum current consumption in Run mode, code with data processing running from Flash and Table 20:

Maximum current consumption in Sleep mode, code running from Flash or RAM .

Figure 17 , Figure 18 and Figure 19 show typical curves (titles changed).

Table 25: High-speed external user clock characteristics and Table 26:

Low-speed external user clock characteristics modified. ACC

HSI values modified in Table 29: HSI oscillator characteristics .

max

FSMC configuration modified for Asynchronous waveforms and timings . Notes modified below Figure 24: Asynchronous nonmultiplexed SRAM/PSRAM/NOR read waveforms and Figure 25:

Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms .

t w(NADV)

values modified in Table 35: Asynchronous non-multiplexed

SRAM/PSRAM/NOR read timings and Table 39: Asynchronous multiplexed PSRAM/NOR write timings . t h(Data_NWE)

modified in

Table 36: Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings

In Table 41: Synchronous multiplexed PSRAM write timings and

Table 43: Synchronous non-multiplexed PSRAM write timings :

– t v(Data-CLK)

renamed as t d(CLKL-Data)

– t d(CLKL-Data) min value removed and max value added

– t h(CLKL-DV)

/ t h(CLKL-ADV) removed

Figure 28: Synchronous multiplexed NOR/PSRAM read timings ,

Figure 29: Synchronous multiplexed PSRAM write timings and

Figure 31: Synchronous non-multiplexed PSRAM write timings modified.

Figure 52: I2S slave timing diagram (Philips protocol)(1) and Figure 53:

I2S master timing diagram (Philips protocol)(1) modified.

WLCSP64 package added (see Figure 8: STM32F103xC and

STM32F103xE performance line WLCSP64 ballout, ball side , Table 8:

High-density STM32F103xx pin definitions , Figure 65: WLCSP, 64-ball

4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline and Table 76: WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data ).

Small text changes.

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142

Revision history STM32F103xC, STM32F103xD, STM32F103xE

Date

21-Jul-2009

24-Sep-2009

Revision

6

7

Table 76.Document revision history

Changes

Figure 1: STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram updated.

Note 5 updated and Note 4 added in

Table 5: High-density

STM32F103xC/D/E pin definitions .

V

RERINT

voltage

.

and T

Coeff

added to

Table 13: Embedded internal reference

Table 16: Maximum current consumption in Sleep mode, code running from Flash or RAM modified.

f

HSE_ext

min modified in Table 21: High-speed external user clock characteristics .

C

L1

and C

L2

replaced by C in Table 23: HSE 4-16 MHz oscillator characteristics and

Table 24: LSE oscillator characteristics (f

LSE

32.768 kHz)

, notes modified and moved below the tables.

=

Note 1 modified below

Figure 29: Synchronous multiplexed PSRAM write timings .

Table 25: HSI oscillator characteristics

modified.

Conditions removed from Table 27: Low-power mode wakeup timings .

Jitter added to Table 28: PLL characteristics .

Figure 47: Recommended NRST pin protection modified.

In

Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings

: t h(BL_NOE)

and t h(A_NOE) modified.

In

Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings

: t h(A_NWE)

and t h(Data_NWE)

modified.

In

Table 33: Asynchronous multiplexed PSRAM/NOR read timings

: t h(AD_NADV)

and t h(A_NOE)

modified.

In

Table 34: Asynchronous multiplexed PSRAM/NOR write timings :

t h(A_NWE)

modified.

In

Table 35: Synchronous multiplexed NOR/PSRAM read timings :

t h(CLKH-NWAITV)

modified.

In

Table 40: Switching characteristics for NAND Flash read and write cycles

: t h(NOE-D)

modified.

Table 53: SPI characteristics

modified. Values added to

Table 54: I

2

S characteristics and

Table 55: SD / MMC characteristics .

C

ADC

and R

AIN

parameters modified in Table 59: ADC characteristics

.

R

AIN

max values modified in Table 60: R

AIN

max for f

ADC

= 14 MHz

.

Table 71: DAC characteristics modified. Figure 61: 12-bit buffered /nonbuffered DAC added.

Figure 63: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline and Table 75: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data updated.

Number of DACs corrected in

Table 3: STM32F103xx family

.

I

DD_VBAT

updated in

Table 17: Typical and maximum current consumptions in Stop and Standby modes

.

Figure 16: Typical current consumption on V

BAT temperature at different V

BAT values added.

with RTC on vs.

IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to

IEC 61967-2 in Section 5.3.11: EMC characteristics on page 86 .

Table 63: DAC characteristics modified. Small text changes.

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DS5792 Rev 13

STM32F103xC, STM32F103xD, STM32F103xE Revision history

Date

19-Apr-2011

30-Sept-2014

23-Feb-2015

Revision

8

9

10

Table 76.Document revision history

Changes

Updated package choice for 103Rx in Table 2

Updated footnotes below

Table 7: Voltage characteristics on page 43 and Table 8: Current characteristics on page 43

Updated tw min in Table 21: High-speed external user clock characteristics on page 58

Updated startup time in

Table 24: LSE oscillator characteristics (f

LSE

32.768 kHz) on page 61

=

Updated note 2 in

Table 51: I

2

C characteristics on page 96

Updated

Figure 48: I

2

C bus AC waveforms and measurement circuit

Updated

Figure 47: Recommended NRST pin protection

Updated

Section 5.3.14: I/O port characteristics

Updated

Table 35: Synchronous multiplexed NOR/PSRAM read timings on page 72

Updated FSMC Figure 26

thru Figure 31

Updated

Figure 41.: NAND controller waveforms for common memory write access and

Figure 48.: I 2 C bus AC waveforms and measurement circuit

Added Section 5.3.13: I/O current injection characteristics

Updated Figure 67 and added

Table 69: WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data on page 120

LQFP64 package mechanical data updated: see Figure 73.: LQFP64 –

10 x 10 mm 64 pin low-profile quad flat package outline

and Table 73:

LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data on page 129

.

Added Note 7

in Table 5: High-density STM32F103xC/D/E pin definitions on page 31

.

Updated

Note 10 in

Table 5: High-density STM32F103xC/D/E pin definitions on page 31

.

Modified Note 2 in Table 62: ADC accuracy on page 108

Modified Note 3 in Table 62: ADC accuracy on page 108

Modified notes in Table 51: I 2 C characteristics on page 96

Updated

Figure 51: SPI timing diagram - master mode

(1)

on page 100

Updated Figure 66.: BGA pad footprint

, Figure 70: LQFP144 - 144-pin,

20 x 20 mm low-profile quad flat package outline ,

Figure 73.: LQFP100

– 14 x 14 mm 100 pin low-profile quad flat package outline ,

Figure 74.:

LQFP100 recommended footprint ,

Figure 76.: LQFP64 – 10 x 10 mm

64 pin low-profile quad flat package outline

,

Figure 77.: LQFP64 - 64pin, 10 x 10 mm low-profile quad flat recommended footprint

Added Figure 72.: LQFP144 marking example (package top view)

,

Figure 75.: LQFP100 marking example (package top view)

,

Figure 78.:

LQFP64 marking example (package top view)

Updated Table 72: LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data

,

Table 73: LQFP64 – 10 x 10 mm 64 pin lowprofile quad flat package mechanical data

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Revision history STM32F103xC, STM32F103xD, STM32F103xE

Date

31-08-2015

26-Nov-2015

10-Jul-2018

Revision

11

12

13

Table 76.Document revision history

Changes

Replaced USBDP and USBDM by USB_DP and USB_DM in the whole document.

Updated:

– Introduction

– Reference standard in

Table 43: ESD absolute maximum ratings

.

– Updated I

DDA

description in

Table 63: DAC characteristics .

–

Section : I2C interface characteristics

–

Figure 62: LFBGA144 – 144-ball low profile fine pitch ball grid array,

10 x 10 mm, 0.8 mm pitch, package outline

– Updated sentence before

Figure 78: LQFP64 marking example

(package top view)

.

–

Figure 65: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline

and sentence before

Figure 75: LQFP100 marking example (package top view)

–

Figure 68: WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline

–

Figure 48: I

2

C bus AC waveforms and measurement circuit on page 97

–

Section 6.1: LFBGA144 package information

and Section 6.2:

LFBGA100 package information

.

–

Table 20: Peripheral current consumption

Added:

–

Figure 63: LFBGA144 – 144-ball low profile fine pitch ball grid array,

10 x 10 mm, 0.8 mm pitch, package recommended footprint

–

Figure 64: LFBGA144 marking example (package top view)

–

Figure 66: LFBGA100 – 100-ball low profile fine pitch ball grid array,

10 x 10 mm, 0.8 mm pitch, package recommended footprintoutline

–

Figure 69: WLCSP64 - 64-ball, 4.4757 x 4.4049 mm, 0.5 mm pitch wafer level chip scale package recommended footprint

–

Table 66: LFBGA144 recommended PCB design rules (0.8 mm pitch

BGA)

–

Table 68: LFBGA100 recommended PCB design rules (0.8 mm pitch

BGA)

–

Table 70: WLCSP64 recommended PCB design rules (0.5 mm pitch)

.

Updated:

–

Table 59: ADC characteristics

–

Table 65: LFBGA144 – 144-ball low profile fine pitch ball grid array,

10 x 10 mm, 0.8 mm pitch, package mechanical data

–

Table 66: LFBGA144 recommended PCB design rules (0.8 mm pitch

BGA)

Added:

–

Note 3

on

Table 7: Voltage characteristics

Updated:

–

Table 2: STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts

–

Section 7: Ordering information

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STM32F103xC, STM32F103xD, STM32F103xE

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