STMicroelectronics STM32L4S5ZI Datasheet

Yes

N/A

Yes

N/A

Yes

N/A

Yes

N/A

Yes

N/A

N/A

N/A

• Write protection (WRP): the protected area is protected against erasing and programming:

– In single bank mode, four areas can be selected with 8-Kbyte granularity.

– In dual bank mode, two areas per bank can be selected with 4-Kbyte granularity.

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• Proprietary code readout protection (PCROP): a part of the Flash memory can be protected against read and write from third parties. The protected area is execute-only and it can only be reached by the STM32 CPU as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited:

– In single bank mode, two areas can be selected with 128-bit granularity.

– In dual bank mode, one area per bank can be selected with 64-bit granularity.

An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0.

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

• Single error detection and correction

• Double error detection

• The address of the ECC fail can be read in the ECC register.

The STM32L4S5xx, STM32L4S7xx and STM32L4S9xx devices feature 640 Kbytes of embedded SRAM. This SRAM is split into three blocks:

• 192 Kbytes mapped at address 0x2000 0000 (SRAM1).

• 64 Kbytes located at address 0x1000 0000 with hardware parity check (SRAM2).

This memory is also mapped at address 0x2003 0000 offering a contiguous address space with the SRAM1.

This block is accessed through the ICode/DCode buses for maximum performance.

These 64 Kbytes SRAM can also be retained in Standby mode.

The SRAM2 can be write-protected with 1 Kbyte granularity.

• 384 Kbytes mapped at address 0x2004 0000 - (SRAM3).

The memory can be accessed in read/write at CPU clock speed with 0 wait states.

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Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

3.6 Multi-AHB matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, DMA2D,

SDMMC1, LCD-TFT and GFXMMU) and the slaves (Flash memory, RAM, FMC, OctoSPI,

AHB and APB peripherals). It also ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.

Figure 2. Multi-AHB bus matrix

Cortex

-M4 with FPU

DMA1 DMA2 DMA2D LCD-TFT SDMMC1 GFXMMU

BusMatrix-S

ICode

DCode

FLASH

2 MB

SRAM1

SRAM2

SRAM3

GFXMMU

AHB1 peripherals

AHB2 peripherals

FSMC

OCTOSPI1

OCTOSPI2

MSv38490V1

3.7 Firewall

These devices embed a firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas.

Each illegal access generates a reset which kills immediately the detected intrusion.

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The main features of the firewall are the following:

• Three segments can be protected and defined thanks to the firewall registers:

– Code segment (located in Flash or SRAM1 if defined as executable protected area)

– Non-volatile data segment (located in Flash)

– Volatile data segment (located in SRAM1)

• The start address and the length of each segment are configurable:

– Code segment: up to 2048 Kbytes with granularity of 256 bytes

– Non-volatile data segment: up to 2048 Kbytes with granularity of 256 bytes

– Volatile data segment: up to 192 Kbytes of SRAM1 with a granularity of 64 bytes

• Specific mechanism implemented to open the firewall to get access to the protected areas (call gate entry sequence)

• Volatile data segment can be shared or not with the non-protected code

• Volatile data segment can be executed or not depending on the firewall configuration

The Flash readout protection must be set to level 2 in order to reach the expected level of protection.

At startup, a BOOT0 pin and an nBOOT1 option bit are used to select one of three boot options:

• Boot from user Flash

• Boot from system memory

• Boot from embedded SRAM

The BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the value of a user option bit to free the GPIO pad if needed.

A Flash empty-check mechanism is implemented to force the boot from system Flash if the first Flash memory location is not programmed and if the boot selection is configured to boot from main Flash.

The boot loader is located in the system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI, CAN or USB OTG FS in device mode through the DFU (device firmware upgrade).

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator with polynomial value and size.

Among other applications, the CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify the Flash memory integrity.

The CRC calculation unit helps to compute a signature of the software during runtime, which can be ulteriorly compared with a reference signature generated at link-time and which can be stored at a given memory location.

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Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

3.10.1 Power supply schemes

The STM32L4x devices require a 1.71 V to 3.6 V V

DD operating voltage supply. Several independent supplies can be provided for specific peripherals:

• V

= 1.71 V to 3.6 V

DD is the external power supply for the I/Os, the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through the VDD pins.

•

DDA

= 1.62 V (ADCs/COMPs) / 1.8 V (DACs/OPAMPs) to 2.4 V (VREFBUF) to 3.6 V

DDA is the external analog power supply for A/D converters, D/A converters, voltage reference buffer, operational amplifiers and comparators. The V

DDA voltage level is independent from the V

DD voltage and should preferably be connected to V

when these peripherals are not used.

• VDDUSB = 3.0 V to 3.6 V

VDDUSB is the external independent power supply for USB transceivers. The

VDDUSB voltage level is independent from the VDD voltage and should preferably be connected to VDD when the USB is not used.

• VDDIO2 = 1.08 V to 3.6 V

• VDDIO2 is the external power supply for 14 I/Os (port G[15:2]). The VDDIO2 voltage level is independent from the VDD voltage and should preferably be connected to VDD when PG[15:2] are not used.

• VDDDSI is an independent DSI power supply dedicated for is used to supply the DSI regulator and MIPI D-PHY. This supply must be connected to the global VDD.

• VCAPDSI pin is the output of DSI regulator (1.2 V) which must be connected externally to VDD12DSI.

• VDD12DSI pin is used to supply the MIPI D-PHY, and to supply clock and data lanes pins. An external capacitor of 2.2 uF must be connected on the VDD12DSI pin.

• V

BAT

= 1.55 V to 3.6 V

BAT

is the power supply for RTC, external clock 32 kHz oscillator and backup registers

(through power switch) when V

DD is not present.

• V REF, V REF+

REF+

is the input reference voltage for ADCs and DACs. It is also the output of the internal voltage reference buffer when enabled.

When V

DDA

< 2 V V

REF+

must be equal to V

DDA

When V

DDA

≥ 2 V V

REF+

must be between 2 V and V

DDA

REF+

can be grounded when ADC and DAC are not active.

The internal voltage reference buffer supports two output voltages, which are configured with VRS bit in the VREFBUF_CSR register:

– V

REF+

around 2.048 V. This requires V

DDA

equal to or higher than 2.4 V.

– V

REF+

around 2.5 V. This requires V

DDA

equal to or higher than 2.8 V.

VREF- and VREF+ pins are not available on all packages. When not available, they are bonded to VSSA and VDDA, respectively.

When the VREF+ is double-bonded with VDDA in a package, the internal voltage reference buffer is not available and must be kept disable (refer to datasheet for

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REF-

must always be equal to V

SSA

An embedded linear voltage-regulator is used to supply the internal digital power V

CORE

CORE is supplied by V

CORE

and V

. is the power supply for digital peripherals, SRAM1, SRAM2 and SRAM3. The Flash

Figure 3. STM32L4S5xx and STM32L4S7xx power supply overview

DDA

SSA

DDA

domain

3 x A/D converters

2 x comparators

2 x D/A converters

2 x operational amplifiers

Voltage reference buffer

DDUSB

DDIO2

USB transceivers

DDIO2

domain

DDIO2

I/O ring

PG[15:2]

domain

DDIO1

I/O ring

Reset block

Temp. sensor

3 x PLL, HSI, MSI

Standby circuitry

(Wakeup logic,

IWDG)

Voltage regulator

CORE

domain

Core

SRAM1

SRAM2

SRAM3

Digital peripherals

BAT

Low voltage detector

Flash memory

Backup domain

LSE crystal 32 K osc

BKP registers

RCC BDCR register

RTC

MSv38489V1

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Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Figure 4. STM32L4S9xx power supply overview

DDA

SSA

DDA

domain

3 x A/D converters

2 x comparators

2 x D/A converters

2 x operational amplifiers

Voltage reference buffer

DDUSB

DDIO2

DDDSI

CAPDSI

DD12DSI

USB transceivers

DDIO2

domain

DDIO2

I/O ring

PG[15:2]

DSI voltage regulator

DSI PHY

domain

DDIO1

I/O ring

Reset block

Temp. sensor

3 x PLL, HSI, MSI

Standby circuitry

(Wakeup logic,

IWDG)

Voltage regulator

CORE

domain

Core

SRAM1

SRAM2

SRAM3

Digital peripherals

Low voltage detector

Flash memory

BAT

Backup domain

LSE crystal 32 K osc

BKP registers

RCC BDCR register

RTC

MSv38488V1

During power-up and power-down phases, the following power sequence requirements must be respected:

• When V

DD is below 1 V, other power supplies (V

DDA

, V remain below VDD +300 mV.

DDIO2

, V

DDUSB and V

LCD

) must

• When V

is above 1 V, all power supplies are independent.

• During the power-down phase, V

can temporarily become lower than other supplies only if the energy provided to the MCU remains below 1 mJ; this allows external decoupling capacitors to be discharged with different time constants during the powerdown transient phase.

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Figure 5. Power-up/down sequence

3.6

DDX

(1)

BOR0

Functional overview

0.3

Power-on Operating mode Power-down time

Invalid supply area V

DDX

< V

+ 300 mV V

DDX

independent from V

MSv47490V1

1. V

DDX

refers to any power supply among V

DDA

, V

DDIO2

, V

DDUSB

and V

LCD.

3.10.2 Power supply supervisor

The STM32L4S5xx, STM32L4S7xx and STM32L4S9xx devices have an integrated ultralow-power Brownout reset (BOR) active in all modes (except for Shutdown mode). The BOR ensures proper operation of the devices after power-on and during power-down. The devices remain in reset mode when the monitored supply voltage V

DD threshold, without the need for an external reset circuit.

is below a specified

The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected through option bytes.The devices feature an embedded programmable voltage detector

(PVD) that monitors the V

power supply and compares it to the VPVD threshold.

An interrupt can be generated when V

drops below the VPVD threshold and/or when V

DD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

In addition, the devices embed a peripheral voltage monitor which compares the independent supply voltages V

DDA

, V

DDUSB

, V

DDIO2

with a fixed threshold in order to ensure that the peripheral is in its functional supply range.

Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR).

• The MR is used in the Run and Sleep modes and in the Stop 0 mode.

• The LPR is used in Low-power run, Low-power sleep, Stop 1 and Stop 2 modes. It is also used to supply the 64 Kbytes SRAM2 in standby with RAM2 retention.

• Both regulators are in power-down while they are in standby and Shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption.

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Functional overview

Note:

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

The ultra-low-power STM32L4Sxxx devices support dynamic voltage scaling to optimize its power consumption in Run mode. The voltage from the main regulator that supplies the logic (VCORE) can be adjusted according to the system’s maximum operating frequency.

The main regulator operates in the following ranges:

• Range 1 boost mode with the CPU running at up to 120 MHz.

• Range 1 normal mode with the CPU running at up to 80 MHz.

• Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also limited to 26 MHz.

The VCORE can be supplied by the low-power regulator, the main regulator being switched off. The system is then in Low-power run mode.

• Low-power run mode with the CPU running at up to 2 MHz. Peripherals with independent clock can be clocked by the HSI16.

The USB and DSIHOST can only be used when the main regulator is in range1 boost mode.

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Mode

Run

LPRun

Sleep

LPSleep

The ultra-low-power STM32L4Sxxx devices support seven low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wake-up sources.

Table 4

shows the related STM32L4Sxxx modes overview.

Regulator

(1)

Range 1

Range2

LPR

Range 1

Range 2

LPR

CPU

Yes

Table 4. STM32L4S5xx modes overview

Flash SRAM Clocks DMA & Peripherals

(2)

(3)

(4)

Any

Any except

PLL

Any

All

All except

OTG_FS, RNG, LCD-TFT

All except

OTG_FS, RNG, LCD-TFT

All

All except

OTG_FS, RNG, LCD-TFT

Any except PLL

All except OTG_FS, RNG, LCD-TFT

Wakeup source

N/A

Any interrupt or event

Stop 0

Range 1

Range 2

No Off ON

LSE

LSI

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1,2)

DACx (x=1,2)

OPAMPx (x=1,2)

USARTx (x=1...5) (5)

LPUART1

(5)

I2Cx (x=1...4)

(6)

LPTIMx (x=1,2)

***

All other peripherals are frozen

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

USARTx (x=1...5)

LPUART1

LPTIMx (x=1,2)

OTG_FS

(7)

Mode

Stop 1

Stop 2

Standby

Shutdown

Regulator

(1)

LPR

OFF

CPU

Powered

Off

Powered

Off

Table 4. STM32L4S5xx modes overview (continued)

Flash SRAM Clocks DMA & Peripherals

(2)

Off

SRAM2 ON

Powered

Off

Powered

Off

LSE

LSI

LSE

LSI

LSE

LSI

LSE

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1,2)

DACx (x=1,2)

OPAMPx (x=1,2)

USARTx (x=1...5)

I2Cx (x=1...4)

LPTIMx (x=1,2)

***

All other peripherals are frozen

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

LPTIM1

***

All other peripherals are frozen

BOR, RTC, IWDG

***

All other peripherals are powered off

***

I/O configuration can be floating, pullup or pull-down

RTC

***

All other peripherals are powered off

***

I/O configuration can be floating, pullup or pull-down

(9)

Wakeup source

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

USARTx (x=1...5)

LPUART1

LPTIMx (x=1,2)

OTG_FS

(7)

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

I2C3

LPUART1

(5)

LPTIM1

Reset pin

5 I/Os (WKUPx)

(8)

BOR, RTC, IWDG

Reset pin

5 I/Os (WKUPx)

(8)

RTC

1. LPR means Main regulator is OFF and Low-power regulator is ON.

2. All peripherals can be active or clock gated to save power consumption.

3. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.

4. The SRAM1, SRAM2 and SRAM3 clocks can be gated on or off independently.

5. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

6. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

7. OTG_FS wakeup by resume from suspend and attach detection protocol event.

8. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.

9. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

By default, the microcontroller is in Run mode after a system or a power reset. It is up to the user to select one of the low-power modes described below:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Low-power run mode

This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16.

• Low-power sleep mode

This mode is entered from the Low-power run mode. Only the CPU clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the Lowpower run mode.

• Stop 0, Stop 1 and Stop 2 modes

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI

RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with wake-up capability can enable the HSI16 RC during Stop mode to detect their wake-up condition.

Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode, most of the VCORE domain is put in a lower leakage mode.

Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator remains ON, allowing a very fast wakeup time but with much higher consumption.

The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI up to 48 MHz or HSI16, depending on software configuration.

• Standby mode

The Standby mode is used to achieve the lowest power consumption with BOR. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.

The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

The Brownout reset (BOR) always remains active in Standby mode.

The state of each I/O during Standby mode can be selected by software: I/O with internal pull-up, internal pull-down or floating.

After entering Standby mode, SRAM1, SRAM3 and register contents are lost except for registers in the Backup domain and Standby circuitry. Optionally, SRAM2 can be

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The device exits Standby mode when an external reset (NRST pin), an IWDG reset,

WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).

The system clock after wakeup is MSI up to 8 MHz.

• Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the

HSI16, the MSI, the LSI and the HSE oscillators are also switched off.

The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported.

SRAM1, SRAM2, SRAM3 and register contents are lost except for registers in the

Backup domain.

The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper).

The system clock after wakeup is MSI at 4 MHz.

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Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Table 5. Functionalities depending on the working mode (1)

Stop 0/1 Stop 2 Standby Shutdown

Peripheral Run Sleep

Lowpower run

Lowpower sleep -

VBAT

CPU

Flash memory

(2 Mbytes)

SRAM1

(192 Kbytes)

SRAM2 (64 Kbytes)

SRAM3

(384 Kbytes)

FSMC

OctoSPIs

Backup Registers

Brownout reset

(BOR)

Programmable

Voltage Detector

(PVD)

Peripheral Voltage

Monitor (PVMx; x=1,2,3,4)

DMA

DMA2D

High speed internal

(HSI16)

Oscillator HSI48

High speed external

(HSE)

Low speed internal

(LSI)

Low speed external

(LSE)

Multi speed internal

(MSI)

Clock security system (CSS)

(2)

(3)

(4)

O O

(5)

O O O O

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Table 5. Functionalities depending on the working mode (1) (continued)

Stop 0/1 Stop 2 Standby Shutdown

Peripheral Run Sleep

Lowpower run

Lowpower sleep -

VBAT

(8)

Clock security system on LSE

RTC / Auto wakeup

Number of RTC

Tamper pins

Camera interface

LCD-TFT

GFXMMU

DSIHOST

USB OTG FS

USARTx

(x=1,2,3,4,5)

Low-power UART

(LPUART)

I2Cx (x=1,2,4)

I2C3

SPIx (x=1,2,3)

CAN(x=1,2)

SDMMC1

SAIx (x=1,2)

DFSDM1

ADC

DACx (x=1,2)

VREFBUF

OPAMPx (x=1,2)

COMPx (x=1,2)

Temperature sensor

Timers (TIMx)

Low-power timer 1

(LPTIM1)

Low-power timer 2

(LPTIM2)

(8)

3 O

(6)

(7)

O O O O

O O -

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Table 5. Functionalities depending on the working mode (1) (continued)

Stop 0/1 Stop 2 Standby Shutdown

Peripheral Run Sleep

Lowpower run

Lowpower sleep -

VBAT

Independent watchdog (IWDG)

Window watchdog

(WWDG)

SysTick timer

Touch sensing controller (TSC)

Random number generator (RNG)

AES hardware accelerator

HASH hardware accelerator

CRC calculation unit

(8)

GPIOs O O O O O O O O

(9)

5 pins

(10)

(11)

5 pins

(10)

1. Legend: Y = yes (enable). O = optional (disable by default, can be enabled by software). - = not available.

Gray cells highlight the wakeup capability in each mode.

2. The Flash can be configured in power-down mode. By default, it is not in power-down mode.

3. The SRAM clock can be gated on or off. In Stop 2 mode, the content of SRAM3 is preserved or not depending on the

RRSTP bit in PWR_CR1 register.

4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.

5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore.

6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

8. Voltage scaling range 1 only.

9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.

10. The I/Os with wakeup from standby/shutdown capability are: PA0, PC13, PE6, PA2, PC5.

11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

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In order to improve the consumption under reset, the I/Os state under and after reset is

“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is deactivated when the reset source is internal.

Note:

The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from V

when there is no external battery and when an external supercapacitor is present. The VBAT pin supplies the RTC with LSE and the backup registers. Three anti-tamper detection pins are available in VBAT mode.

The VBAT operation is automatically activated when V

is not present. An internal VBAT battery charging circuit is embedded and can be activated when V

is present.

When the microcontroller is supplied from VBAT, neither external interrupts nor RTC alarm/events exit the microcontroller from the VBAT operation.

Several peripherals have direct connections between them, which allow autonomous communication between them and support the saving of CPU resources (thus power supply consumption). In addition, these hardware connections allow fast and predictable latency.

Depending on the peripherals, these interconnections can operate in Run, Sleep, Lowpower run and Sleep, Stop 0, Stop 1 and Stop 2 modes. See

Table 6

for more details.

Table 6. STM32L4S5xx, STM32L4S7xx and STM32L4S9xx peripherals interconnect matrix

Interconnect source

Interconnect destination

Interconnect action

TIMx

COMPx

ADCx

TIMx

ADC

DACx

DFSDM1

DMA

COMPx

TIM1, 8

TIM2, 3

LPTIMERx

TIM1, 8

Timers synchronization or chaining

Conversion triggers

Memory to memory transfer trigger

Comparator output blanking

Timer input channel, trigger, break from analog signals comparison

Low-power timer triggered by analog signals comparison

Timer triggered by analog watchdog

Y Y Y Y -

Y Y Y Y Y

(1)

Y Y Y Y -

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Table 6. STM32L4S5xx, STM32L4S7xx and STM32L4S9xx peripherals interconnect matrix (continued)

Interconnect source

Interconnect destination

Interconnect action

RTC

TIM16

LPTIMERx

All clocks sources (internal and external)

TIM2

TIM15, 16, 17

USB

CSS

CPU (hard fault)

RAM (parity error)

Flash memory (ECC error)

COMPx

PVD

DFSDM1 (analog watchdog, short circuit detection)

TIM2

TIM1,8

TIM15,16,17

TIMx

LPTIMERx

GPIO

ADC

DACx

DFSDM1

1. LPTIM1 only.

Timer input channel from RTC events

Low-power timer triggered by RTC alarms or tampers

Y Y Y Y -

Y Y Y Y Y

Clock source used as input channel for

RC measurement and trimming

Timer triggered by USB SOF

Timer break

External trigger

Conversion external trigger

The clock controller (see Figure 6

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3.12 Clocks and startup

) distributes the clocks coming from the different oscillators to the core and to the peripherals. It also manages the clock gating for low-power modes and ensures the clock robustness. It features:

• Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.

• Safe clock switching: clock sources can be changed safely on the fly in Run mode through a configuration register.

• Clock management: to reduce the power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

• System clock source: four different clock sources can be used to drive the master clock SYSCLK:

– 4 to 48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply a PLL. The HSE can also be configured in bypass mode for an external clock.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can supply a PLL

– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate

12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be automatically trimmed by hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the

USB device, saving the need of an external high-speed crystal (HSE). The MSI can supply a PLL.

– System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency at 120 MHz.

• RC48 with clock recovery system (HSI48): internal 48 MHz clock source (HSI48)can be used to drive the USB, the SDMMC or the RNG peripherals. This clock can be output on the MCO.

• Auxiliary clock source: two ultra-low-power clock sources that can be used to drive the real-time clock:

– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for an external clock.

– 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

The LSI clock accuracy is ±5% accuracy.

• Peripheral clock sources: several peripherals (USB, SDMMC, RNG, SAI, USARTs,

I2Cs, LPTimers, ADC) have their own independent clock whatever the system clock.

Three PLLs, each having three independent outputs allowing the highest flexibility, can generate independent clocks for the ADC, the USB/SDMMC/RNG, the two SAIs, LCD-

TFT and DSI-HOST. When using DSI-HOST peripheral, the high-speed external crystal

(HSE) must be available.

• Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

• Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI16 and a software

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• Clock-out capability:

– MCO (microcontroller clock output): it outputs one of the internal clocks for external use by the application

– LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes

(except VBAT).

Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 120 MHz.

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Figure 6. Clock tree to IWDG

LSI RC 32 kHz

LSCO

OSC32_OUT

OSC32_IN

MCO

OSC_OUT

OSC_IN

PLL

PLLSAI1

LSE OSC

32.768 kHz

/ 1→16

HSE OSC

4-48 MHz

Clock detector

100 kHz – 48 MHz

/ R

RC 48 MHz

/ P

/ Q

/ R

/ P

/ Q

HSI RC

16 MHz

MSI RC

PLLSAI3CLK

/ M

PLL48M1CLK

PLLCLK

PLLSAI1CLK

PLL48M2CLK

/ M

PLLADC1CLK

LSE

LSI

MSI

HSI16

HSE

SYSCLK

PLLCLK

HSI48

HSI16

HSE DSI

PLL

PLLSAI2

/ P

/ Q

/ R

DSI - PHY

PLLSAI2CLK

/ M

PLLDSICLK

PLLLCDCLK HSI16

≤ 20 MHz

≤ 62.5 MHz

< 62.5 MHz to RTC

/32

HSE

MSI

HSI16

MSI

HSI16

HSE

Clock source control

SYSCLK

MSI to PWR

AHB PRESC

/ 1,2,..512

HCLK

/ 8 to AHB bus, core, memory and DMA

FCLK Cortex free running clock to Cortex system timer

APB1 PRESC

/ 1,2,4,8,16

PCLK1 to APB1 peripherals x1 or x2 to TIMx x=2..7

LSE

HSI16

SYSCLK to USARTx

X=2..5

to LPUART1

HSI16

SYSCLK

LSI

LSE

HSI16 to I2Cx x=1,2,3,4 to LPTIMx x=1,2

APB2 PRESC

/ 1,2,4,8,16

OCTOSPI clock

CRS clock

PCLK2 to APB2 peripherals x1 or x2 to TIMx x=1,8,15,16,17

LSE

HSI16

SYSCLK to

USART1

MSI

SYSCLK

MSI

HSI16

SDMMC clock

48 MHz clock to USB, RNG to ADC

DSIHOST byte lane clock

DSIHOST rxclkesc clock

DFSDM audio clock to SAI1

PLLSAI2DIVR

SAI1_EXTCLK

SAI2_EXTCLK

LTDC clock to SAI2

MSv38434V7

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Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

3.14 Direct memory access controller (DMA)

The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features

implementation.

Direct memory access (DMA) is used in order to provide a high-speed data transfer between peripherals and memory as well as from memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps the CPU resources free for other operations.

The two DMA controllers have 14 channels in total, each one dedicated to manage memory access requests from one or more peripherals. Each controller has an arbiter for handling the priority between DMA requests.

The DMA supports:

• 14 independently configurable channels (requests)

– Each channel is connected to a dedicated hardware DMA request, a software trigger is also supported on each channel. This configuration is done by software.

• Priorities between requests from channels of one DMA are both software programmable (4 levels: very high, high, medium, low) or hardware programmable in case of equality (request 1 has priority over request 2, etc.)

• Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size

• Support for circular buffer management

• 3 event flags (DMA half transfer, DMA transfer complete and DMA transfer error) logically ORed together in a single interrupt request for each channel

• Memory-to-memory transfer

• Peripheral-to-memory, memory-to-peripheral, and peripheral-to-peripheral transfers

• Access to Flash, SRAM, APB and AHB peripherals as source and destination

• Programmable number of data to be transferred: up to 65536

Table 7. DMA implementation

DMA features DMA1

Number of regular channels 7

DMA2

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3.15 DMA request router (DMAMux)

When a peripheral indicates a request for DMA transfer by setting its DMA request line, the

DMA request is pending until it is served and the corresponding DMA request line is reset.

The DMA request router allows to route the DMA control lines between the peripherals and the DMA controllers of the product.

An embedded multi-channel DMA request generator can be considered as one of such peripherals. The routing function is ensured by a multi-channel DMA request line multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or synchronously with events on synchronization inputs.

For simplicity, the functional description is limited to DMA request lines. The other DMA control lines are not shown in figures or described in the text. The DMA request generator produces DMA requests following events on DMA request trigger inputs.

Chrom-ART Accelerator (DMA2D) is a graphic accelerator that offers an advanced bit blitting, row data copy and pixel format conversion. It supports the following functions:

• Rectangle filling with a fixed color

• Rectangle copy

• Rectangle copy with pixel format conversion

• Rectangle composition with blending and pixel format conversion.

Various image format coding are supported, from indirect 4 bpp color mode up to 32 bpp direct color. It embeds a dedicated memory to store color lookup tables.

An interrupt can be generated when an operation is complete or at a programmed watermark.

All the operations are fully automatized and are running independently from the CPU or the

DMAs.

The Chrom-GRC (GFXMMU) is a graphical oriented memory management unit aimed to:

• Optimize memory usage according to the display shape

• Manage packing/unpacking for 24 bpp frame buffers

The Chrom-GRC features:

• Fully programmable display shape to physically store only the visible pixel

• Up to four virtual buffers

• Each virtual buffer have 4096 bytes per line and 1024 lines

• Each virtual buffer can be physically mapped to any system memory

• 24 bpp packing unit to store unpacked 24bpp data in a packed 24 bpp

• Packing/un-packing management per buffer

• Interrupt in case of buffer overflow (1 per buffer)

• Interrupt in case of memory transfer error

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3.18.1 Nested vectored interrupt controller (NVIC)

The STM32L4S5xx, STM32L4S7xx and STM32L4S9xxdevices embed a nested vectored interrupt controller which is able to manage 16 priority levels, and to handle up to 95 maskable interrupt channels plus the 16 interrupt lines of the Cortex

-M4.

The NVIC benefits are the following:

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

3.18.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 36 edge detector lines used to generate interrupt/event requests and to wake-up the system from the Stop mode. Each external line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently.

A pending register maintains the status of the interrupt requests. The internal lines are connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 114 GPIOs can be connected to the 16 external interrupt lines.

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3.19 Analog-to-digital converter (ADC)

The device embeds a successive approximation analog-to-digital converters with the following features:

• 12-bit native resolution, with built-in calibration

• 5.33 Msps maximum conversion rate with full resolution

– Down to 18.75 ns sampling time

– Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution)

• Up to 16 external channels

• 5 internal channels: internal reference voltage, temperature sensor, VBAT/3, DAC1 and

DAC2 outputs

• One external reference pin is available on some package, allowing the input voltage range to be independent from the power supply

• Single-ended and differential mode inputs

• Low-power design

– Capable of low-current operation at low conversion rate (consumption decreases linearly with speed)

– Dual clock domain architecture: ADC speed independent from CPU frequency

• Highly versatile digital interface

– Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions

– Each ADC support multiple trigger inputs for synchronization with on-chip timers and external signals

– Results stored into a data register or in RAM with DMA controller support

– Data pre-processing: left/right alignment and per channel offset compensation

– Built-in oversampling unit for enhanced SNR

– Channel-wise programmable sampling time

– Analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers

– Hardware assistant to prepare the context of the injected channels to allow fast context switching

The temperature sensor (TS) generates a voltage V

that varies linearly with temperature.

The temperature sensor is internally connected to the ADC1_IN17 input channels which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

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Table 8. Temperature sensor calibration values

Calibration value name Description Memory address

TS_CAL1

TS_CAL2

TS ADC raw data acquired at a temperature of 30 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

TS ADC raw data acquired at a temperature of 130 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

0x1FFF 75A8 - 0x1FFF 75A9

0x1FFF 75CA - 0x1FFF 75CB

3.19.2 Internal voltage reference (V

REFINT

)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and the comparators. The VREFINT is internally connected to the ADC1_IN0 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

Table 9. Internal voltage reference calibration values

Calibration value name Description Memory address

VREFINT

Raw data acquired at a temperature of 30 °C (± 5 °C),

DDA

= V

REF+

= 3.0 V (± 10 mV)

0x1FFF 75AA - 0x1FFF 75AB

3.19.3 V

BAT

battery voltage monitoring

This embedded hardware enables the application to measure the V

BAT the internal ADC channel ADC1_IN18. As the V

BAT

battery voltage using

voltage may be higher than the VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 3. As a consequence, the converted digital value is one third of the V

BAT

voltage.

3.20 Digital to analog converter (DAC)

Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.

This digital interface supports the following features:

• Up to two DAC output channels

• 8-bit or 12-bit output mode

• Buffer offset calibration (factory and user trimming)

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

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• Dual DAC channel independent or simultaneous conversions

• DMA capability for each channel

• External triggers for conversion

• Sample and hold low-power mode, with internal or external capacitor

The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.

The STM32L4Sxxx devices embed a voltage reference buffer which can be used as voltage reference for ADC, DACs and also as voltage reference for external components through the VREF+ pin.

The internal voltage reference buffer supports two voltages:

• 2.048 V

• 2.5 V

An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off.

The VREF+ pin is double-bonded with VDDA on some packages. In these packages the internal voltage reference buffer is not available.

Figure 7. Voltage reference buffer

VREFBUF

Bandgap +

DDA

DAC, ADC

VREF+

Low frequency cut-off capacitor

100 nF

MSv40197V1

The STM32L4Sxxx devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity.

The reference voltage can be one of the following:

• External I/O

• DAC output channels

• Internal reference voltage or submultiple (1/4, 1/2, 3/4).

All comparators can wake up from Stop mode, generate interrupts and breaks for the timers and can also be combined into a window comparator.

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The STM32L4Sxxx devices embed two operational amplifiers with external or internal follower routing and PGA capability.

The operational amplifier features:

• Low input bias current

• Low offset voltage

• Low-power mode

• Rail-to-rail input

3.24 Touch sensing controller (TSC)

Note:

The touch sensing controller provides a simple solution to add capacitive sensing functionality to any application. A capacitive sensing technology is able to detect finger presence near an electrode that is protected from direct touch by a dielectric (glass, plastic or other). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle.

The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application.

The main features of the touch sensing controller are the following:

• Proven and robust surface charge transfer acquisition principle

• Supports up to 24 capacitive sensing channels

• Up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time

• Spread spectrum feature to improve system robustness in noisy environments

• Full hardware management of the charge transfer acquisition sequence

• Programmable charge transfer frequency

• Programmable sampling capacitor I/O pin

• Programmable channel I/O pin

• Programmable max count value to avoid long acquisition when a channel is faulty

• Dedicated end of acquisition and max count error flags with interrupt capability

• One sampling capacitor for up to 3 capacitive sensing channels to reduce the system components

• Compatible with proximity, touchkey, linear and rotary touch sensor implementation

• Designed to operate with STMTouch touch sensing firmware library

The number of capacitive sensing channels is dependent on the size of the packages and subject to I/O availability.

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The LCD-TFT display controller provides a 24-bit parallel digital RGB (red, green, blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels with the following features:

• Two displays layers with dedicated FIFO (64 x 32-bit)

• Color look-up table (CLUT) up to 256 colors (256 x 24-bit) per layer

• Up to 8 input color formats selectable per layer

• Flexible blending between two layers using alpha value (per pixel or constant)

• Flexible programmable parameters for each layer

• Color keying (transparency color)

• Up to four programmable interrupt events

The DSI Host is a dedicated IP that interfaces with the MIPI

DSI compliant displays. It includes a dedicated video interface internally connected to the LTDC and a generic APB interface that can be used to transmit information to the display.

The interfaces are as follows:

• LTDC interface:

– Used to transmit information in Video Mode, in which the transfers from the host processor to the peripheral take the form of a real-time pixel stream (DPI)

– Used to transmit information in full bandwidth in the Adapted Command Mode

(DBI) through a custom mode

• APB slave interface:

– Allows the transmission of generic information in Command mode, and follows a proprietary register interface

– Can operate concurrently with either LTDC interface in either Video Mode or

Adapted Command Mode

• Video mode pattern generator:

– Allows the transmission of horizontal/vertical color bar and D-PHY BER testing pattern without any kind of stimuli

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The DSI Host main features are:

• Compliant with MIPI

Alliance standards

• Interface with MIPI ® D-PHY

• Supports all commands defined in the MIPI

Alliance specification for DCS:

– Transmission of all Command mode packets through the APB interface

– Transmission of commands in low-power and high-speed during Video Mode

• Supports up to two D-PHY data lanes

• Bidirectional communication and escape mode support through data lane 0

• Supports non-continuous clock in D-PHY clock lane for additional power saving

• Supports Ultra Low-Power mode with PLL disabled

• ECC and Checksum capabilities

• Support for end of transmission packet (EoTp)

• Fault recovery schemes

• Configurable selection of system interfaces:

– AMBA APB for control and optional support for generic and DCS commands

– Video Mode interface through LTDC

– Adapted command mode interface through LTDC

• Independently programmable virtual channel ID in

– Video mode

– Adapted command mode

– APB Slave

Video Mode interfaces features:

• LTDC interface color coding mappings into 24-bit interface:

– 16-bit RGB, configurations 1, 2 and 3

– 18-bit RGB, configurations 1 and 2

– 24-bit RGB

• Programmable polarity of all LTDC interface signals

• Maximum resolution is limited by available DSI physical link bandwidth:

– Number of lanes: 2

– Maximum speed per lane: 500 Mbps

Adapted interface features:

• Support for sending large amounts of data through the memory_write_start (WMS) and memory_write_continue (WMC) DCS commands

• LTDC interface color coding mappings into 24-bit interface:

– 16-bit RGB, configurations 1, 2 and 3

– 18-bit RGB, configurations 1 and 2

– 24-bit RGB

Video mode pattern generator:

• Vertical and horizontal color bar generation without LTDC stimuli

• BER pattern without LTDC stimuli

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3.27 Digital filter for sigma-delta modulators (DFSDM)

The STM32L4Sxxx devices embed one DFSDM with four digital filters modules and eight external input serial channels (transceivers) or alternately eight internal parallel inputs support.

The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to the microcontroller and then to perform digital filtering of the received data streams (which represent analog value on Σ∆ modulators inputs).

The DFSDM can also interface the PDM (pulse density modulation) microphones and perform PDM to PCM conversion and filtering in hardware. The DFSDM features optional parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into

DFSDM).

The DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators) and the DFSDM digital filter modules perform digital processing according to the user’s selected filter parameters with up to 24-bit final ADC resolution.

The DFSDM peripheral supports:

• 8 multiplexed input digital serial channels:

– Configurable SPI interface to connect various SD modulator(s)

– Configurable Manchester coded 1 wire interface support

– PDM (pulse density modulation) microphone input support

– Maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)

– Clock output for SD modulator(s): 0..20 MHz

• Alternative inputs from 8 internal digital parallel channels (up to 16-bit input resolution):

– Internal sources: device memory data streams (DMA)

• 4 digital filter modules with adjustable digital signal processing:

– Sinc x

filter: filter order/type (1..5), oversampling ratio (up to 1..1024)

– Integrator: oversampling ratio (1..256)

• Up to 24-bit output data resolution, signed output data format

• Automatic data offset correction (offset stored in register by user)

• Continuous or single conversion

• Start-of-conversion triggered by:

– Software trigger

– Internal timers

– External events

– Start-of-conversion synchronously with first digital filter module (DFSDM0)

• Analog watchdog feature:

– Low value and high-value data threshold registers

– Dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)

– Input from final output data or from selected input digital serial channels

– Continuous monitoring independently from standard conversion

• Short circuit detector to detect saturated analog input values (bottom and top range):

– Up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream

– Monitoring continuously each input serial channel

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• Break signal generation on analog watchdog event or on short circuit detector event

• Extremes detector:

– Storage of minimum and maximum values of final conversion data

– Refreshed by software

• DMA capability to read the final conversion data

• Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence

• “Regular” or “injected” conversions:

– “Regular” conversions can be requested at any time or even in continuous mode without having any impact on the timing of “injected” conversions

– “Injected” conversions for precise timing and with high conversion priority

3.28 Random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit.

The STM32L4Sxxx devices embed a camera interface that can connect with any camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface in order to receive video data.

The camera interface can sustain a data transfer rate up to 54 Mbytes/s at 54 MHz. It features:

• Programmable polarity for the input pixel clock and synchronization signals

• Parallel data communication of 8-, 10-, 12- or 14-bit

• Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG)

• Supports continuous mode or snapshot (a single frame) mode

• Capability to automatically crop the image.

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3.30 Advanced encryption standard hardware accelerator (AES)

The STM32L4Sxxx devices embed an AES hardware accelerator that can be used both to encipher and to decipher data using an AES algorithm.

The AES peripheral supports:

• Encryption/decryption using AES Rijndael block cipher algorithm

• NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm

• 128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x

32-bit registers)

• Electronic codebook (ECB), cipher block chaining (CBC), Counter mode (CTR), Galois

Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher

Message Authentication Code mode (CMAC) supported

• Key scheduler

• Key derivation for decryption

• 128-bit data block processing

• 128-bit, 256-bit key length

• 1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer

• Register access supporting 32-bit data width only

• One 128-bit Register for the initialization vector when AES is configured in CBC mode or for the 32-bit counter initialization when CTR mode is selected, GCM mode or

CMAC mode

• Automatic data flow control with support of direct memory access (DMA) using 2 channels, one for incoming data, and one for outcoming data

• Suspend a message if another message with a higher priority needs to be processed.

The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-

1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and the

HMAC (keyed-hash message authentication code) algorithm suitable for a variety of applications.

It computes a message digest (160 bits for the SHA-1 algorithm, 256 bits for the SHA-256 algorithm and 224 bits for the SHA-224 algorithm,128 bits for the MD5 algorithm) for messages of up to (264 - 1) bits, while the HMAC algorithms provide a way of authenticating messages by means of hash functions. The HMAC algorithms consist in calling the SHA-1,

SHA-224, SHA-256 or MD5 hash function twice.

3.32 Timers and watchdogs

The STM32L4Sxxx devices include two advanced control timers, up to nine generalpurpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer.

The

Table 10 below compares the features of the advanced control, general-purpose and

basic timers.

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Timer type

Advanced control

Generalpurpose

Basic

Timer

TIM1, TIM8

TIM2, TIM5

TIM3, TIM4

TIM15

TIM16, TIM17

TIM6, TIM7

Table 10. Timer feature comparison

Counter resolution

Counter type

Prescaler factor

DMA request generation

16-bit

32-bit

16-bit

Up, down,

Up/down

Up, down,

Up/down

Up, down,

Up/down

Any integer between 1 and 65536

Yes

Capture/ compare channels

Complementary outputs

The advanced-control timers can each be seen as a three-phase PWM multiplexed on six channels. They have complementary PWM outputs with programmable inserted deadtimes. They can also be seen as complete general-purpose timers.

The four independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge or center-aligned modes) with full modulation capability (0-

100%)

• One-pulse mode output

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled in order to turn off any power switches driven by these outputs.

Many features are shared with the general-purpose TIMx timers (described in

Section 3.32.2

) using the same architecture, so the advanced-control timers can work

together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

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timers

TIM17)

There are up to seven synchronizable general-purpose timers embedded in the

STM32L4Sxxx devices (see

Table 10 for differences).

Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base.

• TIM2, TIM3, TIM4 and TIM5

They are full-featured general-purpose timers:

– TIM2 and TIM5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler

– TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler.

These timers feature four independent channels for input capture/output compare,

PWM or one-pulse mode output. They can work together, or with the other generalpurpose timers via the Timer Link feature for synchronization or event chaining.

The counters can be frozen in debug mode.

All have independent DMA request generation and support quadrature encoders.

• TIM15, 16 and 17

They are general-purpose timers with mid-range features:

They have 16-bit auto-reload upcounters and 16-bit prescalers.

– TIM15 has two channels and one complementary channel

– TIM16 and TIM17 have one channel and one complementary channel

All channels can be used for input capture/output compare, PWM or one-pulse mode output.

The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation.

The counters can be frozen in debug mode.

3.32.3 Basic timers (TIM6 and TIM7)

The basic timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit timebases.

The STM32L4Sxxx devices embed two low-power timers. These timers have an independent clock and are running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to wakeup the system from Stop mode.

LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.

LPTIM2 is active in Stop 0 and Stop 1 mode.

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Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

This low-power timer supports the following features:

• 16-bit up counter with 16-bit autoreload register

• 16-bit compare register

• Configurable output: pulse, PWM

• Continuous/ one shot mode

• Selectable software/hardware input trigger

• Selectable clock source

– Internal clock sources: LSE, LSI, HSI16 or APB clock

– External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application).

• Programmable digital glitch filter

• Encoder mode (LPTIM1 only).

The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is clocked from an independent 32 kHz internal RC (LSI) and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

3.32.6 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

• A 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0.

• Programmable clock source

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The RTC is an independent BCD timer/counter. It supports the following features:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format

• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month

• Two programmable alarms

• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock

• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision

• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy

• Three anti-tamper detection pins with programmable filter

• Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to

VBAT mode

• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period

The RTC and the 32 backup registers are supplied through a switch that takes power either from the V

supply when present or from the VBAT pin.

The backup registers are 32-bit registers used to store 128 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from standby or Shutdown mode.

The RTC clock sources can be:

• A 32.768 kHz external crystal (LSE)

• An external resonator or oscillator (LSE)

• The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)

• The high-speed external clock (HSE) divided by 32

The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the

LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes except Shutdown mode.

All RTC events (alarm, wake-up timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes.

The device embeds four I2C. Refer to Table 11: I2C implementation

for the features implementation.

The I

C bus interface handles communications between the microcontroller and the serial

C bus. It controls all I

C bus-specific sequencing, protocol, arbitration and timing.

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Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

The I2C peripheral supports:

• I 2 C-bus specification and user manual rev. 5 compatibility:

– Slave and master modes, multimaster capability

– Standard-mode (Sm), with a bitrate up to 100 kbit/s

– Fast-mode (Fm), with a bitrate up to 400 kbit/s

– Fast-mode plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os

– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

– Programmable setup and hold times

– Optional clock stretching

• System management bus (SMBus) specification rev 2.0 compatibility:

– Hardware PEC (packet error checking) generation and verification with ACK control

– Address resolution protocol (ARP) support

– SMBus alert

• Power system management protocol (PMBus

) specification rev 1.1 compatibility

• Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. Refer to

Figure 6: Clock tree

• Wakeup from Stop mode on address match

• Programmable analog and digital noise filters

• 1-byte buffer with DMA capability

Table 11. I2C implementation

I2C features

(1)

I2C1

Standard-mode (up to 100 kbit/s)

Fast-mode (up to 400 kbit/s)

Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)

Programmable analog and digital noise filters

SMBus/PMBus hardware support

Independent clock

Wakeup from Stop 0, Stop 1 mode on address match

Wakeup from Stop 2 mode on address match

1. X: supported

I2C2

I2C3

I2C4

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(USART)

The STM32L4Sxxx devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4, UART5).

These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN master/slave capability. They provide hardware management of the CTS and RTS signals, and RS485 driver enable. They are able to communicate at speeds of up to

10 Mbit/s.

The USART1, USART2 and USART3 also provide a Smartcard mode (ISO 7816 compliant) and an SPI-like communication capability.

All USART have a clock domain independent from the CPU clock, allowing the USARTx

(x=1,2,3,4,5) to wake up the MCU from Stop mode using baudrates up to 200 Kbaud. The wake up events from Stop mode are programmable and can be:

• Start bit detection

• Any received data frame

• A specific programmed data frame

All USART interfaces can be served by the DMA controller.

Table 12. USART/UART/LPUART features

USART modes/features (1) USART1 USART2 USART3 UART4 UART5 LPUART1

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode

Smartcard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain

Wakeup from Stop 0 / Stop 1 modes

Wakeup from Stop 2 mode

Receiver timeout interrupt

Modbus communication

Auto baud rate detection

Driver enable

LPUART/USART data length

1. X = supported.

X (4 modes)

X X

7, 8 and 9 bits

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Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

(LPUART)

The STM32L4Sxxx devices embed one low-power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports halfduplex single-wire communication and modem operations (CTS/RTS). It allows multiprocessor communication.

The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop mode are programmable and can be:

• Start bit detection

• Any received data frame

• A specific programmed data frame

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates.

The LPUART interface can be served by the DMA controller.

3.37 Serial peripheral interface (SPI)

Three SPI interfaces allow communication up to slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives eight master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and hardware CRC calculation.

All SPI interfaces can be served by the DMA controller.

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The STM32L4Sxxx devices embed two SAI. Refer to Table 13: SAI implementation

for the features implementation. The SAI bus interface handles communications between the microcontroller and the serial audio protocol.

The SAI peripheral supports:

• Two independent audio sub-blocks which can be transmitters or receivers with their respective FIFO.

• 8-word integrated FIFOs for each audio sub-block.

• Synchronous or asynchronous mode between the audio sub-blocks.

• Master or slave configuration independent for both audio sub-blocks.

• Clock generator for each audio block to target independent audio frequency sampling when both audio sub-blocks are configured in master mode.

• Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.

• Peripheral with large configurability and flexibility allowing to target as example the following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF out.

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STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview

• Up to 16 slots available with configurable size and with the possibility to select which ones are active in the audio frame.

• Number of bits by frame may be configurable.

• Frame synchronization active level configurable (offset, bit length, level).

• First active bit position in the slot is configurable.

• LSB first or MSB first for data transfer.

• Mute mode.

• Stereo/Mono audio frame capability.

• Communication clock strobing edge configurable (SCK).

• Error flags with associated interrupts if enabled respectively.

– Overrun and underrun detection.

– Anticipated frame synchronization signal detection in slave mode.

– Late frame synchronization signal detection in slave mode.

– Codec not ready for the AC’97 mode in reception.

• Interruption sources when enabled:

– Errors.

– FIFO requests.

• DMA interface with two dedicated channels to handle access to the dedicated integrated FIFO of each SAI audio sub-block.

Table 13. SAI implementation

SAI features (1) SAI1

I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97

Mute mode

Stereo/Mono audio frame capability.

16 slots

Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit

FIFO size

SPDIF

PDM

1. X: supported

X (8 Word)

SAI2

X (8 Word)

3.39 Controller area network (CAN)

The CAN is compliant with the 2.0A and B (active) specifications with a bit rate of up to

1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The CAN has three transmit mailboxes, two receive

FIFOS with three stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated.

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Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

The CAN peripheral supports:

• CAN protocol version 2.0 A, B Active

• Bit rates of up to 1 Mbit/s

• Transmission

– Three transmit mailboxes

– Configurable transmit priority

• Reception

– Two receive FIFOs with three stages

– Scalable filter banks: 28 filter banks

– Identifier list feature

– Configurable FIFO overrun

• Time-triggered communication option

– Disable automatic retransmission mode

– 16-bit free running timer

– Time Stamp sent in last two data bytes

• Management

– Maskable interrupts

– Software-efficient mailbox mapping at a unique address space

(SDMMC)

The SD/SDIO, MultiMediaCard (MMC) host interface (SDMMC) provides an interface between the AHB bus and SD memory cards, SDIO cards and MMC devices.

The SDMMC features include the following:

• Full compliance with MultiMediaCard System Specification Version 4.51. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit

• Full compatibility with previous versions of MultiMediaCards (backward compatibility)

• Full compliance with SD Memory Card Specifications Version 4.1. (SDR104

SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and UHS-II mode not supported)

• Full compliance with SDIO Card Specification Version 4.0: card support for two different databus modes: 1-bit (default) and 4-bit. (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and UHS-II mode not supported)

• Data transfer up to 104 Mbyte/s for the 8-bit mode (depending maximum allowed IO speed)

• Data and command output enable signals to control external bidirectional drivers.

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3.41 Universal serial bus on-the-go full-speed (OTG_FS)

The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume.

The USB OTG controller requires a dedicated 48 MHz clock that can be provided by the internal multispeed oscillator (MSI) automatically trimmed by 32.768 kHz external oscillator

(LSE).This allows to use the USB device without external high speed crystal (HSE).

The major features are:

• Combined Rx and Tx FIFO size of 1.25 Kbytes with dynamic FIFO sizing

• Supports the session request protocol (SRP) and host negotiation protocol (HNP)

• One bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints

• Eight host channels with periodic OUT support

• HNP/SNP/IP inside (no need for any external resistor)

• Software configurable to OTG 1.3 and OTG 2.0 modes of operation

• OTG 2.0 Supports ADP (Attach detection Protocol)

• USB 2.0 LPM (Link Power Management) support

• Battery charging specification revision 1.2 support

• Internal FS OTG PHY support

For OTG/Host modes, a power switch is needed in case bus-powered devices are connected.

The synchronization for this oscillator can also be taken from the USB data stream itself

(SOF signalization) which allows crystal less operation.

The devices embed a special block which allows automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which could be either derived from USB SOF signalization, from LSE oscillator, from an external signal on

CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action.

3.43 Flexible static memory controller (FSMC)

The flexible static memory controller (FSMC) includes two memory controllers:

• The NOR/PSRAM memory controller

• The NAND/memory controller

This memory controller is also named flexible memory controller (FMC).

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Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

The main features of the FMC controller are the following:

• Interface with static-memory mapped devices including:

– Static random access memory (SRAM)

– NOR Flash memory/OneNAND Flash memory

– PSRAM (four memory banks)

– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data

– Ferroelectric RAM (FRAM)

• 8-,16- bit data bus width

• Independent chip select control for each memory bank

• Independent configuration for each memory bank

• Write FIFO

• The Maximum FMC_CLK frequency for synchronous accesses is HCLK/2.

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost effective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration.

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The OctoSPI is a specialized communication interface targetting single, dual, quad or octal

SPI memories. It can operate in any of the three following modes:

• Indirect mode: all the operations are performed using the OctoSPI registers

• Status polling mode: the external memory status register is periodically read and an interrupt can be generated in case of flag setting

• Memory-mapped mode: the external memory is memory mapped and is seen by the system as if it were an internal memory supporting read and write operation

The OctoSPI supports two frame formats:

• Classical frame format with command, address, alternate byte, dummy cycles and data phase over 1, 2, 4 or 8 data pins

• HyperBus

frame format

The OctoSPI offers the following features:

• Three functional modes: indirect, status-polling, and memory-mapped

• Read and write support in memory-mapped mode

• Supports for single, dual, quad and octal communication

• Dual-quad mode, where 8 bits can be sent/received simultaneously by accessing two quad memories in parallel.

• SDR and DTR support

• Data strobe support

• Fully programmable opcode for both indirect and memory mapped mode

• Fully programmable frame format for both indirect and memory mapped mode

DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Functional overview

• Each of the five following phases can be configured independently (enable, length, single/dual/quad communication)

– Instruction phase

– Address phase

– Alternate bytes phase

– Dummy cycles phase

– Data phase

• HyperBus TM support

• Integrated FIFO for reception and transmission

• 8, 16, and 32-bit data accesses are allowed

• DMA channel for indirect mode operations

• Timeout management

• Interrupt generation on FIFO threshold, timeout, status match, operation complete, and access error

3.45 OctoSPI IO manager (OctoSPIIOM)

The OctoSPI IO Manager is a low level interface allowing:

• Efficient OctoSPI pin assignment with a full IO Matrix (before alternate function map)

• Multiplexing single/dual/quad/octal SPI interface over the same bus

The OctoSPI IO Manager has the following features:

• Support up to two single/dual/quad/octal SPI Interface

• Support up to eight ports for pin assignment

• Fully programmable IO matrix for pin assignment by function (data/control/clock)

• Muxer for Single/Dual/Quad/Octal SPI interface multiplexing over the same bus

The Arm

SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using two pins only instead of five required by the JTAG (JTAG pins could be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

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Functional overview STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

3.46.2 Embedded Trace Macrocell™

The Arm

Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the

STM32L4Sxxx devices through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors.

The Embedded Trace Macrocell operates with third party debugger software tools.

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4 Pinouts and pin description

Pinouts and pin description

Figure 8. STM32L4S5xx and STM32L4S7xx UFBGA169 ballout (1)

PI10

PI9

PH2

PI7

VDD

VSS

PE0

PE1

PB4

PB5

PB3

VDDIO2

VDD

PE4

VSS

PE3

PI11

PE2

PB8

PB9

PB6

PB7

PG15

PG10

E PC13

PC14-

OSC32_IN

PC15-

OSC32_OUT

VBAT

VSS

VDD

PE6

PF2

PF3

H PH0-OSC_IN

VSS

PH1-

OSC_OUT

PC3

PC0

VSSA/VREF-

NRST

PC1

PA0

L VREF+

OPAMP1_VI

N PA2

VDDA

PA3

PA1

PE5

PF1

PF4

PF10

PC2

PA5

PH3-BOOT0

PF0

PF5

PC4

PC5

PB0

PA4

VSS

VDD

PA7 PB1

PA6

OPAMP2_VI

PF11

PB2

PG11

PG12

PG14

PG1

PG0

PF15

PF14

PF13

PF12

PG13

PE10

PE9

PE8

PE7

VSS

VDD

PD4

PD5

PD6

PD7

VSS

PG9

PC9

PG8

PG5

PH4

PH5

PH10

PB10

PH13

PC10

PC11

PA10

PA15

PI6

PA8

PB11

PE15

PE14

PE13

PE12

PE11

PD1

PD2

PD3

PC12

VDD

PD0

PD8

VSS

VDD

PG6

PD15

PG3

PD12

PI8

PH9

PH6

PC6

PA13

PI1

PI3

PI4

PI5

PA9

PA14

PI2

PC8

PG7

PG4

PD14

PD9

PH11

PH8

VDD

PB15

PB12

PC7

VSS

PG2

PD11

PI0

PH15

VSS

PH7

VDDUSB

VDDIO2

VSS

PB14

PB13

VDD

PD10

PD13

VDD

PA12

PA11

VSS

PH14

PH12

MSv38036V4

1. The above figure shows the package top view.

Figure 9. STM32L4S9xx UFBGA169 ballout (1)

PI10

PI9

VDD

PH2

PI7

VSS

E PC13

PC14-

OSC32_IN

PC15-

OSC32_OUT

VBAT

VSS

VDD

H PH0-OSC_IN

VSS

PH1-

OSC_OUT

PC3

PC0

VSSA/VREF-

PE6

PF2

PF3

NRST

PC1

PA0

PE4

VREF+

PE3

VDDA

PE2

PA5

PA1

PA2

PA3

PA4

VSS

VDD

VSS

PI11

PF1

PF4

PF10

PC2

PC4

PA6

PA7

PB0

PE0

PE1

PB8

PB4

PB5

PB6

PB9

PE5

PB7 PG10

PH3-BOOT0 PG11

PB3

VDDIO2

PG15

PF0

PF5

PG1

PG0

PF15

PB1

PF11

PB2

PE8

PF14

PF13

PF12

PG12

PG13

PE10

PE9

PB11

PE15

PE14

PE7

VSS

VDD

PD5

PD6

PD7

PG4

VSS

PG9

PD4

PD13

PD12

PH4

PE13

PE12

PE11

PD2

PD3

PC12

PG3

VDD

PD0

PD1

PG2

PD11

PD9

PH5

PH10

PB10

PC10

PC11

PC8

PG5

PA15

PI6

PH13

PI4

PI5

PG8

PG7

PA14

PI2

PI3

PD15

PD10

PD8

PB15

PH11

PH8

PA10

PA8

PC6

PC7

PA13

PI1

PH9

PI0

PH15

VSS

VDDUSB

PA9

VDDIO2

PG6

PD14 VSS

DSI_D1P DSI_D1N

VDD

VSSDSI

PH14

PH12

VDD

PA12

PA11

VSS

PC9

DSI_CKP DSI_CKN VSSDSI

DSI_D0P DSI_D0N VCAPDSI

VSS

VDD

PB14 VDDDSI

PB12 PB13

MSv45223V2

1. The above figure shows the package top view.

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Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Figure 10. STM32L4S5xx and STM32L4S7xx LQFP144 pinout (1)

PE2

PE3

PE4

PE5

PE6

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PF0

PF1

PF2

PF3

PF4

PF5

VSS

VDD

PF6

PF7

PF8

PF9

PF10

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA

VREF-

VREF+

VDDA

PA0

PA1

PA2

1. The above figure shows the package top view.

LQFP144

PG4

PG3

PG2

PD15

PD14

VDD

VSS

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

VDD

VSS

PA8

PC9

PC8

PC7

PC6

VDDUSB

PA13

PA12

PA11

PA10

PA9

VDDIO2

VSS

PG8

PG7

PG6

PG5

108

107

106

105

104

103

102

101

100

MSv45224V1

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DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description

Figure 11. STM32L4S9xx LQFP144 pinout

(1)

PE2

PE3

PE4

PE5

PE6

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PF0

PF1

PF2

PF3

PF4

PF5

VSS

VDD

PF6

PF7

PF10

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA/VREF-

VREF+

VDDA

PA0

PA1

PA2

PA3

VSS

VDD

LQFP144

PA9

PA8

PC9

PC8

PC7

VDDUSB

PA13

PA12

PA11

PA10

PC6

PG8

PG7

PG6

PG5

PG4

PG3

PG2

PD15

PD14

VDD

VSS

PD13

PD12

PD11

PD10

PD9

PD8

VDD12DSI

DSI_CKN

DSI_CKP

VSSDSI

DSI_D0N

DSI_D0P

VCAPDSI

VDDDSI

103

102

101

100

108

107

106

105

104

MSv45225V1

1. The above figure shows the package top view.

DS12024 Rev 4

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113

Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Figure 12. STM32L4S9xx UFBGA144 ballout (1)

VSS

PE0

3 4

PB9 PH3-BOOT0

B VBAT VDD

VSS PE5

PC14-

OSC32_IN

PC15-

OSC32_OUT

PF2 PF1

PE3

PE2

PE4

PF0

F PF8 PF6

H PH0-OSC_IN

PH1-

OSC_OUT

VDD

NRST

VSS

PC1

PF4

PF10

VSSA/VREFVREF+

VDDA

VSS

PA1

VDD

PC0

PC3

PA0

PA2

PA3

PB8

PE1

PE6

PC13

PF5

PF9

PC2

PA6

PA4

PA5

PA7

PB6

PF3

PF7

PF12

PB2

PB1

PB4

PB5

PB7

PC5

PC4

PB0

PG12

PG10

PG9

PE7

VDDIO2

PB3

PG13

PF15

PF13

PF11

VSS

VDD

PD5

PD7

PG3

PD15

VSS

PD6

PD4

PE11

PE9

PE8

PG0

PF14

PD2

PG8

PG5

PD14

PD3

PD1

PD0

PD10

PE13

PE15

PE10

PG1

PC12

PC7

PG6

PD12

PC11

PA15

PC10

PD9

PB15

PB11

PB10

PE12

PA14

PA13

PA10

PA9

PC8

PG4

PD13

PA8

PG7

VSS

PD11

VDD

PA12

VDDUSB

PD8

VSSDSI

DSI_D1P DSI_D1N

DSI_CKP DSI_CKN

VSS

PA11

PC9

PC6

VDDIO2

PG2

VDD

PB14

PB12

PE14

DSI_D0P DSI_D0N

VDD VCAPDSI

PB13 VSS

MSv38491V4

1. The above figure shows the package top view.

Figure 13. STM32L4S9xx WLCSP144 ballout

(1)

PG7

PD15

VSS

PD9

VSS

VDD

PA11

PC8

PA14

VDDUSB

PA12

PC9

PG8

PG2

VDD

PD8

DSI_D1N

DSI_CKP

DSI_D1P

DSI_CKN

PB15

VSSDSI

DSI_D0P DSI_D0N VCAPDSI

VDD VDD VSS

VDDIO2

PD14

PD13

PB14

PA15

PA13

PC10

PA8

PC6

PD12

PD11

PB13

PD0

PC12

PC11

PA9

PB12

PE15

PB10

PB11

PG6

PG3

PD10

PE14

PD5

PD2

PD1

PA10

PE13

PE10

PE11

PE12

PD6

PG5

PF14

PB1

PG12

PG10

PG9

PD7

PB2

PF11

VDD

PF13

PC7

PG4

PE9

PE8

VDD

VSS

PD4

PD3

PF15

PG0

PG1

PE7

PA6

PC5

PF12

VSS

PB5

PF1

PA5

PA2

VDDIO2

PB3

PB4

PG13

PB7

PE0

PH3-BOOT0 PB9

PB6 PB8

PE5 PE6

PF0

PF5

PF7

PC2

PA0

PA4

PC4

PB0

VBAT

PF4

PA3

PA7

PE1

PE2

PE3

VSS

VDD

PE4

PC13 VSS

PC14-

OSC32_IN

PC15-

OSC32_OUT

PF3 PF2

PF6 VSS VDD

PF10

PC3

PA1

NRST PH0-OSC_IN

PC0

VSSA/VREF-

PH1-

OSC_OUT

PC1

VREF+

VDD

VDDA

VSS

MSv42219V2

1. The above figure shows the package top view

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DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description

Figure 14. STM32L4S5xx WLCSP144 ballout

(1)

VSS

VDD

PA11

PA14

VDDUSB

PA12

PA15

PA13

PC10

PD0

PC12

PC11

PD5

PD2

PD1

VDD

VSS

PD4

PG12

PG10

PG9

VDDIO2

PB3

PB4

PB7

PE0

PH3-BOOT0 PB9

PB6 PB8

PE1

PE2

PE3

VSS

VDD

PE4

PA8

VDDIO2

PD14

PD13

PB14

PB15

VSS

PF4

PG11

VDD

PC2

PA9

PC6

PD12

PD11

PB13

PB12

PE15

PB10

PB11

PA10

PG6

PG3

PD10

PE14

PE13

PE10

PE11

PE12

PE8

PF15

PG0

PG1

PE7

PD3

PC7

PG4

PE9

PD6

PG14

PF0

PB1

PB2

PF11

VDD

PF13

PD7

PD6

PG5

PF14

PD4

PG13

PG12

PG13

PB5

PF1

PA5

PA2

PA6

PC5

PF12

VSS

PG3

PG1

PG0

PF15

PD1

PD0

PG9

PG5

PE5

PF0

PF5

PF7

PC2

PA0

PA4

PC4

PB0

1. The above figure shows the package top view.

NC (not-connected) balls must be left unconnected.

1 2

Figure 15. STM32L4S5xx UFBGA132 ballout

(1)

3 4 5 6 7 8 9 10

A PE3 PE1 PB8 PH3-BOOT0 PD7 PD5 PB4 PB3 PA15 PA14

PD9

VDD

PC8

PG7

PD15

VSS

PE4 PE2

PC13

PC14-

OSC32_IN

PC15-

OSC32_OUT

PE5

PE6

VBAT

PH0-OSC_IN

PH1-

OSC_OUT

PC0

VSS

VDD

NRST

VSSA/VREFPC1

PG15

VREF+

VDDA

PD8

VDD

PC9

PG8

PG2

VDD

PC3

PA0

PA1

PB9

PE0

VSS

PF5

PG6

PG7

PA4

PB7

VDD

PF2

PF3

PA2 PA5

PA3 PA6

OPAMP1_VI

OPAMP2_VI

PB6

PB5

PF1

PA7

PC4

PC5

PB0

VSS

VDD

PG8

PF11

PB2

PB1

VSS

VDDIO2

PF12

PF13

PE8

PE7

PD3

PD2

PG10

PF14

PD9

PE10

PE9

PD8

PE12

PE11

PE6

VBAT

PF4

PF6

PC13 VSS

PC14-

OSC32_IN

PC15-

OSC32_OUT

PF3 PF2

VSS VDD

PF10

PC3

PA1

NRST PH0-OSC_IN

PC0

VSSA/VREF-

PH1-

OSC_OUT

PC1

PA3 VREF+ VDDA

PA7 VDD VSS

MSv43442V1

PC12

PC11

PA9

PC8

PG4

PG2

PD15

PD12

PB15

PB10

PE13

PA13

PC10

VDDUSB

PD14

PD11

PB14

PA8

PC7

VSS

VDD

PB11

PE14

PD13

PD10

PB13

PC9

PC6

VSS

VDD

PA12

PA11

PA10

PB12

PE15

MSv38035V5

1. The above figure shows the package top view.

DS12024 Rev 4

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113

Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Figure 16. STM32L4S5xx and STM32L4S7xx LQFP100 pinout (1)

PE2

PE3

PE4

PE5

PE6

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VSS

VDD

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA

VREF-

VREF+

VDDA

PA0

PA1

PA2

LQFP100

1. The above figure shows the package top view.

PA10

PA9

PA8

PC9

PC8

PC7

VDD

VSS

VDDUSB

PA13

PA12

PA11

PD10

PD9

PD8

PB15

PB14

PB13

PC6

PD15

PD14

PD13

PD12

PD11

PB12

MSv38494V1

70/273

DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description

Figure 17. STM32L4S9xx LQFP100 pinout (1)

9%$7

3&26&B,1

3&26&B287

966

9''

3+26&B,1

3+26&B287

1567

966$95()

9''$95()

966

/4)3

1. The above figure shows the package top view.

9''86%

9'''6,

'6,B&.1

'6,B&.3

966'6,

'6,B'1

'6,B'3

9&$3'6,

9'''6,

06Y9

DS12024 Rev 4

71/273

113

Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Name

Pin name

Pin type

I/O structure

Table 14. Legend/abbreviations used in the pinout table

Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

Supply pin

Input only pin

I/O

RST

Input / output pin

5 V tolerant I/O

3.6 V tolerant I/O

Dedicated BOOT0 pin

Bidirectional reset pin with embedded weak pull-up resistor

Option for TT or FT I/Os

(1)

_l (2)

(3)

(4)

(5)

I/O, Fm+ capable

I/O, with LCD function supplied by V

LCD

I/O, with USB function supplied by V

DDUSB

I/O, with Analog switch function supplied by V

DDA

I/O supplied only by V

DDIO2

Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.

Notes

Pin functions

Alternate functions

Functions selected through GPIOx_AFR registers

Additional functions

Functions directly selected/enabled through peripheral registers

72/273

DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description

Table 15. STM32L4Sxxx pin definitions

STM32L4S5xx

STM32L4S7xx

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

M11 -

1 B11 D3 1

2 C11 D2 2

3 C12 D1 3

4 D9 E4 4

5 D10 E3 5

6 E2 6 E10 E2 6 6

B11

C11

C12

D10

M11

VSS

VDD

PI11

PE2

PE3

PE4

PE5

PE6

B1 E10 E2 VBAT

I/O

I/O FT_l -

OCTOSPIM_P2_IO0

, EVENTOUT

TRACECK,

TIM3_ETR,

SAI1_CK1,

TSC_G7_IO1,

LCD_R0, FMC_A23,

SAI1_MCLK_A,

EVENTOUT

TRACED0,

TIM3_CH1,

OCTOSPIM_P1_DQ

S, TSC_G7_IO2,

LCD_R1, FMC_A19,

SAI1_SD_B,

EVENTOUT

TRACED1,

TIM3_CH2,

SAI1_D2,

DFSDM1_DATIN3,

TSC_G7_IO3,

DCMI_D4, LCD_B0,

FMC_A20,

SAI1_FS_A,

EVENTOUT

TRACED2,

TIM3_CH3,

SAI1_CK2,

DFSDM1_CKIN3,

TSC_G7_IO4,

DCMI_D6, LCD_G0,

FMC_A21,

SAI1_SCK_A,

EVENTOUT

TRACED3,

TIM3_CH4,

SAI1_D1, DCMI_D7,

LCD_G1, FMC_A22,

SAI1_SD_A,

EVENTOUT

RTC_TAMP3,

WKUP3

DS12024 Rev 4

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113

Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

7 C1 7 D11 E1 7 7 E4 D11 E1 PC13 I/O FT

(1)

(2)

EVENTOUT

RTC_TAMP1/R

TC_TS/RTC_O

UT,WKUP2

E11

E12

F12

F11

F10

G10

F12

G10

D2 E12 G1

13 E5 F11 G3

14 F3 F10 G4

E11

F9 G5

10 F2 16 G11 F2 10 16 L6 G11 F2

11 G2 17 G12 G2 11 17 G1 G12 G2

PC14-

OSC32_

(PC14)

PC15-

OSC32_

OUT

(PC15)

I/O FT

PF0

PF1

PF2

PF3

PF4

PF5

VSS

VDD

PF6

PF7

EVENTOUT

I/O FT_f -

I/O

I2C2_SDA,

OCTOSPIM_P2_IO0

, FMC_A0,

EVENTOUT

I2C2_SCL,

OCTOSPIM_P2_IO1

, FMC_A1,

EVENTOUT

I2C2_SMBA,

OCTOSPIM_P2_IO2

, FMC_A2,

EVENTOUT

OCTOSPIM_P2_IO3

, FMC_A3,

EVENTOUT

OCTOSPIM_P2_CL

K, FMC_A4,

EVENTOUT

FMC_A5,

EVENTOUT

TIM5_ETR,

TIM5_CH1,

OCTOSPIM_P1_IO3

, SAI1_SD_B,

EVENTOUT

TIM5_CH2,

OCTOSPIM_P1_IO2

, SAI1_MCLK_B,

EVENTOUT

OSC32_IN

OSC32_OUT

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STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

H10

J12

H11

J11

K12

20 G3 H10 H4

12 F1 23 H12 H1 12 21 H1 H12 H1

J1 H11 H3

J12

J11

K12

PF8

PF9

PF10

I/O

PH0-

OSC_IN

(PH0)

PH1-

OSC_O

(PH1)

I/O

NRST I-O RST -

(3)

TIM5_CH3,

OCTOSPIM_P1_IO0

, SAI1_SCK_B,

EVENTOUT

TIM5_CH4,

OCTOSPIM_P1_IO1

, SAI1_FS_B,

TIM15_CH1,

EVENTOUT

OCTOSPIM_P1_CL

K, DFSDM1_CKOUT,

DCMI_D11,

SAI1_D3,

TIM15_CH2,

EVENTOUT

PC0

PC1

PC2

I/O

FT_fl a

FT_l a

LPTIM1_IN1,

I2C3_SCL,

DFSDM1_DATIN4,

LPUART1_RX,

SAI2_FS_A,

LPTIM2_IN1,

EVENTOUT

TRACED0,

LPTIM1_OUT,

SPI2_MOSI,

I2C3_SDA,

DFSDM1_CKIN4,

LPUART1_TX,

OCTOSPIM_P1_IO4

, SAI1_SD_A,

EVENTOUT

LPTIM1_IN2,

SPI2_MISO,

DFSDM1_CKOUT,

OCTOSPIM_P1_IO5

, EVENTOUT

OSC_IN

OSC_OUT

ADC1_IN1

ADC1_IN2

ADC1_IN3

DS12024 Rev 4

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113

Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

29 J10 K1 18 27 J3 J10 K1 PC3

K11 K2 19 28 K1 K11 K2

VSSA

VREF-

VSSA/V

REF-

I/O FT_a -

LPTIM1_ETR,

SAI1_D1,

SPI2_MOSI,

OCTOSPIM_P1_IO6

, SAI1_SD_A,

LPTIM2_ETR,

EVENTOUT

S -

ADC1_IN4

22 M1 33 L12 L2

L11

K10

20 -

L11

K10

VREF+

L1 L12 L2

VDDA

VDDA/V

REF+

VREFBUF_OU

PA0

OPAMP

1_VINM

I/O FT_a -

TIM2_CH1,

TIM5_CH1,

TIM8_ETR,

USART2_CTS_NSS,

UART4_TX,

SAI1_EXTCLK,

TIM2_ETR,

EVENTOUT

OPAMP1_VIN

P, ADC1_IN5,

RTC_TAMP2,

WKUP1

I TT -

PA1

PA2

I/O

FT_l a

I/O

FT_l a

TIM2_CH2,

TIM5_CH2,

I2C1_SMBA,

SPI1_SCK,

USART2_RTS_DE,

UART4_RX,

OCTOSPIM_P1_DQ

S, TIM15_CH1N,

EVENTOUT

TIM2_CH3,

TIM5_CH3,

USART2_TX,

LPUART1_TX,

OCTOSPIM_P1_NC

S, SAI2_EXTCLK,

TIM15_CH1,

EVENTOUT

OPAMP1_VIN

M, ADC1_IN6

ADC1_IN7,

WKUP4/LSCO

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DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

26 L3 37 L10 M2 24 34 M3 L10 M2

M12

M11

M12

M11

32 J5 43 M10 L4 30 40 M4 M10 M4

PA3

VSS

VDD

PA4

PA5

PA6

OPAMP

2_VINM

I/O TT_a -

I/O FT_a -

TIM2_CH4,

TIM5_CH4,

SAI1_CK1,

USART2_RX,

LPUART1_RX,

OCTOSPIM_P1_CL

K, SAI1_MCLK_A,

TIM15_CH2,

EVENTOUT

OPAMP1_VOU

T, ADC1_IN8

OCTOSPIM_P1_NC

S, SPI1_NSS,

SPI3_NSS,

USART2_CK,

DCMI_HSYNC,

SAI1_FS_B,

LPTIM2_OUT,

EVENTOUT

TIM2_CH1,

TIM2_ETR,

TIM8_CH1N,

SPI1_SCK,

LPTIM2_ETR,

EVENTOUT

ADC1_IN9,

DAC1_OUT1

ADC1_IN10,

DAC1_OUT2

TIM1_BKIN,

TIM3_CH1,

TIM8_BKIN,

DCMI_PIXCLK,

SPI1_MISO,

USART3_CTS_NSS,

LPUART1_CTS,

OCTOSPIM_P1_IO3

, TIM16_CH1,

EVENTOUT

OPAMP2_VIN

P, ADC1_IN11

I TT -

PA7 I/O

FT_fl a

TIM1_CH1N,

TIM3_CH2,

TIM8_CH1N,

I2C3_SCL,

SPI1_MOSI,

OCTOSPIM_P1_IO2

, TIM17_CH1,

EVENTOUT

OPAMP2_VIN

M, ADC1_IN12

DS12024 Rev 4

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113

Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

36 M6 47 H7

K6 49 K7 M5 45 K6

J7 50 L8

51 M8

52 L7

L5 33 43

K7 M5

K7 53 M7 M6 49 J6 M7 M6

PC4

PC5

PB0

PB1

PB2

PF11

PF12

VSS

VDD

PF13

I/O FT_a -

I/O

TT_l a

I/O FT_a -

USART3_TX,

OCTOSPIM_P1_IO7

, EVENTOUT

SAI1_D3,

USART3_RX,

EVENTOUT

COMP1_INM,

ADC1_IN13

COMP1_INP,

ADC1_IN14,

WKUP5

TIM1_CH2N,

TIM3_CH3,

TIM8_CH2N,

SPI1_NSS,

USART3_CK,

OCTOSPIM_P1_IO1

, COMP1_OUT,

SAI1_EXTCLK,

EVENTOUT

TIM1_CH3N,

TIM3_CH4,

TIM8_CH3N,

DFSDM1_DATIN0,

USART3_RTS_DE,

LPUART1_RTS_DE,

OCTOSPIM_P1_IO0

, LPTIM2_IN1,

EVENTOUT

OPAMP2_VOU

T, ADC1_IN15

COMP1_INM,

ADC1_IN16

RTC_OUT,

LPTIM1_OUT,

I2C3_SMBA,

DFSDM1_CKIN0,

OCTOSPIM_P1_DQ

S, LCD_B1,

EVENTOUT

LCD_DE,

DCMI_D12, DSI_TE,

EVENTOUT

OCTOSPIM_P2_DQ

S, LCD_B0,

FMC_A6,

EVENTOUT

I2C4_SMBA,

DFSDM1_DATIN6,

LCD_B1, FMC_A7,

EVENTOUT

COMP1_INP

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DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

J8 54 G7

J9 55 J6

H9 56 K6

G9 57 L6 H6

52 L7 K6 J5

53 M8 L6 H5

PF14

PF15

PG0

PG1

PE7

PE8

PE9

VSS

VDD

PE10

I/O FT_f -

I/O

I2C4_SCL,

DFSDM1_CKIN6,

TSC_G8_IO1,

LCD_G0, FMC_A8,

EVENTOUT

I2C4_SDA,

TSC_G8_IO2,

LCD_G1, FMC_A9,

EVENTOUT

OCTOSPIM_P2_IO4

, TSC_G8_IO3,

FMC_A10,

EVENTOUT

OCTOSPIM_P2_IO5

, TSC_G8_IO4,

FMC_A11,

EVENTOUT

TIM1_ETR,

DFSDM1_DATIN2,

LCD_B6, FMC_D4,

SAI1_SD_B,

EVENTOUT

TIM1_CH1N,

DFSDM1_CKIN2,

LCD_B7, FMC_D5,

SAI1_SCK_B,

EVENTOUT

TIM1_CH1,

DFSDM1_CKOUT,

LCD_G2, FMC_D6,

SAI1_FS_B,

EVENTOUT

TIM1_CH2N,

DFSDM1_DATIN4,

TSC_G5_IO1,

OCTOSPIM_P1_CL

K, LCD_G3,

FMC_D7,

SAI1_MCLK_B,

EVENTOUT

DS12024 Rev 4

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113

Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

47 L10 69 L4 N9

L5 N8

43 L9 65 M5 M8 40 61 M9 M5 M8

M10

M11

M12

M10

PE11

PE12

PE13

PE14

PE15

PB10

I/O

I/O FT_fl -

TIM1_CH2,

DFSDM1_CKIN4,

TSC_G5_IO2,

OCTOSPIM_P1_NC

S, LCD_G4,

FMC_D8,

EVENTOUT

TIM1_CH3N,

SPI1_NSS,

DFSDM1_DATIN5,

TSC_G5_IO3,

OCTOSPIM_1_IO0,

LCD_G5, FMC_D9,

EVENTOUT

TIM1_CH3,

SPI1_SCK,

DFSDM1_CKIN5,

TSC_G5_IO4,

OCTOSPIM_P1_IO1

, LCD_G6,

FMC_D10,

EVENTOUT

TIM1_CH4,

TIM1_BKIN2,

SPI1_MISO,

OCTOSPIM_P1_IO2

, LCD_G7,

FMC_D11,

EVENTOUT

TIM1_BKIN,

SPI1_MOSI,

OCTOSPIM_P1_IO3

, LCD_R2,

FMC_D12,

EVENTOUT

TIM2_CH3,

I2C4_SCL,

I2C2_SCL,

SPI2_SCK,

DFSDM1_DATIN7,

USART3_TX,

LPUART1_RX,

TSC_SYNC,

OCTOSPIM_P1_CL

K, COMP1_OUT,

SAI1_SCK_A,

EVENTOUT

80/273

DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

L11

F12

G12

L12

N10

M10

N11 47

N12 48

M12

L11

L10

N10 PH8

M9 PH10

M10

N11

N12

PB11

PH4

PH5

PH11

VSS

VDD

PB12

I/O FT_fl -

I/O FT_f -

I/O

TIM2_CH4,

I2C4_SDA,

I2C2_SDA,

DFSDM1_CKIN7,

USART3_RX,

LPUART1_TX,

OCTOSPIM_P1_NC

S, DSI_TE,

COMP2_OUT,

EVENTOUT

I2C2_SCL,

OCTOSPIM_P2_DQ

S, EVENTOUT

I2C2_SDA,

DCMI_PIXCLK,

EVENTOUT

I2C3_SDA,

OCTOSPIM_P2_IO3

, DCMI_HSYNC,

EVENTOUT

TIM5_CH1,

OCTOSPIM_P2_IO5

, DCMI_D1,

EVENTOUT

TIM5_CH2,

OCTOSPIM_P2_IO6

, DCMI_D2,

EVENTOUT

TIM1_BKIN,

I2C2_SMBA,

SPI2_NSS,

DFSDM1_DATIN1,

USART3_CK,

LPUART1_RTS_DE,

TSC_G1_IO1,

SAI2_FS_A,

TIM15_BKIN,

EVENTOUT

DS12024 Rev 4

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113

Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

K12

K11

K10

N13 49

M13 50

M12 51

M11

K10

N13

M12

L10

PB13

PB14

PB15

M2 L12 -

L13

L12

VDD S

M13 VDDDSI S

L13

VSS

VCAPD

K11

K12

L11

L12

DSI_D0

I/O

J13 VSSDSI S

J11

J12

K11

K12

DSI_CK

I/O

I/O FT_fl -

I/O FT

TIM1_CH1N,

I2C2_SCL,

SPI2_SCK,

DFSDM1_CKIN1,

USART3_CTS_NSS,

LPUART1_CTS,

TSC_G1_IO2,

SAI2_SCK_A,

TIM15_CH1N,

EVENTOUT

TIM1_CH2N,

TIM8_CH2N,

I2C2_SDA,

SPI2_MISO,

DFSDM1_DATIN2,

USART3_RTS_DE,

TSC_G1_IO3,

SAI2_MCLK_A,

TIM15_CH1,

EVENTOUT

RTC_REFIN,

TIM1_CH3N,

TIM8_CH3N,

SPI2_MOSI,

DFSDM1_CKIN2,

TSC_G1_IO4,

SAI2_SD_A,

TIM15_CH2,

EVENTOUT

82/273

DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

J12

J11

L11

L10

J13

H13

K12

H11

J11

VDD12D

DSI_D1

I/O

H12 J1 J12

DSI_D1

I/O

J10 K3 K13 VSSDSI S

VSS S

H10

G11

K10

J10

PD8

PD9

PD10

VDD

PD11

I/O FT

S -

I/O FT

USART3_TX,

DCMI_HSYNC,

LCD_R3, FMC_D13,

EVENTOUT

USART3_RX,

DCMI_PIXCLK,

LCD_R4, FMC_D14,

SAI2_MCLK_A,

EVENTOUT

USART3_CK,

TSC_G6_IO1,

LCD_R5, FMC_D15,

SAI2_SCK_A,

EVENTOUT

I2C4_SMBA,

USART3_CTS_NSS,

TSC_G6_IO2,

LCD_R6, FMC_A16,

SAI2_SD_A,

LPTIM2_ETR,

EVENTOUT

DS12024 Rev 4

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113

Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

J10

H12

H10

G10

F10

K11

K13

H12

G13

H11 64

J12

J11

J10

G11

G10

G12

61 H11 85 F3 K10 63 89 G8

F12

F10

H12

H13

H11

H10

G12

PD12

PD13

VSS

VDD

PD14

PD15

PG2

PG3

PG4

PG5

PG6

I/O FT_fl -

I/O

I/O FT_s -

TIM4_CH1,

I2C4_SCL,

USART3_RTS_DE,

TSC_G6_IO3,

LCD_R7, FMC_A17,

SAI2_FS_A,

LPTIM2_IN1,

EVENTOUT

TIM4_CH2,

I2C4_SDA,

TSC_G6_IO4,

FMC_A18,

LPTIM2_OUT,

EVENTOUT

TIM4_CH3, LCD_B2,

FMC_D0,

EVENTOUT

TIM4_CH4, LCD_B3,

FMC_D1,

EVENTOUT

SPI1_SCK,

FMC_A12,

SAI2_SCK_B,

EVENTOUT

SPI1_MISO,

FMC_A13,

SAI2_FS_B,

EVENTOUT

SPI1_MOSI,

FMC_A14,

SAI2_MCLK_B,

EVENTOUT

SPI1_NSS,

LPUART1_CTS,

FMC_A15,

SAI2_SD_B,

EVENTOUT

OCTOSPIM_P1_DQ

S, I2C3_SMBA,

LPUART1_RTS_DE,

LCD_R1, DSI_TE,

EVENTOUT

84/273

DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

E12

E11

E10

D12

H10

F13

F12

F11

G12 66

E11

F11 D12 F13

E12

D12

G10 67 100 E10

G10

F10

F11

G11

PG7

PG8

VSS

F12 VDDIO2

PC6

PC7

PC8

I/O

FT_f s

I/O

FT_f s

SAI1_CK1,

I2C3_SCL,

OCTOSPIM_P2_DQ

S, DFSDM1_CKOUT,

LPUART1_TX,

FMC_INT,

SAI1_MCLK_A,

EVENTOUT

I2C3_SDA,

LPUART1_RX,

EVENTOUT

TIM3_CH1,

TIM8_CH1,

DFSDM1_CKIN3,

SDMMC1_D0DIR,

TSC_G4_IO1,

DCMI_D0, LCD_R0,

SDMMC1_D6,

SAI2_MCLK_A,

EVENTOUT

TIM3_CH2,

TIM8_CH2,

DFSDM1_DATIN3,

SDMMC1_D123DIR,

TSC_G4_IO2,

DCMI_D1, LCD_R1,

SDMMC1_D7,

SAI2_MCLK_B,

EVENTOUT

TIM3_CH3,

TIM8_CH3,

TSC_G4_IO3,

DCMI_D2,

SDMMC1_D0,

EVENTOUT

DS12024 Rev 4

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113

Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

D12 99 D2 G9 68 101 C12 D2 G13 PC9

70 B12 103 C1 E13 72 105 B12 C1 E13 PA11

D11 100

D10 101

C12 102

A12 104

G8 69 102 D11

F10 70 103 D10

F9 71 104 C10

D13 73 106 B11

E11

E12

D11

D13

PA8

PA9

PA10

PA12

I/O FT_fl -

I/O FT_f -

I/O

FT_fl u

I/O FT_u -

TRACED0,

TIM8_BKIN2,

TIM3_CH4,

TIM8_CH4,

DCMI_D3,

I2C3_SDA,

TSC_G4_IO4,

OTG_FS_NOE,

SDMMC1_D1,

SAI2_EXTCLK,

EVENTOUT

MCO, TIM1_CH1,

SAI1_CK2,

USART1_CK,

OTG_FS_SOF,

SAI1_SCK_A,

LPTIM2_OUT,

EVENTOUT

TIM1_CH2,

SPI2_SCK,

DCMI_D0,

USART1_TX,

SAI1_FS_A,

TIM15_BKIN,

EVENTOUT

TIM1_CH3,

SAI1_D1, DCMI_D1,

USART1_RX,

OTG_FS_ID,

SAI1_SD_A,

TIM17_BKIN,

EVENTOUT

TIM1_CH4,

TIM1_BKIN2,

SPI1_MISO,

USART1_CTS_NSS,

CAN1_RX,

OTG_FS_DM,

EVENTOUT

TIM1_ETR,

SPI1_MOSI,

USART1_RTS_DE,

CAN1_TX,

OTG_FS_DP,

EVENTOUT

OTG_FS_VBU

86/273

DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

72 A11 105 B3 A11 74 107 B10 B3 A11

PA13

(JTMS/S

WDIO)

I/O FT

(4)

JTMS/SWDIO,

IR_OUT,

OTG_FS_NOE,

SAI1_SD_B,

EVENTOUT

73 C11 106 B2 E12 75 108 C11 B2 D12

74 F11 107 A1 C12 76 109 A12 A1 C12

75 G11 108 B1 C13 77 110 A11 B1 C13

VDDUS

VSS

VDD

E11

D12

D11

B13

A13

B12

A12

C11

B11

C11

B13

A13

B12

A12

B11

PH6

PH7

PH9

PH12

PH14

PH15

PI0

PI8

PI1

S -

I/O

I/O FT_f -

I2C2_SMBA,

OCTOSPIM_P2_CL

K, DCMI_D8,

EVENTOUT

I2C3_SCL,

DCMI_D9,

EVENTOUT

I2C3_SMBA,

OCTOSPIM_P2_IO4

, DCMI_D0,

EVENTOUT

TIM5_CH3,

OCTOSPIM_P2_IO7

, DCMI_D3,

EVENTOUT

TIM8_CH2N,

DCMI_D4,

EVENTOUT

TIM8_CH3N,

OCTOSPIM_P2_IO6

, DCMI_D11,

EVENTOUT

TIM5_CH4,

OCTOSPIM_P1_IO5

, SPI2_NSS,

DCMI_D13,

EVENTOUT

OCTOSPIM_P2_NC

S, DCMI_D12,

EVENTOUT

SPI2_SCK,

DCMI_D8,

EVENTOUT

DS12024 Rev 4

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113

Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

76 A10 109 A2 A10 78 111 A10 A2 A10

PA14

(JTCK/S

WCLK)

110

B10

C10

D10

E10

79 112

B10

C10

D10

E10

PI2

PI3

PI4

PI5

PH13

PI6

PA15

(JTDI)

I/O FT

TIM8_CH4,

SPI2_MISO,

DCMI_D9,

EVENTOUT

TIM8_ETR,

SPI2_MOSI,

DCMI_D10,

EVENTOUT

TIM8_BKIN,

DCMI_D5,

EVENTOUT

TIM8_CH1,

OCTOSPIM_P2_NC

S, DCMI_VSYNC,

EVENTOUT

TIM8_CH1N,

CAN1_TX,

EVENTOUT

TIM8_CH2,

OCTOSPIM_P2_CL

K, DCMI_D6,

EVENTOUT

JTCK/SWCLK,

LPTIM1_OUT,

I2C1_SMBA,

I2C4_SMBA,

OTG_FS_SOF,

SAI1_FS_B,

EVENTOUT

JTDI, TIM2_CH1,

TIM2_ETR,

USART2_RX,

SPI1_NSS,

SPI3_NSS,

USART3_RTS_DE,

UART4_RTS_DE,

TSC_G3_IO1,

SAI2_FS_B,

EVENTOUT

88/273

DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

78 B11 111 C3 D9 80 113 C9 C3 D9

79 C10 112 C4 E9 81 114 A9 C4 E9

80 B10 113 B4 F8 82 115 D9 B4 F8

81 C9 114 A4 B8 83 116 C8 A4 B8

82 B9 115 C5 C8 84 117 B8 C5 C8

83 C8 116 B5 D8 85 118 D8 B5 D8

PC10

PC11

PC12

PD0

PD1

PD2

I/O FT

TRACED1,

SPI3_SCK,

USART3_TX,

UART4_TX,

TSC_G3_IO2,

DCMI_D8,

SDMMC1_D2,

SAI2_SCK_B,

EVENTOUT

DCMI_D2,

OCTOSPIM_P1_NC

S, SPI3_MISO,

USART3_RX,

UART4_RX,

TSC_G3_IO3,

DCMI_D4,

SDMMC1_D3,

SAI2_MCLK_B,

EVENTOUT

TRACED3,

SPI3_MOSI,

USART3_CK,

UART5_TX,

TSC_G3_IO4,

DCMI_D9,

SDMMC1_CK,

SAI2_SD_B,

EVENTOUT

SPI2_NSS,

DFSDM1_DATIN7,

CAN1_RX, LCD_B4,

FMC_D2,

EVENTOUT

SPI2_SCK,

DFSDM1_CKIN7,

CAN1_TX, LCD_B5,

FMC_D3,

EVENTOUT

TRACED2,

TIM3_ETR,

USART3_RTS_DE,

UART5_RX,

TSC_SYNC,

DCMI_D11,

SDMMC1_CMD,

EVENTOUT

DS12024 Rev 4

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113

Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

84 B8 117 D6 E8 86 119 A8 D6 E8

85 B7 118 C6 C7 87 120 C7 C6 C7

86 A6 119 A5 D7 88 121 D7 A5 D7

120

121

122

123

D9 124 C7 B7

122

123

89 124

90 125

126 F6

B6 M3

A6 A8

VSS

VDD

PD3

PD4

PD5

PD6

PD7

PG9

I/O

I/O FT_s -

SPI2_SCK,

DCMI_D5,

SPI2_MISO,

DFSDM1_DATIN0,

USART2_CTS_NSS,

OCTOSPIM_P2_NC

S, LCD_CLK,

FMC_CLK,

EVENTOUT

SPI2_MOSI,

DFSDM1_CKIN0,

USART2_RTS_DE,

OCTOSPIM_P1_IO4

, FMC_NOE,

EVENTOUT

USART2_TX,

OCTOSPIM_P1_IO5

, FMC_NWE,

EVENTOUT

SAI1_D1,

DCMI_D10,

SPI3_MOSI,

DFSDM1_DATIN1,

USART2_RX,

OCTOSPIM_P1_IO6

, LCD_DE,

FMC_NWAIT,

SAI1_SD_A,

EVENTOUT

DFSDM1_CKIN1,

USART2_CK,

OCTOSPIM_P1_IO7

FMC_NCE/FMC_NE

1, EVENTOUT

OCTOSPIM_P2_IO6

, SPI3_SCK,

USART1_TX,

FMC_NCE/FMC_NE

2, SAI2_SCK_A,

TIM15_CH1N,

EVENTOUT

90/273

DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

125

126

127

128

129

130

131

132

127

128

132

129 D6

130 A7

131 A6

89 A8 133 B8 A6 91 133 B6

PG10

PG11

PG12

PG13

PG14

VSS

VDDIO2

PG15

PB3

(JTDO/T

RACES

WO)

I/O FT_s -

I/O

FT_f s

FT_l a

I/O FT_s -

LPTIM1_IN1,

OCTOSPIM_P2_IO7

, SPI3_MISO,

USART1_RX,

FMC_NE3,

SAI2_FS_A,

TIM15_CH1,

EVENTOUT

LPTIM1_IN2,

OCTOSPIM_P1_IO5

, SPI3_MOSI,

USART1_CTS_NSS,

SAI2_MCLK_A,

TIM15_CH2,

EVENTOUT

LPTIM1_ETR,

OCTOSPIM_P2_NC

S, SPI3_NSS,

USART1_RTS_DE,

FMC_NE4,

SAI2_SD_A,

EVENTOUT

I2C1_SDA,

USART1_CK,

LCD_R0, FMC_A24,

EVENTOUT

I2C1_SCL, LCD_R1,

FMC_A25,

EVENTOUT

LPTIM1_OUT,

I2C1_SMBA,

OCTOSPIM_P2_DQ

S, DCMI_D13,

EVENTOUT

JTDO/TRACESWO,

TIM2_CH2,

SPI1_SCK,

SPI3_SCK,

USART1_RTS_DE,

OTG_FS_CRS_SYN

C, SAI1_SCK_B,

EVENTOUT

COMP2_INM

DS12024 Rev 4

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113

Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

90 A7 134 C8 A5 92 134 A5

91 C5 135 E8 B5 93 135 B5

92 B5 136 C9 C5 94 136 D5

C8 A5

PB4

(NJTRST)

PB5

PB6

I/O

FT_f a

FT_l a

FT_f a

Table 32 represent the total MCU consumption

NJTRST, TIM3_CH1,

I2C3_SDA,

SPI1_MISO,

SPI3_MISO,

USART1_CTS_NSS,

UART5_RTS_DE,

TSC_G2_IO1,

DCMI_D12,

SAI1_MCLK_B,

TIM17_BKIN,

EVENTOUT

LPTIM1_IN1,

TIM3_CH2,

I2C1_SMBA,

SPI1_MOSI,

SPI3_MOSI,

USART1_CK,

UART5_CTS,

TSC_G2_IO2,

DCMI_D10,

COMP2_OUT,

SAI1_SD_B,

TIM16_BKIN,

EVENTOUT

LPTIM1_ETR,

TIM4_CH1,

TIM8_BKIN2,

I2C1_SCL,

I2C4_SCL,

DFSDM1_DATIN5,

USART1_TX,

TSC_G2_IO3,

DCMI_D5,

SAI1_FS_B,

TIM16_CH1N,

EVENTOUT

COMP2_INP

92/273

DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Pinouts and pin description

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

93 B4 137 A9 D5 95 137 C5 A9 D5 PB7 I/O

FT_fl a

LPTIM1_IN2,

TIM4_CH2,

TIM8_BKIN,

I2C1_SDA,

I2C4_SDA,

DFSDM1_CKIN5,

USART1_RX,

UART4_CTS,

TSC_G2_IO4,

DCMI_VSYNC,

DSI_TE, FMC_NL,

TIM17_CH1N,

EVENTOUT

138 B9

139 C10

140 B10

141 A10

96 138

97 139

98 140

141

B9 E5

PH3-

BOOT0

I/O FT

C10

B10

A10

PB8

PB9

PE0

EVENTOUT

I/O FT_fl -

I/O FT -

TIM4_CH3,

SAI1_CK1,

I2C1_SCL,

DFSDM1_CKOUT,

DFSDM1_DATIN6,

SDMMC1_CKIN,

CAN1_RX,

DCMI_D6, LCD_B1,

SDMMC1_D4,

SAI1_MCLK_A,

TIM16_CH1,

EVENTOUT

IR_OUT, TIM4_CH4,

SAI1_D2, I2C1_SDA,

SPI2_NSS,

DFSDM1_CKIN6,

SDMMC1_CDIR,

CAN1_TX,

DCMI_D7,

SDMMC1_D5,

SAI1_FS_A,

TIM17_CH1,

EVENTOUT

TIM4_ETR,

DCMI_D2,

LCD_HSYNC,

FMC_NBL0,

TIM16_CH1,

EVENTOUT

COMP2_INM,

PVD_IN

DS12024 Rev 4

93/273

113

Pinouts and pin description STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

STM32L4S5xx

STM32L4S7xx

Table 15. STM32L4Sxxx pin definitions (continued)

Pin Number

STM32L4S9xx Pin name

(functio n after reset)

Alternate functions

Additional functions

98 A2 142 A11 B4 142 C4 A11 B4 PE1 I/O FT -

DCMI_D3,

LCD_VSYNC,

FMC_NBL1,

TIM17_CH1,

EVENTOUT

99 D3 143 A12 B3 99 143 A1 A12 B3

100 C4 144 B12 A3

144 B2 B12 A3

VSS

VDD

PH2

PI7

PI9

PI10

I/O

OCTOSPIM_P1_IO4

, EVENTOUT

TIM8_CH3,

DCMI_D7,

EVENTOUT

OCTOSPIM_P2_IO2

, CAN1_RX,

EVENTOUT

OCTOSPIM_P2_IO1

, EVENTOUT

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current

(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF

- These GPIOs must not be used as current sources (for example to drive a LED).

2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0432 reference manual.

3. NC (not-connected) balls must be left unconnected. However, PF8 and PF9 NC' IOs are not bonded. They must be configured by software to output push-pull and forced to 0 in the output data register to avoid extra current consumption in low-power modes.

4. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated.

94/273

DS12024 Rev 4

AF0 AF1 AF2

Table 16. Alternate function AF0 to AF7 (1)

AF3 AF4 AF5 AF6

Port

PA0

PA1

PA2

PA3

PA4

PA5

OTG_FS/

SYS_AF

TIM1/2/5/8/L

PTIM1

TIM2_CH1

TIM2_CH2

TIM2_CH3

TIM2_CH4

TIM2_CH1

TIM1/2/3/4/

SPI2/SAI1/I2C4/U

SART2/OTG_FS/T

IM1/8/OCTOSPIM

_P1

I2C1/2/3/4/DC

SPI1/2/3/I2C4/DFS

DM1/DCMI/OCTOS

PIM_P1/2

SPI3/I2C3/DFS

DM1/COMP1/O

CTOSPIM_P2

TIM5_CH1

TIM5_CH2

TIM5_CH3

TIM5_CH4

TIM2_ETR

TIM8_ETR

SAI1_CK1

OCTOSPIM_P1_NC

TIM8_CH1N

I2C1_SMBA

SPI1_SCK

SPI1_NSS

SPI1_SCK

SPI3_NSS

PA6

Port

PA7

PA8

PA9

PA10

MCO

TIM1_BKIN

TIM1_CH1N

TIM1_CH1

TIM1_CH2

TIM1_CH3

TIM3_CH1

TIM3_CH2

PA11

PA15

PA12

PA13

PA14

JTMS/SW

DIO

JTCK/SW

CLK

TIM1_ETR

IR_OUT

LPTIM1_OUT

JTDI

TIM1_CH4

TIM2_CH1

TIM1_BKIN2

TIM2_ETR

TIM8_BKIN

TIM8_CH1N

SAI1_CK2

SPI2_SCK

SAI1_D1

USART2_RX

DCMI_PIXCLK

I2C3_SCL

I2C1_SMBA

SPI1_MISO

SPI1_MOSI

DCMI_D0

DCMI_D1

SPI1_MISO

SPI1_MOSI

I2C4_SMBA

SPI1_NSS

SPI3_NSS

AF7

USART1/2/3

USART2_CTS_NSS

USART2_RTS_DE

USART2_TX

USART2_RX

USART2_CK

USART3_CTS_NSS

USART1_CK

USART1_TX

USART1_RX

USART1_CTS_NSS

USART1_RTS_DE

USART3_RTS_DE

AF0 AF1

Table 16. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5 AF6

Port

PB0

PB1

OTG_FS/

SYS_AF

TIM1/2/5/8/L

PTIM1

TIM1_CH2N

TIM1_CH3N

PB2 RTC_OUT LPTIM1_OUT

PB3

JTDO/TRA

CESWO

PB4 NJTRST

PB5 -

TIM2_CH2

LPTIM1_IN1

TIM1/2/3/4/

SPI2/SAI1/I2C4/U

SART2/OTG_FS/T

IM1/8/OCTOSPIM

_P1

I2C1/2/3/4/DC

SPI1/2/3/I2C4/DFS

DM1/DCMI/OCTOS

PIM_P1/2

SPI3/I2C3/DFS

DM1/COMP1/O

CTOSPIM_P2

TIM3_CH3

TIM3_CH4

TIM3_CH1

TIM3_CH2

TIM8_CH2N

TIM8_CH3N

I2C3_SMBA

I2C3_SDA

I2C1_SMBA

SPI1_NSS

SPI1_SCK

SPI1_MISO

SPI1_MOSI

DFSDM1_DATIN0

DFSDM1_CKIN0

SPI3_SCK

SPI3_MISO

SPI3_MOSI

PB6

Port

PB7

PB8

PB9

PB10

PB11

PB12

PB13

PB14

PB15

RTC_

REFIN

LPTIM1_ETR TIM4_CH1

LPTIM1_IN2

IR_OUT

TIM2_CH3

TIM2_CH4

TIM1_BKIN

TIM1_CH1N

TIM1_CH2N

TIM1_CH3N

TIM4_CH2

TIM4_CH3

TIM4_CH4

TIM8_BKIN2

TIM8_BKIN

SAI1_CK1

SAI1_D2

I2C4_SCL

I2C4_SDA

TIM1_BKIN

TIM8_CH2N

TIM8_CH3N

I2C1_SCL

I2C1_SDA

I2C1_SCL

I2C1_SDA

I2C2_SCL

I2C2_SDA

I2C2_SMBA

I2C2_SCL

I2C2_SDA

I2C4_SCL

I2C4_SDA

DFSDM1_CKOUT

SPI2_NSS

SPI2_SCK

SPI2_NSS

SPI2_SCK

SPI2_MISO

DFSDM1_CKIN5

DFSDM1_DATIN6

DFSDM1_CKIN6

DFSDM1_DATIN7

DFSDM1_CKIN7

DFSDM1_DATIN1

DFSDM1_CKIN1

DFSDM1_DATIN2

SPI2_MOSI

DFSDM1_DATIN5

DFSDM1_CKIN2

AF7

USART1/2/3

USART3_CK

USART3_RTS_DE

USART1_RTS_DE

USART1_CTS_NSS

USART1_CK

USART1_TX

USART1_RX

USART3_TX

USART3_RX

USART3_CK

USART3_CTS_NSS

USART3_RTS_DE

AF0 AF1

Table 16. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5 AF6

Port

Port

OTG_FS/

SYS_AF

TIM1/2/5/8/L

PTIM1

TIM1/2/3/4/

SPI2/SAI1/I2C4/U

SART2/OTG_FS/T

IM1/8/OCTOSPIM

_P1

I2C1/2/3/4/DC

SPI1/2/3/I2C4/DFS

DM1/DCMI/OCTOS

PIM_P1/2

SPI3/I2C3/DFS

DM1/COMP1/O

CTOSPIM_P2

PC4

PC5

PC6

PC7

PC0 LPTIM1_IN1

PC1 TRACED0 LPTIM1_OUT

PC2

PC3

LPTIM1_IN2

LPTIM1_ETR

TIM3_CH1

TIM3_CH2

PC8 TIM3_CH3

PC9 TRACED0 TIM8_BKIN2 TIM3_CH4

SPI2_MOSI

SAI1_D1

SAI1_D3

TIM8_CH1

TIM8_CH2

TIM8_CH3

TIM8_CH4

I2C3_SCL

I2C3_SDA

DCMI_D3

SPI2_MISO

SPI2_MOSI

DFSDM1_DATIN4

DFSDM1_CKIN4

DFSDM1_CKOUT

DFSDM1_CKIN3

DFSDM1_DATIN3

I2C3_SDA

PC10 TRACED1 SPI3_SCK

PC11 -

PC12 TRACED3

PC13

PC14

PC15

DCMI_D2 OCTOSPIM_P1_NCS SPI3_MISO

SPI3_MOSI

AF7

USART1/2/3

USART3_TX

USART3_RX

USART3_TX

USART3_RX

USART3_CK

AF0 AF1

Table 16. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5 AF6

Port

PD0

PD1

OTG_FS/

SYS_AF

TIM1/2/5/8/L

PTIM1

TIM1/2/3/4/

SPI2/SAI1/I2C4/U

SART2/OTG_FS/T

IM1/8/OCTOSPIM

_P1

I2C1/2/3/4/DC

SPI1/2/3/I2C4/DFS

DM1/DCMI/OCTOS

PIM_P1/2

SPI3/I2C3/DFS

DM1/COMP1/O

CTOSPIM_P2

SPI2_NSS

SPI2_SCK

DFSDM1_DATIN7

DFSDM1_CKIN7

PD6

Port

D PD7

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

PD2 TRACED2

PD3

PD4

PD5

TIM3_ETR

TIM4_CH1

TIM4_CH2

TIM4_CH3

TIM4_CH4

SPI2_SCK

SAI1_D1

DCMI_D5

DCMI_D10

I2C4_SMBA

I2C4_SCL

I2C4_SDA

SPI2_MISO

SPI2_MOSI

SPI3_MOSI

DFSDM1_DATIN0

DFSDM1_CKIN0

DFSDM1_DATIN1

DFSDM1_CKIN1

AF7

USART1/2/3

USART3_RTS_DE

USART2_CTS_NSS

USART2_RTS_DE

USART2_TX

USART2_RX

USART2_CK

USART3_TX

USART3_RX

USART3_CK

USART3_CTS_NSS

USART3_RTS_DE

AF0 AF1

Table 16. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5 AF6

Port

PE0

PE1

PE2 TRACECK

PE3

PE4 TRACED1

PE5 TRACED2

PE6 TRACED3

PE7 Port

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

OTG_FS/

SYS_AF

TIM1/2/5/8/L

PTIM1

TRACED0

TIM1_ETR

TIM1_CH1N

TIM1_CH1

TIM1_CH2N

TIM1_CH2

TIM1_CH3N

TIM1_CH3

TIM1_CH4

TIM1_BKIN

TIM1/2/3/4/

SPI2/SAI1/I2C4/U

SART2/OTG_FS/T

IM1/8/OCTOSPIM

_P1

I2C1/2/3/4/DC

SPI1/2/3/I2C4/DFS

DM1/DCMI/OCTOS

PIM_P1/2

SPI3/I2C3/DFS

DM1/COMP1/O

CTOSPIM_P2

TIM4_ETR

TIM3_ETR

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

TIM1_BKIN2

SAI1_CK1

OCTOSPIM_P1_DQ

SAI1_D2

SAI1_CK2

SAI1_D1

TIM1_BKIN2

TIM1_BKIN

SPI1_NSS

SPI1_SCK

SPI1_MISO

SPI1_MOSI

DFSDM1_DATIN3

DFSDM1_CKIN3

DFSDM1_DATIN2

DFSDM1_CKIN2

DFSDM1_CKOUT

DFSDM1_DATIN4

DFSDM1_CKIN4

DFSDM1_DATIN5

DFSDM1_CKIN5

AF7

USART1/2/3

AF0 AF1

Table 16. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5 AF6

Port

Port

PF8

PF9

PF10

PF11

PF4

PF5

PF6

PF7

PF0

PF1

PF2

PF3

PF12

PF13

PF14

PF15

OTG_FS/

SYS_AF

TIM1/2/5/8/L

PTIM1

TIM5_ETR

TIM1/2/3/4/

SPI2/SAI1/I2C4/U

SART2/OTG_FS/T

IM1/8/OCTOSPIM

_P1

I2C1/2/3/4/DC

SPI1/2/3/I2C4/DFS

DM1/DCMI/OCTOS

PIM_P1/2

SPI3/I2C3/DFS

DM1/COMP1/O

CTOSPIM_P2

TIM5_CH3

TIM5_CH4

TIM5_CH1

TIM5_CH2

OCTOSPIM_P1_CLK

I2C2_SDA

I2C2_SCL

I2C2_SMBA

I2C4_SMBA

I2C4_SCL

I2C4_SDA

OCTOSPIM_P2_IO0

OCTOSPIM_P2_IO1

OCTOSPIM_P2_IO2

OCTOSPIM_P2_IO3

OCTOSPIM_P2_CLK

DFSDM1_CKOUT

OCTOSPIM_P2_DQS

DFSDM1_DATIN6

DFSDM1_CKIN6

AF7

USART1/2/3

AF0 AF1

Table 16. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5 AF6

Port

PG0

PG1

PG2

PG3

PG4

PG5

PG6

Port

PG7

PG8

OTG_FS/

SYS_AF

TIM1/2/5/8/L

PTIM1

TIM1/2/3/4/

SPI2/SAI1/I2C4/U

SART2/OTG_FS/T

IM1/8/OCTOSPIM

_P1

I2C1/2/3/4/DC

SPI1/2/3/I2C4/DFS

DM1/DCMI/OCTOS

PIM_P1/2

SPI3/I2C3/DFS

DM1/COMP1/O

CTOSPIM_P2

OCTOSPIM_P1_DQ

SAI1_CK1

I2C3_SMBA

I2C3_SCL

I2C3_SDA

OCTOSPIM_P2_IO4

OCTOSPIM_P2_IO5

SPI1_SCK

SPI1_MISO

SPI1_MOSI

SPI1_NSS

OCTOSPIM_P2_DQS DFSDM1_CKOUT

PG9

PG10

PG11

PG12

PG13

PG14

PG15

LPTIM1_IN1

LPTIM1_IN2

LPTIM1_ETR

LPTIM1_OUT

OCTOSPIM_P2_IO6

OCTOSPIM_P1_IO5

I2C1_SDA

OCTOSPIM_P2_IO7

OCTOSPIM_P2_NCS

I2C1_SCL -

I2C1_SMBA OCTOSPIM_P2_DQS

SPI3_SCK

SPI3_MISO

SPI3_MOSI

SPI3_NSS

AF7

USART1/2/3

USART1_TX

USART1_RX

USART1_CTS_NSS

USART1_RTS_DE

USART1_CK

AF0 AF1

Table 16. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5 AF6

Port

PH0

PH1

PH2

PH3

PH4

PH5

PH6

PH7

Port

PH8

PH9

PH10

PH11

PH12

PH13

PH14

PH15

OTG_FS/

SYS_AF

TIM1/2/5/8/L

PTIM1

TIM1/2/3/4/

SPI2/SAI1/I2C4/U

SART2/OTG_FS/T

IM1/8/OCTOSPIM

_P1

I2C1/2/3/4/DC

SPI1/2/3/I2C4/DFS

DM1/DCMI/OCTOS

PIM_P1/2

SPI3/I2C3/DFS

DM1/COMP1/O

CTOSPIM_P2

TIM5_CH1

TIM5_CH2

TIM5_CH3

OCTOSPIM_P1_IO4

TIM8_CH1N

TIM8_CH2N

TIM8_CH3N

I2C2_SCL

I2C2_SDA

I2C2_SMBA

I2C3_SCL

I2C3_SDA

I2C3_SMBA

OCTOSPIM_P2_DQS

OCTOSPIM_P2_CLK

OCTOSPIM_P2_IO3

OCTOSPIM_P2_IO4

OCTOSPIM_P2_IO5

OCTOSPIM_P2_IO6

OCTOSPIM_P2_IO7

OCTOSPIM_P2_IO6

AF7

USART1/2/3

AF0 AF1

Table 16. Alternate function AF0 to AF7 (1) (continued)

AF2 AF3 AF4 AF5 AF6

Port

Port I

PI4

PI5

PI6

PI7

PI0

PI1

PI2

PI3

PI8

PI9

PI10

PI11

OTG_FS/

SYS_AF

TIM1/2/5/8/L

PTIM1

1. Refer to

Table 17

for AF8 to AF15.

TIM1/2/3/4/

SPI2/SAI1/I2C4/U

SART2/OTG_FS/T

IM1/8/OCTOSPIM

_P1

I2C1/2/3/4/DC

SPI1/2/3/I2C4/DFS

DM1/DCMI/OCTOS

PIM_P1/2

SPI3/I2C3/DFS

DM1/COMP1/O

CTOSPIM_P2

TIM5_CH4 OCTOSPIM_P1_IO5

TIM8_CH4

TIM8_ETR

TIM8_BKIN

TIM8_CH1

TIM8_CH2

TIM8_CH3

SPI2_NSS

SPI2_SCK

SPI2_MISO

SPI2_MOSI

OCTOSPIM_P2_NCS

OCTOSPIM_P2_CLK

OCTOSPIM_P2_NCS

OCTOSPIM_P2_IO2

OCTOSPIM_P2_IO1

OCTOSPIM_P2_IO0

AF7

USART1/2/3

AF8 AF9

Port UART4/5/

LPUART1/

CAN2

Port A

PA7

PA8

PA9

PA10

PA0

PA1

UART4_TX

UART4_RX

PA2 LPUART1_TX

PA3 LPUART1_RX

PA4

PA5 -

PA6

LPUART1_CT

CAN1/TSC

Table 17. Alternate function AF8 to AF15 (1)

AF10

OTG_FS/DCMI/

OCTOSPI_P1/P2

OCTOSPIM_P1_DQS

OCTOSPIM_P1_NCS

OCTOSPIM_P1_CLK

DCMI_HSYNC

OCTOSPIM_P1_IO3

OCTOSPIM_P1_IO2

OTG_FS_SOF

OTG_FS_ID

AF11

LCD

AF12

SDMMC/

COMP1/2/

FMC

TIM1_BKIN

AF13

SAI1/2

TIM8_BKIN

AF14

TIM2/15/16/17/

LPTIM2

SAI1_EXTCLK

TIM2_ETR

TIM15_CH1N

SAI2_EXTCLK TIM15_CH1

SAI1_MCLK_A TIM15_CH2

SAI1_FS_B

LPTIM2_OUT

LPTIM2_ETR

TIM16_CH1

TIM17_CH1

SAI1_SCK_A LPTIM2_OUT

SAI1_FS_A

SAI1_SD_A

TIM15_BKIN

TIM17_BKIN

PA11 CAN1_RX

PA12

PA13

PA14

PA15

CAN1_TX

UART4_RTS_

TSC_G3_IO1

OTG_FS_DM

OTG_FS_DP

OTG_FS_NOE

OTG_FS_SOF

TIM1_BKIN2

SAI1_SD_B

SAI1_FS_B

SAI2_FS_B

AF15

EVENOUT

EVENTOUT

AF8 AF9

Table 17. Alternate function AF8 to AF15 (1) (continued)

AF10

Port UART4/5/

LPUART1/

CAN2

CAN1/TSC

OTG_FS/DCMI/

OCTOSPI_P1/P2

PB0

PB1

PB2

LPUART1_

RTS_DE

OCTOSPIM_P1_IO1

OCTOSPIM_P1_IO0

OCTOSPIM_P1_DQS

PB3

PB4

UART5_RTS_

TSC_G2_IO1

PB5 UART5_CTS TSC_G2_IO2

OTG_FS_CRS_SYNC

DCMI_D12

DCMI_D10

AF11

LCD

LCD_B1

AF12 AF13 AF14

SDMMC/

COMP1/2/

FMC

SAI1/2

COMP1_OUT SAI1_EXTCLK

TIM2/15/16/17/

LPTIM2

LPTIM2_IN1

SAI1_SCK_B -

SAI1_MCLK_B TIM17_BKIN

COMP2_OUT SAI1_SD_B TIM16_BKIN

PB6 TSC_G2_IO3 DCMI_D5 TIM8_BKIN2 SAI1_FS_B TIM16_CH1N

DSI_TE

LCD_B1

FMC_NL TIM8_BKIN TIM17_CH1N

SDMMC1_D4 SAI1_MCLK_A TIM16_CH1

Port B

PB7 UART4_CTS TSC_G2_IO4 DCMI_VSYNC

PB8

PB9

SDMMC1_

CKIN

SDMMC1_

CDIR

CAN1_RX

CAN1_TX

DCMI_D6

DCMI_D7

PB10 LPUART1_RX TSC_SYNC OCTOSPIM_P1_CLK

OCTOSPIM_P1_NCS PB11 LPUART1_TX

PB12

PB13

PB14

LPUART1_RT

S_DE

LPUART1_CT

TSC_G1_IO1

TSC_G1_IO2

TSC_G1_IO3 -

PB15 TSC_G1_IO4 -

DSI_TE

SDMMC1_D5 SAI1_FS_A

COMP1_OUT SAI1_SCK_A

COMP2_OUT -

SAI2_FS_A

TIM17_CH1

TIM15_BKIN

SAI2_SCK_A TIM15_CH1N

SAI2_MCLK_A TIM15_CH1

SAI2_SD_A TIM15_CH2

AF15

EVENOUT

EVENTOUT

AF8 AF9

Table 17. Alternate function AF8 to AF15 (1) (continued)

AF10

Port

Port C

UART4/5/

LPUART1/

CAN2

CAN1/TSC

OTG_FS/DCMI/

OCTOSPI_P1/P2

PC0 LPUART1_RX

PC1 LPUART1_TX

PC2

PC3

PC4

PC5

PC6

PC7

PC8

PC9

SDMMC1_

D0DIR

SDMMC1_

D123DIR

TSC_G4_IO1

TSC_G4_IO2

TSC_G4_IO3

TSC_G4_IO4

OCTOSPIM_P1_IO4

OCTOSPIM_P1_IO5

OCTOSPIM_P1_IO6

OCTOSPIM_P1_IO7

DCMI_D0

DCMI_D1

DCMI_D2

OTG_FS_NOE

AF11

LCD

LCD_R0

LCD_R1

AF12 AF13 AF14

SDMMC/

COMP1/2/

FMC

SAI1/2

SAI2_FS_A

SAI1_SD_A

SDMMC1_D6 SAI2_MCLK_A

TIM2/15/16/17/

LPTIM2

LPTIM2_IN1

LPTIM2_ETR

SDMMC1_D7 SAI2_MCLK_B -

SDMMC1_D0 -

SDMMC1_D1 SAI2_EXTCLK TIM8_BKIN2

PC10 UART4_TX TSC_G3_IO2 DCMI_D8 SDMMC1_D2 SAI2_SCK_B -

AF15

EVENOUT

EVENTOUT

PC11 UART4_RX TSC_G3_IO3

PC12 UART5_TX TSC_G3_IO4

PC13

PC14

PC15

DCMI_D4

DCMI_D9

SDMMC1_D3 SAI2_MCLK_B

SDMMC1_CK SAI2_SD_B

EVENTOUT

Port

PD0

PD1

PD2

PD3

PD4

PD5

PD6

Port D

PD7

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15 -

AF8

UART4/5/

LPUART1/

CAN2

UART5_RX TSC_SYNC

AF9

CAN1/TSC

CAN1_RX

CAN1_TX

Table 17. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

OTG_FS/DCMI/

OCTOSPI_P1/P2

DCMI_D11

OCTOSPIM_P2_NCS

OCTOSPIM_P1_IO4

OCTOSPIM_P1_IO5

LCD

LCD_B4

LCD_B5

LCD_CLK

SDMMC/

COMP1/2/

FMC

FMC_D2

FMC_D3

SDMMC1_CM

FMC_CLK

FMC_NOE

FMC_NWE

SAI1/2

OCTOSPIM_P1_IO6

TSC_G6_IO1

TSC_G6_IO2

TSC_G6_IO3

TSC_G6_IO4

OCTOSPIM_P1_IO7

DCMI_HSYNC

DCMI_PIXCLK

LCD_DE

LCD_R3

LCD_R4

LCD_R5

LCD_R6

LCD_R7

LCD_B2

LCD_B3

AF14

TIM2/15/16/17/

LPTIM2

FMC_NWAIT SAI1_SD_A -

FMC_NCE/FM

C_NE1

FMC_D13

FMC_D14 SAI2_MCLK_A

FMC_D15

FMC_A16

SAI2_SCK_A

SAI2_SD_A

FMC_A17

FMC_A18

FMC_D0

FMC_D1

SAI2_FS_A

LPTIM2_ETR

LPTIM2_IN1

LPTIM2_OUT

AF15

EVENOUT

EVENTOUT

Port

Port E

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PE4

PE5

PE6

PE7

PE0

PE1

PE2

PE3

AF8

UART4/5/

LPUART1/

CAN2

AF9

Table 17. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12

CAN1/TSC

OTG_FS/DCMI/

OCTOSPI_P1/P2

LCD

SDMMC/

COMP1/2/

FMC

TSC_G7_IO1

TSC_G7_IO2

TSC_G7_IO3

TSC_G7_IO4

DCMI_D2

DCMI_D3

DCMI_D4

DCMI_D6

DCMI_D7

TSC_G5_IO1 OCTOSPIM_P1_CLK

TSC_G5_IO2 OCTOSPIM_P1_NCS

TSC_G5_IO3 OCTOSPIM_1_IO0

TSC_G5_IO4 OCTOSPIM_P1_IO1

OCTOSPIM_P1_IO2

OCTOSPIM_P1_IO3

LCD_HSYNC FMC_NBL0

LCD_VSYNC FMC_NBL1

LCD_R0

LCD_R1

FMC_A23

FMC_A19

LCD_B0

LCD_G0

LCD_G1

LCD_B6

FMC_A20

FMC_A21

FMC_A22

FMC_D4

LCD_B7

LCD_G2

LCD_G3

LCD_G4

LCD_G5

LCD_G6

LCD_G7

LCD_R2

FMC_D5

FMC_D6

FMC_D7

FMC_D8

FMC_D9

FMC_D10

FMC_D11

FMC_D12

AF13

SAI1/2

SAI1_MCLK_A

SAI1_SD_B

SAI1_FS_A

SAI1_SCK_A

SAI1_SD_A

SAI1_SD_B

SAI1_SCK_B

SAI1_FS_B

SAI1_MCLK_B

AF14

TIM2/15/16/17/

LPTIM2

TIM16_CH1

TIM17_CH1

AF15

EVENOUT

EVENTOUT

Port

Port F

PF8

PF9

PF10

PF11

PF12

PF13

PF14

PF15

PF4

PF5

PF6

PF7

PF0

PF1

PF2

PF3

AF8

UART4/5/

LPUART1/

CAN2

AF9

CAN1/TSC

Table 17. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

OTG_FS/DCMI/

OCTOSPI_P1/P2

LCD_DE

TSC_G8_IO1

TSC_G8_IO2

OCTOSPIM_P1_IO3

OCTOSPIM_P1_IO2

OCTOSPIM_P1_IO0

OCTOSPIM_P1_IO1

DCMI_D11

DCMI_D12

LCD

DSI_TE

LCD_B0

LCD_B1

LCD_G0

LCD_G1

SDMMC/

COMP1/2/

FMC

FMC_A6

FMC_A7

FMC_A8

FMC_A9

FMC_A0

FMC_A1

FMC_A2

FMC_A3

FMC_A4

FMC_A5

SAI1/2

SAI1_SD_B

SAI1_MCLK_B

SAI1_SCK_B

SAI1_FS_B

SAI1_D3

AF14

TIM2/15/16/17/

LPTIM2

TIM15_CH1

TIM15_CH2

AF15

EVENOUT

EVENTOUT

AF8 AF9

Port

Port G

UART4/5/

LPUART1/

CAN2

CAN1/TSC

PG0

PG1

PG2

PG3

PG4

PG5

PG6

LPUART1_CT

LPUART1_RT

S_DE

PG7 LPUART1_TX

PG8 LPUART1_RX

TSC_G8_IO3

TSC_G8_IO4

LCD_R1

Table 17. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

OTG_FS/DCMI/

OCTOSPI_P1/P2

LCD

DSI_TE

SDMMC/

COMP1/2/

FMC

FMC_A10

FMC_A11

FMC_A12

FMC_A13

FMC_A14

FMC_A15

SAI1/2

SAI2_SCK_B

SAI2_FS_B

SAI2_MCLK_B

SAI2_SD_B

PG9

PG10

PG11

PG12

PG13

PG14

PG15

DCMI_D13

LCD_R0

LCD_R1

AF14

TIM2/15/16/17/

LPTIM2

FMC_INT

FMC_NCE/FM

C_NE2

SAI1_MCLK_A

SAI2_SCK_A

TIM15_CH1N

FMC_NE3

FMC_NE4

FMC_A24

FMC_A25

SAI2_FS_A TIM15_CH1

SAI2_MCLK_A TIM15_CH2

SAI2_SD_A

AF15

EVENOUT

EVENTOUT

Port

Port H

PH8

PH9

PH10

PH11

PH12

PH13

PH14

PH15

PH4

PH5

PH6

PH7

PH0

PH1

PH2

PH3

AF8

UART4/5/

LPUART1/

CAN2

CAN1_TX

AF9

CAN1/TSC

Table 17. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

OTG_FS/DCMI/

OCTOSPI_P1/P2

DCMI_PIXCLK

DCMI_D8

DCMI_D9

DCMI_HSYNC

DCMI_D0

DCMI_D1

DCMI_D2

DCMI_D3

DCMI_D4

DCMI_D11

LCD

SDMMC/

COMP1/2/

FMC

SAI1/2

AF14 AF15

TIM2/15/16/17/

LPTIM2

EVENOUT

EVENTOUT

AF8 AF9

Port UART4/5/

LPUART1/

CAN2

CAN1/TSC

Port I

PI4

PI5

PI6

PI7

PI0

PI1

PI2

PI3

PI8

PI9

PI10

PI11

1. Refer to

Table 16

for AF0 to AF7.

CAN1_RX

Table 17. Alternate function AF8 to AF15 (1) (continued)

AF10 AF11 AF12 AF13

OTG_FS/DCMI/

OCTOSPI_P1/P2

DCMI_D13

DCMI_D8

DCMI_D9

DCMI_D10

DCMI_D5

DCMI_VSYNC

DCMI_D6

DCMI_D7

DCMI_D12

LCD

SDMMC/

COMP1/2/

FMC

SAI1/2

AF14 AF15

TIM2/15/16/17/

LPTIM2

EVENOUT

EVENTOUT

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Memory mapping

For memory map and peripheral register boundary addresses refer to the corresponding section of reference manual RM0432.

DS12024 Rev 4

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113

Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

6.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3 σ ).

Unless otherwise specified, typical data are based on T

A are given only as design guidelines and are not tested.

= 25 °C, V

= V

DDA

= 3 V. They

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2 σ )

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.5

The loading conditions used for pin parameter measurement are shown in

Figure 18

Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 19 .

Figure 18. Pin loading conditions Figure 19. Pin input voltage

MCU pin MCU pin

C = 50 pF

MS19210V1

MS19211V1

114/273

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6.1.6 Power supply scheme

Figure 20. Power supply scheme

Electrical characteristics

VBAT

1.55 – 3.6 V

DD n x VDD

Power switch

Regulator

DDIO1

OUT

Backup circuitry

(LSE, RTC,

Backup registers)

CORE n x 100 nF

+1 x 4.7 μF

GPIOs n x VSS m x100 nF

+4.7 μF

DDIO2 m x VDDIO2

GPIOs m x VSS

2.2 uF

VDDDSI

VCAPDSI

VDD12DSI

DDIO2

OUT

DSI

Voltage regulator

DSI PHY

IO logic

Kernel logic

(CPU, Digital

& Memories)

IO logic

10 nF

+1 μF

DDA

REF

VDDA

100 nF +1 μF

REF+

REF-

ADCs/

DACs/

OPAMPs/

COMPs/

VREFBUF

VSSA

MSv47745V1

Caution: Each power supply pair (V

, V

DDA

SSA

etc.) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

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248

Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Figure 21. Current consumption measurement

DD_USB

DDUSB

DD_VBAT

BAT

DDIO2

DDA

6.2

MSv47746V1

The I

DD_ALL

parameters given in

Table 25 to

including the current supplying V

, V

DDIO2

, V

DDA

, V

DDUSB

and V

BAT

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 18: Voltage characteristics

Table 19: Current characteristics

and

Table 20: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Symbol

DDX

- V

Table 18. Voltage characteristics (1)

Ratings Min

External main supply voltage (including V

DDA

, V

DDIO2

, V

DDUSB

, V

BAT

, V

REF+

)

-0.3

Max

4.0

Unit

(2)

Input voltage on FT_xxx pins

Input voltage on TT_xx pins

Input voltage on BOOT0 pin

Input voltage on any other pins

-0.3

min (V

DDIO2

, V

+ 4.0

, V

DDA

)

4.0

9.0

4.0

116/273

DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Electrical characteristics

Symbol

Table 18. Voltage characteristics (1) (continued)

Ratings Min Max

| ∆ V

SSx

DDx

-V

Variations between different V

DDX of the same domain

power pins

Variations between all the different ground pins

(5)

REF+

- V

DDA

Allowed voltage difference for V

REF+

> V

DDA

0.4

1. All main power (V , V

DDA

, V , V

DDUSB

, V

BAT

) and ground (V

, V

SSA

) pins must always be

Unit mV

2. V

maximum must always be respected. Refer to

Table 19: Current characteristics

for the maximum allowed injected current values.

3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.

4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

5. Include VREF- pin.

Table 19. Current characteristics

Symbol

∑

∑ IV

DD(PIN)

SS(PIN)

Ratings

Total current into sum of all V

power lines (source)

(1)

Total current out of sum of all V

ground lines (sink)

Maximum current into each V

power pin (source)

Maximum current out of each V

ground pin (sink)

Output current sunk by any I/O and control pin except FT_f

Max

200

100

IO(PIN)

Output current sunk by any FT_f pin 20

Output current sourced by any I/O and control pin 20

∑ I

IO(PIN)

Total output current sunk by sum of all I/Os and control pins

(2)

Total output current sourced by sum of all I/Os and control pins

Voltage characteristics

100

Injected current on FT_xxx, TT_xx, RST and B pins, except PA4, PA5 -5/+0

(4)

INJ(PIN)

(3)

Injected current on PA4, PA5

∑ |I

INJ(PIN)

| Total injected current (sum of all I/Os and control pins) (5)

-5/0

1. All main power (V , V

DDA

, V , V

DDUSB

, V

BAT

) and ground (V

, V

SSA

) pins must always be

Unit mA

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count

QFP packages.

3. Positive injection (when V

> V

DDIOx

) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

4. A negative injection is induced by V

< V

. I

INJ(PIN)

must never be exceeded. Refer also to

Table 18:

for the minimum allowed input voltage values.

5. When several inputs are submitted to a current injection, the maximum ∑ |I the negative injected currents (instantaneous values).

INJ(PIN)

| is the absolute sum of

DS12024 Rev 4

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248

Electrical characteristics

Symbol

STG

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Table 20. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

Unit

°C

6.3.1 General operating conditions

Symbol f

HCLK f

PCLK1 f

PCLK2

Table 21. General operating conditions

Parameter Conditions Min

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Standard operating voltage

1.71

(1)

Max

0 120

3.6

DDIO2

PG[15:2] I/Os supply voltage

DDA

BAT

DDUSB

USB supply voltage

Analog supply voltage

Backup operating voltage

I/O input voltage

At least one I/O in PG[15:2] used

PG[15:2] not used

ADC or COMP used

DAC or OPAMP used

VREFBUF used

ADC, DAC, OPAMP, COMP,

VREFBUF not used

USB used

USB not used

TT_xx I/O

BOOT0

1.08

1.62

1.8

2.4

1.55

3.0

-0.3

All I/O except BOOT0 and

TT_xx

-0.3

3.6

DDIOx

+0.3

MIN(MIN(V

DDA

LCD

, V

DDIO2

DDUSB

5.5 V)

)+3.6 V,

(2)(3)

Unit

MHz

118/273

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STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Electrical characteristics

Symbol

Table 21. General operating conditions (continued)

Parameter Conditions Min Max Unit

Power dissipation at

= 85 °C for suffix 6

Ambient temperature for the suffix 6 version

(4)

Ambient temperature for the suffix 3 version

= 125 °C for suffix 3

(see Section 7.7: Thermal

LQFP144

LQFP100

UFBGA169

UFBGA132

WLCSP144

LQFP144

LQFP100

UFBGA169

UFBGA132

WLCSP144 -

Maximum power dissipation –40

Low-power dissipation

(5)

–40

Maximum power dissipation –40

Low-power dissipation

(5)

–40

831

105

125

130

664

156

119

625

476

385

364 mW mW

°C

Junction temperature range

Suffix 6 version –40 105

°C

Suffix 3 version –40 130

1. When RESET is released functionality is guaranteed down to V

BOR0

Min.

2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between MIN(V

DDUSB

)+3.6 V and 5.5V.

, V

DDA

, V

DDIO2

3. For operation with voltage higher than Min (V

Pull-Down resistors must be disabled.

, V

DDA

, V

DDIO2

, V

DDUSB

) +0.3 V, the internal Pull-up and

4. If T

is lower, higher P

characteristics ).

values are allowed as long as T

does not exceed T

Jmax

5. In low-power dissipation state, T

can be extended to this range as long as T

Section 7.7: Thermal characteristics ).

does not exceed T

Jmax

(see

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248

Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

6.3.3

The parameters given in

Table 22 are derived from tests performed under the ambient

temperature condition summarized in

Table 23 are derived from tests performed under the ambient

Symbol t

VDD t

VDDA t

VDDUSB t

VDDIO2

Table 22. Operating conditions at power-up / power-down

Parameter Conditions Min Max

rise time rate

fall time rate

DDA

rise time rate

DDA

fall time rate

DDUSB

rise time rate

DDUSB

fall time rate

DDIO2

rise time rate

DDIO2

fall time rate

∞

Unit

µs/V

Embedded reset and power control block characteristics

The parameters given in

temperature conditions summarized in Table 21: General operating conditions

Table 23. Embedded reset and power control block characteristics

Symbol Parameter Conditions

(1)

Min Typ Max t

RSTTEMPO

(2)

Reset temporization after

BOR0 is detected

DD rising 250 400

BOR0

BOR1

BOR2

BOR3

BOR4

PVD0

PVD1

Brown-out reset threshold 0

Brown-out reset threshold 1

Brown-out reset threshold 2

Brown-out reset threshold 3

Brown-out reset threshold 4

Programmable voltage detector threshold 0

PVD threshold 1

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

2.56

2.47

2.85

2.76

2.1

2.26

2.15

1.62

1.6

2.06

1.96

2.26

2.16

2.61

2.52

2.90

2.81

2.15

2.05

2.31

2.20

1.66

1.64

2.1

2.31

2.20

2.66

2.57

2.95

2.86

2.19

2.1

2.36

2.25

1.7

1.69

2.14

2.04

2.35

2.24

Unit

μ s

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STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Electrical characteristics

Table 23. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions (1) Min Typ Max Unit

PVD2

PVD3

PVD4

PVD5

PVD6 hyst_BORH0

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

PVD threshold 6

Hysteresis voltage of BORH0

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Hysteresis in continuous mode

Hysteresis in other mode

V hyst_BOR_PVD

(BOR_PVD)

PVM1

Hysteresis voltage of BORH

(except BORH0) and PVD

BOR

(3)

(except BOR0) and

PVD consumption from V

DDUSB

peripheral voltage monitoring

PVM3

PVM4

V hyst_PVM3

V hyst_PVM4

(PVM1/PVM2)

DDA

peripheral voltage monitoring

PVM3 hysteresis

PVM4 hysteresis

PVM1 and PVM2 consumption from V

Rising edge

Falling edge

Rising edge

Falling edge

2.69

2.59

2.85

2.75

2.41

2.31

2.56

2.47

2.92

2.84

1.18

1.61

1.6

1.78

1.77

100

1.1

1.22

1.65

1.64

1.82

1.81

2.74

2.64

2.91

2.81

2.46

2.36

2.61

2.52

2.98

2.90

0.2

1.69

1.68

1.86

1.85

2.79

2.69

2.96

2.86

2.51

2.41

2.66

2.57

3.04

2.96

1.6

1.26

V mV mV

µA

V mV mV

µA

(PVM3/PVM4)

Table 24 are derived from tests performed under the ambient

PVM3 and PVM4 consumption from V

2 µA

1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

2. Guaranteed by design.

3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current characteristics tables.

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248

Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

The parameters given in

temperature and supply voltage conditions summarized in Table 21: General operating conditions

Symbol

Table 24. Embedded internal voltage reference

Parameter Conditions Min Typ Max Unit t t

REFINT

S_vrefint

(1) start_vrefint

Internal reference voltage

ADC sampling time when reading the internal reference voltage

Start time of reference voltage buffer when

ADC is enable

–40 °C < T

< +130 °C 1.182 1.212 1.232

(2)

8 12

REFINTBUF

)

∆ V

REFINT

Coeff

REFINT

buffer consumption from V

DD when converted by

ADC

Internal reference voltage spread over the temperature range

Average temperature coefficient

= 3 V

–40°C < T

< +130°C -

12.5

7.5

Figure 21: Current consumption measurement .

Coeff

Long term stability 1000 hours, T = 25°C 300

1000

)

1200

)

µs

µA mV ppm/°C ppm ppm/V V

DDCoeff

Average voltage coefficient

3.0 V < V

< 3.6 V 250

REFINT_DIV1

REFINT_DIV2

REFINT_DIV3

1/4 reference voltage

1/2 reference voltage

3/4 reference voltage

1. The shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design.

REFINT

122/273

DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Electrical characteristics

Figure 22. V

REFINT

versus temperature

1.235

1.23

1.225

1.22

1.215

1.21

1.205

1.2

1.195

1.19

1.185

-40 -20 0 20

Mean

Min

Max

80 100 120 °C

MSv40169V2

DS12024 Rev 4

123/273

248

Electrical characteristics

6.3.5 Supply current characteristics

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code

The current consumption is measured as described in

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in analog input mode

• All peripherals are disabled except when explicitly mentioned

• The Flash memory access time is adjusted with the minimum wait states number, depending on the f

HCLK

frequency (refer to the table “Number of wait states according to CPU clock (HCLK) frequency” available in the RM0432 reference manual).

• When the peripherals are enabled f

PCLK

= f

HCLK

• The voltage scaling Range 1 is adjusted to f

HCLK

frequency as follows:

– Voltage Range 1 Boost mode for 80 MHz < f

HCLK

<= 120 MHz

– Voltage Range 1 Normal mode for 26 MHz < f

HCLK

<= 80 MHz

The parameters given in

Table 25 to

Table 32 are derived from tests performed under

ambient temperature and supply voltage conditions summarized in

Table 21: General operating conditions

124/273

DS12024 Rev 4

Symbol Parameter

Table 25. Current consumption in Run and Low-power run modes, code with data processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF)

Conditions TYP MAX

(1) f

HCLK

Voltage scaling

25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Unit

I DD (Run)

I DD

(LPRun)

Range 2

26 MHz 3.40

3.80

4.90

16 MHz 2.20

2.55

3.70

8 MHz 1.25

1.60

2.70

4 MHz 0.740

1.10

2.20

6.55

5.30

4.30

3.80

9.45

8.20

7.20

6.70

Supply current in

Run mode

Supply current in

Low-power run mode f HCLK = f HSE up to 48 MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

2 MHz 0.495 0.860

1.95

1 MHz 0.370 0.740

1.85

100 KHz 0.265 0.630

1.75

Range 1

Boost Mode

120 MHz 18.5

19.5

21.0

80 MHz 11.5

12.0

13.5

72 MHz 10.5

11.0

12.5

64 MHz 9.25

9.75

11.0

Range 1

Normal

Mode

48 MHz 7.35

7.85

9.30

32 MHz 5.00

5.50

6.95

f HCLK = f MSI all peripherals disable

15.5

14.5

13.5

6.45

6.35

6.25

19.0

18.0

17.0

24 MHz 3.85

4.35

5.75

16 MHz 2.65

3.15

4.55

2 MHz

1 MHz

490

305

910

770

2200

2050

11.5

8.95

7.75

6.55

4050

3900

15.0

12.5

11.5

10.0

7250

7100

400 KHz 250

100 KHz 210

3.55

3.45

3.35

23.0

27.0

695 2000 3800 7000

645 1950 3750 7000

1. Guaranteed by characterization results, unless otherwise specified.

21.0

13.0

12.0

11.0

8.3

5.7

4.4

3.1

690

490

430

380

0.7

0.6

0.4

3.9

2.6

1.6

1.0

1.5

1.4

1.2

4.8

3.4

2.3

1.8

23.0

3.5

3.4

3.2

6.8

5.4

4.3

3.8

26.0

11.0

8.7

7.6

7.1

6.8

6.6

6.5

30.0

14.0

13.0

12.0

9.3

6.7

5.4

4.1

17.0

16.0

14.0

12.0

9.2

7.9

6.6

21.0

20.0

18.0

16.0

14.0

12.0

11.0

1600 4000 7700 14000

1500 3900 7500 14000

1400 3800 7500 14000

1400 3700 7400 14000

28.0

27.0

26.0

23.0

21.0

19.0

18.0

17.0

15.0

14.0

13.0

38.0

µA

Symbol Parameter

Table 26. Current consumption in Run and Low-power run modes, code with data processing running from Flash in dual bank, ART enable (Cache ON Prefetch OFF)

Conditions TYP MAX

(1) f

HCLK

Voltage scaling

25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Unit

Range 2

26 MHz 3.60

3.95

5.05

6.65

9.55

16 MHz 2.30

2.65

3.75

5.35

8.20

8 MHz 1.30

1.65

2.70

4.30

7.15

4 MHz 0.770

1.10

2.20

3.75

6.60

2 MHz 0.515

0.865

1.95

3.50

6.35

1 MHz 0.380

0.735

1.80

3.35

6.20

100 KHz 0.265

0.620

1.70

3.25

6.10

0.7

0.6

0.4

4.2

2.7

1.6

1.0

1.5

1.4

1.2

5.0

3.6

2.4

1.8

3.5

3.4

3.2

7.1

5.6

4.4

3.8

11.0

17.0

8.9

15.0

7.7

7.1

14.0

6.8

6.7

6.5

13.0

I DD

(Run)

Supply current in

Run mode f HCLK = f HSE up to 48MHz included, bypass mode

PLL ON above 48

MHz all peripherals disable

Range 1

Boost Mode

120 MHz 17.0

18.0

19.5

21.5

25.5

19.0

21.0

24.0

28.0

36.0

I DD

(LPRun)

Supply current in

Low-power run mode f HCLK = f MSI

Range 1

Normal

Mode all peripherals disable

80 MHz 12.5

13.0

14.0

16.0

19.5

14.0

15.0

18.0

22.0

29.0

72 MHz 11.0

11.5

13.0

15.0

18.5

13.0

14.0

17.0

21.0

28.0

64 MHz 9.90

10.5

12.0

14.0

17.5

12.0

13.0

15.0

19.0

26.0

48 MHz 7.85

8.30

9.75

11.5

15.0

32 MHz 5.35

5.80

7.20

9.20

12.5

24 MHz 4.10

4.55

5.95

7.90

11.5

16 MHz 2.80

3.30

4.65

6.60

10.0

8.7

6.1

4.7

3.3

9.9

7.1

5.7

4.3

13.0

17.0

24.0

9.6

8.2

6.8

14.0

13.0

11.0

21.0

20.0

18.0

2 MHz

1 MHz

460

355

400 KHz 240

100 KHz 200

905 2150 3950 7100 660 1700 4100 7700 15000

760 2000 3800 6950 540 1500 3900 7600 14000

685 1950 3700 6850 410 1400 3800 7500 14000

635 1900 3650 6800 370 1400 3700 7500 14000

1. Guaranteed by characterization results, unless otherwise specified.

µA

Symbol Parameter

Table 27. Current consumption in Run and Low-power run modes, code with data processing running from Flash in single bank, ART disable

Conditions TYP f

HCLK

Voltage scaling

MAX

(1)

25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Unit

Range 2

26 MHz 4.00

4.40

5.55

16 MHz 2.65

3.05

4.15

8 MHz 1.50

1.85

2.90

4 MHz 0.875

1.25

2.35

2 MHz 0.565

0.925

2.05

1 MHz 0.405

0.770

1.90

100 KHz 0.265

0.635

1.75

7.20

5.80

4.45

3.95

3.65

3.50

3.35

10.0

8.75

7.25

6.90

6.55

6.40

6.25

4.60

3.10

1.80

1.20

0.77

0.60

0.44

1.6

1.4

1.2

5.5

4.0

2.6

1.9

3.6

3.4

3.2

7.5

6.0

4.6

3.9

11.0

9.3

7.9

7.2

6.8

6.7

6.5

I DD (Run)

Supply current in

Run mode f HCLK = f HSE up to 48MHz included, bypass mode

PLL ON above 48

MHz all peripherals disable

Range 1

Boost Mode

120 MHz 18.5

19.5

21.0

23.5

27.0

21.00

23.0

26.0

30.0

38.0

I DD

(LPRun)

Supply current in

Low-power run mode

Range 1

Normal

Mode f HCLK = f MSI all peripherals disable

80 MHz 13.0

13.5

15.5

72 MHz 12.0

12.5

14.0

64 MHz 10.5

11.0

12.5

48 MHz 8.75

9.30

11.0

32 MHz 6.20

6.70

8.20

24 MHz 4.70

5.20

6.70

16 MHz 3.35

3.85

5.25

17.5

16.0

15.0

13.0

10.0

10.5

7.30

21.0

15.00

17.0

20.0

14.00

15.0

18.5

12.00

14.0

16.5

14.0

12.5

11.0

9.80

7.00

5.40

3.90

12.0

8.2

6.5

4.9

19.0

18.0

16.0

14.0

11.0

9.0

7.4

23.0

22.0

20.0

18.0

15.0

13.0

12.0

2 MHz

1 MHz

595 1000 2300 4150 7350 810.00

1700 4100 7800 15000

370 800 2100 3950 7150 560.00

1500 3900 7600 14000

400 KHz 245

100 KHz 230

705

655

2000

1950

3850

3800

7050

7000

420.00

400.00

1400

3800

3700

7500

7400

14000

30.0

29.0

28.0

25.0

22.0

20.0

19.0

1. Guaranteed by characterization results, unless otherwise specified.

17.0

16.0

14.0

13.0

µA

Symbol Parameter

Table 28. Current consumption in Run and Low-power run modes, code with data processing running from Flash in dual bank, ART disable

Conditions TYP f

HCLK

Voltage scaling

MAX

(1)

25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Unit

Range 2

26 MHz 4.10

4.50

5.60

16 MHz 2.75

3.10

4.25

8 MHz

4 MHz

1.25

0.91

1.90

1.25

2.95

2.35

2 MHz

1 MHz

0.59

0.42

0.94

0.77

2.00

1.85

100 KHz 0.27

0.63

1.70

7.20

10.00

5.85

8.70

4.55

3.90

7.35

6.75

3.60

3.40

3.25

6.40

6.25

6.10

0.8

0.6

0.4

4.7

3.2

1.7

1.2

5.6

4.1

2.7

2.0

1.6

1.4

1.2

3.6

3.4

3.2

7.6

6.1

4.7

4.0

11.0

9.4

8.0

7.3

6.9

6.7

6.5

I DD

(Run)

Supply current in

Run mode f HCLK = f HSE up to

48MHz included, bypass mode PLL

ON above

48 MHz all peripherals disable

Range 1

Boost

Mode

120 MHz 17.00 18.00 19.50

21.50

25.50

19.0

21.0

24.0

28.0

36.0

I DD

(LPRun)

Supply current in

Low-power run mode

Range 1

Normal

Mode f HCLK = f MSI all peripherals disable

80 MHz 13.00 13.50 15.00

17.00

20.50

15.0

72 MHz 11.50

12.00 14.00

16.00

19.50

13.0

64 MHz 10.50

11.00

12.50

14.50

18.00

12.0

48 MHz 9.00

9.50

11.00

13.00

16.50

11.0

16.0

15.0

13.0

12.0

19.0

18.0

16.0

15.0

23.0

22.0

20.0

19.0

30.0

29.0

27.0

26.0

32 MHz 6.45

6.95

8.40

10.50

14.00

24 MHz 4.90

5.40

6.85

8.80

12.50

7.3

5.6

8.5

6.7

12.0

9.3

16.0

14.0

23.0

21.0

16 MHz 3.55

4.00

5.40

2 MHz 590 1000 2300

7.40

4050

11.00

7200

4.1

800.0

5.2

1800

7.7

4200

12.0

7800

19.0

15000

1 MHz 390

400 KHz 245

100 KHz 195

805 2100 3850 7000 580.0

1600 4000 7600 14000

655 1950 3750 6900 420.0

1400 3800 7500 14000

610 1900 3700 6850 370.0

1400 3700 7500 14000

1. Guaranteed by characterization results, unless otherwise specified.

17.0

16.0

14.0

13.0

µA

Symbol Parameter

Table 29. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1

Conditions TYP f

HCLK

Voltage scaling

MAX

(1)

25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Unit

Range 2

26 MHz 3.35

3.75

4.85

6.45

9.30

4.70

16 MHz 2.20

2.55

3.65

5.20

8.10

3.20

8 MHz

4 MHz

1.20

0.74

1.55

1.10

2.65

2.15

4.25

3.75

7.10

6.60

1.70

1.20

2 MHz

1 MHz

0.49

0.37

0.85

0.73

1.95

1.80

3.50

3.40

6.35

6.20

0.79

0.61

100 KHz 0.26

0.62

1.70

3.25

6.10

0.44

1.6

1.4

1.2

5.6

4.1

2.7

2.0

7.6

6.1

4.7

4.0

3.6

3.4

3.2

11.0

17.0

9.4

16.0

8.0

7.3

14.0

6.9

6.7

6.5

13.0

I DD (Run)

Supply current in

Run mode f HCLK = f HSE up to 48MHz included, bypass mode

PLL ON above 48

MHz all peripherals disable

Range 1

Boost Mode

120 MHz 18.00 18.50 20.00

22.50

26.50

19.00

21.0

24.0

28.0

36.0

(2)

I DD

(LPRun)

Supply current in

Low-power run mode f HCLK = f MSI

Range 1

Normal

Mode all peripherals disable

FLASH in power-down

80 MHz 11.00

11.50 13.50

15.50

19.00

15.00

16.0

19.0

23.0

30.0

72 MHz 10.00 10.50 12.00

14.00

18.00

13.00

15.0

18.0

22.0

29.0

64 MHz 9.10

9.60

11.00

13.00

16.50

12.00

13.0

16.0

20.0

27.0

48 MHz 7.20

7.70

9.20

11.00

14.50

11.00

12.0

15.0

19.0

26.0

32 MHz 4.90

5.40

6.85

8.80

12.50

7.30

8.5

12.0

16.0

23.0

24 MHz 3.75

4.25

5.65

7.65

11.00

5.60

16 MHz 2.60

3.10

4.50

6.45

9.90

4.10

6.7

5.2

9.3

7.7

14.0

12.0

21.0

19.0

2 MHz

1 MHz

435

300

400 KHz 225

100 KHz 180

885 2150 3950 7100 800 1800 4200 7800 15000

745 2000 3800 6950 580 1600 4000 7600 14000

655 1900 3700 6850 420 1400 3800 7500 14000

620 1900 3650 6800 370 1400 3700 7500 14000

1. Guaranteed by characterization results, unless otherwise specified.

2. Guaranteed by test in production.

µA

Symbol Parameter

Table 30. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF)

Conditions

Code

TYP

Single Bank

Mode

TYP

Dual Bank

Mode

Unit

TYP

Single Bank

Mode

TYP

Dual Bank

Mode

Voltage scaling

25°C 25°C 25°C 25°C

(Run)

Supply current in

Run mode f HCLK =f HSE to 48 MHZ included,

up bypass mode

PLL ON above

48 MHz all peripherals disable f

Range2

HCLK =26MHz

Range 1

Normal Mode f HCLK = 80

MHz

Range 1

Boost Mode f HCLK = 120

MHz

Reduced code

(1)

Coremark

Dhrystone2.1

Fibonacci

Reduced code

Coremark

Dhrystone2.1

Fibonacci

Reduced code

Coremark

Dhrystone2.1

Fibonacci

3.40

3.90

4.25

3.65

3.15

11.5

13.5

14.5

12.5

10.5

18.5

21.5

22.5

20.0

16.5

3.60

3.95

4.30

3.90

3.15

12.5

13.5

14.5

14.0

10.5

17.0

21.5

22.5

21.0

16.5

mA mA mA

131

150

163

140

121

144

154

179

188

167

138

169

181

156

131

138

179

188

175

138

169

181

175

131

152

165

150

121

156

142

Unit

µA/MHz

Symbol Parameter

Table 30. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) (continued)

Conditions

Code

TYP

Single Bank

Mode

TYP

Dual Bank

Mode

Unit

TYP

Single Bank

Mode

TYP

Dual Bank

Mode

Voltage scaling

25°C 25°C 25°C 25°C

I DD

(LPRun)

Supply current in

Low-power run f HCLK = f MSI = 2MHz all pripherals disable

Reduced code

Coremark

Dhrystone2.1

Fibonacci

1. Reduced code used for characterization results provided in

Table 25

Table 27 ,

Table 29 .

490

520

530

470

455

460

515

530

495

515

µA

245

260

265

235

228

230

258

265

248

258

Unit

µA/MHz

Symbol Parameter

Table 31. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART disable

Conditions

Code

TYP

Single Bank

Mode

TYP

Dual Bank

Mode

Unit

TYP

Single Bank

Mode

Voltage scaling

25°C

(Run)

(LPRun)

Supply current in

Run mode

Supply current in

Low-power run f HCLK =f HSE up to 48 MHZ included, bypass mode

PLL ON above 48 MHz all peripherals disable f

Range2

HCLK

MHz

=26

Range 1

Normal

Mode f HCLK =

80 MHz

Range 1

Boost

Mode f HCLK =

120 MHz f HCLK = f MSI = 2MHz all pripherals disable

Reduced code

Coremark

Dhrystone2.1

Fibonacci

Reduced code

Coremark

Dhrystone2.1

Fibonacci

Reduced code

Coremark

Dhrystone2.1

Fibonacci

Reduced code

Coremark

Dhrystone2.1

Fibonacci

1. Reduced code used for characterization results provided in

Table 25

, Table 27 ,

Table 29 .

18.0

19.0

16.0

16.5

14.0

11.5

10.5

18.5

595

620

645

670

470

4.00

4.15

4.40

3.80

3.15

13.0

25°C

16.0

16.5

15.0

16.5

12.5

11.0

10.5

17.0

590

580

655

580

685

4.10

3.80

4.00

3.60

3.15

13.0

12.0

mA mA mA

µA

25°C

150

158

133

138

175

144

131

154

298

310

323

335

235

154

160

169

146

121.2

163

TYP

Dual Bank

Mode

25°C

133

138

125

138

156

138

131

142

295

290

328

290

343

158

146

154

138

121.2

163

150

Unit

µA/MHz

Symbol

DD (Run)

I DD (LPRun)

Table 32. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1

Conditions TYP TYP

Parameter Code Unit

Voltage scaling

25°C 25°C

Supply current in

Run mode

Supply current in

Low-power run f HCLK =f HSE up to 48

MHZ included, bypass mode PLL ON above 48

MHz all peripherals disable f

Range2

HCLK

MHz

=26

Range 1

Normal

Mode f HCLK = 80

MHz

Range 1

Boost

Mode f HCLK = 120

MHz f HCLK = f MSI = 2MHz all pripherals disable

Reduced code

(1)

Coremark

Dhrystone2.1

Fibonacci

Reduced code

Coremark

Dhrystone2.1

Fibonacci

Reduced code

Coremark

Dhrystone2.1

Fibonacci

Reduced code

Coremark

Dhrystone2.1

Fibonacci

16.5

19.5

17.5

15.0

12.5

10.5

9.40

18.0

435

395

470

425

455

3.35

3.10

3.65

3.20

2.85

11.0

10.5

mA mA mA

µA

138

163

146

125

156

131

118

150

218

198

235

213

228

129

119

140

123

110

138

131

1. Reduced code used for characterization results provided in

Table 25

, Table 27 ,

Table 29 .

Unit

µA/MHz

Symbol Parameter

Table 33. Current consumption in Sleep and Low-power sleep mode, Flash ON

Conditions TYP f

HCLK

Voltage scaling

MAX

(1)

25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Un it

Range 2

26 MHz 1.10

16 MHz 0.78

8 MHz

4 MHz

0.52

0.38

2 MHz

1 MHz

0.32

0.29

100 KHz 0.26

IDD

(Sleep)

IDD

(LPSleep)

Supply current in

Sleep mode fHCLK = fHSE up to 48MHz included, bypass mode

PLL ON above

48 MHz all peripherals disable

Range 1

Boost

Mode

Supply current in

Low-power sleep mode fHCLK = fMSI

Range 1

Normal

Mode all peripherals disable

120 MHz 4.20

80 MHz 2.80

72 MHz 2.55

64 MHz 2.30

48 MHz 2.15

32 MHz 1.55

24 MHz 1.25

16 MHz 0.93

2 MHz 235

1 MHz 220

400 KHz 215

100 KHz 210

1. Guaranteed by characterization results, unless otherwise specified.

1.45

1.15

0.87

0.74

0.63

0.61

0.58

4.70

2.00

1.70

1.40

625

3.25

3.00

2.75

2.60

605

595

2.55

2.25

1.95

1.85

1.75

1.70

6.25

4.15

3.80

3.55

3.40

3.35

3.30

3.25

7.00

6.65

6.35

6.25

6.15

6.10

8.40

12.00

4.80

4.65

4.40

4.20

4.00

6.60

10.00

3.30

6.40

9.85

3.00

6.15

6.00

9.60

9.45

2.70

2.60

3.40

3.10

5.35

5.05

8.80

8.50

2.80

4.70

8.20

1950 3750 6900

1.90

1.60

1.20

410

1900 3700 6850

1900 3700 6800

390

380

1.40

1.00

0.72

0.57

0.50

0.46

0.43

1.3

1.2

2.2

1.8

1.5

1.4

6.0

3.3

3.2

4.2

3.8

3.5

3.4

8.7

6.6

6.5

7.5

7.1

6.8

6.7

13.0

14.0

13.0

21.0

4.3

4.0

3.8

3.5

6.8

6.5

6.3

6.0

11.0

10.0

18.0

2.9

2.5

5.4

5.0

9.3

9.0

17.0

16.0

2.2

4.7

8.6

16.0

1400 3800 7500 14000

1400 3700 7500 14000

1300 3700 7500 14000

µA

Symbol Parameter

Table 34. Current consumption in Low-power sleep mode, Flash in power-down

Conditions TYP MAX

(1) f

HCLK

Voltage scaling

25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

I DD

(LPSleep)

Supply current in

Low-power sleep mode f HCLK = f MSI all peripherals disable

2 MHz 255 645 1950 3700 6850 430 1400 3700 7400 14000

1 MHz 195 620 1900 3700 6850 370 1300 3700 7400 14000

400 KHz 180 600 1900 3700 6800 350 1300 3700 7400 14000

100 KHz 175 595 1900 3650 6800 340 1300 3700 7400 14000

1. Guaranteed by characterization results, unless otherwise specified.

Unit

µA

Table 35. Current consumption in Stop 2 mode, SRAM3 disabled

Conditions TYP MAX

(1)

Symbol Parameter

DD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

I DD

(Stop 2)

I DD (Stop 2 with RTC)

Supply current in

Stop 2 mode,

RTC disabled

Supply current in

STOP 2 mode,

RTC enabled

RTC clocked by LSI

RTC clocked by LSE bypassed at 32768 Hz

RTC clocked by LSE quartz in low drive mode

1.8 V 2.50

2.4 V 2.50

3 V 2.55

3.6 V 2.60

1.8 V 2.75

2.4 V 2.90

3 V 3.05

3.6 V 3.20

1.8 V 2.95

2.4 V 3.05

3 V 3.25

3.6 V 3.55

1.8 V 2.80

2.4 V 2.90

3 V 3.05

3.6 V 3.15

9.30

9.45

9.65

9.95

9.65

9.85

10.0

10.5

9.45

9.60

9.85

10.0

9.10

9.20

9.30

9.50

36.0

36.5

37.0

38.0

37.0

37.5

38.0

39.0

36.5

37.0

38.0

38.5

36.5

37.0

37.5

38.0

84.5

85.5

87.0

89.0

84.5

86.0

87.5

90.0

84.5

85.5

87.0

89.5

84.0

85.0

87.0

89.0

185

190

195

185

190

195

185

190

195

7.60

7.70

7.90

8.00

7.80

7.90

8.10

8.50

8.30

8.50

8.60

9.00

7.70

8.00

8.30

24.0

25.0

27.0

31.0

32.0

33.0

30.0

31.0

32.0

I DD (wakeu p from

Stop 2)

Supply current during wakeup from

Stop 2 mode

Wakeup clock is MSI = 48

MHz, voltage Range 1

(2)

Wakeup clock is MSI = 4

MHz, voltage Range 2

Wakeup clock is HSI = 16

MHz, voltage Range 1

2. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 43: Low-power mode wakeup timings .

3 V

3.55

1.25

2.90

1. Guaranteed by characterization results, unless otherwise specified.

90.0

92.0

93.0

95.0

93.0

94.0

95.0

98.0

120

130

120

130

220

230

220

230

270

280

270

280

470

480

490

580

590

600

610

580

590

600

610

Unit

µA mA

Symbol Parameter

Table 36. Current consumption in Stop 2 mode, SRAM3 enabled

Conditions TYP

MAX

(1)

DD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Unit

I DD

(Stop 2)

(Stop 2 with RTC)

Supply current in Stop 2 mode,

RTC disabled

RTC clocked by LSI

Supply current in STOP 2 mode,

RTC enabled

RTC clocked by LSE bypassed at 32768 Hz

RTC clocked by LSE quartz in low drive mode

1.8 V 3.90

15.0

2.4 V 3.95

15.0

3 V 3.95

15.0

3.6 V 3.95

15.0

1.8 V 4.10

15.0

2.4 V 4.25

15.5

3 V 4.50

15.5

3.6 V 4.70

16.0

1.8 V 4.35

15.5

2.4 V 4.50

15.5

3 V 4.70

16.0

3.6 V 4.80

16.5

1.8 V 4.30

15.5

2.4 V 4.40

16.0

3 V 4.45

16.0

3.6 V 4.85

16.5

63.5

64.0

64.5

65.5

61.0

62.0

63.0

60.5

61.5

62.5

59.5

60.0

60.5

61.5

150

155

140

145

140

145

140

145

310

315

320

325

310

315

320

325

310

315

320

9.40

9.50

9.60

11.0

9.50

9.60

9.90

10.0

11.0

12.0

13.0

14.0

39.0

40.0

42.0

39.0

40.0

42.0

53.0

54.0

56.0

52.0

53.0

54.0

I DD (wakeup from Stop 2)

Supply current during wakeup from Stop 2 mode

Wakeup clock is MSI = 48

MHz, voltage Range 1

(3)

Wakeup clock is MSI = 4

MHz, voltage Range 2

Wakeup clock is HSI = 16

MHz, voltage Range 1

3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 43: Low-power mode wakeup timings .

3 V 3.80

3 V 1.30

3 V 2.95

1. Guaranteed by characterization results, unless otherwise specified.

2. Guaranteed by test in production.

160

170

160

210

220

210

380

390

350

370

480

490

1100

480

1100

480 1100

490 1100

(2)

780

790

800

820

µA mA

Symbol Parameter

Conditions

Table 37. Current consumption in Stop 1 mode

TYP MAX

(1)

V DD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C -

(Stop 1)

(Stop 1 with

RTC)

Supply current in Stop 1 mode,

RTC disabled

Supply current in STOP 1 mode,

RTC enabled

RTC clocked by LSI

RTC clocked by LSE bypassed at 32768 Hz

RTC clocked by LSE quartz

(3)

in low drive mode

3.6 V

1.8 V

2.4 V

3 V

3.6 V

1.8 V

2.4 V

3 V

3.6 V

1.8 V

2.4 V

3 V

3.6 V

1.8 V

2.4 V

3 V

125

120

125

120

125

120

125

120

125

435

420

425

435

430

435

430

1400

1350

1400

2750

2700

2750

2700

2750

5150

5050

5100

5150

5050

5100

5150

5050

5100

320

300

280

300

320

280

1100

I DD

(wakeup from

Stop 1)

Supply current during wakeup from

Stop 1 mode

Wakeup clock is MSI = 48

MHz, voltage Range 1

(4)

Wakeup clock is MSI = 4

MHz, voltage Range 2

Wakeup clock is HSI = 16

MHz, voltage Range 1

4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 43: Low-power mode wakeup timings

3 V

2.10

0.70

1.50

1. Guaranteed by characterization results, unless otherwise specified.

2. Guaranteed by test in production.

3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

3300

3500

3400

3300

6600

6900

6800

6500 13000

6600 13000

(2)

6500

6600

13000

Unit

µA mA

Symbol

I DD (Stop 0)

Parameter

Supply current in Stop 0 mode,

RTC disabled

Conditions

Table 38. Current consumption in Stop 0 mode

TYP

MAX

(1)

DD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 V

2.4 V

3 V

3.6 V

290

295

735

740

2050

3800

3850

6950

7000

560

570

1600

4500

8700 16000

8700 17000

8800 17000

8800

17000

(2)

1. Guaranteed by characterization results, unless otherwise specified.

2. Guaranteed by test in production.

Unit

µA

Symbol

I DD

(Standby)

Parameter

Supply current in Standby mode (backup registers retained),

RTC disabled

Table 39. Current consumption in Standby mode

Conditions TYP

No independent watchdog

With independent watchdog

MAX

(1)

DD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 V 125

2.4 V 135

3 V 150

3.6 V 190

1.8 V 295

2.4 V 355

3 V 420

3.6 V 510 -

380 1900 5200 13500 340 1100 5300 15000 41000

440 2200 6050 15500 350 1300 6100 18000 47000

535 2700 7500 19500 370 1500 7100 21000 54000

665 3200 8850 23000 400 1900 8400 24000 62000

Unit nA

Symbol Parameter

Table 39. Current consumption in Standby mode (continued)

Conditions TYP

MAX

(1)

DD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

RTC clocked by LSI, no independent watchdog

1.8 V 370

2.4 V 455

640 2100 5300 13500 1100 1400 6400 16000 41000

760 2500 6250 15500 1200 1700 6800 18000 47000

3 V

3.6 V

560

690

930 3050 7650 19000 1300 1900 8100 21000 55000

1150 3700 9200 23000 1400 2400 9000 24000

62000

(2)

I DD

(Standby with

RTC)

(SRAM2) (4)

Supply current in Standby mode (backup registers retained),

RTC enabled

Supply current to be added in

Standby mode when SRAM2 is retained

RTC clocked by LSI, with independent watchdog

RTC clocked by LSE bypassed at

32768 Hz

RTC clocked by LSE quartz

(3)

in low drive mode

1.8 V 420

2.4 V 525

3 V 645 -

3.6 V 795

1.8 V 480

750 2200 5400 13500

2.4 V 615

3 V 770

930

1150

2650

3250

6400

7900

15500

19500

3.6 V 975 1450 3950 9500 23000

1.8 V 420 685 2150 5400 13500

2.4 V 520

3 V 650

830

1000

2550

3100

6400

7800

15500

19500

3.6 V 825 1300 3800 9400 23000

1.8 V 380 1420 5600 13300 28500

2.4 V 380 1410 5650 12950 29000

3 V 385 1415 5600 13000 28500

3.6 V 400 1435 5700 13150 29000

Unit nA nA nA

Symbol Parameter

Table 39. Current consumption in Standby mode (continued)

Conditions TYP

MAX

(1)

DD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

( wakeup from Standby)

Supply current during wakeup from Standby mode

Wakeup clock is MSI = 4

MHz

(5)

3 V 2.0

1. Guaranteed by characterization results, unless otherwise specified.

2. Guaranteed by test in production.

3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

4. The supply current in Standby with SRAM2 mode is:

I I

DD_ALL (Standby + RTC) + I

DD_ALL (SRAM2).

DD_ALL (Standby) + I

DD_ALL (SRAM2). The supply current in Standby with RTC with SRAM2 mode is:

5. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 43: Low-power mode wakeup timings .

Unit mA

Symbol

I DD

(Shutdown)

Parameter

Supply current in Shutdown mode (backup registers retained) RTC disabled

Table 40. Current consumption in Shutdown mode

Conditions TYP

DD 25°C

1.8 V

2.4 V

3 V

33.0

43.0

60.0

3.6 V 92.0

55°C

205

250

320

430

MAX

(1)

85°C 105°C 125°C 25°C 55°C

1250

1450

1850

3650

4300

5450

10500

12000

15500

150

170

190

620

740

920

2300 6700 18500 270

85°C 105°C 125°C

3800 12000 35000

4400 14000 39000

5200 16000 45000

1200 6200 19000 51000

Unit nA

Symbol Parameter

Table 40. Current consumption in Shutdown mode (continued)

Conditions TYP

DD 25°C 55°C 85°C 105°C 125°C 25°C 55°C

MAX

(1)

I DD

(Shutdown with

RTC)

DD (wakeup from

Shutdown)

Supply current in Shutdown mode (backup registers retained) RTC enabled

Supply current during wakeup from Shutdown mode

RTC clocked by

LSE bypassed at 32768

RTC clocked by

LSE quartz

(2)

in low drive mode

Wakeup clock is

MSI = 4

MHz

(3)

1.8 V

2.4 V

3 V

3.6 V

1.8 V

2.4 V

3 V

3.6 V

3 V

245

340

465

615

335

435

560

730

0.5

420

555

730

945

520

650

830

1050

1450

1750

2250

2850

1550

1850

2350

2950

3850

4600

5900

7250

4000

4750

6050

7400

10500

12500

15500

19000

85°C 105°C 125°C

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 43: Low-power mode wakeup timings .

Unit nA mA

Symbol Parameter

Table 41. Current consumption in VBAT mode

Conditions TYP

MAX

(1)

BAT 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

IDD(VBAT)

Backup domain supply current

RTC disabled

RTC enabled and clocked by

LSE bypassed at

32768 Hz

1.8 V

2.4 V

3 V

3.6 V

1.8 V

2.4 V

3 V

3.6 V

3.00

4.00

6.00

14.0

215

305

415

540

27.0

31.0

43.0

83.0

240

340

455

595

165

190

255

485

390

510

680

925

495

560

750

1450

730

900

1200

1900

1350

1550

2000

4050

8.0

10.0

13.0

34.0

67.0

76.0

91.0

200

RTC enabled and clocked by

LSE quartz

(2)

1.8 V

2.4 V

3 V

3.6 V

305

395

510

650

345

440

565

740

510

625

805

1200

865

1050

1350

2200

1600

1800

2300

4450

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

390

440

510

1100

1200

1300

1500

3100

3000

3300

3800

8300

Unit nA

Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

Table 66: I/O static characteristics

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see

Table 43: Low-power mode wakeup timings ), the I/Os used by an application also contribute

to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load

(internal or external) connected to the pin:

= V

DDIOx

×

C where

is the current sunk by a switching I/O to charge/discharge the capacitive load

DDIOx

is the I/O supply voltage f

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

+ C

is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

144/273

DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Electrical characteristics

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in

Table 43 . The MCU is placed

under the following conditions:

• All I/O pins are in Analog mode

• The given value is calculated by measuring the difference of the current consumptions:

– when the peripheral is clocked on

– when the peripheral is clocked off

•

Ambient operating temperature and supply voltage conditions summarized in Table 18:

Voltage characteristics

• The power consumption of the digital part of the on-chip peripherals is given in

Table 43 . The power consumption of the analog part of the peripherals (where

applicable) is indicated in each related section of the datasheet.

AHB

Peripheral

Table 42. Peripheral current consumption

Range 1

Boost

Mode

Range 1

Normal

Mode

Range 2

Low-power run and sleep

10.5

9.65

7.7

FLASH

FMC

GFXMMU

GPIOA

GPIOB

GPIOC

GPIOD

GPIOE

GPIOF

GPIOG

GPIOH

Bus Matrix

ADC independent clock domain

ADC AHB clock domain

AES

CRC

DCMI

DMA1

DMA2

DMA2D

DMAMUX

0.25

7.25

9.65

5.25

1.75

1.65

2.25

2.75

0.875

6.65

2.9

2.65

27.5

5.15

1.75

2.15

7.75

10.5

5.6

1.85

1.75

2.4

0.835

7.15

3.15

2.85

29.5

5.35

1.85

2.25

2.35

0.25

2.75

0.125

2.6

0.5

3.5

6.25

8.35

4.6

1.4

1.35

1.9

2.15

0.835

5.5

2.5

22.5

4.15

1.45

1.55

1.8

6.5

9.5

4.5

1.5

2.5

0.5

2.5

4.5

1.5

2.5

Unit

µA/MHz

DS12024 Rev 4

145/273

248

Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

AHB

(Cont.)

APB1

Table 42. Peripheral current consumption (continued)

Peripheral

Range 1

Boost

Mode

Range 1

Normal

Mode

Range 2

Low-power run and sleep

GPIOI

HASH1

OTG_FS independent clock domain

OTG_FS AHB clock domain

OSPIM independent clock domain

OSPIM AHB clock domain

OSPI1 independent clock domain

OSPI1 AHB clock domain

OSPI2 independent clock domain

OSPI2 AHB clock domain

RNG independent clock domain

RNG AHB clock domain

SDMMC1 independent clock domain

SDMMC1 AHB clock domain

SRAM1

SRAM2

SRAM3

TSC

All AHB Peripherals

AHB to APB1 bridge

CAN1

CRS

DAC1

I2C1 independent clock domain

1.6

2.6

25.5

0.15

0.665

2.5

6.15

1.9

5.5

3.9

2.65

24.5

23.5

2.65

2.25

5.35

1.85

165

0.084

4.85

0.335

2.75

3.75

1.4

2.4

16.5

0.115

0.625

2.4

5.75

1.65

5.25

4.25

2.5

23.5

0.25

4.5

0.25

2.5

2.65

1.75

150

3.4

1.25

0.084

0.54

2.1

4.6

1.25

4.15

2.1

1.75

4.25

1.65

125

0.165

3.75

0.415

2.1

2.9

0.5

2.5

5.5

2.5

0.5

4.5

0.5

2.5

5.5

145

Unit

µA/MHz

146/273

DS12024 Rev 4

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APB1

(Cont.)

Table 42. Peripheral current consumption (continued)

Peripheral

Range 1

Boost

Mode

Range 1

Normal

Mode

Range 2

Low-power run and sleep

I2C1 APB clock domain

I2C2 independent clock domain

I2C2 APB clock domain

I2C3 independent clock domain

I2C3 APB clock domain

I2C4 independent clock domain

I2C4 APB clock domain

LPUART1 independent clock domain

LPUART1 APB clock domain

LPTIM1 independent clock domain

LPTIM1 APB clock domain

LPTIM2 independent clock domain

LPTIM2 APB clock domain

OPAMP

PWR

RTCAPB

SPI2

SPI3

TIM2

TIM3

TIM4

TIM5

TIM6

TIM7

1.4

3.5

1.4

3.25

1.15

3.5

1.35

3.15

1.65

3.6

3.4

1.1

0.415

0.5

1.25

2.6

6.15

5.25

5.15

6.5

1.35

1.25

1.4

3.4

1.25

3.15

3.25

1.25

1.5

3.5

0.875

3.25

0.375

1.15

2.4

2.75

5.75

4.9

4.75

1.15

1.25

2.5

1.25

2.9

0.835

2.75

2.45

1.3

2.9

0.835

2.55

0.79

0.415

1.25

2.1

2.5

4.65

4.15

1.25

0.835

3.5

1.5

3.5

0.5

2.5

4.5

Unit

µA/MHz

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

APB1

(Cont.)

APB2

Table 42. Peripheral current consumption (continued)

Peripheral

Range 1

Boost

Mode

Range 1

Normal

Mode

Range 2

Low-power run and sleep

USART2 independent clock domain

USART2 APB clock domain

USART3 independent clock domain

USART3 APB clock domain

UART4 independent clock domain

UART4 APB clock domain

UART5 independent clock domain

UART5 APB clock domain

WWDG

All APB1 on

AHB to APB2 bridge

DFSDM

DSI independent clock domain

DSI APB clock domain

LTDC independent clock domain

LTDC APB clock domain

SAI1 independent clock domain

SAI1 APB clock domain

SAI2 independent clock domain

SAI2 APB clock domain

SPI1

SYSCFG/VREFBUF/C

OMP

5.35

6.35

2.6

5.15

2.5

5.4

2.4

0.75

110

0.185

9.5

0.665

35.5

3.1

2.6

3.15

2.6

2.25

0.565

2.75

2.4

4.9

2.25

0.625

100

0.15

34.5

7.15

0.625

34.5

2.9

2.4

2.15

0.6

4.15

2.5

2.1

3.75

2.1

4.15

2.1

0.835

0.125

7.5

29.5

0.5

2.5

1.9

2.55

1.9

1.75

0.5

4.5

2.5

5.5

2.5

4.5

2.5

0.5

8.5

0.5

2.5

0.5

Unit

µA/MHz

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APB2

(Cont.)

Table 42. Peripheral current consumption (continued)

Peripheral

Range 1

Boost

Mode

Range 1

Normal

Mode

Range 2

Low-power run and sleep

TIM1

TIM8

TIM15

TIM16

TIM17

USART1 independent clock domain

USART1 APB clock domain

All APB2 on

ALL

8.25

8.4

2.9

3.15

6.5

2.9

340

7.75

3.9

2.9

6.15

2.75

320

6.25

6.65

3.35

2.35

2.5

5.25

2.25

62.5

265

6.5

2.5

1.5

310

Unit

µA/MHz

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Electrical characteristics

6.3.6

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Wakeup time from low-power modes and voltage scaling transition times

The wakeup times given in

Table 43 are the latency between the event and the execution of

the first user instruction.

The device goes in low-power mode after the WFE (Wait For Event) instruction.

Symbol

Table 43. Low-power mode wakeup timings

(1)

Parameter t

WUSLEEP t

WULPSLEEP

Wakeup time from Sleep mode to Run mode

Wakeup time from Lowpower sleep mode to Lowpower run mode

Conditions

Wakeup in Flash with Flash in power-down during low-power sleep mode (SLEEP_PD=1 in FLASH_ACR) and with clock MSI = 2 MHz t

WUSTOP0

Wake up time from Stop 0 mode to Run mode in

Flash

Wake up time from Stop 0 mode to Run mode in

SRAM1

Range 1

Range 2

Range 1

Range 2

Typ Max Unit

Wakeup clock MSI = 48 MHz

Wakeup clock HSI16 = 16 MHz

Wakeup clock MSI = 24 MHz

9.1

8.5

18.8

9.8

9.0

19.7

Wakeup clock HSI16 = 16 MHz 17.6

18.3

Wakeup clock MSI = 4 MHz

Wakeup clock MSI = 48 MHz

Wakeup clock HSI16 = 16 MHz

23.9

25.7

1.9

2.5

2.6

2.9

Wakeup clock MSI = 24 MHz

Wakeup clock HSI16 = 16 MHz

Wakeup clock MSI = 4 MHz

2.6

3.1

3.0

10.0

11.5

Nb of

CPU cycles

µs

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DS12024 Rev 4

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Symbol t

WUSTOP1 t

WUSTOP2

Table 43. Low-power mode wakeup timings (1) (continued)

Parameter Conditions Typ Max Unit

Wake up time from Stop 1 mode to Run in

Flash

Wake up time from Stop 1 mode to Run mode in

SRAM1

Range 1

Range 2

Range 1

Range 2

Wakeup clock MSI = 48 MHz 12.6

14.5

Wakeup clock HSI16 = 16 MHz 12.2

14.0

Wakeup clock MSI = 24 MHz 22.1

24.1

Wakeup clock HSI16 = 16 MHz 21.3

23.3

Wakeup clock MSI = 4 MHz

Wakeup clock MSI = 48 MHz

Wakeup clock HSI16 = 16 MHz

Wakeup clock MSI = 24 MHz

Wakeup clock HSI16 = 16 MHz

Wakeup clock MSI = 4 MHz

25.1

27.1

5.3

6.2

5.8

6.2

10.9

7.0

8.0

7.5

8.0

12.6

µs

Wake up time from Stop 1 mode to Lowpower run mode in Flash

Wake up time from Stop 1 mode to Lowpower run mode in

SRAM1

Regulator in lowpower mode

(LPR=1 in

PWR_CR1

)

Wakeup clock MSI = 2 MHz

20.4

22.4

16.8

19.0

Wake up time from Stop 2 mode to Run mode in

Flash

Wake up time from Stop 2 mode to Run mode in

SRAM1

Range 1

Range 2

Range 1

Range 2

Wakeup clock MSI = 48 MHz 13.1

14.8

Wakeup clock HSI16 = 16 MHz 12.6

14.4

Wakeup clock MSI = 24 MHz 22.6

24.6

Wakeup clock HSI16 = 16 MHz 21.7

23.7

Wakeup clock MSI = 4 MHz 25.8

27.9

Wakeup clock MSI = 48 MHz

Wakeup clock HSI16 = 16 MHz

Wakeup clock MSI = 24 MHz

Wakeup clock HSI16 = 16 MHz

Wakeup clock MSI = 4 MHz

5.8

6.9

6.4

7.5

8.5

8.0

6.9

8.5

11.9

13.6

µs

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Symbol

Table 43. Low-power mode wakeup timings (1) (continued)

Parameter Conditions t t t

WUSTBY

SRAM2

WUSHDN

Wakeup time from Standby mode to Run mode

Wakeup time from Standby with SRAM2 to

Run mode

Wakeup time from

Shutdown mode to Run mode

Range 1

1. Guaranteed by characterization results.

Wakeup clock MSI = 8 MHz

Wakeup clock MSI = 4 MHz

Wakeup clock MSI = 8 MHz

Wakeup clock MSI = 4 MHz

Typ Max Unit

30.7

47.8

40.4

55.6

32.1

49.1

41.5

55.5

265.0 339.4

µs

Symbol

Table 44. Regulator modes transition times (1)

Parameter Conditions t t

WULPRUN

VOST

Wakeup time from Low- power run mode to Run mode

(2)

Code run with MSI 2 MHz

Regulator transition time from

Range 2 to Range 1 or

Range 1 to Range 2

(3)

Code run with MSI 24 MHz

1. Guaranteed by characterization results.

2. Time until REGLPF flag is cleared in PWR_SR2.

3. Time until VOSF flag is cleared in PWR_SR2.

Typ Max Unit

5 7

μ s

20 40

Symbol

Table 45. Wakeup time using USART/LPUART (1)

Parameter t t

WUUSART

WULPUART

Wakeup time needed to calculate the maximum USART/LPUART baudrate allowing to wakeup up from stop mode when

USART/LPUART clock source is

HSI

1. Guaranteed by characterization results.

Conditions

Stop mode 0

Stop mode 1/2

Typ Max Unit

1.7

8.5

μ s

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STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Electrical characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.17

. However,

Symbol

Table 46. High-speed external user clock characteristics (1)

Parameter Conditions Min f

HSE_ext

User external clock source frequency

Voltage scaling

Range 1

Voltage scaling

Range 2

t t

HSEH

HSEL w(HSEH) w(HSEL)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

Voltage scaling

Range 1

Voltage scaling

Range 2

1. Guaranteed by design.

0.7 V

DDIOx

Typ

Max

DDIOx

0.3 V

DDIOx

Unit

MHz

V ns

Figure 23. High-speed external clock source AC timing diagram tw(HSEH)

VHSEH

VHSEL

90%

10% tr(HSE)

THSE tf(HSE) tw(HSEL) t

MS19214V2

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.17

. However,

Symbol

Table 47. Low-speed external user clock characteristics (1)

Parameter f

LSE_ext

LSEH

User external clock source frequency

OSC32_IN input pin high level voltage

LSEL

OSC32_IN input pin low level voltage t w(LSEH) t w(LSEL)

OSC32_IN high or low time

1. Guaranteed by design.

Conditions

Min

0.7 V

DDIOx

250

Typ

32.768

Max

1000

DDIOx

0.3 V

DDIOx

Unit kHz

V ns

Figure 24. Low-speed external clock source AC timing diagram tw(LSEH)

VLSEH

VLSEL

90%

10% tr(LSE)

TLSE tf(LSE) tw(LSEL) t

MS19215V2

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DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Electrical characteristics

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 48 . In the

application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics

(frequency, package, accuracy).

Symbol

Table 48. HSE oscillator characteristics (1)

Parameter Conditions

(2)

Min Typ Max Unit

I f

OSC_IN

DD(HSE)

Oscillator frequency

Feedback resistor

HSE current consumption

During startup

(3)

= 3 V,

Rm = 30 Ω ,

CL = 10 pF@8 MHz

= 3 V,

Rm = 45 Ω ,

CL = 10 pF@8 MHz

= 3 V,

Rm = 30 Ω ,

CL = 5 pF@48 MHz

= 3 V,

Rm = 30 Ω ,

CL = 10 pF@48 MHz

200

0.44

0.45

0.68

0.94

5.5

MHz k Ω mA

= 3 V,

Rm = 30 Ω ,

CL = 20 pF@48 MHz

1.77

G m

Maximum critical crystal transconductance

Startup 1.5

mA/V t

SU(HSE)

(4)

Startup time V

is stabilized 2 ms

1. Guaranteed by design.

2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

3. This consumption level occurs during the first 2/3 of the t

SU(HSE) startup time

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see Figure 25

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

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248

Electrical characteristics

Note:

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 25. Typical application with an 8 MHz crystal

Resonator with integrated capacitors

OSC_IN f

HSE

8 MHz resonator

EXT

(1) OSC_OUT

Bias controlled gain

MS19876V1

1. R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 49 . In the application, the

resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

156/273

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Note:

Electrical characteristics

Symbol

Table 49. LSE oscillator characteristics (f

LSE

= 32.768 kHz) (1)

Parameter Conditions

(2)

Min Typ Max Unit

DD(LSE)

LSE current consumption

LSEDRV[1:0] = 00

Low drive capability

LSEDRV[1:0] = 01

Medium low drive capability

LSEDRV[1:0] = 10

Medium high drive capability

LSEDRV[1:0] = 11

High drive capability

250

315

500

630 -

LSEDRV[1:0] = 00

Low drive capability

LSEDRV[1:0] = 01

Medium low drive capability

0.5

0.75

Gm critmax

Maximum critical crystal gm

1.7

µA/V

LSEDRV[1:0] = 10

Medium high drive capability

LSEDRV[1:0] = 11

High drive capability

2.7

SU(LSE)

(3)

Startup time V

is stabilized 2 -

1. Guaranteed by design.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”.

3. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized

32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer s

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 26. Typical application with a 32.768 kHz crystal

Resonator with integrated capacitors

OSC32_IN f

LSE

32.768 kHz resonator

Drive programmable amplifier

OSC32_OUT

Note:

MS30253V2

An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

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Electrical characteristics

6.3.8

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Internal clock source characteristics

The parameters given in

Table 50 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 21: General operating conditions

. The provided curves are characterization results, not tested in production.

High-speed internal (HSI16) RC oscillator

Symbol

Table 50. HSI16 oscillator characteristics (1)

Parameter Conditions Min Typ Max Unit

DuCy(HSI16)

(2) t

∆

Temp

VDD t su stab

DD f

HSI16

TRIM

(HSI16)

HSI16 Frequency

HSI16 user trimming step

=3.0 V, T

=30 °C 15.88

Trimming code is not a multiple of 64

0.2

Trimming code is a multiple of 64

-4

45 Duty Cycle

HSI16 oscillator frequency drift over temperature

= 0 to 85 °C

= -40 to 125 °C

HSI16 oscillator frequency drift over V

HSI16 oscillator start-up time

=1.62 V to 3.6 V

-1

-2

-0.1

HSI16 oscillator stabilization time

HSI16 oscillator power consumption

1. Guaranteed by characterization results.

2. Guaranteed by design.

0.3

-6

0.8

16.08 MHz

0.4

-8

1.5

0.05

1.2

μ s

155 190 μ A

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DS12024 Rev 4

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Figure 27. HSI16 frequency versus temperature

MHz

16.4

16.3

16.2

16.1

15.9

15.8

15.7

15.6

-40 -20 0

Mean

+2 %

+1.5 %

+1 %

-1 %

-1.5 %

-2 %

40 min

60 80 max

100 120 °C

MSv39299V2

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Multi-speed internal (MSI) RC oscillator

Symbol f

MSI

∆

TEMP

(MSI)

Parameter

Table 51. MSI oscillator characteristics

(1)

Conditions Min

MSI frequency after factory calibration, done at V

=3 V and

=30 °C

MSI oscillator frequency drift over temperature

MSI mode

PLL mode

XTAL=

32.768 kHz

Range 0

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

Range 0

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

= -0 to 85 °C

MSI mode

= -40 to 125 °C

-3.5

7.896

15.79

23.69

31.58

47.38

98.7

197.4

394.8

7896

0.987

1.974

3.948

-8

Typ

196.608

393.216

786.432

1.016

1.999

3.998

7.995

15.991

23.986

32.014

48.005

98.304

100

200

400

800

Max Unit

101.3

202.6

405.2

810.4

1.013

2.026

4.052

kHz

8.104

MHz

16.21

24.31

32.42

48.62

kHz

MHz

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Symbol

Table 51. MSI oscillator characteristics (1) (continued)

Parameter Conditions

∆

VDD

(MSI)

(2)

MSI oscillator frequency drift over V

(reference is

3 V)

MSI mode

Range 0 to 3

Range 4 to 7

=1.62 V to 3.6 V

=2.4 V to 3.6 V

=1.62 V to 3.6 V

=2.4 V to 3.6 V

Range 8 to 11

=1.62 V to 3.6 V

=2.4 V to 3.6 V

= -40 to 85 °C

∆ F

(MSI)

Frequency variation in sampling mode

(3)

MSI mode

= -40 to 125 °C t

P_USB

STAB

MT_USB

Period jitter for

USB clock

(4)

Medium term jitter for USB clock

(5)

MSI oscillator stabilization time

PLL mode

Range 11

PLL mode

Range 11

PLL mode

Range 11

CC jitter(MSI)

(6)

P jitter(MSI)

RMS cycle-tocycle jitter

PLL mode Range 11

RMS Period jitter PLL mode Range 11

Range 0

Range 1

Range 2 t

(MSI)

MSI oscillator start-up time

Range 3

Range 4 to 7

Range 8 to 11 for next transition for paired transition for next transition for paired transition

10 % of final frequency

5 % of final frequency

1 % of final frequency

Min

-1.2

-0.5

-2.5

-0.8

-5

-1.6

Typ

2.5

0.25

0.5

Max Unit

0.5

0.7

3.458

3.916

1 ns

0.5

ps ps us

1.25

2.5

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Symbol

Table 51. MSI oscillator characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit

(MSI)

MSI oscillator power consumption

MSI and

PLL mode

Range 0

Range 1

Range 2

Range 3

Range 4

Range 5

Range 6

Range 7

Range 8

Range 9

Range 10

Range 11

0.6

0.8

1.2

1.9

4.7

6.5

18.5

110

155

µA

1. Guaranteed by characterization results.

2. This is a deviation for an individual part once the initial frequency has been measured.

3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.

4. Average period of MSI @48 MHz is compared to a real 48 MHz clock over 28 cycles. It includes frequency tolerance + jitter of MSI @48 MHz clock.

5. Only accumulated jitter of MSI @48 MHz is extracted over 28 cycles.

For next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of the MSI @48 MHz, for 1000 captures over 28 cycles.

For paired transitions: min. and max. jitter of 2 consecutive frame of 56 cycles of the MSI @48 MHz, for 1000 captures over

56 cycles.

6. Guaranteed by design.

1.2

1.7

2.5

110

130

190

Figure 28. Typical current consumption versus MSI frequency

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DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Electrical characteristics

High-speed internal 48 MHz (HSI48) RC oscillator

Symbol

Table 52. HSI48 oscillator characteristics

(1)

Parameter Conditions Min Typ Max Unit f

HSI48

TRIM

HSI48 Frequency

HSI48 user trimming step

=3.0V, T

=30°C

USER TRIM

COVERAGE

ACC

D t

HSI48_REL

VDD su

(HSI48)

HSI48 user trimming coverage

DuCy(HSI48) Duty Cycle

±32 steps

±3

(3)

Accuracy of the HSI48 oscillator over temperature

(factory calibrated)

HSI48 oscillator frequency drift with V

= 3.0 V to 3.6 V,

= –15 to 85 °C

= 1.65 V to 3.6 V,

= –40 to 125 °C

= 3 V to 3.6 V

= 1.65 V to 3.6 V -

HSI48 oscillator start-up time

(HSI48)

jitter

HSI48 oscillator power consumption

Next transition jitter

Accumulated jitter on 28 cycles

(4)

Paired transition jitter

Accumulated jitter on 56

cycles (4)

0.11

±3.5

(2)

0.025

0.05

2.5

340

1. V

= 3 V, T

= –40 to 125°C unless otherwise specified.

2. Guaranteed by design.

3. Guaranteed by characterization results.

4. Jitter measurement are performed without clock source activated in parallel.

+/-0.15

+/-0.25

0.18

Table 54 are derived from tests performed under temperature and

MHz

±3

±4.5

0.05

0.1

380

μ s

A ns ns

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248

Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Figure 29. HSI48 frequency versus temperature

-2

-4

-6

-50 -30 -10

Avg

10 30 min

50 70

Low-speed internal (LSI) RC oscillator

Symbol

Table 53. LSI oscillator characteristics (1)

Parameter Conditions t t

STAB

DD f

LSI

(LSI)

(2)

LSI Frequency

= 3.0 V,

= 30 °C

= 1.62 to 3.6 V,

= -40 to 125 °C

LSI oscillator start-up time

LSI oscillator stabilization time

5% of final frequency

LSI oscillator power consumption

1. Guaranteed by characterization results.

2. Guaranteed by design.

Min

31.04

29.5

90 max

110 130

°C

MSv40989V1

Typ

125

110

Max Unit

32.96

130

180

180 kHz

μ s

μ s nA

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The parameters given in

supply voltage conditions summarized in

Table 21: General operating conditions .

Symbol

Table 54. PLL, PLLSAI1, PLLSAI2 characteristics

(1)

Parameter

PLL input clock

(2)

Conditions

Min

2.66

Typ Max Unit

16 MHz f f

PLL_IN

PLL_P_OUT

PLL input clock duty cycle

PLL multiplier output clock P

Voltage scaling Range 1

Normal mode

2.0645

Voltage scaling Range 1

Boost mode

2.0645

Voltage scaling Range 2 2.0645

PLL_Q_OUT

Voltage scaling Range 1

Normal mode

PLL multiplier output clock Q Voltage scaling Range 1

Boost mode

Voltage scaling Range 2

Voltage scaling Range 1

Normal mode

8 -

120

MHz f

PLL_R_OUT

PLL multiplier output clock R f

VCO_OUT t

LOCK

PLL VCO output

Voltage scaling Range 1

Boost mode

Voltage scaling Range 2

Voltage scaling Range 1

Voltage scaling Range 2

Jitter

PLL lock time

RMS cycle-to-cycle jitter

RMS period jitter

System clock 80 MHz

(PLL)

PLL power consumption on

VCO freq = 64 MHz

VCO freq = 96 MHz

VCO freq = 192 MHz

VCO freq = 344 MHz

120

150 200

200 260

300 380

520 650

344

128

μ s

±ps

μ A

1. Guaranteed by design.

2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between the 3 PLLs.

6.3.10 MIPI D-PHY characteristics

The parameters given in

Table 55 and

Table 56

are derived from tests performed under temperature and V

supply voltage conditions summarized in

Table 57 are derived from tests performed under temperature and

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Symbol

Table 55. MIPI D-PHY characteristics (1)

Parameter Conditions Min

| ∆

INST

CMTX

UI instantaneous

Hi-speed input/output characteristics

HS transmit common mode voltage

CMTX

mismatch when output is Differential-1 or Differential-0

150

∆

OHHS

∆ t

HSr

& t

HSf

HS transmit differential voltage

mismatch when output is

Differential-1 or Differential-0

HS output high voltage

Single ended output impedance

140

Single ended output impedance mismatch

20%-80% rise and fall time -

LP receiver input characteristics

100

Logic 0 input voltage (not in

ULP State)

IL-ULPS

V hys

Logic 0 input voltage in ULP

State

Input high level voltage

Voltage hysteresis

880

IL-ULPS

LP emitter output characteristics

Output low level voltage

Output high level voltage

1.1

-50

Output impedance of LP transmitter

110

V hys

15%-85% rise and fall time -

ILCD

IHCD

LP contention detector characteristics

Logic 0 contention threshold

1. Guaranteed by characterization results.

450

Typ

200

1.2

Max

12.5

250

0.35*UI

550

300

200

1.2

270

360

62.5

Unit ns mV

Ω

% ps mV mV

V mV

Ω ns

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Table 56. MIPI D-PHY AC characteristics LP mode and HS/LP transitions (1)

Symbol Parameter Conditions Min Typ Max Unit

LPX

CLK-PREPARE

CLK-ZERO

CLK-PRE

CLK-POST

CLK-TRAIL

HS-PREPARE

HS-ZERO

HS-TRAIL

HS-EXIT

REOT

EOT

Transmitted length of any Low-

Power state period

Time that the transmitter drives the Clock Lane LP-00 Line state immediately before the

HS-0 Line state starting the HS transmission.

Time that the transmitter drives the HS-0 state prior to starting the clock.

Time that the HS clock shall be driven by the transmitter prior to any associated Data Lane beginning the transition from

LP to HS mode.

Time that the transmitter continues to send HS clock after the last associated Data

Lane has transitioned to LP

Mode.

Time that the transmitter drives the HS-0 state after the last payload clock bit of an HS transmission burst.

Time that the transmitter drives the Data Lane LP-00 Line state immediately before the HS-0

Line state starting the HS transmission.

HS-PREPARE+

Time that the transmitter drives the HS-0 state prior to transmitting the

Sync sequence.

Time that the transmitter drives the flipped differential state after last payload data bit of a

HS transmission burst.

Time that the transmitter drives

LP-11 following a HS burst.

30%-85% rise time and fall time

Transmitted time interval from the start of T

HS-TRAIL

CLK-TRAIL

, to the start of the

LP-11 state following a HS burst.

1. Guaranteed by characterization results.

300

62+52*UI

40+4*UI

145+10*UI

Max

(n*8*UI,

60+n*4*UI)

100

85+6*UI

105+ n*12UI ns

UI ns

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Figure 30. MIPI D-PHY HS/LP clock lane transition timing diagram

CLK-POST

EOT

IL Clock

Lane

CLK-TRAIL

HS-EXIT

LPX

CLK-PREPARE

CLK-ZERO

CLK-PRE

LPX

HS-PREPARE

Data

Lane

Figure 31. MIPI D-PHY HS/LP data lane transition timing diagram

MS38282V1

Clock

Lane

LPX

HS-PREPARE

HS-ZERO

Data

Lane

LP-11 LP-01 LP-00

EOT

HS-TRAIL

REOT

HS-EXIT

MS38283V1

6.3.11 MIPI D-PHY PLL characteristics

The parameters given in

supply voltage conditions summarized in

Table 58 are derived from tests performed under temperature and

Symbol

Table 57. DSI-PLL characteristics (1)

Parameter f

PLL_IN f

PLL_INFIN f

PLL_OUT f

VCO_OUT t

LOCK

PLL input clock

PFD input clock

PLL multiplier output clock

PLL VCO output

PLL lock time

Conditions

Min Typ Max Unit

31.25

500

100

500

1000

200

MHz

µs

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Symbol

Table 57. DSI-PLL characteristics (1) (continued)

Parameter Conditions

DD(PLL)

PLL power consumption on V

DD12 f

VCO_OUT

= 500 MHz f

VCO_OUT

= 600 MHz f

VCO_OUT

= 1000 MHz

1. Guaranteed by characterization results.

Min Typ Max Unit

0.55

0.70

0.65

0.80

0.95

1.20

6.3.12 MIPI D-PHY regulator characteristics

The parameters given in

supply voltage conditions summarized in

Symbol

Table 58. DSI regulator characteristics

(1)

Parameter Conditions

DD12DSI

EXT

ESR

DDDSIREG

DDDSI

DDDSILP

1.2 V internal voltage on V

External capacitor on V

External Serial Resistor

DD12DSI

CAPDSI

Regulator power consumption

DSI system (regulator, PLL and

D-PHY) current consumption on V

DDDSI

DSI system current consumption on

DDDSI

in LP mode communication

(2)

Ultra Low Power Mode

(Reg. ON + PLL OFF)

Stop State

(Reg. ON + PLL OFF)

10 MHz escape clock

(Reg. ON + PLL OFF)

20 MHz escape clock

(Reg. ON + PLL OFF)

300 Mbps - 1 data lane

(Reg. ON + PLL ON)

DDDSIHS

DSI system (regulator, PLL and

D-PHY) current consumption on V in HS mode communication

(3)

DDDSI

300 Mbps - 2data lane

(Reg. ON + PLL ON)

500 Mbps - 1 data lane

(Reg. ON + PLL ON)

500 Mbps - 2data lane

(Reg. ON + PLL ON)

DSI system (regulator, PLL and

D-PHY) current consumption on V in HS mode with CLK like payload

DDDSI

500 Mbps - 2data lane

(Reg. ON + PLL ON) t

WAKEUP

Startup delay

EXT

= 2.2 µF

EXT

= 3.3 µF

External capacitor load at start I

INRUSH

Inrush current on V

DDDSI

1. Guaranteed by characterization results.

2. Values based on an average traffic in LP Command Mode.

3. Values based on an average traffic (3/4 HS traffic & 1/4 LP) in Video Mode.

Min Typ Max Unit

1.15

1.20

1.30

1.1

2.2

3.3

μ F

0 25 600 m Ω

100 120 125 µA

290 600

4.3

5.0

4.3

5.0

8.0

8.8

11.4

12.5

13.5

14.7

18.0

19.6

21.4

23.3

µA mA mA

110

160

µs

60 200 mA

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx t

Symbol t prog prog_row t prog_page

Table 59. Flash memory characteristics (1)

Parameter

64-bit programming time

One row (64 double word) programming time

One page (4 Kbytes) programming time

Conditions

Normal programming

Fast programming

Normal programming

Fast programming

Typ

81.7

5.2

3.8

41.8

30.4

ERASE

Page (4 Kbytes) erase time

22 t prog_bank

One bank (1 Mbyte) programming time

Normal programming

Fast programming

10.7

7.7

Mass erase time

(one or two banks)

22.1

Average consumption from V

Maximum current (peak)

Write mode

Erase mode

Write mode

Erase mode

3.4

7 (for 6 μ s)

7 (for 67 μ s)

1. Guaranteed by design.

Symbol

Table 60. Flash memory endurance and data retention

Parameter Conditions

N t

END

RET

Endurance

Data retention

= –40 to +105 °C

1 kcycle (2) at T

= 85 °C

= 105 °C

= 125 °C

10 kcycles

at T

= 55 °C

10 kcycles

(2) at T

= 85 °C

10 kcycles

The test results are given in Table 61

at T

= 105 °C

1. Guaranteed by characterization results.

2. Cycling performed over the whole temperature range.

Min (1)

Unit kcycles

Years

Max Unit

90.8

µs

5.5

31 ms

24.5

8 s ms mA

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Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

and

A device reset allows normal operations to be resumed.

. They are based on the EMS levels and classes defined in application note AN1709.

Symbol

Table 61. EMS characteristics

Parameter Conditions

Level/

Class

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

and V pins to induce a functional disturbance

SS f

= 3.3 V, T

HCLK

= +25 °C,

= 120 MHz, conforming to IEC 61000-4-2 f

= 3.3 V, T

HCLK

= +25 °C,

= 120 MHz, conforming to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (control registers...)

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Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Symbol Parameter

EMI

Table 62. EMI characteristics

Conditions

Peak level

= 3.6 V, T

25 °C,

UFBGA169 package compliant with

IEC 61967-2

Monitored frequency band

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1 GHz

1 GHz to 2 GHz

EMI Level

Max vs. [f

HSE

HCLK

]

Unit

8 MHz / 120 MHz

-2

3 dBµV

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard.

Symbol

Table 63. ESD absolute maximum ratings

Ratings Conditions Class

Maximum value

(1)

Unit

ESD(HBM)

Electrostatic discharge voltage (human body model)

ESD(CDM)

Electrostatic discharge voltage (charge device model)

= +25 °C, conforming to ANSI/ESDA/JEDEC

JS-001

= +25 °C, conforming to ANSI/ESD

STM5.3.1

1. Guaranteed by characterization results.

2000

250

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Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin.

• A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Symbol Parameter

Table 64. Electrical sensitivities

Conditions

LU Static latch-up class T

= +105 °C conforming to JESD78A

1. Negative injection is limited to -30 mA for PF0, PF1, PG6, PG7, PG8, PG12, PG13, PG14.

Class

II level A

(1)

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

DDIOx product operation. However, in order to give an indication of the robustness of the

(for standard, 3.3 V-capable I/O pins) should be avoided during normal microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation).

The characterization results are given in

Table 65 .

Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection.

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Symbol

Table 65. I/O current injection susceptibility

Functional susceptibility

Description

Negative injection

Positive injection

INJ

(1)

Injected current on all pins except PA4, PA5, PB0, PF13,

PE15, PC8, PA13, PH3-BOOT0, PB8, PE0,

OPAMP1_V1NM, OPAMP2_V1NM

Injected current on pins PF13, PE15, PC8, PA13, PH3-

BOOT0, PB8, PE0

Injected current on pins OPAMP1_V1NM,

OPAMP2_V1NM

Injected current on PA4, PA5, PB0 pins

1. Guaranteed by characterization.

-5

Unit mA

General input/output characteristics

Unless otherwise specified, the parameters given in

Table 66 are derived from tests

performed under the conditions summarized in Table 21: General operating conditions

. All

I/Os are designed as CMOS- and TTL-compliant (except BOOT0).

Sym bol

Parameter

Table 66. I/O static characteristics

Conditions Min Typ Max Unit

I/O input low level voltage except BOOT0

1.62 V<V

1.08 V<V

DDIOx

<3.6 V

<1.62 V

BOOT0 I/O input low level voltage

1.62 V<V

DDIOx

<3.6 V -

0.3xV

0.39xV

0.43xV

-0.06

-0.1

0.17xV

DDIOx

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Table 66. I/O static characteristics (continued)

Sym bol

Parameter Conditions

C lkg

I/O input high level voltage except BOOT0

1.62 V<V

1.08 V<V

DDIOx

<3.6 V

<1.62 V

BOOT0 I/O input high level voltage

1.62 V<V

DDIOx

<3.6 V

TT_xx, FT_xxx and NRST I/O input hysteresis

1.62 V<V

DDIOx

<3.6 V

FT_sx 1.08 V<V

DDIOx

<1.62 V

BOOT0 I/O input hysteresis

1.62 V<V

DDIOx

<3.6 V

FT_xx input leakage

current

≤ Max(V

DDXXX

) (4)

Max(V

DDXXX

Max(V

DDXXX

) ≤ V

)+1 V

≤

FT_lu, FT_u,

PB2 and PC3 IO

Max(V

VIN ≤

5.5 V

)+1 V <

≤ Max(V

DDXXX

)

Max(V

DDXXX

Max(V

DDXXX

) ≤ V

)+1 V

≤

TT_xx input leakage current

Max(V

VIN ≤

5.5 V

)+1 V <

≤ Max(V

DDXXX

)

Max(V

3.6 V

) ≤ V

OPAMPx_VINM

(x=1,2) dedicated input leakage current

Weak pull-up equivalent resistor

(9)

Weak pull-down equivalent

resistor

(9)

I/O pin capacitance

= V

DDIOx

0.7xV

DDIOx

0.49xV

0.61xV

Min

0.77xV

DDIOX

+0.26

+0.05

Typ

200

150

200

Max

650

(3)(6)

200

(6)

250

(7)

2000

1. Refer to Figure 32: I/O input characteristics .

±100

±150

2500

(3)(7)

±150

(8)

Unit

V mV nA k Ω k Ω pF

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

2. Tested in production.

3. Guaranteed by design.

4. Max(V

DDXXX

) is the maximum value of all the I/O supplies.

5. All TX_xx IO except FT_lu, FT_u, PB2 and PC3.

6. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula:

Total_Ileak_max

= 10 µA + [number of IOs where V

is applied on the pad] ₓ I lkg

(Max).

7. To sustain a voltage higher than MIN(V resistors must be disabled.

, V

DDA

, V

DDUSB

, V

LCD

) +0.3 V, the internal Pull-up and Pull-Down

8. Refer to I current.

bias

in Table 82: OPAMP characteristics

for the values of the OPAMP dedicated input leakage

9. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable

PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order).

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements is shown in Figure 32

for standard I/Os, and in

Figure 32

for

5 V tolerant I/Os.

Figure 32. I/O input characteristics

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TTL requirement Vih min = 2V

Vih

min = 0

.7xV

DDIO x

Teste

1xV

Based on simu on Vi h min = 0.6

lation V il max

=0.43xV

DDIOx

-0.1 for 1.08

uirement Vil m ax = 0.3xVdd

DDIOx

+0.2

6 for V

DDIOx

>1.6

DDIOx

<1.62 or

0.49xV

DDIOx

+0.05

for 1.08<V

DDIOx

<1.62 or 0.39xV

DDIOx

-0.06 for

DDIO x

>1.62

TTL requirement Vil max = 0.8V

Tested in produ ction CMOS req

MSv37613V1

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ± 20 mA (with a relaxed V

DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Electrical characteristics

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2

• The sum of the currents sourced by all the I/Os on V

DDIOx, consumption of the MCU sourced on V

DD,

Σ I

VDD

(see Table 18: Voltage characteristics ).

plus the maximum cannot exceed the absolute maximum rating

• The sum of the currents sunk by all the I/Os on V

, plus the maximum consumption of the MCU sunk on V

, cannot exceed the absolute maximum rating

Table 18: Voltage characteristics

Σ I

VSS

(see

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 21: General operating conditions . All I/Os are CMOS- and TTL-compliant (FT OR TT

unless otherwise specified).

Symbol

Table 67. Output voltage characteristics (1)

Parameter Conditions Min Max Unit

(3)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

CMOS port

(2)

= 8 mA

DDIOx

≥ 2.7 V

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

TTL port

DDIOx

Table 18: Voltage characteristics

= 8 mA

≥ 2.7 V

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

| = 20 mA

DDIOx

≥ 2.7 V

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

| = 4 mA

DDIOx

≥ 1.62 V

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

| = 2 mA

1.62 V ≥ V

1.08 V

DDIOx

≥

Output low level voltage for an FT I/O pin in FM+ mode

(FT I/O with "f" option)

| = 20 mA

DDIOx

≥ 2.7 V

| = 10 mA

DDIOx

≥ 1.62 V

| = 2 mA

1.62 V ≥ V

1.08 V

DDIOx

≥

0.65

ₓ

DDIOx

2.4

DDIOx

-0.4

-1.3

-0.45

DDIOx

0.4

1.3

0.45

0.35

0.4

ₓ

DDIOx

1. The I in

current sourced or sunk by the device must always respect the absolute maximum rating specified

, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings Σ I

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. Guaranteed by design.

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 33

and

Table 68 , respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 21: General operating conditions

Speed Symbol

Fmax

Tr/Tf

Fmax

Tr/Tf

Table 68. I/O AC characteristics (1)(2)

Parameter Conditions

Maximum frequency

Output rise and fall time

Maximum frequency

Output rise and fall time

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

Unit

MHz ns

Min

Max

140

110

0.1

1.5

0.1

4.5

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Speed Symbol

Table 68. I/O AC characteristics (1)(2) (continued)

Parameter Conditions Min Max Unit

Fm+

Fmax

Tr/Tf

Fmax

Tr/Tf

Fmax

Maximum frequency

Output rise and fall time

Maximum frequency

Output rise and fall time

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=50 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=50 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=50 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=30 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=30 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=30 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=10 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=10 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=10 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

C=30 pF, 2.7 V ≤ V

DDIOx

≤ 3.6 V

C=30 pF, 1.62 V ≤ V

DDIOx

≤ 2.7 V

C=30 pF, 1.08 V ≤ V

DDIOx

≤ 1.62 V

Maximum frequency

Output fall time

(4)

C=50 pF, 1.6 V ≤ V

DDIOx

≤ 3.6 V

1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the

SYSCFG_CFGR1 register. Refer to the RM0432 reference manual for a description of GPIO Port configuration register.

2. Guaranteed by design.

3. This value represents the I/O capability but the maximum system frequency is limited to 80 MHz.

4. The fall time is defined between 70% and 30% of the output waveform accordingly to I 2 C specification.

100

(3)

37.5

5.8

2.5

120

180

1. Refer to Table 68: I/O AC characteristics .

3.3

MHz ns

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Figure 33. I/O AC characteristics definition

(1)

90% 10%

50% 50%

10% 90% t r(IO)out t f(IO)out

T when loaded by the specified capacitance.

MS32132V2

6.3.18 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, R

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 21: General operating conditions .

Symbol

Table 69. NRST pin characteristics (1)

Parameter Conditions Min Typ Max Unit

IL(NRST)

IH(NRST)

V hys(NRST)

F(NRST)

NF(NRST)

NRST input low level voltage

NRST input high level voltage

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(2)

NRST input filtered pulse

NRST input not filtered pulse

= V

1.71 V ≤ V

≤ 3.6 V

0.7

ₓ V

DDIOx

350

200

0.3

ₓ V

DDIOx

V mV k Ω ns ns

1. Guaranteed by design.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order)

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Figure 34. Recommended NRST pin protection

External reset circuit

(1) V

NRST

(2)

Filter

Internal reset

0.1 μF

MS19878V3

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

IL(NRST)

max level specified in

Table 69: NRST pin characteristics

. Otherwise the reset will not be taken into account by the device.

3. The external capacitor on NRST must be placed as close as possible to the device.

6.3.19 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length in order to guarantee that it is detected by the event controller.

Symbol

Table 70. EXTI input characteristics (1)

Parameter

PLEC

Pulse length to event controller

1. Guaranteed by design.

Conditions

Min

Typ

Max

Unit ns

6.3.20 Analog switches booster

Symbol

Table 71. Analog switches booster characteristics

(1)

Parameter

DD t

SU(BOOST)

Supply voltage

Booster startup time

DD(BOOST)

Booster consumption for

1.62 V ≤ V

≤ 2.0 V

Booster consumption for

2.0 V ≤ V

≤ 2.7 V

Booster consumption for

2.7 V ≤ V

≤ 3 .6 V

1. Guaranteed by design.

Min

1.62

Typ

Max

3.6

240

250

500

900

Unit

µs

µA

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Note:

Unless otherwise specified, the parameters given in Table 72

are preliminary values derived from tests performed under ambient temperature, f

PCLK frequency and V

conditions summarized in Table 21: General operating conditions

DDA

supply voltage

It is recommended to perform a calibration after each power-up.

Symbol

DDA

REF+

REFf

ADC f s f

TRIG

AIN

(3)

AIN

ADC

Table 72. ADC characteristics

(1) (2)

Parameter Conditions Min

Analog supply voltage

Positive reference voltage

Negative reference voltage

DDA

≥ 2 V

< 2 V

ADC clock frequency

Sampling rate for FAST channels

Sampling rate for SLOW channels

External trigger frequency

Range 1

Range 2

Resolution = 12 bits

Resolution = 10 bits

Resolution = 8 bits

Resolution = 6 bits

Resolution = 12 bits

Resolution = 10 bits

Resolution = 8 bits

Resolution = 6 bits f

ADC

= 80 MHz

Resolution = 12 bits

Conversion voltage range(2)

External input impedance

Internal sample and hold capacitor

1.62

Typ

DDA

SSA

Max

3.6

DDA

5.33

6.15

7.27

8.88

4.21

4.71

5.33

6.15

5.33

REF+

Unit

MHz

Msps

MHz

1/f

ADC

V k Ω pF t

STAB t

CAL

Power-up time -

Calibration time f

ADC

= 80 MHz

1.45

116 conversi on cycle

µs

1/f

ADC

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Symbol

Table 72. ADC characteristics (1) (2) (continued)

Parameter Conditions Min Typ Max Unit t t t

LATR

LATRINJ t s

ADCVREG_STU

Trigger conversion latency Regular and injected channels without conversion abort

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11

Trigger conversion latency Injected channels aborting a regular conversion

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11

Sampling time f

ADC

= 80 MHz

ADC voltage regulator startup time

Total conversion time

(including sampling time) f

ADC

= 80 MHz

Resolution = 12 bits

1.5

2.5

0.03125

2.5

0.1875

2.5

2.0

2.25

2.125

3.5

3.0

3.25

3.125

8.00625

640.5

8.1625

1/f

ADC

µs

ADC

µs

I t

CONV

DDA

(ADC)

DDV_S

DDV_D

(ADC)

ADC consumption from the V

DDA supply

ADC consumption from the V

REF+ single ended mode

ADC consumption from the V

REF+ differential mode fs = 5 Msps fs = 1 Msps fs = 10 ksps fs = 5 Msps fs = 1 Msps fs = 10 ksps fs = 5 Msps fs = 1 Msps fs = 10 ksps ts + 12.5 cycles for successive approximation

= 15 to 653

730 830

160

130

0.6

260

1.3

220

160

310

1/f

ADC

µA

1. Guaranteed by design

2. The I/O analog switch voltage booster is enable when V

SYSCFG_CFGR1 when V

DDA

< 2.4V). It is disable when V

< 2.4 V (BOOSTEN = 1 in the

DDA

≥ 2.4 V.

REF+

can be internally connected to V the package.

DDA

and V

REF-

can be internally connected to V

Refer to Section 4: Pinouts and pin description for further details.

SSA

, depending on

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The maximum value of R

AIN

can be found in Table 73: Maximum ADC RAIN .

Resolution

Table 73. Maximum ADC R

AIN

(1)(2)

Sampling cycle

@80 MHz

Sampling time

[ns] @80 MHz

AIN

max ( Ω )

Fast channels

(3)

12 bits

10 bits

8 bits

6 bits

92.5

247.5

640.5

2.5

6.5

12.5

640.5

2.5

6.5

12.5

24.5

47.5

24.5

47.5

92.5

247.5

640.5

2.5

6.5

12.5

24.5

47.5

92.5

247.5

2.5

6.5

12.5

24.5

47.5

92.5

247.5

8006.75

31.25

81.25

156.25

306.25

593.75

1156.25

3093.75

8006.75

31.25

81.25

156.25

8006.75

31.25

81.25

156.25

306.25

593.75

1156.25

3093.75

31.25

81.25

156.25

306.25

593.75

1156.25

3093.75

306.25

593.75

1156.25

3093.75

8006.75

6800

15000

50000

220

560

1200

47000

180

470

1000

1800

2700

39000

120

390

820

1500

2200

5600

12000

100

330

680

1500

2200

4700

12000

2700

3900

8200

18000

50000

5600

12000

50000

N/A

330

1000

39000

N/A

270

680

1500

2200

33000

N/A

180

560

1200

1800

4700

10000

N/A

100

470

1200

1800

3900

10000

2200

3300

6800

15000

50000

(4)

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1. Guaranteed by design.

2. The I/O analog switch voltage booster is enable when V

SYSCFG_CFGR1 when V

DDA

< 2.4V). It is disable when V

< 2.4 V (BOOSTEN = 1 in the

DDA

≥ 2.4 V.

3. Fast channels are: PC0, PC1, PC2, PC3, PA0.

4. Slow channels are: all ADC inputs except the fast channels.

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Table 74. ADC accuracy - limited test conditions 1 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

DDA

= VREF+ = 3 V,

TA = 25 °C

Single ended

Differential

Single ended

Differential

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

1.5

2.5

Fast channel (max speed) 10.4 10.5

Slow channel (max speed) 10.4 10.5

Fast channel (max speed) 10.8 10.9

Slow channel (max speed) 10.8 10.9

Fast channel (max speed) 64.4 65 -

Slow channel (max speed) 64.4 65 -

Fast channel (max speed) 66.8 67.4

Slow channel (max speed) 66.8 67.4

Fast channel (max speed) 65 66 -

Slow channel (max speed) 65 66

Fast channel (max speed) 67 68

Slow channel (max speed) 67 68

4 5

3.5

4.5

3.5

4.5

1 2.5

1.5

2.5

1.5

2.5

4.5

2.5

4.5

2.5

3.5

2.5

3.5

1 1.5

1 1.2

1.5

2.5

LSB bits dB

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Table 74. ADC accuracy - limited test conditions 1 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

DDA

= V

REF+

= 3 V,

TA = 25 °C

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-74 -73

-79 -76

-79 -76 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

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Table 75. ADC accuracy - limited test conditions 2 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Differential linearity error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

2 V ≤ V

DDA Integral linearity error

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

1 1.5

1 1.2

1.5

3.5

1.5

3.5

1 3

Slow channel (max speed) 1 2.5

Fast channel (max speed) 10 10.5

Slow channel (max speed) 10 10.5

Fast channel (max speed) 10.7 10.9

Slow channel (max speed) 10.7 10.9

Fast channel (max speed) 62 65 -

Slow channel (max speed) 62 65

Fast channel (max speed) 66 67.4

Slow channel (max speed) 66 67.4

Fast channel (max speed) 64 66

Slow channel (max speed) 64 66

Fast channel (max speed) 66.5 68

Slow channel (max speed) 66.5 68

4 6.5

3.5

5.5

3.5

5.5

1 4.5

1 5

1.5

2.5

3.5

2.5

3.5

1 1.5

LSB bits dB

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Table 75. ADC accuracy - limited test conditions 2 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

2 V ≤ V

DDA

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-74 -65

-74 -67

-79 -70

-79 -71 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

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Table 76. ADC accuracy - limited test conditions 3 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Differential linearity error

Integral linearity error

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

1.65 V ≤ V

DDA

3.6 V,

= V

REF+

≤

Voltage scaling Range 1

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

1.2

1.5

1 1.2

3 3.5

2.5

3.5

2 2.5

Slow channel (max speed) 2 2.5

Fast channel (max speed) 10 10.4

Slow channel (max speed) 10 10.4

Fast channel (max speed) 10.6 10.7

Slow channel (max speed) 10.6 10.7

Fast channel (max speed) 62 64 -

Slow channel (max speed) 62 64

Fast channel (max speed) 65 66

Slow channel (max speed) 65 66

Fast channel (max speed) 63 65

Slow channel (max speed) 63 65

Fast channel (max speed) 66 67

Slow channel (max speed) 66 67

5.5

7.5

4.5

6.5

4.5

7.5

4.5

5.5

2 5

2.5

2 3.5

2.5

4.5

3.5

1.2

1.5

LSB bits dB

190/273

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Table 76. ADC accuracy - limited test conditions 3 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency ≤

80 MHz,

Sampling rate ≤ 5.33 Msps,

1.65 V ≤ V

DDA

3.6 V,

= V

REF+

≤

Voltage scaling Range 1

Single ended

Differential

Fast channel (max speed)

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-69 -67

-71 -67

-72 -71

-72 -71 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Table 77. ADC accuracy - limited test conditions 4 (1)(2)(3)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

ENOB

SINAD

SNR

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

ADC clock frequency ≤

26 MHz,

1.65 V ≤ V

DDA

3.6 V,

= VREF+ ≤

Voltage scaling Range 2

Effective number of bits

Signal-tonoise and distortion ratio

Signal-tonoise ratio

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

1 1.5

1 1.2

2.5

2 2.5

Slow channel (max speed) 2 2.5

Fast channel (max speed) 10.2 10.5

Slow channel (max speed) 10.2 10.5

Fast channel (max speed) 10.6 10.7

Slow channel (max speed) 10.6 10.7

Fast channel (max speed) 63 65 -

Slow channel (max speed) 63 65

Fast channel (max speed) 65 66

Slow channel (max speed) 65 66

Fast channel (max speed) 64 65

Slow channel (max speed) 64 65

Fast channel (max speed) 66 67

Slow channel (max speed) 66 67

5 5.4

3.5

4.5

2 4

2 3.5

4 4.5

1 1.5

LSB bits dB

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Table 77. ADC accuracy - limited test conditions 4 (1)(2)(3) (continued)

Symbol

Parameter Conditions

(4)

Min Typ Max Unit

THD

Total harmonic distortion

ADC clock frequency

26 MHz,

1.65 V ≤ V

DDA

3.6 V,

≤

= VREF+ ≤

Voltage scaling Range 2

Single ended

Differential

Fast channel (max speed) -

Slow channel (max speed) -

Fast channel (max speed) -

Slow channel (max speed) -

-71 -69

-73 -72

-73 -72 dB

1. Guaranteed by design.

2. ADC DC accuracy values are measured after internal calibration.

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

4. The I/O analog switch voltage booster is enable when V

DDA

< 2.4 V). It is disable when V

DDA

< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

≥ 2.4 V. No oversampling.

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Figure 35. ADC accuracy characteristics

SSA

4095

4094

4093

E O

1 LSB

IDEAL

1 2 3 4 5 6 7

(2)

E D

(3)

(1)

E G

4093 4094 4095 4096

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

= total unajusted error : maximum deviation

between the actual and ideal transfer curves.

= offset error : maximum deviation

between the first actual transition and

the first ideal one.

= gain error : deviation between the last

ideal transition and the last actual one.

= differential linearity error : maximum

deviation between actual steps and the ideal ones.

= integral linearity error : maximum deviation

between any actual transition and the end point

correlation line.

DDA

MS19880V2

Figure 36. Typical connection diagram using the ADC

DDA

AIN

(1)

AINx

C parasitic

(2)

I lkg

(3)

Sample and hold ADC converter

ADC

12-bit converter

ADC

MS33900V5

1. Refer to Table 72: ADC characteristics

for the values of R

AIN

and C

ADC

2. C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

Table 66: I/O static characteristics for the value of the pad capacitance). A high

C parasitic

value will downgrade conversion accuracy. To remedy this, f

ADC

should be reduced.

3. Refer to Table 66: I/O static characteristics for the values of I

lkg

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 20: Power supply scheme

. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

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Symbol

DDA

REF+

Parameter

Table 78. DAC characteristics (1)

Analog supply voltage for

DAC ON

Conditions Min

DAC output buffer OFF, DAC_OUT pin not connected (internal connection only)

1.71

Other modes 1.80

Positive reference voltage

DAC output buffer OFF, DAC_OUT pin not connected (internal connection only)

Other modes

1.71

1.80

REF-

BON

BOFF

Negative reference voltage -

Resistive load

Output Impedance

Output impedance sample and hold mode, output buffer ON

Output impedance sample and hold mode, output buffer OFF

Capacitive load

DAC output buffer ON connected to V

SSA connected to V

DDA

DAC output buffer OFF

= 2.7 V

= 2.0 V

= 2.7 V

= 2.0 V

DAC output buffer ON

Sample and hold mode

DAC_OUT t

SETTLING t

WAKEUP

(2)

PSRR

Voltage on DAC_OUT output

DAC output buffer ON

DAC output buffer OFF

±0.5 LSB

Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes when

DAC_OUT reaches final value ±0.5LSB, ±1 LSB,

±2 LSB, ±4 LSB, ±8 LSB)

Normal mode

DAC output buffer ON

CL ≤ 50 pF,

RL ≥ 5 k Ω

±1 LSB

±2 LSB

±4 LSB

±8 LSB

Normal mode DAC output buffer

OFF, ±1LSB, CL = 10 pF

Wakeup time from off state

(setting the ENx bit in the

DAC Control register) until final value ±1 LSB

DDA

supply rejection ratio

Normal mode DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

Normal mode DAC output buffer

OFF, CL ≤ 10 pF

Normal mode DAC output buffer ON

CL ≤ 50 pF, RL = 5 k Ω , DC

0.2

9.6

Typ Max Unit

3.6

DDA

1.7

1.6

1.55

1.48

1.4

SSA

11.7

0.1

13.8

3.5

16.5

18.0

REF+

– 0.2

REF+

2.9

2.85

2.8

2.75

2 2.5

V k Ω k Ω k Ω k Ω pF

µF

µs

4.2

-80

7.5

-28

µs dB

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Symbol

W_to_W t

SAMP

I leak

CI int t

TRIM

V offset

DDA

(DAC)

Table 78. DAC characteristics (1) (continued)

Parameter Conditions Min

Minimal time between two consecutive writes into the

DAC_DORx register to guarantee a correct

DAC_OUT for a small variation of the input code

(1 LSB)

DAC_MCR:MODEx[2:0] =

000 or 001

DAC_MCR:MODEx[2:0] =

010 or 011

Sampling time in sample and hold mode (code transition between the lowest input code and the highest input code when

DACOUT reaches final value ±1LSB)

Output leakage current

CL ≤ 50 pF, RL ≥ 5 k Ω

CL ≤ 10 pF

DAC_OUT pin connected

DAC output buffer

ON, C

= 100 nF

DAC output buffer

OFF, C

= 100 nF

DAC_OUT pin not connected

(internal connection only)

DAC output buffer

OFF

Sample and hold mode,

DAC_OUT pin connected

Internal sample and hold capacitor

Middle code offset trim time DAC output buffer ON

Middle code offset for 1 trim code step

REF+

= 3.6 V

REF+

= 1.8 V

DAC output buffer ON

No load, middle code (0x800)

No load, worst code

(0xF1C)

DAC consumption from

DDA

DAC output buffer OFF

No load, middle code (0x800)

1.4

5.2

Sample and hold mode, C

100 nF

Typ

0.7

10.5

1500

750

315

450

Max

3.5

(3)

670

0.2

315 ₓ

Ton/(Ton

+Toff)

(4)

670 ₓ

Ton/(Ton

+Toff)

8.8

500

Unit

µs ms

µs nA pF

µs

µV

µA

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Symbol

DDV

(DAC)

Table 78. DAC characteristics (1) (continued)

Parameter Conditions Min

DAC output buffer ON

DAC output buffer OFF

No load, middle code (0x800)

No load, worst code

(0xF1C)

No load, middle code (0x800)

DAC consumption from

REF+

Sample and hold mode, buffer ON,

= 100 nF, worst case

Typ

185

340

155

Max

240

400

205

185 ₓ

Ton/(Ton

+Toff)

400 ₓ

Ton/(Ton

+Toff)

Unit

µA

Sample and hold mode, buffer OFF,

= 100 nF, worst case

155 ₓ

Ton/(Ton

+Toff)

205 ₓ

Ton/(Ton

+Toff)

3. Refer to Table 66: I/O static characteristics .

1. Guaranteed by design.

2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0432 reference manual for more details.

Figure 37. 12-bit buffered / non-buffered DAC

Buffered/non-buffered DAC

Buffer

(1)

LOAD

12-bit digital to analog converter

DACx_OUT

LOAD ai17157d

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Symbol

DNL

INL

Parameter

Table 79. DAC accuracy (1)

Conditions

Differential non linearity

(2) monotonicity

Integral non linearity

(3)

DAC output buffer ON

DAC output buffer OFF

10 bits

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

DAC output buffer OFF

CL ≤ 50 pF, no RL

Offset

Offset1

Offset error at code 0x800

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

Offset error at code 0x001

(4)

DAC output buffer OFF

CL ≤ 50 pF, no RL

DAC output buffer OFF

CL ≤ 50 pF, no RL

REF+

= 3.6 V

= 1.8 V

OffsetCal

Gain

TUE

TUECal

SNR

THD

Offset Error at code 0x800 after calibration

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

REF+

= 3.6 V

REF+

= 1.8 V

Gain error

Total unadjusted error

(5)

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

DAC output buffer OFF

CL ≤ 50 pF, no RL

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

DAC output buffer OFF

CL ≤ 50 pF, no RL

Total unadjusted error after calibration

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

Signal-to-noise ratio

Total harmonic distortion

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω

1 kHz, BW 500 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

BW 500 kHz

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω , 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

Min

Typ

guaranteed

Max

±2

±4

±5

±7

±0.5

±30

±12

±25

±8

±5

71.2

71.6

-78

-79

±23

Unit

LSB

LSB dB dB

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Symbol Parameter

Table 79. DAC accuracy (1) (continued)

Conditions Min Typ Max Unit

SINAD

ENOB

Signal-to-noise and distortion ratio

Effective number of bits

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω , 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 k Ω , 1 kHz

DAC output buffer OFF

CL ≤ 50 pF, no RL, 1 kHz

70.4

11.4

11.5

dB bits

1. Guaranteed by design.

2. Difference between two consecutive codes - 1 LSB.

3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.

4. Difference between the value measured at Code (0x001) and the ideal value.

5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (V

REF+

– 0.2) V when buffer is ON.

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Symbol

DDA

REFBUF_

OUT

TRIM

CL esr

I load

I line_reg

I load_reg

Parameter

Table 80. VREFBUF characteristics (1)

Conditions

Analog supply voltage

Voltage reference output

Normal mode

Degraded mode

(2)

Normal mode

Degraded mode

= 0

= 1

= 0

= 1

= 0

= 1

= 0

= 1

Trim step resolution

Load capacitor

Equivalent

Serial Resistor of Cload

Static load current

Line regulation 2.8 V ≤ V

DDA

≤ 3.6 V

I load

= 500 µA

I load

= 4 mA

Load regulation

500 μ A ≤ I load

≤ 4 mA Normal mode

Min

0.5

2.4

2.8

1.65

2.037

2.494

DDA

-150 mV

DDA

-150 mV

Typ

2.042

2.5

±0.05

200

100

Coeff

PSRR t

START

INRUSH

Temperature coefficient

-40 °C < TJ < +125 °C

0 °C < TJ < +50 °C

Power supply rejection

Start-up time

100 kHz

CL = 0.5 µF

(3)

CL = 1.1 µF

CL = 1.5 µF

2. Refer to Table 24: Embedded internal voltage reference

Control of maximum DC current drive on VREFBUF_

OUT during start-up phase

(4)

300

500

650

Max

2.047

2.506

DDA

3.6

2.4

2.8

±0.1

1.5

µF

4 mA

1000

500

500 ppm/V ppm/mA

T coeff_ vrefint +

T coeff_ vrefint

350

650

800 ppm/ °C dB

µs

Unit

Ω mA

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Symbol Parameter

Table 80. VREFBUF characteristics (1) (continued)

Conditions Min Typ Max Unit

DDA

(VREF

BUF)

VREFBUF consumption from V

DDA

I load

= 0 µA

I load

= 500 µA

I load

= 4 mA -

µA

1. Guaranteed by design, unless otherwise specified.

2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (V drop voltage).

DDA

3. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise.

4. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the V the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for V

= 0 and V

= 1.

DDA

voltage should be in

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Symbol Parameter

Table 81. COMP characteristics (1)

Conditions

DDA

Analog supply voltage

Comparator input voltage range

Scaler input voltage

(2)

Scaler offset voltage

BRG_EN=0 (bridge disable)

DDA

(SCALER)

Scaler static consumption from V

DDA t

START_SCALER

Scaler startup time t

START

V t

(3) offset

BRG_EN=1 (bridge enable)

Comparator startup time to reach propagation delay specification

High-speed mode

DDA

≥ 2.7 V

DDA

< 2.7 V

Medium mode

DDA

≥ 2.7 V

DDA

< 2.7 V

Ultra-low-power mode

Propagation delay for

200 mV step with 100 mV overdrive

Comparator offset error

High-speed mode

DDA

≥ 2.7 V

DDA

< 2.7 V

DDA

≥ 2.7 V

Medium mode

DDA

< 2.7 V

Ultra-low-power mode

Full common mode range

V hys

Comparator hysteresis

No hysteresis

Low hysteresis

Medium hysteresis

High hysteresis -

Min Typ Max Unit

1.62

3.6

V 0 V

DDA

0.55

0.65

0.8

100

REFINT

±5

200

±10

300

200

100

0.9

±5 ±20

µs ns

µs mV mV nA

µA

µs

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Symbol

DDA

(COMP)

Table 81. COMP characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit

400 600

Ultra-lowpower mode

Comparator consumption from V

DDA

Medium mode

High-speed mode

Static -

With 50 kHz

±100 mV overdrive square signal

Static -

With 50 kHz

±100 mV overdrive square signal

Static -

With 50 kHz

±100 mV overdrive square signal

1200

100 nA

µA

I bias

Comparator input bias current

1. Guaranteed by design, unless otherwise specified.

3. Guaranteed by characterization results.

4. Mostly I/O leakage when used in analog mode. Refer to I lkg

parameter in Table 66: I/O static characteristics .

(4) nA

Symbol

DDA

CMIR

OFFSET

∆ VI

OFFSET

Parameter

Table 82. OPAMP characteristics (1)

Conditions

Analog supply voltage

Common mode input range

Input offset voltage

Input offset voltage drift

25 °C, No Load on output.

All voltage/Temp.

Normal mode

Low-power mode

TRIMOFFSETP

TRIMLPOFFSETP

TRIMOFFSETN

TRIMLPOFFSETN

Offset trim step at low common input voltage

(0.1 ₓ V

DDA

)

Offset trim step at high common input voltage

(0.9 ₓ V

DDA

)

Min

1.8

Typ

Max

3.6

Unit

±5

±10

DDA

±1.5

±3

V mV

μ V/°C

0.8

1.1

1.35

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248

Electrical characteristics

Symbol

LOAD

LOAD_PGA

LOAD

LOAD_PGA

LOAD

CMRR

PSRR

GBW

(2)

OHSAT

OLSAT

φ m

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Table 82. OPAMP characteristics (1) (continued)

Parameter Conditions Min

Drive current

Drive current in

PGA mode

Normal mode

Low-power mode

Normal mode

Low-power mode

DDA

≥ 2 V

DDA

≥ 2 V

Resistive load

(connected to

VSSA or to

VDDA)

Normal mode

Low-power mode

DDA

< 2 V

Typ

Max

500

100

450

Unit

µA

Resistive load in PGA mode

(connected to

VSSA or to

DDA

)

Capacitive load

Power supply rejection ratio

Low saturation voltage

Phase margin

Normal mode

Low-power mode

Common mode rejection ratio

Normal mode

Low-power mode

Normal mode

Low-power mode

Normal mode

Gain Bandwidth

Product

Low-power mode

Normal mode

Low-power mode

Slew rate

(from 10 and

90% of output voltage)

Open loop gain

Normal mode

Low-power mode

Normal mode

Low-power mode

Normal mode

Low-power mode

High saturation voltage

Normal mode

Low-power mode

Normal mode

Low-power mode

Normal mode

Low-power mode

DDA

< 2 V

4.5

40 -

-85

-90

LOAD

≤ 50 pf,

≥ 4 k Ω DC

LOAD

≤ 50 pf,

≥ 20 k Ω DC

DDA

≥ 2.4 V

(OPA_RANGE = 1)

DDA

< 2.4 V

(OPA_RANGE = 0)

≥ 2.4 V

< 2.4 V

I load

= max or R load min Input at V

DDA

100

DDA

load

= max or R load min Input at 0.

90 -

550 1600 2200

100 420 600

250

700

180

950

280

700

180

300

80 -

110

110 -

100

k Ω pF dB dB kHz

V/ms dB mV

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Symbol

GM t

WAKEUP

I bias

PGA gain

Table 82. OPAMP characteristics (1) (continued)

Parameter Conditions Min

Gain margin

Wake up time from OFF state.

OPAMP input bias current

Normal mode

Low-power mode

Normal mode

Low-power mode

LOAD

≤

≥ follower

50 pf,

4 k Ω configuration

LOAD

≤

≥ follower

50 pf,

20 k Ω configuration

General purpose input (all packages except UFBGA132 and UFBGA169 only)

Dedicated input

(UFBGA132 and

UFBGA169 only)

≤ 75 °C

≤ 85 °C

≤ 105 °C

≤ 125 °C

Non inverting gain value

PGA Gain = 2

R network

R2/R1 internal resistance values in PGA mode

(4)

PGA Gain = 4

PGA Gain = 8

PGA Gain = 16

Delta R

Resistance variation (R1 or

R2)

PGA gain error PGA gain error

Gain = 2

-15

-1

PGA BW

PGA bandwidth for different non inverting gain

Gain = 4

Gain = 8

Gain = 16 -

Typ

GBW/

80/80

120/

140/

150/

Max

(3)

Unit dB

µs nA

k Ω /k Ω

MHz

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Symbol

Table 82. OPAMP characteristics (1) (continued)

Parameter Conditions Min Typ Max Unit en

Voltage noise density

Normal mode

Low-power mode

Normal mode

Low-power mode at 1 kHz, Output loaded with 4 k Ω at 1 kHz, Output loaded with 20 k Ω at 10 kHz, Output loaded with 4 k Ω at 10 kHz, Output loaded with 20 k Ω

500

600

180

290 -

nV/ √

DDA

(OPAMP)

Table 66: I/O static characteristics

OPAMP consumption from V

DDA

Normal mode

Low-power mode no Load, quiescent mode

120

260

100

1. Guaranteed by design, unless otherwise specified.

2. Guaranteed by characterization results.

3. Mostly I/O leakage, when used in analog mode. Refer to I lkg

parameter in

4. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between

OPAMP inverting input and ground. The PGA gain =1+R2/R1

µA

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6.3.26 Temperature sensor characteristics

Symbol

(1)

Avg_Slope

(2)

30 t

START

(TS_BUF)

I t t

S_temp

Table 83. TS characteristics

Parameter

linearity with temperature

Average slope

Voltage at 30°C (±5 °C)

(3)

Sensor Buffer Start-up time in continuous mode

(4)

Start-up time when entering in continuous mode

Table 8: Temperature sensor calibration values .

ADC sampling time when reading the temperature

Temperature sensor consumption from V

DD when selected by ADC

Min

2.3

0.742

Typ

±1

2.5

0.76

4.7

Max

±2

2.7

0.785

120

Unit

°C mV/°C

µs

µA

1. Guaranteed by design.

2. Guaranteed by characterization results.

3. Measured at V

DDA

= 3.0 V ±10 mV. The V

ADC conversion result is stored in the TS_CAL1 byte. Refer to

4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

6.3.27 V

BAT

monitoring characteristics

Symbol

Table 84. V

BAT

monitoring characteristics

Parameter

(1)

Resistor bridge for V

BAT

Ratio on V

BAT

measurement

Error on Q t

S_vbat

conditions summarized in Table 21: General operating conditions

ADC sampling time when reading the VBAT

1. Guaranteed by design.

Min

-10

Typ

Max

Symbol

Table 85. V

BAT

charging characteristics

Parameter Conditions Min Typ

Battery charging resistor

VBRS = 0

VBRS = 1 -

1.5

Max

Unit k Ω

µs

Unit k Ω

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Unless otherwise specified, the parameters given in

Table 86

for DFSDM are derived from tests performed under the ambient temperature, f

APB2

frequency and V

supply voltage

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5 x V

Refer to Section 6.3.17: I/O port characteristics

for more details on the input/output alternate function characteristics (DFSDM1_CKINy, DFSDM1_DATINy, DFSDM1_CKOUT for

DFSDM).

Symbol Parameter

Table 86. DFSDM characteristics (1)

Conditions Min Typ f

DFSDMCLK f f

CKIN

(1/T

CKIN

CKOUT

)

DFSDM clock

Input clock frequency

Output clock frequency

SPI mode (SITP[1:0] =

01)

DuCy

CKOUT

Output clock frequency duty cycle

T t t wh(CKIN) wl(CKIN) t t su h

Manchester

Input clock high and low time

Data input setup time

Data input hold time

SPI mode (SITP[1:0] =

01),

External clock mode

(SPICKSEL[1:0] = 0)

SPI mode

(SITP[1:0]=01),

External clock mode

(SPICKSEL[1:0] = 0)

SPI mode

(SITP[1:0]=01),

External clock mode

(SPICKSEL[1:0] = 0)

Manchester data period

(recovered clock period)

Manchester mode

(SITP[1:0] = 10 or 11),

Internal clock mode

(SPICKSEL[1:0] ≠ 0)

CKIN

(CKOUT

DIV+1) ₓ

DFSDMCLK

1. Data based on characterization results, not tested in production.

0.5

1.5

/2-

CKIN

Max f

SYSCLK

(2 ₓ

CKOUTDIV) ₓ

DFSDMCLK

Unit

MHz

% ns

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Figure 16: DFSDM timing diagram

63,&.6(/

6,73

63,&.6(/

6,73

5HFRYHUHGFORFN

5HFRYHUHGGDWD

06Y9

The parameters given in the following tables are guaranteed by design.

Refer to Section 6.3.17: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Symbol Parameter

Table 87. TIMx (1) characteristics

Conditions Min t t res(TIM) f

EXT

Res

TIM

COUNTER

Timer resolution time

Timer external clock frequency on CH1 to

CH4

TIMxCLK

= 120 MHz

Timer resolution

16-bit counter clock period t

MAX_COUNT

Maximum possible count with 32-bit counter f

TIMxCLK

= 120 MHz

8.33

0 f

TIMxCLK

= 120 MHz

TIMx (except TIM2 and TIM5)

TIM2 and TIM5

1 f

TIMxCLK

= 120 MHz 0.00833

Max

TIMxCLK

Unit t

TIMxCLK ns

MHz

16 bit

65536

546.13

TIMxCLK

µs

65536 × 65536 t

TIMxCLK

35.77

1. TIMx

, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.

Table 88. IWDG min/max timeout period at 32 kHz (LSI) (1)

Prescaler divider PR[2:0] bits

Min timeout RL[11:0]=

0x000

Max timeout RL[11:0]=

0xFFF

Unit

/16

/32

/64

/128

/256

6 or 7

0.125

0.250

0.500

1.0

2.0

4.0

8.0

512

1024

2048

4096

8192

16384

32768 ms

1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.

Prescaler

Table 89. WWDG min/max timeout value at 120 MHz (PCLK)

WDGTB Min timeout value Max timeout value

0.0341

0.0683

0.1356

0.2731

2.1845

4.3691

8.7381

17.4763

Unit ms

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6.3.30 Communication interfaces characteristics

I

C interface characteristics

The I2C interface meets the timings requirements of the I 2 C-bus specification and user manual rev. 03 for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s

• Fast-mode (Fm): with a bit rate up to 400 kbit/s

• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0432 reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and

SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V

DDIOx

is disabled, but is still present. Only FT_f I/O pins support Fm+ low level output current maximum requirement. Refer to

Section 6.3.17: I/O port characteristics for the I2C I/Os characteristics.

All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 90

below for the analog filter characteristics:

Symbol

Table 90. I2C analog filter characteristics

(1)

Parameter t

Maximum pulse width of spikes that are suppressed by the analog filter

1. Guaranteed by design.

2. Spikes with widths below t

AF(min) are filtered.

3. Spikes with widths above t

AF(max)

are not filtered

Min

(2)

Max

260

(3)

Unit ns

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SPI characteristics

Unless otherwise specified, the parameters given in

Table 91

for SPI are derived from tests performed under the ambient temperature, f

PCLKx frequency and supply voltage conditions summarized in

Table 21: General operating conditions .

• Output speed is set to OSPEEDRy[1:0] = 11

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5 x V

Refer to Section 6.3.17: I/O port characteristics

for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI).

Symbol Parameter

Table 91. SPI characteristics

(1)

Conditions

1/t

SCK c(SCK)

SPI clock frequency

Master mode

2.7 V < V

< 3.6 V

Voltage Range V1

Master mode

1.71 V < V

< 3.6 V

Voltage Range V1

Master transmitter mode

1.71 V < V

< 3.6 V

Voltage Range V1

Slave receiver mode

1.71 V < V

< 3.6 V

Voltage Range V1

Slave mode transmitter/full duplex

2.7 V < V

< 3.6 V

Voltage Range V1

Slave mode transmitter/full duplex

1.71 V < V

< 3.6 V

Voltage Range V1

1.71 V < V

< 3.6 V

Voltage Range V2

1.08 V < V

< 1.32 V (3)

Slave mode, SPI prescaler = 2 t su(NSS) t h(NSS) t w(SCKH) t w(SCKL) t su(MI) t su(SI) t h(MI) t h(SI) t a(SO)

NSS setup time

NSS hold time

SCK high and low time Master mode

Data input setup time

Data input hold time

Slave mode, SPI prescaler = 2

Master mode

Slave mode

Master mode

Slave mode

Data output access time Slave mode

Min

4 ₓ T

PCLK

2 ₓ T

PCLK

2.5

5.5

Typ

PCLK

-1 T

PCLK

Max

(2)

Unit

MHz ns ns

PCLK

+1 ns ns ns ns

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Symbol Parameter

Table 91. SPI characteristics (1) (continued)

Conditions Min Typ Max (2) Unit t dis(SO) t v(SO)

Data output disable time Slave mode

Slave mode

2.7 V < V

< 3.6 V

Voltage Range V1

Data output valid time

Slave mode

1.71 V < V

< 3.6 V

Voltage Range V1

Slave mode

1.71 V < V

< 3.6 V

Voltage Range V2

Slave mode

1.08 V < V

< 1.32 V

Master mode

29 39 t v(MO)

2 4 t h(SO)

Data output hold time

Slave mode 1.71 V < V

< 3.6 V

Slave mode 1.08 < V

< 1.32 V

Unless otherwise specified, the parameters given in Table 92 for SAI are derived from tests

Master mode

26 -

t h(MO)

1 -

1. Guaranteed by characterization results.

2. The maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into

SCK low or high-phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50%.

3. SPI mapped on Port G.

ns ns

Figure 38. SPI timing diagram - slave mode and CPHA = 0

NSS input t su(NSS) t w(SCKH) t c(SCK) t r(SCK) t h(NSS)

CPHA=0

CPOL=0

CPHA=0

CPOL=1 t a(SO)

MISO output t w(SCKL)

First bit OUT t h(SI) t v(SO) t h(SO)

Next bits OUT t f(SCK)

Last bit OUT t dis(SO) t su(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V1

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Figure 39. SPI timing diagram - slave mode and CPHA = 1

NSS input t su(NSS) t w(SCKH) t c(SCK) t f(SCK) t h(NSS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO output

MOSI input t a(SO) t w(SCKL) t v(SO) t su(SI)

First bit OUT t h(SI)

First bit IN t h(SO)

Next bits OUT

Next bits IN t r(SCK) t dis(SO)

Last bit OUT

Last bit IN

MSv41659V1

1. Measurement points are done at CMOS levels: 0.3 V

and 0.7 V

Figure 40. SPI timing diagram - master mode

High

NSS input tc(SCK)

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTPUT tsu(MI) tw(SCKH) tw(SCKL)

MSB IN th(MI)

MSB OUT tv(MO)

BIT6 IN

B I T1 OUT th(MO)

1. Measurement points are done at CMOS levels: 0.3 V

and 0.7 V

tr(SCK) tf(SCK)

LSB IN

LSB OUT ai14136c

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SAI characteristics

performed under the ambient temperature, f

PCLKx

frequency and V

supply voltage condi-

tions summarized in Table 21: General operating conditions , with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5 x V

Refer to Section 6.3.17: I/O port characteristics

for more details on the input/output alternate function characteristics (CK,SD,FS).

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Symbol

Table 92. SAI characteristics (1)

Parameter Conditions Max Unit f

MCLK f

SAI Main clock output

SAI clock frequency

(2)

Master transmitter

2.7 V ≤ V

≤ 3.6 V

Voltage Range 1

Master transmitter

1.71 V ≤ V

≤ 3.6 V

Voltage Range 1

Master receiver

Voltage Range 1

Slave transmitter

2.7 V ≤ V

≤ 3.6 V

Voltage Range 1

Slave transmitter

1.71 V ≤ V

≤ 3.6 V

Voltage Range 1

Slave receiver

Voltage Range 1 t v(FS) t h(FS) t su(FS) t h(FS) t su(SD_A_MR) t su(SD_B_SR) t h(SD_A_MR) t h(SD_B_SR) t t v(SD_B_ST) h(SD_B_ST)

FS valid time

FS hold time

FS setup time

FS hold time

Data input setup time

Voltage Range 2

1.08 V ≤ V

≤ 1.32 V

Master mode

2.7 V ≤ V

≤ 3.6 V

Master mode

1.71 V ≤ V

≤ 3.6 V

Master mode

Slave mode

Master receiver

Slave receiver

Master receiver

Data input hold time

Slave receiver

Data output valid time

Slave transmitter (after enable edge)

2.7 V ≤ V

≤ 3.6 V

Slave transmitter (after enable edge)

1.71 V ≤ V

≤ 3.6 V

Slave transmitter (after enable edge)

1.08 V < V

<1.32 V

Data output hold time Slave transmitter (after enable edge)

1.5

2.5

1.5

6.5

2.5

50 MHz

23.5

MHz ns ns ns ns ns ns ns ns

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Symbol

Table 92. SAI characteristics (1) (continued)

Parameter Conditions Max Unit t v(SD_A_MT)

Data output valid time

Master transmitter (after enable edge)

2.7 V ≤ V

≤ 3.6 V

Master transmitter (after enable edge)

1.71 V ≤ V

≤ 3.6 V

Master transmitter (after enable edge)

1.08 V ≤ V

≤ 1.32 V

Data output hold time Master transmitter (after enable edge) t h(SD_A_MT)

1. Guaranteed by characterization results.

2. APB clock frequency must be at least twice SAI clock frequency.

ns ns

Figure 41. SAI master timing waveforms

1/fSCK

SAI_SCK_X th(FS)

SAI_FS_X

(output)

SAI_SD_X

(transmit) tv(FS)

SAI_SD_X

(receive) tsu(SD_MR) tv(SD_MT)

Slot n th(SD_MR)

Slot n+2

Slot n th(SD_MT)

MS32771V1

Figure 42. SAI slave timing waveforms

1/fSCK

SAI_SCK_X tw(CKH_X)

SAI_FS_X

(input)

SAI_SD_X

(transmit) tsu(FS)

SAI_SD_X

(receive) tw(CKL_X) th(FS) tsu(SD_SR) tv(SD_ST)

Slot n th(SD_SR)

Slot n+2

Slot n th(SD_ST)

MS32772V1

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Electrical characteristics

Note:

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

USB OTG full speed (FS) characteristics

The device’s USB interface is fully compliant with the USB specification version 2.0 and is

USB-IF certified (for Full-speed device operation).

Symbol

Table 93. USB electrical characteristics

Parameter Conditions Min

(1)

Typ Max

(1)

Unit

DDUSB

USB OTG full speed transceiver operating voltage

3.0

(2)

3.6

(3)

(3)

Differential input sensitivity

Differential input common mode range

Single ended receiver input threshold

Over VCM range

Includes V range

0.2

0.8

2.5

2.0

Static output level low

Static output level high

of 1.5 k Ω to

3.6 V

(4)

of 15 k Ω to

3.6 V

(4)

2.8

0.3

3.6

(3)

Pull down resistor on PA11,

PA12 (USB_FS_DP/DM)

Pull Up Resistor on PA12

(USB_FS_DP)

Pull Up Resistor on PA12

(USB_FS_DP)

Pull Up Resistor on PA10

(OTG_FS_ID)

= V during idle

= V

SS during reception

14.25

0.9

1.425

1.25

2.25

24.8

1.575

3.09

14.5

1. All the voltages are measured from the local ground potential.

2. The STM32L4S5xx USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full

USB full speed electrical characteristics which are degraded in the 2.7-to-3.0 V V

voltage range.

3. Guaranteed by design.

4. R

is the load connected on the USB OTG full speed drivers.

Ω

When VBUS sensing feature is enabled, PA9 should be left at its default state (floating input), not as alternate function. A typical 200 μ A current consumption of the sensing block

(current to voltage conversion to determine the different sessions) can be observed on PA9 when the feature is enabled.

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Figure 43. USB OTG timings – definition of data signal rise and fall time

Cross over points

Differential data lines

CRS

SS t f t r ai14137b

Table 94. USB OTG electrical characteristics (1)

Driver characteristics

Symbol Parameter Conditions Min Max Unit t rLS t fLS t rfmLS t rFS t fFS t rfmFS

Rise time in LS

Fall time in LS

(2)

(2)

Rise/ fall time matching in LS

Rise time in FS

Fall time in FS

(2)

Rise/ fall time matching in FS

= 200 to 600 pF t r

/ t f

= 50 pF

= 50 pF t r

/ t f

300

125

111

CRS

Output signal crossover voltage

(LS/FS)

Output driver impedance

(3)

1.3

2.0

DRV

Driving high or low 28 44

1. Guaranteed by design

2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching impedance is included in the embedded driver.

% ns

Ω

Symbol

DD(USBBCD)

RDAT_LKG

VDAT_LKG

RDCP_DAT

VLGC_HI

VLGC_LOW

Table 95. USB BCD DC electrical characteristics

(1)

Driver characteristics

Conditions Min Typ Max Unit Parameter

Primary detection mode consumption

Secondary detection mode consumption

Data line leakage resistance

Data line leakage voltage

Dedicated charging port resistance across D+/D-

Logic high

Logic low -

300

0.0

2.0

300

3.6

200

3.6

0.8

μ A k Ω

Ω

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Table 95. USB BCD DC electrical characteristics (1) (continued)

Driver characteristics

Symbol Parameter

VLGC

VDAT_REF

VDP_SRC

VDM_SRC

IDP_SINK

IDM_SINK

1. Guaranteed by design

Logic threshold

Data detect voltage

D+ source voltage

D- source voltage

D+ sink current

D- sink current

Conditions Min Typ Max Unit

0.8

0.25

0.5

2.0

0.4

0.7

175

μ A

CAN (controller area network) interface

Refer to Section 6.3.17: I/O port characteristics

for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX).

Unless otherwise specified, the parameters given in

Table 96

to Table 109

for the FMC interface are derived from tests performed under the ambient temperature, f

HCLK and V

frequency

supply voltage conditions summarized in

Table 21 , with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11

• Capacitive load C = 30 pF

• Measurement points are done at CMOS levels: 0.5 x V

Refer to Section 6.3.17: I/O port characteristics for more details on the input/output

characteristics.

Asynchronous waveforms and timings

Figure 44

through Figure 47 represent asynchronous waveforms and

Table 96 through

Table 103

provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration:

• AddressSetupTime = 0x1

• AddressHoldTime = 0x1

• DataHoldTime = 0x1

• ByteLaneSetup = 0x1

• DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)

• BusTurnAroundDuration = 0x0

In all timing tables, the THCLK is the HCLK clock period.

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Figure 44. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms t w(NE)

FMC_NE t v(NOE_NE) t w(NOE) t h(NE_NOE)

FMC_NOE

FMC_NWE

FMC_A[25:0] t v(A_NE) t v(BL_NE)

Address t h(A_NOE) t h(BL_NOE)

FMC_NBL[1:0] t h(Data_NE) t h(Data_NOE)

FMC_D[15:0] t su(Data_NOE) t su(Data_NE)

Data t v(NADV_NE) t w(NADV)

FMC_NADV (1)

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32753V1

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Table 96. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings (1)(2)

Symbol Parameter Min Max Unit t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t v(A_NE) t h(A_NOE) t su(Data_NE) t su(Data_NOE) t h(Data_NOE) t h(Data_NE) t v(NADV_NE) t w(NADV)

FMC_NE low time

FMC_NEx low to FMC_NOE low

FMC_NOE low time

FMC_NOE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

Address hold time after FMC_NOE high

Data to FMC_NEx high setup time

Data to FMC_NOEx high setup time

Data hold time after FMC_NOE high

Data hold time after FMC_NEx high

FMC_NEx low to FMC_NADV low

FMC_NADV low time

1. CL = 30 pF.

2. Guaranteed by characterization results.

HCLK

-0.5

HCLK

-0.5

HCLK

-1

HCLK

+14

HCLK

+1.5

Table 97. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings (1)(2)

Symbol Parameter Min Max Unit t w(NE)

FMC_NE low time 8T

HCLK

-0.5

HCLK

+1 t w(NOE) t w(NWAIT) t su(NWAIT_NE) t h(NE_NWAIT)

FMC_NWE low time

FMC_NWAIT low time

FMC_NWAIT valid before FMC_NEx high

1. CL = 30 pF.

2. Guaranteed by characterization results.

HCLK

-0.5

HCLK

+0.5

HCLK

+12.5

FMC_NEx hold time after FMC_NWAIT invalid 4T

HCLK

+12 -

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Figure 45. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE)

FMC_NEx

FMC_NOE

FMC_NWE

FMC_A[25:0]

FMC_NBL[1:0]

FMC_D[15:0] tv(NWE_NE) tw(NWE) tv(A_NE) tv(BL_NE) tv(Data_NE) th(A_NWE)

Address th(BL_NWE)

NBL th(Data_NWE)

Data t v(NADV_NE) tw(NADV) t h(NE_NWE)

FMC_NADV (1)

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32754V1

Table 98. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings

(1)(2)

Symbol Parameter Min Max Unit t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t h(A_NWE) t v(BL_NE) t h(BL_NWE) t v(Data_NE) t h(Data_NWE) t v(NADV_NE) t w(NADV)

FMC_NE low time

FMC_NEx low to FMC_NWE low

FMC_NWE low time

FMC_NWE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

Address hold time after FMC_NWE high

FMC_NEx low to FMC_BL valid

FMC_BL hold time after FMC_NWE high

Data to FMC_NEx low to Data valid

Data hold time after FMC_NWE high

FMC_NEx low to FMC_NADV low

FMC_NADV low time

1. CL = 30 pF.

2. Guaranteed by characterization results.

HCLK

-0.5

HCLK

-0.5

HCLK

-0.5

HCLK

-0.5

HCLK

-1

HCLK

-0.5

HCLK

+1.5

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Table 99. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings (1)(2)

Symbol Parameter Min Max Unit t w(NE) t w(NWE) t su(NWAIT_NE) t h(NE_NWAIT)

FMC_NE low time

FMC_NWE low time

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

1. CL = 30 pF.

2. Guaranteed by characterization results.

HCLK

-0.5

HCLK

+1.5

HCLK

-0.5

HCLK

-13 -

HCLK

+13 ns

Figure 46. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE)

FMC_ NE tv(NOE_NE) t h(NE_NOE)

FMC_NOE tw(NOE)

FMC_NWE tv(A_NE) th(A_NOE)

FMC_ A[25:16]

Address tv(BL_NE) th(BL_NOE)

FMC_ NBL[1:0] NBL th(Data_NE)

FMC_ AD[15:0] t v(NADV_NE) t v(A_NE)

Address th(AD_NADV) tw(NADV) tsu(Data_NE) tsu(Data_NOE)

Data th(Data_NOE)

FMC_NADV

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32755V1

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Table 100. Asynchronous multiplexed PSRAM/NOR read timings (1)(2)

Symbol Parameter Min Max t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t v(A_NE) t v(NADV_NE) t w(NADV)

FMC_NE low time

FMC_NEx low to FMC_NOE low

FMC_NOE low time

FMC_NOE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

FMC_NEx low to FMC_NADV low t h(AD_NADV)

FMC_NADV low time

FMC_AD(address) valid hold time after

FMC_NADV high t h(A_NOE) t su(Data_NE) t su(Data_NOE) t h(Data_NE) t h(Data_NOE)

Address hold time after FMC_NOE high

Data to FMC_NEx high setup time

Data to FMC_NOE high setup time

Data hold time after FMC_NEx high

Data hold time after FMC_NOE high

1. CL = 30 pF.

2. Guaranteed by characterization results.

HCLK

-0.5

HCLK

-0.5

HCLK

-0.5

HCLK

-1

0.5

HCLK

-3

HCLK

+14

HCLK

+0.5

1.5

HCLK

+1.5

Unit ns

Table 101. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings (1)(2)

Symbol Parameter Min Max Unit t w(NE) t w(NOE) t su(NWAIT_NE)

FMC_NE low time

FMC_NWE low time

FMC_NWAIT valid before FMC_NEx high

HCLK

-0.5

HCLK

+ 1

HCLK

-0.5

HCLK

+12 -

t h(NE_NWAIT)

FMC_NEx hold time after FMC_NWAIT invalid 4T

HCLK

+11

1. CL = 30 pF.

2. Guaranteed by characterization results.

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Figure 47. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE)

FMC_ NEx

226/273

FMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE)

FMC_NWE

FMC_ A[25:16]

FMC_ NBL[1:0]

FMC_ AD[15:0] t v(NADV_NE) tv(A_NE) tv(BL_NE) t v(A_NE)

Address th(A_NWE)

Address th(BL_NWE)

NBL tv(Data_NADV)

Data th(AD_NADV) tw(NADV) th(Data_NWE)

FMC_NADV

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32756V1

Table 102. Asynchronous multiplexed PSRAM/NOR write timings (1)(2)

Symbol Parameter Min Max t t t w(NE) t v(NWE_NE) t t w(NWE) h(NE_NWE) t v(A_NE) t v(NADV_NE) w(NADV) h(AD_NADV)

FMC_NE low time

FMC_NEx low to FMC_NWE low

FMC_NWE low time

FMC_NWE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

FMC_NEx low to FMC_NADV low

FMC_NADV low time

FMC_AD(adress) valid hold time after

FMC_NADV high t h(A_NWE) t h(BL_NWE) t v(BL_NE) t v(Data_NADV) t h(Data_NWE)

Address hold time after FMC_NWE high

FMC_BL hold time after FMC_NWE high

FMC_NEx low to FMC_BL valid

FMC_NADV high to Data valid

Data hold time after FMC_NWE high

HCLK

-0.5

HCLK

-0.5

HCLK

-0.5

HCLK

+0.5

HCLK

-0.5

0 1

HCLK

+0.5

HCLK

+1.5

HCLK

-3

HCLK

-0.5

HCLK

+0.5

HCLK

Unit ns

DS12024 Rev 4

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Electrical characteristics

1. CL = 30 pF.

2. Guaranteed by characterization results.

Table 103. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings (1)(2)

Symbol Parameter Min Max Unit t w(NE)

FMC_NE low time t w(NWE)

FMC_NWE low time t su(NWAIT_NE) t h(NE_NWAIT)

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

1. CL = 30 pF.

2. Guaranteed by characterization results.

10T

HCLK

-0.5

10T

HCLK

-0.5

HCLK

+0.5

HCLK

+12.5

HCLK

+13

Synchronous waveforms and timings

Table 107

provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration:

• BurstAccessMode = FMC_BurstAccessMode_Enable

• MemoryType = FMC_MemoryType_CRAM

• WriteBurst = FMC_WriteBurst_Enable

• CLKDivision = 1

• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

In all timing tables, the T

HCLK

is the HCLK clock period.

• For 2.7 V ≤ V

≤ 3.6 V, maximum FMC_CLK = 60 MHz for CLKDIV = 0x1 and 54 MHz for CLKDIV = 0x0 at CL = 30 pF (on FMC_CLK).

• For 1.71 V ≤ V

≤ 2.7 V, maximum FMC_CLK = 60 MHz for CLKDIV = 0x1 and

32 MHz for CLKDIV = 0x0 at CL= 20 pF (on FMC_CLK).

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Figure 48. Synchronous multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK)

BUSTURN = 0

FMC_CLK

Data latency = 0 td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx t d(CLKL-NADVL)

FMC_NADV td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16] td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE td(CLKL-ADV)

FMC_AD[15:0] td(CLKL-ADIV) tsu(ADV-CLKH)

AD[15:0] tsu(NWAITV-CLKH)

D1 th(CLKH-ADV) tsu(ADV-CLKH)

D2 th(CLKH-NWAITV) th(CLKH-ADV)

FMC_NWAIT

(WAITCFG = 1b,

WAITPOL + 0b)

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) tsu(NWAITV-CLKH) tsu(NWAITV-CLKH) th(CLKH-NWAITV) th(CLKH-NWAITV)

MS32757V1

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Table 104. Synchronous multiplexed NOR/PSRAM read timings (1)(2)(3)

Symbol Parameter Min Max Unit t w(CLK) t d(CLKL-NExL) t d(CLKH_NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NOEL) t d(CLKH-NOEH) t d(CLKL-ADV) t d(CLKL-ADIV) t su(ADV-CLKH) t h(CLKH-ADV) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NOE low

FMC_CLK high to FMC_NOE high

FMC_CLK low to FMC_AD[15:0] valid

FMC_CLK low to FMC_AD[15:0] invalid

FMC_A/D[15:0] valid data before FMC_CLK high

FMC_A/D[15:0] valid data after FMC_CLK high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. CL = 30 pF.

2. Guaranteed by characterization results.

3. Clock ratio R = (HCLK period /FMC_CLK period).

RxT

HCLK

-0.5

RxT

HCLK

/2 +1

RxT

HCLK

/2 +1

RxT

HCLK

/2 +1

1.5

4 ns

5.5

2.5

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Figure 49. Synchronous multiplexed PSRAM write timings

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230/273

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STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Electrical characteristics

Symbol

Table 105. Synchronous multiplexed PSRAM write timings (1)(2)(3)

Parameter Min Max Unit t w(CLK) t d(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NWEL) t d(CLKH-NWEH) t d(CLKL-ADV) t d(CLKL-ADIV) t d(CLKL-DATA) t d(CLKL-NBLL) t d(CLKH-NBLH) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NWE low

FMC_CLK high to FMC_NWE high

FMC_CLK low to FMC_AD[15:0] valid

FMC_CLK low to FMC_AD[15:0] invalid

FMC_A/D[15:0] valid data after FMC_CLK low

FMC_CLK low to FMC_NBL low

FMC_CLK high to FMC_NBL high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. CL = 30 pF.

2. Guaranteed by characterization results.

3. Clock ratio R = (HCLK period /FMC_CLK period).

RxT

HCLK

- 0.5

RxT

HCLK

/2 +1

RxT

HCLK

/2 +1

RxT

HCLK

/2 +1

RxT

HCLK

/2 +1.5

1.5

4 ns

3.5

5.5

2.5

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Figure 50. Synchronous non-multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK)

FMC_CLK td(CLKL-NExL)

FMC_NEx td(CLKL-NADVL)

Data latency = 0 td(CLKL-NADVH) td(CLKH-NExH)

FMC_NADV td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0] td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE

FMC_D[15:0] tsu(DV-CLKH) tsu(NWAITV-CLKH)

D1 th(CLKH-DV) tsu(DV-CLKH)

D2 th(CLKH-NWAITV) th(CLKH-DV)

FMC_NWAIT

(WAITCFG = 1b,

WAITPOL + 0b)

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) tsu(NWAITV-CLKH) t h(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32759V1

Symbol t w(CLK) t d(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NOEL) t d(CLKH-NOEH) t su(DV-CLKH) t h(CLKH-DV)

Table 106. Synchronous non-multiplexed NOR/PSRAM read timings

(1)(2)(3)

Parameter Min

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK high to FMC_NOE high

FMC_D[15:0] valid data before FMC_CLK high

FMC_D[15:0] valid data after FMC_CLK high

RxT

HCLK

-0.5

RxT

HCLK

/2 +1

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25) RxT

HCLK

/2 +0.5

FMC_CLK low to FMC_NOE low -

RxT

HCLK

/2 +1

Max Unit

5.5

2.5

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STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Electrical characteristics

Table 106. Synchronous non-multiplexed NOR/PSRAM read timings (1)(2)(3) (continued)

Parameter Min Symbol t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. CL = 30 pF.

2. Guaranteed by characterization results.

3. Clock ratio R = (HCLK period /FMC_CLK period).

1.5

Figure 51. Synchronous non-multiplexed PSRAM write timings

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DS12024 Rev 4

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Table 107. Synchronous non-multiplexed PSRAM write timings (1)(2)(3)

Symbol Parameter Min Max Unit t w(CLK) t d(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NWEL) t d(CLKH-NWEH) t d(CLKL-Data) t d(CLKL-NBLL) t d(CLKH-NBLH) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK low to FMC_NWE low

FMC_CLK high to FMC_NWE high

FMC_D[15:0] valid data after FMC_CLK low

FMC_CLK low to FMC_NBL low

FMC_CLK high to FMC_NBL high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. CL = 30 pF.

2. Guaranteed by characterization results.

3. Clock ratio R = (HCLK period /FMC_CLK period).

RxT

FMC_CLK high to FMC_Ax invalid (x=16…25) RxT

RxT

HCLK

1.5

-0.5

/2 +1

/2 +0.5

/2 +1

/2 +1.5

3.5

5.5

2.5

NAND controller waveforms and timings

Figure 52

through Figure 55 represent synchronous waveforms, and Table 108 and

Table 109

provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration:

• COM.FMC_SetupTime = 0x01

• COM.FMC_WaitSetupTime = 0x03

• COM.FMC_HoldSetupTime = 0x02

• COM.FMC_HiZSetupTime = 0x01

• ATT.FMC_SetupTime = 0x01

• ATT.FMC_WaitSetupTime = 0x03

• ATT.FMC_HoldSetupTime = 0x02

• ATT.FMC_HiZSetupTime = 0x01

• Bank = FMC_Bank_NAND

• MemoryDataWidth = FMC_MemoryDataWidth_16b

• ECC = FMC_ECC_Enable

• ECCPageSize = FMC_ECCPageSize_512Bytes

• TCLRSetupTime = 0

• TARSetupTime = 0

In all timing tables, the T

HCLK

is the HCLK clock period.

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STM32L4S5xx, STM32L4S7xx and STM32L4S9xx Electrical characteristics

Figure 52. NAND controller waveforms for read access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NWE t d(NCE-NOE) t h(NOE-ALE)

FMC_NOE (NRE) t su(D-NOE) t h(NOE-D)

FMC_D[15:0]

MSv38003V1

FMC_NCEx

Figure 53. NAND controller waveforms for write access

ALE (FMC_A17)

CLE (FMC_A16) t d(NCE-NWE)

FMC_NWE t h(NWE-ALE)

FMC_NOE (NRE) t v(NWE-D) t h(NWE-D)

FMC_D[15:0]

MSv38004V1

Figure 54. NAND controller waveforms for common memory read access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NWE

FMC_NOE t d(NCE-NOE) t w(NOE) t h(NOE-ALE) t su(D-NOE) t h(NOE-D)

FMC_D[15:0]

MSv38005V1

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Figure 55. NAND controller waveforms for common memory write access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16) t d(NCE-NWE)

FMC_NWE t w(NWE) t h(NOE-ALE)

FMC_NOE t d(D-NWE) t v(NWE-D) t h(NWE-D)

FMC_D[15:0]

MSv38006V1

Table 108. Switching characteristics for NAND Flash read cycles (1)(2)

Symbol Parameter Min Max

T w(N0E)

T su(D-NOE)

T h(NOE-D)

T d(NCE-NOE)

T h(NOE-ALE)

FMC_NOE low width

FMC_D[15-0] valid data before FMC_NOE high

FMC_D[15-0] valid data after FMC_NOE high

FMC_NCE valid before FMC_NOE low

FMC_NOE high to FMC_ALE invalid

1. CL = 30 pF.

2. Guaranteed by characterization results.

HCLK

-0.5 4T

HCLK

+0.5

14 -

0 -

HCLK

-0.5

HCLK

Unit ns

Table 109. Switching characteristics for NAND Flash write cycles

(1)(2)

Symbol Parameter Min Max

T w(NWE)

T v(NWE-D)

T h(NWE-D)

T d(D-NWE)

T d(NCE_NWE)

T h(NWE-ALE)

FMC_NWE low width

FMC_NWE low to FMC_D[15-0] valid

FMC_NWE high to FMC_D[15-0] invalid

FMC_D[15-0] valid before FMC_NWE high

FMC_NCE valid before FMC_NWE low

FMC_NWE high to FMC_ALE invalid

1. CL = 30 pF.

2. Guaranteed by characterization results.

HCLK

-0.5

HCLK

+0.5

5 -

HCLK

-1

-0.5

HCLK

-1

Unit ns

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Unless otherwise specified, the parameters given in

Table 110 ,

Table 111

and

Table 112 for

OctoSPI are derived from tests performed under the ambient temperature, f

AHB

frequency and V

supply voltage conditions summarized in

Table 21: General operating conditions ,

with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11

• Measurement points are done at CMOS levels: 0.5 x V

Refer to Section 6.3.17: I/O port characteristics

for more details on the input/output alternate function characteristics.

Symbol

Table 110. OctoSPI (1) characteristics in SDR mode (2)

Parameter Conditions

F(QCK) t t t t w(CKH) w(CKL) t t s(IN) h(IN) v(OUT) h(OUT)

1.71 V < V

< 3.6 V

Voltage Range 1

LOAD

= 20 pF

2.7 V < V

LOAD

< 3.6 V

Voltage Range 1

= 20 pF

OctoSPI clock frequency

1.71 V < V

< 3.6 V

Voltage Range 1

LOAD

= 15 pF

1.71 V < V

< 3.6 V

Voltage Range 2

LOAD

= 20 pF

OctoSPI clock high and low time

Prescaler = 0

Data input setup time

Data input hold time

Data output valid time

Data output hold time

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2

1. Values in the table applies to Octal and Quad SPI mode.

2. Guaranteed by characterization results.

Min

(CK)

/2-1 t

(CK)

/2-1

0.5

7.75

10.5

Typ

Max

26 t

(CK)

/2 t

(CK)

3.5

5.5

Unit

MHz ns

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Symbol

Table 111. OctoSPI (1) characteristics in DTR mode (no DQS) (2)

Parameter Conditions

1/t

(CK)

OctoSPI clock frequency

1.71 V < V

< 3.6 V

Voltage Range 1

LOAD

= 20 pF

2.7 V < V

< 3.6 V

Voltage Range 1

LOAD

= 20 pF

1.71 V < V

< 3.6 V

Voltage Range 1

LOAD

= 15 pF

1.71 V < V

< 3.6 V

Voltage Range 2

LOAD

= 20 pF t w(CKH) t w(CKL)

OctoSPI clock high and low time

t t t t sf(IN) sr(IN) hf(IN) hr(IN)

Data input setup time

Data input hold time

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2 t t t t vr(OUT) vf(OUT) hr(OUT) hf(OUT)

Data output valid time

Data output hold time

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2

1. Values in the table applies to Octal and Quad SPI mode.

2. Guaranteed by characterization results.

DHQC = 0

DHQC = 1

Pres=1,2 ...

DHQC = 0

DHQC = 1

Pres=1,2 ...

DHQC = 0

Min

(CK)

/2-1 t

(CK)

/2-1

0.5

7.75

10.75

1 tpclk/4-2

3.5

Typ

4.5

8.5

tpclk/4+1

Max

26 t

(CK)

/2+0.5

(CK)

/2+0.5

6 tpclk/4+3

Unit

MHz ns

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Table 112. OctoSPI characteristics in DTR mode (with DQS) (1) /Octal and HyperBus™

Symbol Parameter Conditions Min Typ Max

(2)

Unit

1/t

(CK)

OctoSPI clock frequency

(Octal Flash and

HyperFlash™)

OctoSPI clock frequency

(HyperRAM™)

1.71 V < V

< 3.6 V

Voltage Range 1

LOAD

= 20 pF

2.7 V < V

< 3.6 V

Voltage Range 1

LOAD

= 20 pF

1.71 V < V

< 3.6 V

Voltage Range 1

LOAD

= 15 pF

1.71 V < V

< 3.6 V

Voltage Range 2

LOAD

= 20 pF

1.71 < V

< 3.6 V

Voltage Range V1

LOAD

= 20 pF t

CKDS

= 9ns

Prescaler =

0,1,3,5...

Prescaler =

2,4,6...

2.7 < V

< 3.6 V

Voltage Range V1

LOAD

= 20 pF t

CKDS

= 9ns

1.71 < V

< 3.6 V

Voltage Range V2

LOAD

= 20 pF t

CKDS

= 9ns

Prescaler =

0,1,3,5...

Prescaler =

2,4,6...

MHz

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Electrical characteristics STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

Table 112. OctoSPI characteristics in DTR mode (with DQS) (1) /Octal and HyperBus™ (continued)

Symbol Parameter Conditions Min Typ Max (2) Unit t w(CKH) t w(CKL) t t t t v(CK) h(CK) w(CS) v(DQ)

OctoSPI clock high and low time

Clock valid time

Clock hold time

Chip select high time

Data input vallid time t t v(DS) h(DS)

Data storbe input valid time

Data storbe input hold time t v(RWDS)

Data storbe output valid time

t t

(CK) t

(CK)

/2-0.5

3 x t

/2-1

/2-0.5

(CK)

t t t t t t sr(IN) sf(IN) hr(IN) hf(IN) vr(OUT) vf(OUT)

Data input setup time

Data input hold time

Data output valid time

Voltage Range 1

Voltage Range 2

Voltage Range 1

Voltage Range 2

Voltage Range 1

DHQC = 0

DHQC = 1

Pres=1,2 ...

Voltage Range 2 DHQC = 0

-3.5

-5.5

5.75

t t hr(OUT) hf(OUT)

Data output hold time

Voltage Range 1

DHQC = 0

DHQC = 1

Pres=1,2 ...

Voltage Range 2 DHQC = 0

0.5

tpclk/4-1.75

0.75

1. Guaranteed by characterization results.

2. Maximum frequency values are given for a RWDS to DQ skew of maximum +/-1.0 ns.

3. Data input setup time maximum does not take into account Data level switching duration.

4.5

tpclk/4+1.

(CK)

/2+0.5

(CK)

/2+0.5

(CK)

3 x t

(CK) t

(CK)

/2-5.75

(3) t

(CK)

/2-9