STMicroelectronics TSC2011 Datasheet
विज्ञापन
विज्ञापन
TSC2010, TSC2011, TSC2012
Datasheet
High voltage, precision, bidirectional current sense amplifiers
SO8
MiniSO8
Maturity status link
TSC2010 , TSC2011 , TSC2012
Features
• Wide common mode voltage: - 20 to 70 V
• Offset voltage: ± 200 µV max
• 2.7 to 5.5 V supply voltage
• Different gain available
– TSC2010: 20 V/V
– TSC2011: 60 V/V
– TSC2012: 100 V/V
• Gain error: 0.3% max
• Offset drift: 5 µV/°C max
• Quiescent current: 20 µA in shutdown mode
• SO8 and MiniSO8 package
Applications
• High-side current sensing
• Low-side current sensing
• Data acquisition and instrumentation
• Test and measurement equipment
• Industrial process control
• Motor control
• Solenoid control
Description
The TSC2010 , TSC2011 and TSC2012 are precision bidirectional current sense amplifiers. They can sense the current thanks to a shunt resistor over a wide range of common mode voltages, from - 20 to + 70 V, whatever the supply voltage is. They are available with an amplifier gain of 20V/V for TSC2010 , 60 V/V for TSC2011 and
100 V/V for TSC2012 .
They are able to sense very low drop voltages as low as 10 mV full scale minimizing the measurement error.
The TSC2010 , TSC2011 and TSC2012 can also be used in other functions such as: precision current measurement, overcurrent protection, current monitoring, and feedback loops.
This device fully operates over the broad supply voltage range from 2.7 to 5.5 V and over the industrial temperature range from -40 to 125 °C.
DS13057 - Rev 6 - September 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1 Diagram
Figure 1. Block diagram
TSC2010, TSC2011, TSC2012
Diagram
DS13057 - Rev 6 page 2/53
2 Pin configuration
Figure 2. Pin connection (top view)
TSC2010, TSC2011, TSC2012
Pin configuration
Pin
3
4
1
2
5
6
7
8
Pin name
IN -
GND
VREF2
SHDN
OUT
VCC
VREF1
IN +
Table 1. Pin description
Description
Negative input
Ground
Reference voltage 2
Shutdown
Output
Supply voltage
Reference voltage 1
Positive input
DS13057 - Rev 6 page 3/53
3
TSC2010, TSC2011, TSC2012
Maximum ratings
Maximum ratings
Table 2. Absolute maximum ratings
Symbol
V
CC
V
ICM
V
DIF
V
REF1
V
REF2
V
OUT
I
IN
T
STG
T
J
R
THJA
ESD
Supply voltage
Storage temperature
Parameter
Common mode voltage on input pins
Differential voltage between input pins (In+, In-)
Voltage present on pins Ref1, Ref2, Out
Input current to any pins
Junction temperature
Thermal resistance junction to ambient
SO8
MiniSO8
Human body model (HBM)
Charged device model (CDM)
Latch-up immunity
Value
-0.3 to 7
-25 to 76
7
Gnd - 0.3 to V cc
+ 0.3
5
-65 to 150
150
125
190
2000
1000
200
Unit
V
V
V
V mA
°C
°C
°C/W
V mA
1. All voltage values, except the differential voltage are with respect to the network ground terminal.
2. Input voltage can go beyond supply voltage but input current must be limited. Using a serial resistor with the input is highly recommended in that case.
3. Short-circuits can cause excessive heating and destructive dissipation.
4. R th
are typical values.
5. According to JEDEC standard JESD22-A114F.
6. According to ANSI/ESD STM5.3.1.According to ANSI/ESD STM5.3.1.
Symbol
V cc
V icm
V ref
T
Table 3. Operating conditions
Parameter
Supply voltage
Common mode voltage on input pins
Output offset adjustment range
Operating free-air temperature range
Value
2.7 to 5.5
-20 to +70
0 to V cc
-40 to 125
Unit
V
V
V
°C
DS13057 - Rev 6 page 4/53
4
TSC2010, TSC2011, TSC2012
Electrical characteristics
Electrical characteristics
Table 4. Electrical characteristics V cc
= 2.7 V, V icm
= 12 V, T = 25 °C (unless otherwise specified).
Symbol Parameter Conditions Min.
Typ.
Max.
Unit
Power supply
I cc
Current consumption
Current consumption with shutdown active
V icm
= -20 to 70 V
T min
< T < T max
V icm
= - 20 to 70 V
T min
< T < T max
Input os
|ΔV os
|V
|V
CMR
I
I ib+ ib-
|
/ΔT| sense
|
Offset drift vs. temperature
Common mode rejection
Input bias current
Input bias current
Vsense operating range with
V icm
= 1 V
T min
< T < T max
V icm
= 12 V
T min
< T < T max
V icm
= 1 V, T min
< T < T max
V icm
= 12 V, T min
< T < T max
V icm
= -20 to 70 V, DC mode
T min
< T < T max
V icm
= 12 V
T min
< T < T max
, V icm
= -20 to 70 V
V icm
= 12 V
T min
< T < T max
, V icm
= - 20 to 70 V
TSC2010
T min
< T < T max
TSC2011
T min
< T < T max
TSC2012
T min
< T < T max
Output
G
Eg
ΔEg/ΔT
V
NLE cc
- V oh
Gain
Gain error vs. temperature
Gain error drift
Linearity error
Drop voltage output high
TSC2010
TSC2011
TSC2012
ΔV out
= 100 mV to (V cc
- 100 mV)
T min
< T < T max
T min
< T < T max
V icm
= 12 V
I source
= 0.2 mA
T min
< T < T max
90
85
-400
-150
1.5
20
115
350
100
20
60
100
0.03
8
2.3
2.3
50
150
200
700
500
1100
5
8
600
350
123.6
122.4
40.5
39.3
23.9
22.7
0.3
0.3
25
15
20 mA
µA
µV
µV/°C dB
µA mV
V/V
% ppm/°C
% mV
DS13057 - Rev 6 page 5/53
DS13057 - Rev 6
TSC2010, TSC2011, TSC2012
Electrical characteristics
Symbol
I
V ol out
Parameter
Output voltage low
Output current
Conditions
I sink
= 0.2 mA
T min
< T < T max
Sink mode
T min
< T < T max
Source mode
T min
< T < T max
I out
= - 10 to +4 mA Reg Load Load regulation
OFFSET adjustment
R t
Acc
T
T on off
Ratiometric accuracy
Accuracy, RTO
Shutdown function (active high)
V il
V ih
I ih
Logical low level
Logical high level
Leakage current
Turn-on time
Turn-off time
Voltage applied to Vref1 and Vref2 in parallel
Dynamic performances
BW
SR
E n
Small signal -3 dB bandwidth
R l
= 10 kΩ, C l
= 100 pF
TSC2010
TSC2010, T min
< T < T max
TSC2011
TSC2011, T min
< T < T max
TSC2012
TSC2012, T min
< T < T max
R l
= 10 kΩ, C l
= 100 pF, V icm
= 1 V
TSC2010, Vsense = 120 mV
Slew rate
Noise, RTI
Spectral density, RTI
TSC2010, T min
< T < T max
TSC2011, Vsense = 40 mV
TSC2011, T min
< T < T max
TSC2012, Vsense = 24 mV
TSC2012, T min
< T < T max
0.1 Hz to 10 Hz f = 1 kHz
V shdn
= V cc
(Shutdown mode)
V shdn
= 2.7 V to 0 V, R l
= 10 kΩ
TSC2011
TSC2010, TSC2012
V shdn
= 0 V to 2.7 V, R l
= 10 kΩ
TSC2011
TSC2010, TSC2012
Min.
12
8
6
4
0
0.7xV
cc
3.0
2.7
2.7
2.5
2.0
1.8
600
300
500
250
330
170
Typ.
12
20
10
0.3
0.5
0.1
750
620
415
3.9
3.5
2.8
37
100
0.9
6
8
4
5
0.3xV
cc
V cc
Max.
20
30
25
30
14
17
1.5
Unit mV mA mV/mA
V/V
% kHz
V/µs
µVpp nV/√Hz
V
µA
µs
µs page 6/53
Symbol
I out
Parameter
Output leakage current
1. RTI stands for “Related to input”.
2. V sense
=(V in+
) – (V in-
).
Shdn active
Conditions
TSC2010, TSC2011, TSC2012
Electrical characteristics
Min.
Typ.
50
Max.
Unit nA
DS13057 - Rev 6 page 7/53
DS13057 - Rev 6
TSC2010, TSC2011, TSC2012
Electrical characteristics
Table 5. Electrical characteristics (V cc
= 5 V, V icm
= 12 V, T = 25 °C unless otherwise specified)
Symbol Parameter Conditions Min.
Typ.
Max.
Unit
Power supply
I cc
SVR
Current consumption
Current consumption with shutdown active
Supply voltage rejection
V icm
= -20 to 70 V
T min
< T < T max
V icm
= - 20 to 70 V
T min
< T < T max
V cc
= 2.7 to 5.5 V
T min
< T < T max
80
75
1.6
20
100
2.4
2.4
50
150 mA
µA dB
Input os
|ΔV os
|V
|V
CMR
I
I ib+ ib-
|
/ΔT| sense
|
Offset drift vs. temperature
Common mode rejection
Input bias current
Input bias current
Vsense operating range with
V icm
= 1 V
T min
< T < T max
V icm
= 12 V
T min
< T < T max
V icm
= 1 V, T min
< T < T max
V icm
= 12 V, T min
< T < T max
V icm
= -20 to 70 V, DC mode
T min
< T < T max
V icm
= 12 V
T min
< T < T max
, V icm
= -20 to 70 V
V icm
= 12 V
T min
< T < T max
, V icm
= - 20 to 70 V
TSC2010
T min
< T < T max
TSC2011
T min
< T < T max
TSC2012
T min
< T < T max
Output
G
Eg
ΔEg/ΔT
V
NLE cc
- V oh
Gain
Gain error vs. temperature
Gain error drift
Linearity error
Drop voltage output high
TSC2010
TSC2011
TSC2012
ΔV out
= 100 mV to (V cc
- 100 mV)
T min
< T < T max
T min
< T < T max
V icm
= 12 V
I source
= 0.2 mA
T min
< T < T max
90
85
-400
-150
120
350
100
20
60
100
0.03
15
200
700
500
1100
5
8
600
350
238.3
237.1
78
77.6
46.9
45.7
0.3
0.3
25
30
35
µV
µV/°C dB
µA mV
V/V
% ppm/°C
% mV page 8/53
DS13057 - Rev 6
TSC2010, TSC2011, TSC2012
Electrical characteristics
Symbol
I
V ol out
Parameter
Output voltage low
Output current
Conditions
I sink
= 0.2 mA
T min
< T < T max
Sink mode
T min
< T < T max
Source mode
T min
< T < T max
I out
= -10 to +10 mA Reg Load Load regulation
OFFSET adjustment
R t
Acc
T
T on off
Ratiometric accuracy
Accuracy, RTO
Shutdown function (active high)
V il
V ih
I ih
Logical low level
Logical high level
Leakage current
Turn-on time
Turn-off time
Voltage applied to Vref1 and Vref2 in parallel
Dynamic performance
BW
SR
E n
Small signal -3 dB bandwidth
R l
= 10 kΩ, C l
= 100 pF
TSC2010
TSC2010, T min
< T < T max
TSC2011
TSC2011, T min
< T < T max
TSC2012
TSC2012, T min
< T < T max
R l
= 10 kΩ, C l
= 100 pF, V icm
= 1 V
TSC2010, Vsense = 230 mV
Slew rate
Noise, RTI
Spectral density, RTI
TSC2010, T min
< T < T max
TSC2011, Vsense = 78 mV
TSC2011, T min
< T < T max
TSC2012, Vsense = 47 mV
TSC2012, T min
< T < T max
0.1 Hz to 10 Hz f = 1 kHz
V shdn
= V cc
(Shutdown mode)
V shdn
= 5 V to 0 V, R l
= 10 kΩ
TSC2011
TSC2010, TSC2012
V shdn
= 0 V to 5 V, R l
= 10 kΩ
TSC2011
TSC2010, TSC2012
Min.
0
0.7xV
cc
650
330
600
300
390
200
25
15
12
8
5.7
4.4
5.4
4.1
4.4
3.2
Typ.
26
36
25
0.3
0.5
0.1
820
750
490
7.5
7
5.2
37
100
1.2
6
8
4
5
0.3xV
cc
V cc
Max.
40
50
50
60
45
55
1.5
Unit mV mA mV/mA
V/V
% kHz
V/µs
µVpp nV/√Hz
V
µA
µs
µs page 9/53
Symbol
I out
Parameter
Output leakage current
1. RTI stands for “Related to input”.
2. V sense
= (V in+
) – (V in-
).
Shdn active
Conditions
TSC2010, TSC2011, TSC2012
Electrical characteristics
Min.
Typ.
50
Max.
Unit nA
DS13057 - Rev 6 page 10/53
TSC2010, TSC2011, TSC2012
Typical characteristics
4.1
Typical characteristics
TSC2011 is used for typical characteristics, unless otherwise noted.
Figure 3. Supply current vs. supply voltage
1.9
Vicm=2.5V
1.7
Vicm=0V
Vicm=12V
1.5
Vicm=70V
Vref=Vcc/2
Vsense=0V
T=25°C
1.3
2.8
3.1
3.5
3.9
4.2
4.5
4.9
5.3
Supply voltage (V)
1.3
-20 -10
Figure 4. Supply current vs. input common mode
1.9
Vref=Vcc/2
Vsense=0V
T=25°C
1.7
1.5
Vcc=5V
Vcc=3.3V
Vcc=2.7V
10 30
Vicm (V)
50 70
1.9
Figure 5. Supply current vs. temperature
Vicm= -20V
1.7
Vicm=0V
Vicm=12V
Vicm=48V
1.5
Vref=Vcc/2
Vsense=0V
Vcc=5V
1.3
-40 -20
Vicm=70V
20 40 60
Temperature (°C)
80 100 120
Figure 6. Supply current vs. input common mode with active shutdown mode
22
18
14
Vcc=5V
Vcc=3.3V
10
6 Vref=Vcc/2
SHDN=Vcc
Vsense=0V
T=25°C
2
-20 -10 10 30
Vicm (V)
Vcc=2.7V
50 70
DS13057 - Rev 6 page 11/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 7. Input bias current vs. input common mode with shutdown active
Figure 8. Input bias current vs. temperature V
CC
= 2.7 V
300
Iibp
100
Iibn
-100
-300
Vref=Vcc/2
SHDN=Vcc
Vsense=0V
T=25 °C
Vcc=2.7 to 5.5V
-20 -10 0 10 20 30 40 50 60 70
Vicm (V)
500
300 Iibp 25°C Iibp -40 °C
100
-100
Iibn [-40° : 125°]
-300
-500
20 -10 0
Iibp 125°C
Vref=V
CC
/2
Vsense=0V
Vcc=2.7V
10 20 30 40 50 60 70
Vicm (V)
Figure 9. Input bias current vs. temperature with V
CC
= 5 V
500
300 Iibp -40 °C
100
Iibp 25°C
-100
Iibn [ -40 °:125 °]
-300
-500
-20 -10 0
Iibp 125 °C
10 20 30 40 50 60 70
Vicm (V)
Vref=Vcc/2
Vsense=0V
Vcc=5V
Figure 10. Input offset voltage vs. temperature
700
500
300
100
100
200
300
-
-
400
500
Vref=Vcc/2
Vsense=0V
Vcc=5V
600
700
40 -20
Vicm=48V
Vicm= -20V
Vicm=0V
Vicm=12V
Vicm=70V
20 60
Temperature (°C)
80 100 120
DS13057 - Rev 6 page 12/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 11. Input offset voltage vs. input common mode with V
CC
= 2.7 V
700
600
500
400
300
200
100
0
-100
-200
-300
T=-20°C
-400
-500
-600
Vref=Vcc/2
Vsense=0V
Vcc=2.7V
-700
-20 -10 0
T=-40°C
T=125°C
T=25°C
T=85°C
T=0°C
10 20 30 40 50 60 70
Vicm (V)
Figure 12. Input offset voltage vs. input common mode with V
CC
= 5 V
700
500
300
100
-100
T=-40°C
-300
-500
Vref=Vcc/2
Vsense=0V
Vcc=5V
-700
-20 -10 0
T=125 °C
T=25 °C
T=-20°C
T=85 °C
T=0°C
10 20 30 40 50 60 70
Vicm (V)
Figure 13. Input offset voltage vs. supply voltage
500
300
Vicm=5V
Vicm=12V
100
-100
Vicm=1V
Vicm=48V
Vicm=70V
-300
Vicm= -20V
Vicm= -10V
Vref=Vcc/2
Vsense=0V
T=25°C
-500
Vcc (V)
Figure 14. Output current vs. output voltage
35
Isink
25
15
Vcc=2.7V
Vcc=3.3V
Vcc=5.5V
5
-5
-15
-25
-35
Isource
Vref=Vcc/2
Vsense=100mV
Vicm=12V
T=25°C
-40
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Vout (V)
DS13057 - Rev 6 page 13/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 15. Output current vs. temperature with V
CC
= 5 V Figure 16. Output current vs. temperature with V
CC
= 2.7 V
50
45
40
35
30
25
20
15
Isource
Isink
10
5
Vcc=5V
Vicm=12V
Vref=Vcc/2
Vsense=100mV
0
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
50
45
40
35
30
Vcc=2.7V
Vicm=12V
Vref=Vcc/2
Vsense=100mV
25
20
15
10
Isink
5
0
-40 -20 0
Isource
20 40 60
Temperature (°C)
80 100 120
Figure 17. V oh
and V ol
vs. input common mode voltage with V
CC
= 5 V
43
Vcc=5V; Vref=Vcc/2
Vsense= 100mV
Rl=10k Ω connected to Vcc/2
T=25 °C
26 V
OL
V
OH
9
20 -10 0 10 20 30 40 50 60 70
Vicm (V)
Figure 18. (Output voltage + V ref
) vs. V sense unidirectionnal with V
CC
= 5 V
5.4
4.2
Vref=0V
Vcc=5V
T=25 °C
Unidirectionnal
3.0
1.8
0.6
-0.6
-10 0 10 20 30 40 50 60 70 80 90
Vsense (mV)
DS13057 - Rev 6 page 14/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 19. (Output voltage + V ref
) vs. V sense
bidirectionnal with V
CC
= 5 V
Figure 20. Output rail linearity vs. load with V
CC
= 5 V
5.4
4.2
Vref=Vcc/2
Vcc=5V
T=25 °C
Bidirectionnal
3.0
1.8
0.6
-0.6
-20 0 10 20 30 40 50
Vsense (mV)
Vcc=5V
Vicm=12V
Vref=Vcc/2
T=25°C
Rl=1k Ω
Rl=4.7k
Ω
Rl=2k Ω
Rl=10k Ω
No load
Vsense (mV)
Figure 21. Linearity vs. V
Vicm=-10V sense
with V
Vicm=1V
CC
= 5 V
Vicm=12V
Vref=Vcc/2
Vcc=5V
T=25°C
-50 -40 -30 -20 -10 0 10 20 30 40 50
Vsense (mV)
Figure 22. Linearity vs. V sense
and temperature
0.15
0.12
0.09
0.06
0.03
0.00
T=25°C
-0.03
T=-40°C
-0.06
T=125°C
-0.09
-0.12
Vref=Vcc/2
Vcc=5V
Vicm=12V
-0.15
-50 -40 -30 -20 -10 0 10 20 30 40 50
Vsense (mV)
DS13057 - Rev 6 page 15/53
Figure 23. Gain error vs. input common mode
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
-0.25
Vref=Vcc/2
T=25°C
-0.30
-20 -10 0
Vcc=3.3V
Vcc=5V
Vcc=2.7V
10 20 30 40 50 60 70
Vicm (V)
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 24. Gain error vs. input common mode and temperature
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
-0.25
Vref=Vcc/2
Vcc=5V
-0.30
-20 -10 0
T=125°C
T=-40°C
T=25°C
10 20 30 40 50 60 70
Vicm (V)
Figure 25. Load regulation with V
CC
= 5 V
1.30
Isource Isink
1.25
Vicm=70V
Vicm=12V
1.20
1.15
1.10
-15.0
Vicm=-20V
Vicm=0V
-10.0
-5.0
0.0
Iout (mA)
5.0
Vref=Vcc/2
Vsense=19.8mV
Vcc=5V
T=25°C
10.0
15.0
Figure 26. Gain vs. frequency
40
20
0
Vcc = 2.7 V
Vcc = 3.3 V
Vcc = 5 V
-20
-40
1
Vicm = 12 V, Vref = Vcc / 2
Rl = 10kΩ , Cl = 100 pF connected to Vcc / 2
10 100
Frequency (kHz)
1000 10000
DS13057 - Rev 6 page 16/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 27. Gain vs. frequency V
CC
= 5 V
40
20
0
TSC2010
TSC2012
TSC2011
-20
-40
Vcc = 5 V, Vicm = 12 V, Vref = Vcc/2
Rl = 10kΩ , Cl = 10 pF connected to Vcc/2
1 10 100
Frequency (kHz)
1000 10000
Figure 28. Gain vs. frequency different capacitive load
40
CI = 100 pF
20
0
CI = 330 pF
CI = 470 pF
-20
-40
1
Vcc=5V, Vicm=12V, Vref=Vcc/2
RI=10kΩ connected to Vcc/2
10 100
Frequency (kHz)
1000 10000
Figure 29. Gain vs. frequency different capacitive load
(TSC2010)
Figure 30. Gain vs. frequency different capacitive load
(TSC2012)
40
20
Cl = 330 pF
0
Cl = 470 pF
Cl = 680 pF
-20
-40
1
Vcc = 5 V, Vicm = 12 V, Vref = Vcc/2
Rl = 10 kΩ connected to Vcc/2
10 100 1000
Frequency (kHz)
Cl = 100 pF
10000
40
20
0
Cl = 330 pF
Cl = 470 pF
Cl = 680 pF
-20
-40
1
Vcc = 5 V, Vicm = 12 V, Vref = Vcc / 2
RI = 10kΩ connected to Vcc / 2
10 100 1000
Frequency (kHz)
Cl = 100 pF
10000
DS13057 - Rev 6 page 17/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 31. Bandwidth vs. input common mode
1.1M
1.0M
900.0k
800.0k
T = -40°C
T = 25°C
700.0k
600.0k
T =125°C
500.0k
400.0k
300.0k
200.0k
100.0k
Vref=Vcc/2
Vcc=5V
Rl=10kΩ , Cl=100pF connected to Vcc/2
0.0
-20 -10 0 10 20 30 40 50
Vicm (V)
60 70
Figure 32. Bandwidth vs. input common mode (TSC2010)
1.1M
900.0k
T = -40 °C
T = 25 °C
700.0k
T = 125 °C
500.0k
300.0k
100.0k
Vref = Vcc/2
Vcc = 5 V
Rl = 10 kΩ ,Cl = 100 pF connected to Vcc/2
-20 -10 10 30
Vicm (V)
50 70
Figure 33. Bandwidth vs. input common mode (TSC2012)
900.0k
800.0k
700.0k
600.0k
500.0k
400.0k
T=-40°C
T=25°C
T=125°C
300.0k
200.0k
100.0k
Vref=Vcc/2
Vcc=5V
Rl=10kΩ , Cl=100pF connected to Vcc/2
0.0
-20 -10 0 10 20 30 40 50 60 70
Vicm (V)
Figure 34. Overshoot vs. capacitive load
40
35
30
25
20
15
10
5
TSC2011
Vsensestep=10mVpp
TSC2010
Vsensestep=30mVpp
100
TSC2012
Vsensestep=6mVpp
-
Vcc = 5 V,
Vref=Vcc/2, Vicm[-20V:70V],
Rl = 10 k Ω, Cl connect to Gnd
200 300 400 500
Capacitive load (pF)
600 700
DS13057 - Rev 6 page 18/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 36. Small signal response with V
CC
= 5 V
(TSC2010)
Figure 35. Small signal response with V
CC
= 5 V
1.0
50
0.5
Vout
0.0
-0.5
-1.0
-60µ
25
Vsense
0
-25
Vcc=5V, Vicm=12V, Vsense=10mVpp
T=25°C, Cl=100pF
-40µ -20µ 0
Time (s)
-50
20µ
Figure 37. Small signal response with V
CC
= 5 V
(TSC2012)
1.0
50
Vout
0.5
25
0.0
-0.5
-1.0
-60µ
0
Vsense
Vcc = 5 V, Vicm = 12 V, Vsense = 6 mVpp
T = 25 °C, Cl = 100 pF
-40µ -20µ 0
Time (s)
-25
20µ
-50
Figure 38. Small signal response with V
CC
= 2.7 V
1.0
50
0.5
Vout
0.0
25
Vsense
0
-0.5
-1.0
-60µ
-25
Vcc=2.7V, Vicm=12V, Vsense=10mVpp
T=25°C, Cl=100pF
-40µ -20µ 0
Time (s)
20µ
-50
DS13057 - Rev 6 page 19/53
Figure 39. Large signal response with V
CC
= 5 V
-1
-2
-3
-5µ
3
2
1
0
Vsense
0
Vcc=5V,
Vicm=12V,
Vsense=80mVpp
Cl=100pF,
T=25°C
5µ
Time (s)
10µ
50
25
Vout
0
-25
15µ
-50
Figure 41. Large signal response with V
CC
= 5 V
(TSC2012)
3
2
1
0
Vsense
-1
-2
-3
-5µ 0
Vcc = 5 V,
Vicm = 12 V,
Vsense = 45 mVpp
Cl = 100 pF,
T = 25°C
10µ
Vout
150
25
0
-25
125
100
75
50
-50
-75
-100
-125
-150
15µ 5µ
Time (s)
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 40. Large signal response with V
CC
= 5 V
(TSC2010)
3
2
-1
-2
1
0
Vsense
-3
-5µ 0
Vcc = 5 V,
Vicm = 12 V,
Vsense = 230 mVpp
Cl = 100 pF,
T = 25 °C
5µ 10µ
Vout
150
125
100
75
50
25
0
-25
-50
-75
-100
-125
-150
15µ
Time (s)
Figure 42. Large signal response with V
CC
= 2.7 V
-1
-2
-3
-5µ
3
2
1
0
Vsense
0
Vcc=2.7V,
Vicm=12V,
Vsense=40mVpp
Cl=100pF,
T=25°C
5µ
Time (s)
10µ
50
25
Vout
0
-25
15µ
-50
DS13057 - Rev 6 page 20/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 43. 12 V common mode step response recovery Figure 44. 50 V common mode step response recovery
5
4
3
2
1
0
-1
-2
Vicm
-10µ 0
Vcc=5V,
Vicm edge 10ns,
Vsense=0V, Vref=2.5V
Rl=10k Ω , Cl=100pF,
T=25°C
20µ 10µ
Time (s)
30µ
Vout
20
15
10
5
0
-5
-10
-15
-20
5
4
3
2
1
0
-1
-2
Vicm
-10µ 0
Vcc=5V,
Vicm edge 10ns,
Vsense=0V, Vref=2.5V
Rl=10kΩ, Cl=100pF,
T=25°C
20µ 10µ
Time (s)
30µ
Vout
70
60
50
40
30
20
10
0
-10
-20
-30
-40
-50
-60
-70
Figure 45. PSRR vs. frequency
-120
-100
-80
-60
Vcc=2.7V
Vcc=3.3V
-40
-20
0
100
Vicm=12V
Vripple=100mVpp
T=25°C
1k 10k 100k
Frequency (Hz)
Vcc=5V
1M 10M
Figure 46. CMRR vs. frequency
-120
-100
-80
-60
Vcc=3.3V
Vcc=2.7V
-40
-20
0
100
Vicm=12V
Vripple=100mVpp
T=25°C
1k 10k 100k
Frequency (Hz)
1M
Vcc=5V
10M
DS13057 - Rev 6 page 21/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 47. Positive overvoltage recovery V
CC
= 2.7 V
3
2
1 Vsense
Vout
Vcc=2.7V,
Vicm=12V,
CI=100pF
T=25°C
0
-50
-3µ -2µ -1µ 0 1µ 2µ
Time (s)
3µ 4µ 5µ 6µ
-100
200
150
100
50
0
Figure 48. Negative overvoltage recovery V
CC
= 2.7 V
100
0
50
Vsense
0
-1
-2
-3
-3µ -2µ -1µ 0
-50
Vout
Vcc=2.7V,
Vicm=12V,
CI=100pF,
T=25°C
-100
-150
1µ 2µ 3µ 4µ 5µ 6µ
-200
Time (s)
Figure 49. Overvoltage recovery vs. V icm
V
CC
= 5 V
1.0
0.8
0.5
0.3
0.0
-20
2.0
1.8
1.5
1.3
-10 0
Vref = Vcc / 2
Vcc = 5 V,
T = 25 °C
Vout = 100 mV drop after Vsense edge
Negative recovery time
Positive recovery time
10
Vicm (V)
20 30 40
Figure 50. Noise vs. frequency
10000
1000
100
2.7V
5V
3.3V
Lorem ipsum
10
Vicm=Vcc/2
Tamb=25°C
1
100m 1 10 100 1k
Frequency (Hz)
10k 100k 1M
DS13057 - Rev 6 page 22/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 51. ON/OFF delay for shutdown mode
3
2
1
VSHDN
Vout
0
-1
Vref=Vcc/2
Vsense=20mV,
Vcc=5V, Vicm=12V,
RI=10k Ω connected to Vcc-,
T=25°C
-2
-3
-10µ 0 10µ 20µ 30µ 40µ 50µ 60µ 70µ
Time (s)
Figure 52. Output voltage vs. Vsense beyond the sense operating
4.0
3.2
2.4
1.6
0.8
Vout phase reversal for Vsense<-4V
0.0
-0.8
-1.6
-2.4
-3.2
Vref=Vcc/2
Vcc=5V
Vicm=12V
T=25°C
-4.0
-7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
Vsense (V)
Figure 53. Power up time delay
6
5 Vcc
2
1
4
3
Vout
0
-1
-2
Vref=0V
Vsense=20mV,
Vcc=5V, Vicm=12V,
RI=10k Ω , Cl=100pF connected to Vcc-,
T=25°C
-3
-40µ -20µ 0 20µ 40µ 60µ 80µ 100µ 120µ 140µ
Time (s)
DS13057 - Rev 6 page 23/53
TSC2010, TSC2011, TSC2012
Application information
5 Application information
5.1
5.2
Overview
The TSC2011 is especially designed to accurately measure the current by amplifying the voltage across a shunt resistor connected to its input. This voltage drop V sense
is then amplified by an instrumentation amplifier providing a max. input offset voltage of 500 µV (25°C) for an input common voltage of 12 V.
The TSC2011 is a fixed gain current sensing amplifier of 60 V/V. Thanks to a thin film resistor, the TSC2011 offers an extremely precise gain and a very high CMRR performance even in a high frequency range. Moreover, by fixing the output common mode voltage, the TSC2011 can be either used as unidirectional or bidirectional current sensing amplifier.
The TSC2011 provides an extended input common range from - 20 V below the negative supply voltage, and up to 70 V allowing either low-side or high-side current sensing, while the TSC2011 device can operate from 2.7 to
5.5 V.
The parameters are very stable in the full V cc
range and characterization curves show the TSC2011 characteristics at 2.7 V and 5.0 V. Moreover, the main specifications are guaranteed in an extended temperature range from -40 to 125 °C.
•
Theory of operation
The main feature of the TSC2011 is the ability to work with an input common mode voltage largely beyond the power supply V cc
range (2.7 V to 5.5 V). It is ideal, for example for automotive applications where a reverse battery can be supported by the TSC2011 without any damage. It also works with 48 V battery applications as the
TSC2011 can support and measure the current on line at voltage up to 70 V. No additional protective components are needed in that range.
V cc
< V icm
< 70 V
In this case, the power supply of the TSC2011 is issued by the input and not only by the V cc
power supply. More precisely, a current is drawn by the common mode rail as depicted in the
Figure 54. Power supply when V icm
Figure 54. Power supply when V icm
> V cc
DS13057 - Rev 6 page 24/53
DS13057 - Rev 6
TSC2010, TSC2011, TSC2012
Theory of operation
In
Figure 55. Input bias current vs. common mode voltage V cc
, the current used to power the TSC2011 increases together with the V icm
voltage. The slope represents the internal common mode resistances. The most part of the current is drawn by the pin In+ as we can see on the i ibp
curve of
Figure 9. Input bias current vs.
the current is around 450 µA. Some of it being V icm input stage of the circuit, roughly 250 µA. On the In- pin 250 µA is drawn only.
/ (R
4
+R
1
) and some supplies the
So due to the architecture of the TSC2011, the current to be measured must be much larger than the input bias current. In case of small current to measure the Iib current must be taken into account.
Figure 55. Input bias current vs. common mode voltage V cc
= 5 V
600
500
400
300
200
100
0
-100
-200
-300
-400
-500
-600
-20 -10
Iibp
0
Iibn
Vref=Vcc/2
Vsense=0V
Vcc=5V
10 20 30 40 50 60 70
Vicm (V)
• Gnd < V icm
< V cc
In this manner, the TSC2011 is only powered by the power supply V cc
, and the iib currents are very close to 0 µA and do not have any impact on the current measurement.
• - 20 V < V icm
< Gnd
The TSC2011 is fully functional in this range of common mode voltage and has also been characterized.
As the high positive common mode voltage, in this specific range, the TSC2011 is also powered by the input, see
Figure 56. Power supply when V icm
page 25/53
DS13057 - Rev 6
TSC2010, TSC2011, TSC2012
Theory of operation
Figure 56. Power supply when V icm
< Gnd
Most part of the current is still due to the pin I n+
as we can see on the i ibp
curve of
Figure 9. Input bias current vs. temperature with V
. The current is about - 300 µA, some of it being V icm
/ (R
4
+ R
1
) and some other supplies the circuit, roughly 250 µA. A small part of the current, coming from the common mode rail, is also due to the input I n–
in order to power the TSC2011, in a range of - 100 µV.
• Output common mode range
The TSC2011 output common mode voltage level can be set thanks to voltages applied on the Vref1 and Vref2 pins. These two pins allow the device to be set either in bidirectional or in unidirectional operation. The voltage applied to those pins must not exceed the V cc
range. The different configurations are detailed in the section
Unidirectionnal/Bidirectionnal operation.
As depicted by the
powered by an external voltage source
, Vref1 and Vref2 pins can be driven by an external voltage source capable of sourcing/sinking a current following the equation below:
Iref =
Vicm − Vref
5kΩ + 275kΩ + 25kΩ
(1)
Figure 57. V ref
powered by an external voltage source page 26/53
TSC2010, TSC2011, TSC2012
Theory of operation
When the output common mode voltage is supplied by an external power supply, in order to improve the output voltage measurement, it is recommended to measure the V out
differentially with respect to V ref
voltage. It provides a better CMRR measurement, better noise immunity and also a more accurate V out
voltage. A decoupling capacitance of 1 nF minimum can be also added to better filter the power supply, and can also be used as a tank capacitance in case an ADC is connected to this reference voltage.
DS13057 - Rev 6 page 27/53
5.3
TSC2010, TSC2011, TSC2012
Unidirectionnal / bidirectionnal operation
•
Unidirectionnal / bidirectionnal operation
Unidirectional operation
Unidirectional mode of operation allows the device to measure the current through a shunt resistor in one direction only. The output reference can be ground or V cc
and can be set by using Vref1 and Vref2 pins for adjustment.
• Ground referenced
Figure 58. Output reference to ground
In this configuration Vref1 pin and Vref2 pin are connected together to the ground. The output common mode voltage is then automatically set to GND when no current flows through the R shunt
resistance. This configuration allows the full scale output in unidirectional mode. It allows a current to be measured as described in
Figure 58. Output reference to ground
.
• V cc
referenced
Figure 59. Output reference to V cc
DS13057 - Rev 6 page 28/53
TSC2010, TSC2011, TSC2012
Unidirectionnal / bidirectionnal operation
In this configuration Vref1 pin and Vref2 pin are connected together to the V cc
power supply. The output common mode voltage is then automatically set to V cc
voltage when no current flows through the R shunt
resistance.
This configuration allows the full scale output in unidirectional mode. It measures the current as described in
Figure 59. Output reference to V cc
.
• Bidirectional operation
Bidirectional mode of operation allows the device to measure currents through a shunt resistor in two directions.
The output reference can be set anywhere within the power supply range. If the output common mode voltage is set at mid-range, the full scale current measurement range is equal in both directions. This is achieved by connecting one Vref pin to Vcc and the other Vref pin to Gnd as described by
. It can be done as well connecting both Vref pins to V cc
/ 2 voltage as described by Figure 61. External supply . In case the
current measurement is not equal in both directions, user can set the output in a non-symmetrical configuration, adjusting Vref according to the user's needs.
• Split supply
Figure 60. Split supply
DS13057 - Rev 6
The great advantage of this configuration, is that the TSC2011 can be used in bidirectional mode with an output common mode voltage set at the middle of scale, with an accuracy of 0.1%, without any added external component or power supply. This configuration creates a midscale offset ratiometric to the power supply.
• External
Figure 61. External supply page 29/53
5.4
5.5
TSC2010, TSC2011, TSC2012
RSENSE selection
In this configuration, Vref1 pin and Vref2 pin are connected together to a reference voltage. The output common mode voltage is then automatically set to this reference voltage value when no current flows through the R shunt resistance. This configuration adjusts the output offset as needed by the application. A DAC for calibration of the analog chain could also be used.
R
SENSE
selection
The selection of the shunt resistor is a tradeoff between the dynamic range and power dissipation.
Generally, in high current sensing application, the main focus is to reduce as much as possible the power dissipation (I²R) by choosing the smallest value of shunt. It could be quite easy if a full scale current to measure is small.
In low current applications the R sense
value could be higher, to minimize the impact of the offset voltage on the circuit. Due to input bias current of several µA, the TSC2011 cannot measure the current in the same range, when the common mode voltage overpasses the power supply voltage (refer to section about theory of operation).
The tradeoff is mainly when a dynamic range of current to measure is large, meaning ability to measure with the same shunt value from low current to high current. Generally, the current full scale (Imax-Imin) defines the shunt value thanks to the full output voltage range, the gain of the TSC2011. The TSC2011 can work with a full scale
∆V out
= 100 mV to V cc
- 100 mV with maximum gain accuracy of 0.3%.
At first order, the full current range to measure through R sense
can be defined by equation 2, just by taking the gain error and input offset voltage as inaccuracy parameters:
Isense_full_scale*Rsense =
Vcc − 200mV
TSC_Gain 1 + Eg − 2 Vio
The V sense
parameter is defined in the electrical characteristics following the equation 2.
Its purpose is to highlight that the product R sense
*T
SC_gain
is determined by the application, and that once one of these two parameters is selected, the maximum value of the second one can be calculated.
• If power dissipation in the shunt is the key point, R
Sense
should be chosen as follows:
(2)
• and then choosing the right gain. For example, for high current to sense, the TSC2012 can offer a gain of
100, in this manner a smaller shunt can be used and so limited power losses. However accuracy can be lower.
Or choosing the product available on the shelf, and then size the shunt resistor value accordingly.
Input offset voltage drift overtemperature
The maximum input offset voltage drift overtemperature is defined as the offset variation related to the offset value measured at 25 °C. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift overtemperature enables the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using equation 3:
(3)
Where T = -40 °C and 125 °C.
The TSC2011 datasheet maximum value is guaranteed by measurements on a representative sample size ensuring a C pk
(process capability index) greater than 1.3.
DS13057 - Rev 6 page 30/53
5.6
TSC2010, TSC2011, TSC2012
Error calculation
Error calculation
The principal source of error, such as: input offset voltage, gain error, common mode rejection ration, are described separately in the electrical characteristics. This chapter summarizes the most important error to take into account during a design phase.
• Input offset voltage error
The equation 2 depicts a first order error calculation just by taking into account the input offset voltage. In a temperature environment, the deviation of the V io
and the error linked to the input offset on the output voltage can be written as equation 4:
•
Vio Error = ± Vio ± Dvio/Dt *Gain
Gain error and shunt resistance accuracy
(4)
Gain error = Gain 1 + εgain
Rsense error = Gain 1 + εRsense
Where εgain is the gain error 0.3% max for the TSC2011.
Where εRsense is the shunt resistance error. Shunt resistors from 5 mΩ to 100 mΩ are available with 1% accuracy or better.
• CMR error
(5)
(6)
In the electrical characteristics, CMR is specified at one input common mode voltage. So in order to take into consideration the variation of the input voltage offset depending the V icm
, the calculus must be done till this known point. Let us get the V icm
= 12 V as reference point.
So the error on V out
due to a common mode voltage variation can be written as the equation 7:
*Gain
• Output common mode error (Vocm)
This error can be taken into account when the output common mode voltage is set like suggested in the
Figure 62. Schematic for V ocm
, and so by using the internal divider bridge. Otherwise it is important to take into consideration the error linked to the voltage source applied on the V
Ref1
pin and V ref2
pin.
(7)
Figure 62. Schematic for V ocm
error
DS13057 - Rev 6
The divider bridge is made by two resistances of 50 kΩ given an output common mode voltage of:
Vref1 + Vref2
2
Due to a small mismatch of the internal resistance the error, on the output common mode voltage, can be described as equation 8: page 31/53
TSC2010, TSC2011, TSC2012
Error calculation
. 1 + εAcc
Where εAcc is the accuracy referred to the output with a typical value of 0.1%.
• Noise
(8)
The
kHz frequency. Above this limit the white noise density is 29 nV/ Hz , until the bandwidth of the TSC2011.
The noise can be then expressed as two terms, the former related to the 1/f noise and the latter due to the white noise. If we consider that there is no additional filter on the TSC2011 and it is only bandwidth limited, it can be considered that over the 750 kHz, there is an attenuation of the noise with a first order filtering. So the equivalent noise bandwidth is 750kHz .
π
2
.
The RMS value of the output noise is the integration of the spectral noise over the bandwidth of interest and can be expressed as equation 9:
2 enRMS = ∫0.1
f
10 . 103
(9)
• Total error
The maximum total error expected on the output of the device can be described as the sum of the different source described just above. The total output accuracy can be written as equation 10.
Vouterr = Gain*Rsense* Iload εgain + εRsense + Gain . Vio + Gain .
Vocm εAcc + noise
Vicm − 12V
CMR
+ (10)
I load
is described in
and the output noise is described by the equation 9.
Note that the input bias currents are not taken into account in this section, as they are already integrated in the
V sense
. The Figure 63. Input current
below depicts the current flowing from the source to the load when the input common mode voltage is higher than the supply voltage.
Figure 63. Input current
DS13057 - Rev 6
From a calculation approach, when V
Input bias current (I ib icm
voltage is beyond V cc
, I load
must be considered as the sum of I source
). Note that the input bias current on the pin – is largely lower and can be neglected.
and
The
also expresses that the TSC2011 cannot measure the current in the same order as input bias current (several hundreds of µA).
The linearity is not taken into account in the error calculus as it represents 0.03% of error only and it is negligible.
Nevertheless, as the gain error has been calculated thanks to the best fit line approach, it gives the information that the gain error can be relatively constant throughout the linear input range of the TSC2011.
The equation 10 has been described for a temperature of 25 °C. For sure with a temperature variation, D vio
/DT error term must be added. And if the power supply is susceptible to change, the SVR parameter must also be taken into account.
page 32/53
5.7
TSC2010, TSC2011, TSC2012
Shutdown mode
• Example
Let us consider that the maximum total error can happen on the output of the TSC2011.
• Use case:
– V cc
= 5 V
– V icm
= 24 V
– V ocm
= 2.5 V
– Temperature = 25 °C
– I load
= 5 A
– Shunt 5 mΩ with 1% accuracy
Theoretically the expected output voltage should be V out
= R shunt
* I load
*60 + V ocm
= 4 V.
From the equations above, all the error terms are detailed by using the maximum value of the electrical characteristics (when available), in order to express as much as possible, the worst case condition. The % error on output of the following table is expressed in reference of V out
– V ref
, so in this typical example: 1.5 V.
Error source
Gain error
V io
error
Table 6. Gain error
Calculus
60*5 . 10−3*5*0.3%
60*500µV
Output voltage error
4.5 mV
30 mV
% error on output
0.3%
2%
CMRR error
V ocm
error
Noise
Total
10
90
20
2.5*0.1%
π
2 − 0.1Hz
22.7 mV
2.5 mV
1.98 mV
RMS
60 mV
+1.98 mV
RMS
1.5%
0.2%
0.4%
4.4%
1. The percentage is based on voltage peak value, which is 3 times RMS value.
So the maximum output voltage in the worst case condition at ambient temperature is 4.060 V + 1.98 mV
RMS instead of 4 V expected. This represents an error on the current reading about 4.4%. 1% more must be added due to the shunt accuracy.
This calculus comes from all the maximum values and all the error terms which have been added to each other, meaning that the chance to get 4.4% precision in the use case above is extremely low and on the whole population, the error is largely smaller.
Shutdown mode
If the SHDN pin is driven between 0.7 x V cc
and V cc
the TSC2011 enters low power shutdown mode, drawing less than 20 µA, over the V cc
and V icm
range. In SHDN mode the output is in HiZ state.
Although there is an internal current source of 500 nA on the SHDN pin, keeping a low state allowing the
TSC2011 to work without any voltage applied on the SHDN pin, it is strongly recommended to apply the dedicated voltage on the SHDN pin to ensure the full functionality of the TSC2011, especially when fast common mode variation appears.
The figure below depicts the architecture of the SHDN pin.
DS13057 - Rev 6 page 33/53
Figure 64. SHDN pin
TSC2010, TSC2011, TSC2012
Stability
5.8
•
•
With GND applied to SHDN pin the TSC2011 is in active mode
With V cc
applied to SHDN pin the TSC2011 is in shutdown mode
•
Stability
Driving switched capacitive loads
Some ADCs get their signal thanks to a sample and hold capacitor. If before a sampling this capacitance is fully discharged, a fast current load can appear on the output of the TSC2011 during the sampling phase.
The scope probe in the figure below shows the output voltage of the TSC2011 excited by a 40 pF capacitor with a
3.3 Vpp signal at 50 kHz to simulate the sample and hold circuit of the ADC120.
Figure 65. Capacitive load response at V cc
= 3.3 V
-1
-2
2
1
0
-3
-4
-5
-6
-7
-8
-4µ
6
5
4
3
8
7
0
Sample and hold
Vcc=3.3V, Vicm=1.65V, Vsense=0Vpp
T=25°C,
50kHz square signal of 3.3V amplitude injected in the output through 40pF
Vout
1000
900
800
700
600
500
400
300
200
100
0
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
8µ 12µ 4µ
Time (s)
The ADC120 has a conversion rate of 50 ksps, which is perfect to sample and hold the output of the TSC2011 without any error.
The graph shows the behavior of the output of the TSC2011 under the worst case condition, as for example, when there is an ADC120 channel change between two measurements.
If a single channel is used, for sure the change on the sample and hold capacitance are very small, and so the recovery time is extremely low as described by the figure below.
DS13057 - Rev 6 page 34/53
TSC2010, TSC2011, TSC2012
Stability
Figure 66. Capacitive load response at V cc
= 3.3 V with a step of 100 mV
100
80
60
40
-20
-40
20
0
-60
-80
-100
-4µ
Sample and hold
Vout
0
Vcc=3.3V, Vicm=1.65V, Vsense=0Vpp
T=25°C,
50kHz square signal of 100mV amplitude injected in the output through 40pF
4µ
Time (s)
8µ 12µ
1000
900
800
700
600
500
400
300
200
100
0
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
The effect of the ADC sampling and hold can be easily smoothed thanks to an RC filter. As suggested on the schematic below. The capacitor of the external filter must be chosen much higher than the internal ADC capacitor, in order to easily absorb the sudden voltage variation on the output due to the sampling and hold of the ADC. The resistance must be chosen accordingly to the application speed of the system in order not to impact the whole application. The main advantage of using an RC filter is to have an antialiasing system. For sure the used ADC must have sample and hold conversion in accordance with the RC filter value, in order to let the output recover before sampling.
Figure 67. RC filter when driving ADC
DS13057 - Rev 6
In the figure
Figure 68. Capacitive load response at V cc
= 3.3 V with 720 kHz RC filter
an R s
= 470 Ω resistance and a C t
= 470 pF capacitance have been set. Given a low-pass filter of 720 kHz and a response time of roughly
660 ns.
In the figure
Figure 69. Capacitive load response at V cc
= 3.3 V with 194 kHz RC filter
an R s
= 820 Ω resistance and a C t
= 1 nF capacitance have been set. Given a low-pass filter of 194 kHz and a response time of roughly 2.5
µs.
page 35/53
TSC2010, TSC2011, TSC2012
Stability
Figure 68. Capacitive load response at V cc
= 3.3 V with
720 kHz RC filter
Figure 69. Capacitive load response at V cc
= 3.3 V with
194 kHz RC filter
8
7
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-4µ
Sample and hold
0
Vcc=3.3V, Vicm=1.65V, Vsense=0Vpp
T=25°C,
Rs=470 Ω ,Ct=470pF
50kHz square signal of 3.3V amplitude injected in the output through 40pF
4µ 8µ
Time (s)
Vout
200
100
0
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
1000
900
800
700
600
500
400
300
12µ
6
5
4
3
0
-1
2
1
8
7
-2
-3
-4
-5
-6
-7
-8
-4µ
Sample and hold
0
Vcc=3.3V, Vicm=1.65V, Vsense=0Vpp
T=25°C,
Rs=820Ω,Ct=1nF
50kHz square signal of 3.3V amplitude injected in the output through 40pF
4µ 8µ
Time (s)
Vout
1000
900
800
700
600
500
400
300
200
100
0
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
12µ
The value of the added external capacitor must be taken into account. Indeed, if this one is chosen with an excessive value and the serial resistance with a too small value, the risk of instability on the output of the
TSC2011 is high.
• Driving large capacitive C load
Increasing the load capacitance produces gain peaking in the frequency response, with an overshoot and ringing in the step response.
The figure below, shows the serial resistors that must be added to the output, to make a system stable. The chosen criteria ensures the stability of the system and it is an overshoot lower than 24%.
Figure 70. Stability criteria with a serial resistor at V
CC
= 5 V
500
400
Vcc=5V, Vicm=0V,
Vref=Vcc/2,
T=25°C,
300
Stable
200
100
0
0.1
Unstable
1
Capacitive Load (nF)
10 100
DS13057 - Rev 6 page 36/53
5.9
5.10
TSC2010, TSC2011, TSC2012
Power supply recommendation
Power supply recommendation
In order to decouple correctly the TSC2011, a 100 nF bypass capacitor can be placed between V cc
and Gnd. This capacitor must be placed as closer as possible to the supply pins. The figure below shows a start-up time with a decoupling capacitance of 100 nF.
Figure 71. Start-up time with a decoupling capacitance of 100 nF
6
5
4
3
2
1
0
-1
-2
-3
-200µ
Vout
0
Vref=0V
Vsense=20mV,
Vcc=5V, Vicm=12V,
RI=10k Ω , Cl=10pF connected to Vcc-,
T=25°C
200µ 400µ 600µ
Time (s)
Vcc
800µ
V ref
pin is used to fix the output common mode voltage and it is driven by a low impedance voltage source and can be decoupled thanks to a 10 nF bypass capacitor.
A greater bypass capacitor added on V cc
pin and V ref
pin helps to enhance CMRR and PSRR performance.
PCB layout recommendations
The layout of the PCB tracks connected to the current sensing, load and power supply is very important. It is a good practice to use short and wide PCB traces to minimize voltage drops and parasitic inductance.
When a shunt resistance, lower than 1 Ω, is used, a 4-wire connection technique should be used to sense the current as described in the schematic below. This technique separates pairs of current carrying and voltagesensing electrodes to make more accurate measurements by eliminating the lead and contact resistance from the measurement.
The track connected to the input pin of the TSC2011 has to be considered as a differential pair, it must have the same length and width, and ideally placed on the same PCB plane, and above all must be routed as far as possible from noisy source. As this track carries the input bias current, in a range of hundreds of µA, it can be designed small but always by taking care of its resistivity. Any via in these input tracks are non-recommended to avoid any parasitic resistance in this path.
To minimize parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top layer ground planes together in many locations is often used.
A ground plane generally helps to reduce EMI, that is why a multilayer PCB use is suggested as well as the ground planes as a shield to protect the internal track. In this case, the digital from the analog ground must be separated and any ground loop must be avoided. Loop area or antenna must be reduced to minimize EMI impact.
The
effect.
DS13057 - Rev 6 page 37/53
TSC2010, TSC2011, TSC2012
EMI rejection ration (EMIRR)
Figure 72. Recommended layout
5.11
EMI rejection ration (EMIRR)
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of current sensing device. An adverse effect that is common to many current sensing is a change in the offset voltage as a result of RF signal rectification. A first order internal low pass filter is included on the input of the TSC2011 to minimize
susceptibility to EMIRR. Figure 73 shows the EMIRR on pin IN+, Figure 74
shows the EMIRR on pin IN- of the
TSC2011 measured from 400 MHz up to 2.4 GHz.
Figure 73. EMIRR on pin+
120
100
80
60
40
20
Vcc=5V, T=25°C
Prf=-10dBm
0
400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
Frequency (MHz)
Figure 74. EMIRR on pin-
120
100
80
60
40
20
Vcc=5V, T=25°C
Prf=-10dBm
0
400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
Frequency (MHz)
10 MHz up to 2.4 GHz.
DS13057 - Rev 6 page 38/53
Figure 75. EMIRR on pin+ (TSC2010)
120
100
80
60
40
20
0
Vcc = 5 V, T = 25°C
Prf = 10 dBm
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
Frequency (MHz)
TSC2010, TSC2011, TSC2012
EMI rejection ration (EMIRR)
Figure 76. EMIRR on pin- (TSC2010)
120
100
80
60
40
20
0
Vcc = 5 V, T = 25°C
Prf = 10 dBm
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
Frequency (MHz)
DS13057 - Rev 6 page 39/53
TSC2010, TSC2011, TSC2012
Overload recovery
5.12
Overload recovery
Overload recovery is defined as the time required for the current sensing output to recover from a saturated state to a linear state.
The saturation state occurs when the output voltage gets very close to rails in the application. It results from an excessive input voltage.
When the output of the TSC2011 enters saturation state, less than 1 µs is needed to get back to a linear state as shown by
Figure 47 and Figure 48 show the overvoltage recovery for a V
CC
= 2.7 V.
Figure 77. Negative overvoltage recovery V
CC
= ± 2.5 V Figure 78. Positive overvoltage recovery V
CC
= ± 2.5 V
DS13057 - Rev 6 page 40/53
TSC2010, TSC2011, TSC2012
Application examples
5.13
5.13.1
Application examples
H-Bridge motor control
The H-Bridge topology is very popular in motor control, DC-DC converters, LED lighting control and other bidirectional loads from a single supply potential.
The TSC2011 provides a feedback control system about current but also detects overload conditions.
The
Figure 79. H-Bridge application describes a typical schematic using the TSC2011 in a motor control
application. A 20 mΩ shunt resistance in series with the motor monitors a measurable voltage drop representing the load current, and the TSC2011 amplifies the V sense
in order to give some information about the current flowing into the motor in real time. These information are then digitalizing by the 12-bit ADC (ADC120).
Figure 79. H-Bridge application
DS13057 - Rev 6
General overview:
To make the motor rotation occur, the NMOS H1, H2, L1, L2 are driven by a H-Bridge quad power MOSFET driver. We have to consider that the current flows from the 12 V to the GND, through H1 NMOS and L2 NMOS. A
PWM is applied on the NMOS L2 in order to control the current and thus the speed of the motor.
By PWM, the average voltage applied on the motor is controlled. H1 remains always ON and the PWM is applied on L2. When L2 is turned off, H2 must be turned ON, for freewheeling, allowing the discharge of the motor inductance current. This phenomenon generates a fast input common mode voltage transition on the TSC2011, from 0 V to 12 V.
Thanks to a good recovery time due to fast input common mode change, the TSC2011 follows the current flowing into the motor as depicted by the scope probe in
Figure 80. TSC2011 H-Bridge application .
The black curve represents the fast V icm
variation step of 12 V in 500 ns when the freewheeling is activated. The blue curve represents the current flowing into the motor measured with a current probe.
The red curve represents the output voltage - 1.35 V (Vref voltage) of the TSC2011 probe after the RC filter.
The RC filter, used to drive the ADC120, smooths a bit the output signal and adds a small constant time, in the range of 1 µs.
page 41/53
TSC2010, TSC2011, TSC2012
Application examples
5.13.2
Figure 80. TSC2011 H-Bridge application
1.0
1.20
0.8
Vicm variation from 0V to 12V
0.96
0.6
0.72
0.4
0.48
0.2
0.24
Vout
0.0
0.00
-0.2
Current flowing into the motor
-0.4
-50µ -40µ -30µ -20µ -10µ 0
Time (s)
10µ
-0.24
20µ 30µ 40µ 50µ
-0.48
After a fast variation of the input common mode, the TSC2011 needs less than 5 µs to recover its normal behavior.
Solenoid valve
In automotive applications, the automatic transmission relies on bands and clutches to change gears, and the only way they can be applied is by fluid pressure. The transmission solenoid is responsible for opening or closing valves in the valve body to allow transmission fluid to enter, at which point the fluid can pressurize the clutches and bands. Solenoids consist of a spring loaded plunger wrapped with a coil of wire, and it is generally driven thanks to a MOS transistor.
In the schematic below the TSC2011 is used in mono directional mode. When the MOS is ON, the current can flow through the solenoid and actuate this one. The input common mode is high in this case.
When the MOS is turned OFF, as the current stored into the solenoid cannot stop instantaneously, the diode turns
ON allowing a freewheeling to discharge the solenoid resulting in a common mode one diode voltage drop below ground.
Thanks to its large input common mode range, the TSC2011 can be used for such applications depicted in figure below.
In order not to saturate the output when no current is flowing into R sense
, a small voltage on V ref
has to be applied.
DS13057 - Rev 6 page 42/53
TSC2010, TSC2011, TSC2012
Application examples
Figure 81. Solenoid valve application
DS13057 - Rev 6 page 43/53
6
TSC2010, TSC2011, TSC2012
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
DS13057 - Rev 6 page 44/53
6.1
SO8 package information
Figure 82. SO8 package outline
TSC2010, TSC2011, TSC2012
SO8 package information
DS13057 - Rev 6
Dim.
L
L1 k ccc
E1 e h
A
A1
A2 b c
D
E
0.1
1.25
0.28
0.17
4.8
5.8
3.8
Min.
0.25
0.4
0 mm
4.9
6
3.9
1.27
Typ.
Table 7. SO-8 mechanical data
Inches
Min.
Max.
1.75
0.25
0.48
0.23
5
6.2
4
0.004
0.049
0.011
0.007
0.189
0.228
0.15
0.5
1.27
0.01
0.016
1.04
8 °
0.1
1 °
Typ.
0.193
0.236
0.154
0.05
0.04
Max.
0.069
0.01
0.019
0.01
0.197
0.244
0.157
0.02
0.05
8 °
0.004
page 45/53
6.2
TSC2010, TSC2011, TSC2012
MiniSO8 package information
MiniSO8 package information
Figure 83. MiniSO8 package outline
DS13057 - Rev 6
Dim.
L2 k ccc
D
E
E1 e
L
L1
A
A1
A2 b c
Min.
Millimeters
Typ.
0
0.75
0.22
0.08
2.8
4.65
2.8
0.4
3
4.9
3
0.65
0.6
0.95
0.25
Table 8. MiniSO8 mechanical data
Inches
Min.
0.85
Max.
1.1
0.15
0.95
0.4
0.23
3.2
5.15
3.1
0.8
0
0.03
0.009
0.003
0.11
0.183
0.11
0.016
0° 8°
0.1
0°
Typ.
0.033
0.118
0.193
0.118
0.026
0.024
0.037
0.01
Max.
0.043
0.006
0.037
0.016
0.009
0.126
0.203
0.122
0.031
8°
0.004
page 46/53
7
TSC2010, TSC2011, TSC2012
Ordering information
Ordering information
Table 9. Order codes
Order code
TSC2010IDT
TSC2011IDT
TSC2011IYDT
TSC2012IDT
TSC2010IST
TSC2011IST
TSC2011IYST
TSC2012IST
Gain (V/V)
20
60
100
20
60
100
Package
SO8
MiniSO8
Packaging
Tape and reel
Marking
TSC2010
TSC2010Y
TSC2011
TSC2011Y
TSC2012
TSC2012Y
O117
O120
O118
O121
O119
O122
1. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 &
Q002 or equivalent.
DS13057 - Rev 6 page 47/53
TSC2010, TSC2011, TSC2012
Revision history
Date
11-Sep-2019
30-Jan-2020
10-Apr-2020
05-Aug-2020
06-May-2021
15-Sep-2021
Revision
1
2
3
4
5
6
Table 10. Document revision history
Changes
Initial release.
Added new part number TSC2012, Figure 25. Gain vs. frequency (V
CC
= 5 V),
Figure 27. Gain vs. different capacitive load (TSC2012), Figure 29. Bandwidth vs.
input common mode (TSC2012) and Figure 32. Small signal response with V
CC
= 5 V
(TSC2012).
Updated description on the cover page, Figure 30. Overshoot vs. capacitive load,
Figure 42. Overvoltage recovery vs. V icm
, V
CC
= 5 V, Table 4. Electrical characteristics
V
CC
= 2.7 V, V icm
= 12 V, T = 25 °C (unless otherwise specified)., Table 5. Electrical characteristics (V
CC
= 5 V, V icm
= 12 V, T = 25 °C unless otherwise specified) and
Table 9. Order codes.
Added new part number TSC2010, Figure 75 and Figure 76.
Updated:
- Features and description on the cover page
- |Vsense|, G, BW and SR conditions in Table 4 and Table 5.
- Section 4.1 Typical characteristics.
- Table 9. Order codes.
Updated Figure 77 and Figure 78.
Updated Section 5.13.1 H-Bridge motor control
.
Updated Figure 33. Bandwidth vs. input common mode (TSC2012)
.
DS13057 - Rev 6 page 48/53
TSC2010, TSC2011, TSC2012
Contents
Contents
DS13057 - Rev 6 page 49/53
TSC2010, TSC2011, TSC2012
List of tables
List of tables
Table 4. Electrical characteristics V cc
= 12 V, T = 25 °C (unless otherwise specified). . . . . . . . . . . . . . . . . . . 5
Table 5. Electrical characteristics (V cc
= 12 V, T = 25 °C unless otherwise specified). . . . . . . . . . . . . . . . . . . . 8
DS13057 - Rev 6 page 50/53
TSC2010, TSC2011, TSC2012
List of figures
List of figures
Figure 8. Input bias current vs. temperature V
= 2.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Input bias current vs. temperature with V
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Input offset voltage vs. input common mode with V
= 2.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Input offset voltage vs. input common mode with V
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 15. Output current vs. temperature with V
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16. Output current vs. temperature with V
= 2.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
vs. input common mode voltage with V
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18. (Output voltage + V ref
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 19. (Output voltage + V ref
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 20. Output rail linearity vs. load with V
Figure 21. Linearity vs. V sense
Figure 22. Linearity vs. V sense
Figure 25. Load regulation with V
Figure 27. Gain vs. frequency V
Figure 35. Small signal response with V
Figure 36. Small signal response with V
Figure 37. Small signal response with V
Figure 38. Small signal response with V
Figure 39. Large signal response with V
Figure 40. Large signal response with V
Figure 41. Large signal response with V
Figure 42. Large signal response with V
Figure 47. Positive overvoltage recovery V
Figure 48. Negative overvoltage recovery V
Figure 49. Overvoltage recovery vs. V icm
DS13057 - Rev 6 page 51/53
TSC2010, TSC2011, TSC2012
List of figures
Figure 54. Power supply when V icm
Figure 55. Input bias current vs. common mode voltage V cc
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 56. Power supply when V icm
Figure 59. Output reference to V cc
Figure 62. Schematic for V ocm
Figure 65. Capacitive load response at V cc
Figure 66. Capacitive load response at V cc
= 3.3 V with a step of 100 mV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 68. Capacitive load response at V cc
Figure 69. Capacitive load response at V cc
Figure 70. Stability criteria with a serial resistor at V
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 77. Negative overvoltage recovery V
Figure 78. Positive overvoltage recovery V
DS13057 - Rev 6 page 52/53
TSC2010, TSC2011, TSC2012
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS13057 - Rev 6 page 53/53
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