STMicroelectronics A5973D Datasheet
જાહેરાત
જાહેરાત
A5973D
Up to 2 A step-down switching regulator for automotive applications
Datasheet
-
production data
Applications
Dedicated to automotive applications
HSOP8 - exposed pad
Description
Features
Qualified following the AEC-Q100 requirements (see PPAP for more details)
2 A DC output current
Operating input voltage from 4 V to 36 V
3.3 V / ( ± 2%) reference voltage
Output voltage adjustable from 1.235 V to 35 V
Low dropout operation: 100% duty cycle
250 kHz internally fixed frequency
Voltage feedforward
Zero load current operation
Internal current limiting
Inhibit for zero current consumption
Synchronization
Protection against feedback disconnection
Thermal shutdown
The A5973D is a step-down monolithic power switching regulator with a minimum switch current limit of 2.25 A so it is able to deliver up to 2 A DC current to the load depending on the application conditions. The output voltage can be set from
1.235 V to 35 V. The high current level is also achieved thanks to an HSOP8 package with exposed frame, that allows to reduce the R th(JA) down to approximately 40 °C/W. The device uses an internal P-channel DMOS transistor (with a typical R
DS(on)
of 250 m
Ω
) as switching element to minimize the size of the external components.
An internal oscillator fixes the switching frequency at 250 kHz. Having a minimum input voltage of
4 V only it fits the automotive applications requiring the device operation even in cold crank conditions. A pulse-by-pulse current limit with the internal frequency modulation offers an effective constant current short-circuit protection.
Figure 1. Application schematic
November 2015
This is information on a product in full production.
DocID13957 Rev 9 1/41 www.st.com
Contents
Contents
A5973D
Datasheet parameters over the temperature range . . . . . . . . . . . . . . . . 8
Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PWM comparator and power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Additional features and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Error amplifier and compensation network . . . . . . . . . . . . . . . . . . . . . . . . 17
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A5973D
Contents
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Negative buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Synchronization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Compensation network with MLCC at the output . . . . . . . . . . . . . . . . . . . 33
External SOFT_START network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
HSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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41
Pin settings
Figure 2. Pin connection (top view)
A5973D
3
4
No.
1
2
5
6
7
8
Pin
OUT
SYNCH
INH
COMP
FB
VREF
GND
VCC
Table 1. Pin description
Description
Regulator output.
Master/slave synchronization.
A logical signal (active high) disables the device. If INH not used the pin must be grounded. When it is open an internal pull-up disables the device.
E/A output for frequency compensation.
Feedback input. Connecting directly to this pin results in an output voltage of 1.23 V. An external resistive divider is required for higher output voltages.
3.3 V V
REF
. No cap is requested for stability.
Ground.
Unregulated DC input voltage.
4/41 DocID13957 Rev 9
A5973D Electrical data
Symbol
V
8
V
1
I
1
V
4
, V
5
V
3
V
2
P
TOT
T
J
T
STG
Table 2. Absolute maximum ratings
Parameter
Input voltage
OUT pin DC voltage
OUT pin peak voltage at t = 0.1 s
Maximum output current
Analog pins
INH
SYNCH
Power dissipation at T
A
70 °C
Operating junction temperature range
Storage temperature range
Value
40
-1 to 40
-5 to 40
Int. limit.
4
-0.3 to V
CC
-0.3 to 4
2.25
-40 to 150
-55 to 150
Unit
V
V
V
V
V
V
W
°C
°C
Symbol
Table 3. Thermal data
Parameter
R thJA
Maximum thermal resistance junction ambient
1. Package mounted on the evaluation board.
Value
40
(1)
Unit
°C/W
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41
Electrical characteristics A5973D
T
J
= -40 °C to 125 °C, V
CC
= 12 V, unless otherwise specified.
Symbol
R
V
CC
DS(on) f
I
L
SW
Table 4. Electrical characteristics
Test condition
Dynamic characteristics (see test circuit)
V
5 h
Voltage feedback
Efficiency
4.4 V < V
CC
< 36 V, 20 mA < I
0
< 2 A 1.198
1.235
1.272
V
0
= 5 V, V
CC
= 12 V 90
I qop
I q
I qst-by
Inhibit
Parameter
Operating input voltage range V
0
= 1.235 V; I
0
= 2 A
MOSFET on resistance
Maximum limiting current
(1)
Switching frequency
Duty cycle
DC characteristics
Total operating quiescent current
Quiescent current
Total standby quiescent current
V
CC
= 5 V
V
CC
= 5 V, T
J
= 25 °C
Duty cycle = 0; V
FB
= 1.5 V
V inh
> 2.2 V
V
C C
= 36 V; V inh
> 2.2 V
Min.
Typ.
Max.
Unit
4
2.25
2.5
212
0
0.250
3
3
250
3
50
80
36
0.5
3.5
3.5
280
100
5
2.5
100
150
V
%
V
A kHz
% mA mA
A
A
INH threshold voltage
Device ON
Device OFF 2.2
0.8
V
V
Error amplifier
V
OH
High level output voltage
V
OL
Low level output voltage
I o source
Source output current
I o sink
I b
Sink output current
Source bias current
DC open loop gain gm Transconductance
V
FB
= 1 V
V
FB
= 1.5 V
V
COMP
= 1.9 V; V
FB
= 1 V
V
COMP
= 1.9 V; V
FB
= 1.5 V
R
L
=
I
COMP
= -0.1 mA to 0.1 mA;
V
COMP
= 1.9 V
3.5
190
1
50
300
1.5
2.5
65
2.3
0.4
4 mA
A dB
V
V
A mS
Synch function
High input voltage
Low input voltage
V
CC
= 4.4 to 36 V
V
CC
= 4.4 to 36 V
2.5
V
REF
0.74
V
V
6/41 DocID13957 Rev 9
A5973D Electrical characteristics
Symbol
Table 4. Electrical characteristics (continued)
Parameter Test condition Min.
Typ.
Max.
Unit
Slave synch current
(2)
Master output amplitude
Output pulse width
V synch
= 0.74 V
V synch
= 2.33 V
I source
= 3 mA no load, V synch
= 1.65 V
0.11
0.21
2.75
0.20
3
0.35
0.25
0.45
mA
V
s
Reference section
Reference voltage
Line regulation
I
REF
= 0 to 5 mA
V
CC
= 4.4 V to 36 V
I
REF
= 0 mA
V
CC
= 4.4 V to 36 V
I
REF
= 0 mA
3.2
Load regulation
Short-circuit current 5
1. With T
J
= 85 °C, I lim_min
= 2.5 A, assured by design, characterization and statistical correlation.
2. Guaranteed by design.
3.3
3.399
5
8
18
10
15
35
V mV mV mA
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Datasheet parameters over the temperature range
4
A5973D
Datasheet parameters over the temperature range
The 100% of the population in the production flow is tested at three different ambient temperatures (-40 C, +25 C, +125 C) to guarantee the datasheet parameters inside the junction temperature range (-40 C, +125 C).
The device operation is so guaranteed when the junction temperature is inside the (-40 C,
+150 C) temperature range. The designer can estimate the silicon temperature increase respect to the ambient temperature evaluating the internal power losses generated during the device operation (please refer to the
).
However the embedded thermal protection disables the switching activity to protect the device in case the junction temperature reaches the T
SHTDWN temperature.
(+150 C ± 10 C)
All the datasheet parameters can be guaranteed to a maximum junction temperature of
+125 C to avoid triggering the thermal shutdown protection during the testing phase because of self-heating.
8/41 DocID13957 Rev 9
A5973D Functional description
The main internal blocks are shown in the device block diagram in Figure 3
. They are:
A voltage regulator supplying the internal circuitry. From this regulator, a 3.3 V reference voltage is externally available.
A voltage monitor circuit which checks the input and the internal voltages.
A fully integrated sawtooth oscillator with a frequency of 250 kHz 15 %, including also the voltage feedforward function and an input/output synchronization pin.
Two embedded current limitation circuits which control the current that flows through the power switch. The pulse-by-pulse current limit forces the power switch OFF cycle by cycle if the current reaches an internal threshold, while the frequency shifter reduces the switching frequency in order to significantly reduce the duty cycle.
A transconductance error amplifier.
A pulse width modulator (PWM) comparator and the relative logic circuitry necessary to drive the internal power.
A high-side driver for the internal P-MOS switch.
An inhibit block for standby operation.
A circuit to implement the thermal protection function.
Figure 3. Block diagram
The internal regulator circuit (shown in Figure 4
) consists of a start-up circuit, an internal voltage pre-regulator, the bandgap voltage reference and the bias block that provides current to all the blocks. The starter supplies the start-up currents to the entire device when the input voltage goes high and the device is enabled (inhibit pin connected to ground). The pre-regulator block supplies the bandgap cell with a pre-regulated voltage V
REG a very low supply voltage noise sensitivity.
that has
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Functional description A5973D
An internal block continuously senses the V cc
, V ref
and V bg
. If the voltages go higher than their thresholds, the regulator begins operating. There is also a hysteresis on the V
CC
(UVLO).
Figure 4. Internal circuit
5.3 Oscillator synchronization
Figure 5 shows the block diagram of the oscillator circuit.
The clock generator provides the switching frequency of the device, which is internally fixed at 250 kHz. The frequency shifter block acts to reduce the switching frequency in case of strong overcurrent or short-circuit. The clock signal is then used in the internal logic circuitry and is the input of the ramp generator and synchronizer blocks.
The ramp generator circuit provides the sawtooth signal, used for PWM control and the internal voltage feedforward, while the synchronizer circuit generates the synchronization signal. The device also has a synchronization pin which can work both as master and slave.
Beating frequency noise is an issue when more than one voltage rail is on the same board.
A simple way to avoid this issue is to operate all the regulators at the same switching frequency.
The synchronization feature of a set of the A5973D is simply get connecting together their
SYNCH pin. The device with highest switching frequency will be the MASTER and it provides the synchronization signal to the others. Therefore the SYNCH is an I/O pin to deliver or recognize a frequency signal. The synchronization circuitry is powered by the internal reference (V
REF
) so a small filtering capacitor ( 100 nF) connected between V pin and the signal ground of the master device is suggested for its proper operation.
REF
However when a set of synchronized devices populates a board it is not possible to know in advance the one working as master, so the filtering capacitor have to be designed for whole set of devices.
When one or more devices are synchronized to an external signal, its amplitude have to be in comply with specifications given in
. The frequency of the synchronization signal must be, at a minimum, higher than the maximum guaranteed natural switching frequency of the device (275 kHz, see
) while the duty cycle of the synchronization signal can vary from approximately 10% to 90%. The small capacitor under
V
REF
pin is required for this operation.
10/41 DocID13957 Rev 9
A5973D
Figure 5. Oscillator circuit block diagram
Functional description
Figure 6. Synchronization example
The A5973D device features two types of current limit protection: pulse-by-pulse and frequency foldback.
The schematic of the current limitation circuitry for the pulse-by-pulse protection is shown in
Figure 7 . The output power PDMOS transistor is split into two parallel PDMOS transistors.
The smallest one includes a resistor in series, R
SENSE
R
SENSE
. The current is sensed through
and if it reaches the threshold, the mirror becomes unbalanced and the PDMOS is switched off until the next falling edge of the internal clock pulse. Due to this reduction of the
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Functional description A5973D
ON time, the output voltage decreases. Since the minimum switch ON time necessary to sense the current in order to avoid a false overcurrent signal is too short to obtain a sufficiently low duty cycle at 250 kHz (see
Section 8.4 on page 26 ), the output current in
strong overcurrent or short-circuit conditions could be not properly limited. For this reason the switching frequency is also reduced, thus keeping the inductor current under its maximum threshold. The frequency shifter (
Figure 5 ) functions based on the feedback
voltage. As the feedback voltage decreases (due to the reduced duty cycle), the switching frequency decreases also.
Figure 7. Current limitation circuitry
12/41
The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose non inverting input is connected to the internal voltage reference (1.235 V), while the inverting input (FB) is connected to the external divider or directly to the output voltage. The output (COMP) is connected to the external compensation network. The uncompensated error amplifier has the following characteristics:
Table 5. Uncompensated error amplifier characteristics
Description Values
Transconductance
Low frequency gain
Minimum sink/source voltage
Output voltage swing
Input bias current
2300 µS
65 dB
1500 µA/300 µA
0.4 V/3.65 V
2.5 µA
The error amplifier output is compared to the oscillator sawtooth to perform PWM control.
DocID13957 Rev 9
A5973D
5.6
Functional description
PWM comparator and power stage
This block compares the oscillator sawtooth and the error amplifier output signals to generate the PWM signal for the driving stage.
The power stage is a highly critical block, as it functions to guarantee a correct turn ON and turn OFF of the PDMOS. The turn ON of the power element, or more accurately, the rise time of the current at turn ON, is a very critical parameter. At a first approach, it appears that the faster the rise time, the lower the turn ON losses.
However, there is a limit introduced by the recovery time of the recirculation diode.
In fact, when the current of the power element is equal to the inductor current, the diode turns OFF and the drain of the power is able to go high. But during its recovery time, the diode can be considered a high value capacitor and this produces a very high peak current, responsible for numerous problems:
Spikes on the device supply voltage that cause oscillations (and thus noise) due to the board parasites.
Turn ON overcurrent leads to a decrease in the efficiency and system reliability.
Major EMI problems.
Shorter freewheeling diode life.
The fall time of the current during turn OFF is also critical, as it produces voltage spikes (due to the parasites elements of the board) that increase the voltage drop across the PDMOS.
In order to minimize these problems, a new driving circuit topology has been used and the block diagram is shown in
Figure 8 . The basic idea is to change the current levels used to
turn the power switch ON and OFF, based on the PDMOS and the gate clamp status.
This circuitry allows the power switch to be turned OFF and ON quickly and addresses the freewheeling diode recovery time problem. The gate clamp is necessary to ensure that V
GS of the internal switch does not go higher than V
GS max. The ON/OFF Control block protects against any cross conduction between the supply line and ground.
Figure 8. Driving circuitry
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Functional description A5973D
The inhibit feature is used to put the device in standby mode. With the INH pin higher than
2.2 V the device is disabled and the power consumption is reduced to less than 100 µA.
With the INH pin lower than 0.8 V, the device is enabled. If the INH pin is left floating, an internal pull up ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also V
CC
compatible.
The shutdown block generates a signal that turns OFF the power stage if the temperature of the chip goes higher than a fixed internal threshold (150 ± 10 °C). The sensing element of the chip is very close to the PDMOS area, ensuring fast and accurate temperature detection. A hysteresis of approximately 20 °C keeps the device from turning ON and OFF continuously.
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A5973D
6
Additional features and protection
Additional features and protection
6.2
If the feedback is disconnected, the duty cycle increases towards the maximum allowed value, bringing the output voltage close to the input supply. This condition could destroy the load.
To avoid this hazardous condition, the device is turned OFF if the feedback pin is left floating.
Output overvoltage protection
Overvoltage protection, or OVP, is achieved by using an internal comparator connected to the feedback, which turns OFF the power stage when the OVP threshold is reached. This threshold is typically 30% higher than the feedback voltage.
When a voltage divider is required to adjust the output voltage ( Figure 15 on page 27 ), the
OVP intervention will be set at:
Equation 1
V
OVP
= 1.3
R
1
+
R
2
R
------------------- V
FB
Where R
1
R
2
is the resistor connected between the output voltage and the feedback pin, and
is between the feedback pin and ground.
Due to the fact that the internal power is a PDMOS, no boostrap capacitor is required and so the device works properly even with no load at the output. In this case it works in burst mode, with a random burst repetition rate.
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Closing the loop
7 Closing the loop
Figure 9. Block diagram of the loop
A5973D
16/41 DocID13957 Rev 9
A5973D
7.1
Closing the loop
Error amplifier and compensation network
The output L-C filter of a step-down converter contributes with 180 degrees phase shift in the control loop. For this reason a compensation network between the COMP pin and
GROUND is added. The simplest compensation network together with the equivalent circuit
of the error amplifier are shown in Figure 10 . R
C
and C
C
introduce a pole and a zero in the open loop gain. CP does not significantly affect system stability but it is useful to reduce the noise of the COMP pin.
The transfer function of the error amplifier and its compensation network is:
Equation 2
A
0
= s
2
R
0
C
0
+ C p
R c
A
C c
+
s
1 s
R
0
R
C c
+
C
R
0
C
0
+ C p
+ R c
C c
+ 1
Where A vo
= G m
· R o
Figure 10. Error amplifier equivalent circuit and compensation network
The poles of this transfer function are (if C c
>> C
0
+ C
P
):
Equation 3
F
P1
=
2
1
R
0
C c
Equation 4
F
P2
=
2 R c
1
C
0
+ C p
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41
Closing the loop A5973D whereas the zero is defined as:
Equation 5
F
Z1
=
2
1
R c
C c
F
P1
is the low frequency which sets the bandwidth, while the zero F
Z1
is usually put near to the frequency of the double pole of the L-C filter (see below). F
P2
is usually at a very high frequency.
18/41
The transfer function of the L-C filter is given by:
Equation 6
A
LC
= s
OUT
R
LOAD
+
+ s
OUT
s
OUT
R
LOAD
+ L + R
LOAD where R
LOAD
is defined as the ratio between V
OUT
and I
OUT
.
If R
LOAD
>> ESR, the previous expression of A
LC
can be simplified and becomes:
Equation 7
A
LC
=
1 ESR C
s
2
+
OUT
s
----------------------------------------------------------------------------------------------
OUT
ESR C
OUT
+
The zero of this transfer function is given by:
Equation 8
F
O
=
2
1
ESR C
OUT
F
0
is the zero introduced by the ESR of the output capacitor and it is very important to increase the phase margin of the loop.
The poles of the transfer function can be calculated through the following expression:
Equation 9
=
– ESR COUT – COUT
COUT
2
In the denominator of A
LC
the typical second order system equation can be recognized:
Equation 10 s
2
+ 2 n
s +
2 n
If the damping coefficient is very close to zero, the roots of the equation become a double root whose value is n
.
DocID13957 Rev 9
A5973D Closing the loop
Similarly for A
LC
the poles can usually be defined as a double pole whose value is:
Equation 11
F
PLC
=
2
OUT
The PWM gain is given by the following formula:
Equation 12
G
PWM s =
V
OSCMAX
V cc
–
OSCMIN
where V
OSCMAX is the maximum value of a sawtooth waveform and V
OSCMIN
is the minimum value. A voltage feedforward is implemented to ensure a constant GPWM. This is obtained by generating a sawtooth waveform directly proportional to the input voltage V
CC
.
Equation 13
V
OSCMAX
– V
OSCMIN
=
CC
Where K is equal to 0.076. Therefore the PWM gain is also equal to:
Equation 14
G
PWM
=
1
K
= const
This means that even if the input voltage changes, the error amplifier does not change its value to keep the loop in regulation, thus ensuring a better line regulation and line transient response.
In summary, the open loop gain can be expressed as:
Equation 15
G s = G
PWM
R
1
R
2
R
2
A
O
A
LC
Example 1
Considering R
C
= 2.7 k , C
C
= 22 nF and C
P
= 220 pF, the poles and zeroes of A
0
are:
F
P1
= 9 Hz
F
P2
= 256 kHz
F
Z1
= 2.68 kHz
If L = 22 µH, C
OUT
= 100 µF and ESR = 80 m , the poles and zeroes of A
LC
become:
F
PLC
= 3.39 kHz
F
0
= 19.89 kHz
Finally R
1
= 5.6 k and R
2
= 3.3 k .
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Closing the loop A5973D
The gain and phase bode diagrams are plotted respectively in
and
Figure 11. Module plot
Figure 12. Phase plot
20/41
The cut-off frequency and the phase margin are:
Equation 16
F
C
= 22.8KHz
phase margin = 39.8°
DocID13957 Rev 9
A5973D Application information
Input capacitor
The input capacitor must be able to support the maximum input operating voltage and the maximum RMS input current.
Since step-down converters draw current from the input in pulses, the input current is squared and the height of each pulse is equal to the output current. The input capacitor has to absorb all this switching current, which can be up to the load current divided by two (worst case, with duty cycle of 50 %). For this reason, the quality of these capacitors has to be very high to minimize the power dissipation generated by the internal ESR, thereby improving system reliability and efficiency. The critical parameter is usually the RMS current rating, which must be higher than the RMS input current. The maximum RMS input current (flowing through the input capacitor) is:
Equation 17
I
RMS
= I
O
D –
2
---------------+
D
2
-------
2
Where is the expected system efficiency, is equal to I
O
D is the duty cycle and I
O
is the output DC current. This function reaches its maximum value at D = 0.5 and the equivalent RMS current
divided by 2 (considering = 1). The maximum and minimum duty cycles are:
Equation 18
D
MAX
=
V
V
INMIN
+
–
V
V
F
SW and
Equation 19
D
MIN
=
V
V
INMAX
+
–
V
V
F
SW
Where V
F
is the freewheeling diode forward voltage and V
SW
I internal PDMOS. Considering the range D
MIN
RMS
going through the input capacitor.
to D
MAX
the voltage drop across the
, it is possible to determine the max.
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41
Application information A5973D
Capacitors that can be considered are:
Electrolytic capacitors:
These are widely used due to their low price and their availability in a wide range of
RMS current ratings.
The only drawback is that, considering ripple current rating requirements, they are physically larger than other capacitors.
Ceramic capacitors:
If available for the required value and voltage rating, these capacitors usually have a higher RMS current rating for a given physical dimension (due to very low ESR).
The drawback is the considerably high cost.
Tantalum capacitors:
Very good, small tantalum capacitors with very low ESR are becoming more available.
However, they can occasionally burn if subjected to very high current during charge.
Therefore, it is better to avoid this type of capacitor for the input filter of the device.
They can, however, be subjected to high surge current when connected to the power supply.
Manufacturer
Table 6. List of ceramic capacitors for the A5973D
Series Capacitor value (µF) Rated voltage (V)
TAIYO YUDEN
MURATA
UMK325BJ106MM-T
GRM42-2 X7R 475K 50
10
4.7
50
50
High dv/dt voltage spikes on the input side can be critical for DC/DC converters. A good power layout and input voltage filtering help to minimize this issue. In addition to the above considerations, a 1 µF/50 V ceramic capacitor as close as possible to the VCC and GND pins is always suggested to adequately filter VCC spikes.
Output capacitor
The output capacitor is very important to meet the output voltage ripple requirement.
Using a small inductor value is useful to reduce the size of the choke but it increases the current ripple. So, to reduce the output voltage ripple, a low ESR capacitor is required.
Nevertheless, the ESR of the output capacitor introduces a zero in the open loop gain, which helps to increase the phase margin of the system. If the zero goes to a very high frequency, its effect is negligible. For this reason, ceramic capacitors and very low ESR capacitors in general should be avoided.
Tantalum and electrolytic capacitors are usually a good choice for this purpose. A list of some tantalum capacitor manufacturers is provided in
Table 7: Output capacitor selection
.
22/41 DocID13957 Rev 9
A5973D Application information
Manufacturer
Sanyo POSCAP
AVX
KEMET
Sprague
(1)
Table 7. Output capacitor selection
Series
TAE
THB/C/E
TPS
T494/5
595D
Cap. value ( µ F) Rated voltage (V)
100 to 470
100 to 470
100 to 470
100 to 470
220 to 390
4 to 16
4 to 16
4 to 35
4 to 20
4 to 20
1. POSCAP capacitors have some characteristics which are very similar to tantalum.
ESR (m )
25 to 35
25 to 55
50 to 200
30 to 200
160 to 650
Inductor
The inductor value is very important as it fixes the ripple current flowing through the output
I capacitor. The ripple current is usually fixed at 20 - 40% of I
Omax
Omax
, which is 0.4 - 0.8 A with
= 2 A. The approximate inductor value is obtained using the following formula:
Equation 20
L =
V –
V
I
OUT
T
ON where T
ON
V
OUT
is the ON time of the internal switch, given by D · T. For example, with
= 3.3 V, V
IN
= 2 V and I
O through the inductor is given by:
= 0.6 A, the inductor value is about 17 µH. The peak current
Equation 21
I
PK
= I
O
+
I
2 and it can be observed that if the inductor value decreases, the peak current (which must be lower than the current limit of the device) increases. So, when the peak current is fixed,
a higher inductor value allows a higher value for the output current. In Table 8
some inductor manufacturers are listed.
Manufacturer
Coilcraft
Coiltronics
BI
Epcos
Wurth Elektronik
Table 8. Inductor selection
Series Inductor value ( µ H) Saturation current (A)
DO3316T
UP1B
HM76-3
B82476
74456115
15 to 33
22 to 33
15 to 33
15 to 33
15 to 33
2.0 to 3.0
2.0 to 2.4
2.5 to 3.3
2 to 3
2.5 to 3
DocID13957 Rev 9 23/41
41
Application information A5973D
The layout of switching DC-DC converters is very important to minimize noise and interference. Power-generating portions of the layout are the main cause of noise and so high switching current loop areas should be kept as small as possible and lead lengths as short as possible.
High impedance paths (in particular the feedback connections) are susceptible to interference, so they should be as far as possible from the high current paths. A layout
example is provided in Figure 13
.
The input and output loops are minimized to avoid radiation and high frequency resonance problems. The feedback pin connections to the external divider are very close to the device to avoid pick-up noise. Another important issue is the ground plane of the board. Since the package has an exposed pad, it is very important to connect it to an extended ground plane in order to reduce the thermal resistance junction to ambient.
Figure 13. Layout example
24/41 DocID13957 Rev 9
A5973D Application information
The dissipated power of the device is tied to three different sources:
Conduction losses due to the not insignificant R
DSON
, which are equal to:
Equation 22
P
ON
= R
DSON
I
OUT
2
D
Where D is the duty cycle of the application. Note that the duty cycle is theoretically given by the ratio between V
OUT
and V
IN
, but in practice it is substantially higher than this value to compensate for the losses in the overall application. For this reason, the switching losses related to the R
DSON
increases compared to an ideal case.
Switching losses due to turning ON and OFF. These are derived using the following equation:
Equation 23
P
SW
= V
IN
I
OUT
T
ON
+
2
T
----------------------------------- F
SW
= V
IN
I
OUT
T
SW
F
SW
Where T
RISE
and T
FALL
represent the switching times of the power element that cause the switching losses when driving an inductive load (see switching time.
T
SW
is the equivalent
Figure 14. Switching losses
Quiescent current losses.
Equation 24
Where I
Q
is the quiescent current.
P
Q
= V
IN
I
Q
DocID13957 Rev 9 25/41
41
Application information A5973D
Example 2 :
V
IN
= 12 V
V
OUT
= 3.3 V
I
OUT
= 2 A
R
DS(on)
has a typical value of 0.25 at 25 °C and increases up to a maximum value of 0.5 at
150 °C. We can consider a value of 0.4 .
T
SW
is approximately 70 ns.
I
Q
has a typical value of 2.5 mA at V
IN
= 12 V.
The overall losses are:
Equation 25
=
P
TOT
=
2
R
DSON
I
OUT
2
+ 70
+
IN
10
– 9
I
OUT
250 10
– 3
T
SW
+
F
SW
+
V
IN
10
– 3
I
Q
=
0.93W
The junction temperature of device will be:
Equation 26
T
J
= T
A
+ Rth P
TOT
Where T
A
is the ambient temperature and Rth
J-A
is the thermal resistance junction to ambient. Considering that the device is mounted on board with a good ground plane, that it has a thermal resistance junction to ambient (Rth
J-A temperature of about 70 °C:
) of about 42 °C/W, and an ambient
Equation 27
T
J
= + C
26/41
In overcurrent protection mode, when the peak current reaches the current limit, the device reduces the T
ON
down to its minimum value (approximately 250 nsec) and the switching frequency to approximately one third of its nominal value even when synchronized to an
external signal (see Section 5.4: Current protection on page 11
). In these conditions, the duty cycle is strongly reduced and, in most applications, this is enough to limit the current to
ILIM. In any event, in case of heavy short-circuit at the output (V
O the application conditions (V cc
= 0 V) and depending on
value and parasitic effect of external components) the current peak could reach values higher than ILIM. This can be understood considering the inductor current ripple during the ON and OFF phases:
ON phase
Equation 28
I
L TON
=
V
IN
– V out
– DCR
L
L
+ R
DSON
I
T
ON
OFF phase
DocID13957 Rev 9
A5973D Application information
Equation 29
I
L TOFF
=
– V + V out
L
+ DCR
L
I
T
OFF
where V
D
is the voltage drop across the diode, DCR
L
is the series resistance of the inductor.
In short-circuit conditions V
OUT
is negligible so during T
OFF
the voltage across the inductor is very small as equal to the voltage drop across parasitic components (typically the DCR of the inductor and the V
FW
of the freewheeling diode) while during T
ON inductor is instead maximized as approximately equal to V
IN
.
the voltage applied the
So Equation 28 and Equation 29 in overcurrent conditions can be simplified to:
Equation 30
I
L TON
=
V
IN
– DCR
L
L
+ R I
T
ON MIN
V
L
250ns considering T
ON
that has been already reduced to its minimum.
Equation 31
I
L TOFF
=
– V
D
+ V out
L
+ DCR
L
I
SW
– V + V out
L
+ DCR
L
I
---------------------------------------------------------------
12 s considering that f
SW
has been already reduced to one third of the nominal.
In case a short-circuit at the output is applied and V
IN
= 12 V the inductor current is controlled in most of the applications (see
). When the application must sustain the short-circuit condition for an extended period, the external components (mainly the inductor and diode) must be selected based on this value.
In case the V
IN
is very high, it could occur that the ripple current during T
OFF does not compensate the current increase during T
ON example of a power up phase with V
IN
= V
IN MAX
( Equation 30
= 36 V, where
IL TON
>
( Equation 31 )
IL TOFF
so the current escalates and the balance between Equation 30 and Equation 31 occurs at a current slightly higher than the current limit. This must be taken into account in particular to avoid the risk of an abrupt inductor saturation.
Figure 15. Short-circuit current V
IN
= 12 V
DocID13957 Rev 9 27/41
41
Application information
Figure 16. Short-circuit current V
IN
= 24 V
A5973D
Figure 17. Short-circuit current V
IN
= 36 V
28/41 DocID13957 Rev 9
A5973D Application information
shows the evaluation board application circuit, where the input supply voltage,
V
CC
, can range from 4 V to 36 V and the output voltage is adjustable from 1.235 V to 6.3 V due to the voltage rating of the output capacitor,.
Figure 18. Evaluation board application circuit
Reference
C4
R1
R2
R3
C1
C2
C3
D1
L1
Table 9. Component list
Part number Description
GRM42-2 X7R 475K 50
POSCAP 6TAE330ML
C1206C221J5GAC
C1206C223K5RAC
STPS3L40U
DO3316T-153MLD
4.7 µF, 50 V
330 µF, 6.3 V
47 pF, 5%, 50 V
22 nF, 10%, 50 V
5.6 k , 1%, 0.1 W 0603
3.3 k , 1%, 0.1 W 0603
22 k , 1%, 0.1 W 0603
2 A, 40 V
15 µH, 3.1 A
Manufacturer
Murata
Sanyo
KEMET
KEMET
Neohm
Neohm
Neohm
STMicroelectronics
Coilcraft
DocID13957 Rev 9 29/41
41
Application information
Figure 19. PCB layout (component side)
A5973D
Figure 20. PCB layout (bottom side)
LS
Figure 21. PCB layout (front side)
LC
30/41 DocID13957 Rev 9
A5973D
8.6
Application information
Positive buck-boost regulator
The device can be used to implement a step-up/down converter with a positive output voltage.
The output voltage is given by:
Equation 32
V
OUT
= V
IN
where the ideal duty cycle D for the buck boost converter is:
Equation 33
D =
IN
V
OUT
+ V
OUT
However, due to power losses in the passive elements, the real duty cycle is always higher than this. The real value (that can be measured in the application) should be used in the following formulas.
The peak current flowing in the embedded switch is:
Equation 34
I
SW
=
I
LOAD
+
I
RIPPLE
=
I
--------------+
V
IN
f
SW while its average current is equal to:
Equation 35
I
SW
=
I
LOAD
This is due to the fact that the current flowing through the internal power switch is delivered to the output only during the OFF phase.
The switch peak current must be lower than the minimum current limit of the overcurrent
protection (see Table 4 on page 6
for details) while the average current must be lower than the rated DC current of the device.
As a consequence, the maximum output current is:
Equation 36
I
OUT MAX
I
SW MAX
where I
SW MAX
represents the rated current of the device.
The current capability is reduced by the term (1 - D) and so, for example, with a duty cycle of
0.5, and considering an average current through the switch of 2 A, the maximum output current deliverable to the load is 1 A.
DocID13957 Rev 9 31/41
41
Application information A5973D
shows the schematic circuit of this topology for a 12 V output voltage and 5 V input.
Figure 22. Positive buck-boost regulator
32/41
In
Figure 23 the schematic circuit for a standard buck-boost topology is shown. The output
voltage is:
Equation 37
V
OUT
= – V
IN
where the ideal duty cycle D for the buck boost converter is:
Equation 38
D =
– V
V
IN
– V
OUT
The considerations given in
for the real duty cycle are still valid here.
Also the Equation 34 till Equation 36 can be used to calculate the maximum output current.
So, as an example, considering the conversion V
IN
= 12 V to V
OUT
= -5 V, I
LOAD
= 0.5 A:
Equation 39
D =
5
= 0.706
Equation 40
I
SW
=
I
LOAD
=
0.5
= 1.7A
An important thing to take into account is that the ground pin of the device is connected to the negative output voltage. Therefore, the device is subjected to a voltage equal to
V
IN
- V
O
, which must be lower than 36 V (the maximum operating input voltage).
DocID13957 Rev 9
A5973D
Figure 23. Negative buck-boost regulator
Application information
See
Section 5.3: Oscillator and synchronization on page 10 for details.
Figure 24. Synchronization example
MLCCs (multiple layer ceramic capacitor) with values in the range of 10 µF - 22 µF and rated voltages in the range of 10 V - 25 V are available today at relatively low cost from many manufacturers.
These capacitors have very low ESR values (a few m ) and thus are occasionally used for the output filter in order to reduce the voltage ripple and the overall size of the application.
However, a very low ESR value affects the compensation of the loop (see
16 ) and in order to keep the system stable, a more complicated compensation network may
be required. However, due to the architecture of the internal error amplifier the bandwidth with this compensation is limited.
That is why output capacitors with a not negligible ESR are suggested. The selection of the output capacitor has to guarantee that the zero introduced by this component is inside the
DocID13957 Rev 9 33/41
41
Application information A5973D designed system bandwidth and close to the frequency of the double pole introduced by the
LC filter. A general rule for the selection of this compound for the system stability is provided in Equation 41 .
Equation 41 f
Z ESR
=
2 f
LC
f
Z ESR
OUT
bandwidth
LC
shows an example of a compensation network stabilizing the system with ceramic capacitors at the output (the optimum component value depends on the application).
Figure 25. MLCC compensation network example
34/41 DocID13957 Rev 9
A5973D Application information
At start-up the device can quickly increase the current up to the current limit in order to charge the output capacitor. If soft ramp-up of the output voltage is required, an external soft-start network can be implemented as shown in
. The capacitor C is charged up to an external reference through R and the BJT clamps the COMP pin.
This clamps the duty cycle, limiting the slew rate of the output voltage.
Figure 26. Soft-start network example
DocID13957 Rev 9 35/41
41
Typical characteristics A5973D
Figure 27. Line regulator Figure 28. Shutdown current vs. junction temperature
Figure 29. Output voltage vs. junction temperature
Figure 30. Switching frequency vs. junction temperature
Figure 31. Quiescent current vs. junction temperature
36/41 DocID13957 Rev 9
A5973D Typical characteristics
Figure 32. Junction temperature vs. output current - V
IN
= 5 V
Figure 33. Junction temperature vs. output current - V
IN
= 12 V
Figure 34. Efficiency vs. output current -
V
IN
= 5 V
Figure 35. Efficiency vs. output current -
V
IN
= 12 V
DocID13957 Rev 9 37/41
41
Package information A5973D
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK is an ST trademark.
10.1 HSOP8 package information
Figure 36. HSOP8 package outline
38/41 DocID13957 Rev 9
A5973D
Symbol h
L k ccc
E1
E2 e c
D
D1
E
A
A1
A2 b
Package information
0.00
1.25
0.31
0.17
4.80
3
5.80
3.80
2.31
Min.
0.25
0.40
Table 10. HSOP8 package mechanical data
Dimensions mm
Typ.
Min.
Max.
1.70
0.10
inch
Typ.
0.00
4.90
3.1
6.00
3.90
2.41
1.27
0.51
0.25
5.00
3.2
6.20
4.00
2.51
0.0492
0.0122
0.0067
0.1890
0.118
0.2283
0.1496
0.091
0.1929
0.122
0.095
0.50
1.27
0.0098
0.0157
0 ° (min), 8 ° (max.)
0.10
Max.
0.0669
0.0039
0.0201
0.0098
0.1969
0.126
0.2441
0.1575
0.099
0.0197
0.0500
0.0039
DocID13957 Rev 9 39/41
41
Order codes
Order code
A5973D
A5973D013TR
Table 11. Ordering information
Package
HSOP8
Packaging
Tube
Tape and reel
A5973D
Date
06-May-2008
29-Aug-2008
07-Apr-2009
03-Apr-2014
14-Aug-2014
04-Nov-2015
Revision
Table 12. Document revision history
Changes
8
9
4
5
6
7
Updated: Table 5 on page 12
Updated Table 4 on page 6
Updated Table 4 on page 6
Updated Chapter 7 on page 16
Updated Section 8.1: Component selection on page 21 (updated units in “Capacitor value” - header of Table 6 , added text below
Table 6 ).
Updated titles from Figure 32 to Figure 35 on page 37 (added values of “V
IN
”).
Updated Section 10: Package information on page 38 (reversed order of Figure 36 and Table 10 , updated titles, minor modifications).
Updated cross-references throughout document.
Minor modifications throughout document.
Updated unit in Table 4 on page 6 (replaced “W” by “ ” in row of
R
DS(on) symbol).
Added
Section 11: Order codes on page 40 .
40/41 DocID13957 Rev 9
A5973D
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© 2015 STMicroelectronics – All rights reserved
DocID13957 Rev 9 41/41
41
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