STMicroelectronics TSV522 Datasheet
Advertisement
Advertisement
DFN8 2x2
QFN16 3x3
TSV521, TSV522, TSV524,
TSV521A, TSV522A, TSV524A
High merit factor (1.15 MHz for 45
μ
A) CMOS op amps
SC70-5
MiniSO8
TSSOP14
Features
•
Gain bandwidth product: 1.15 MHz typ. at 5 V
•
Low power consumption: 45 µA typ. at 5 V
•
Rail-to-rail input and output
•
Low input bias current: 1 pA typ.
•
Supply voltage: 2.7 to 5.5 V
•
Low offset voltage: 800 µV max.
•
Unity gain stable on 100 pF capacitor
•
Automotive grade
Benefits
• Increased lifetime in battery powered applications
• Easy interfacing with high impedance sensors
Datasheet
-
production data
Related products
•
See TSV631, TSV632, TSV634 series for lower minimum supply voltage (1.5 V)
•
See LMV821, LMV822, LMV824 series for higher gain bandwidth products (5.5 MHz)
Applications
• Battery powered applications
• Portable devices
• Automotive signal conditioning
• Active filtering
• Medical instrumentation
Description
The TSV52x and TSV52xA series of operational amplifiers offer low voltage operation and rail-torail input and output. The TSV521 device is the single version, the TSV522 device the dual version, and the TSV524 device the quad version, with pinouts compatible with industry standards.
The TSV52x and TSV52xA series offer an outstanding speed/power consumption ratio,
1.15 MHz gain bandwidth product while consuming only 45 µA at 5 V. The devices are housed in the smallest industrial packages.
These features make the TSV52x, TSV52xA family ideal for sensor interfaces, battery supplied and portable applications. The wide temperature range and high ESD tolerance facilitate their use in harsh automotive applications.
Single
Table 1. Device summary
Standard V io
TSV521
Enhanced V io
TSV521A
Dual
Quad
TSV522
TSV524
TSV522A
TSV524A
April 2017
This is information on a product in full production.
DocID022743 Rev 3 1/27 www.st.com
1
Contents
Contents
TSV52x, TSV52xA
Package pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 4
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Common-mode voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Driving resistive and capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input offset voltage drift over temperature . . . . . . . . . . . . . . . . . . . . . . . . 15
Long term input offset voltage drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SC705 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DFN8 2x2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MiniSO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
QFN16 3x3 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TSSOP14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/27 DocID022743 Rev 3
TSV52x, TSV52xA
1 Package pin connections
Package pin connections
Figure 1. Pin connections for each package (top view)
OUT1 1
IN12
IN1+ 3
VCC4
NC
IN+ 1
VCC2
IN3
8
7
VCC+
OUT2
5 IN2+
TSV521
SC70-5
OUT1 1
IN12
IN1+ 3
VCC 4
5 VCC+
4 OUT
TSV522
DFN8
TSV522
MiniSO8
8
7
VCC+
OUT2
IN1+
1
2
NC
3
IN2+
4
16 15 14 13
NC
12
IN4+
11
10
NC
9
IN3+
5 6 7 8
TSV524
QFN16
TSV524
TSSOP14
1.
The exposed pads of the DFN8 (2x2) and QFN16 (3x3) can be connected to VCC- or left floating.
DocID022743 Rev 3 3/27
27
Absolute maximum ratings and operating conditions
2
TSV52x, TSV52xA
Absolute maximum ratings and operating conditions
Symbol
V
CC
V id
V in
I in
T stg
R thja
T j
ESD
Table 2. Absolute maximum ratings (AMR)
Parameter Value
Supply voltage
(1)
Differential input voltage
(2)
Input voltage
(3)
Input current
(4)
Storage temperature
Thermal resistance junction-to-ambient
(5)(6)
SC70-5
DFN8 2x2
QFN16 3x3
MiniSO8
TSSOP14
Maximum junction temperature
HBM: human body model
(7)
MM: machine model
(8)
CDM: charged device model
(9)
(all packages except SC70-5 and DFN8)
CDM: charged device model (SC70-5 and DFN8)
Latch-up immunity
6
±V
CC
V
CC-
- 0.2 to V
CC+
+ 0.2
10
-65 to +150
205
57
45
190
100
150
4
300
1.5
1.3
200
Unit
V mA
°C
°C/W
°C kV
V kV mA
1.
All voltage values, except differential voltages are with respect to network ground terminal.
2.
Differential voltages are the non inverting input terminal with respect to the inverting input terminal.
3.
V
CC
- V in
must not exceed 6 V, V in
must not exceed 6 V.
4.
Input current must be limited by a resistor in series with the inputs.
5.
Short-circuits can cause excessive heating and destructive dissipation.
6.
R th
are typical values.
7.
Human body model: 100 pF discharged through a 1.5 k
Ω resistor between two pins of the device, done for all couples of pin combinations with other pins floating.
8.
Machine model: a 200 pF cap is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5
Ω
), done for all couples of pin combinations with other pins floating.
9.
Charged device model: all pins plus package are charged together to the specified voltage and then discharged directly to ground.
Symbol
V
CC
V icm
T oper
Table 3. Operating conditions
Parameter
Supply voltage
Common-mode input voltage range
Operating free air temperature range
Value
2.7 to 5.5
V
CC-
- 0.1 to V
CC+
+ 0.1
-40 to +125
Unit
V
°C
4/27 DocID022743 Rev 3
TSV52x, TSV52xA Electrical characteristics
Table 4. Electrical characteristics at V
CC+
= +2.7 V with V
CC-
R
L
= 10 k
Ω
connected to V
CC
= 0 V, V icm
= V
CC
/2 (unless otherwise specified)
/2, T = 25 °C, and
Symbol Parameter Conditions Min.
Typ.
Max.
Unit
DC performance
V io
Offset voltage
TSV52xA, T = 25 °C
TSV52xA, -40 °C < T < 125 °C
TSV52x, T = 25 °C
Δ V io
CMR
A
V
V
I
I
I
I io ib
/ vd
OH
OL out
CC
Δ T Input offset voltage drift
Input offset current
(V out
= V
CC
/2)
TSV52x, -40 °C < T < 125 °C
T = 25 °C
-40° C < T < 125 °C
Input bias current
(V out
= V
CC
/2)
T = 25 °C
-40 °C < T < 125 °C
Common-mode rejection ratio 20 log ( Δ V ic
/ Δ V io
)
V ic
V
= -0.1 V to V
CC out
= V
CC
/2, R
L
+0.1V,
= 1 M Ω
Large signal voltage gain
V out
R
L
= 0.5 V to (V
= 1 M
Ω
CC
- 0.5V),
T = 25 °C
-40 °C < T < 125 °C
T = 25 °C
-40 °C < T < 125 °C
High level output voltage
Low level output voltage
T = 25 °C
-40 °C < T < 125 °C
T = 25 °C
-40 °C < T < 125 °C
I
I sink source
V out
= V
CC
, T = 25 °C
V out
= V
CC
, -40 °C < T < 125 °C
V out
= 0 V, T = 25 °C
V out
= 0 V, -40 °C < T < 125 °C
Supply current (per channel)
V out
= V
CC
/2, R
L
> 1 M Ω
T = 25 °C
-40 °C < T < 125 °C
AC performance
GBP Gain bandwidth product
F u
Φ m
G m
Unity gain frequency
Phase margin
Gain margin
R
L
= 10 k Ω , C
L
= 100 pF
SR Slew rate
R
L
= 10 k Ω, C
L
= 100 pF,
V out
= 0.5 V to V
CC
- 0.5 V
50
46
90
60
12
8
12
8
0.62
1
1
3
1
1
72
105
3
6
22
18
30
30
1
900
55
7
0.74
800
2600
1.5
3.3
18
10
10
35
50
35
50
51
51
µV mV
µV/°C pA dB mV mA
µA
MHz kHz degrees dB
V/µs
DocID022743 Rev 3 5/27
27
Electrical characteristics TSV52x, TSV52xA
Table 4. Electrical characteristics at V
CC+
= +2.7 V with V
CC-
R
L
= 10 k
Ω
connected to V
CC
= 0 V, V icm
= V
CC
/2, T = 25 °C, and
/2 (unless otherwise specified) (continued)
Symbol Parameter Conditions Min.
Typ.
Max.
Unit e n
THD+N
Equivalent input noise voltage
Total harmonic distortion + noise f = 1 kHz f = 10 kHz
Follower configuration, f
R
L
= 100 k Ω , V icm
= V
CC in
= 1 kHz,
/2,
BW = 22 kHz, V out
= 1 V pp
61
43
0.003
Hz
%
Table 5. Electrical characteristics at V
CC+
= +3.3 V with V
CC-
R
L
= 10 k Ω connected to V
CC
= 0 V, V icm
= V
CC
/2 (unless otherwise specified)
/2, T = 25 °C, and
Symbol Parameter Conditions Min.
Typ.
Max.
Unit
DC performance
V io
Offset voltage
TSV52xA, T = 25 °C
TSV52xA, -40 °C < T < 125 °C
TSV52x, T = 25 °C
TSV52x, -40 °C < T < 125 °C
Δ V io
/ Δ T Input offset voltage drift
Δ V io
Long term input offset voltage drift
I
I
CMR
A
V
V
I
I io ib vd
OH
OL out
CC
T = 25 °C
Input offset current
(V out
= V
CC
/2)
T = 25 °C
-40 °C < T < 125 °C
Input bias current
(V out
= V
CC
/2)
T = 25 °C
-40 °C < T < 125 °C
Common-mode rejection ratio 20 log (
Δ
V ic
/
Δ
V io
)
V ic
V
= -0.1 V to V
CC out
= V
CC
/2, R
L
+0.1 V,
= 1 M
Ω
Large signal voltage gain
V out
R
L
= 0.5 V to (V
= 1 M Ω
CC
- 0.5 V),
T = 25 °C
-40 °C < T < 125 °C
T = 25 °C
-40 °C < T < 125 °C
High level output voltage
T = 25 °C
-40 °C < T < 125 °C
Low level output voltage
T = 25 °C
-40 °C < T < 125 °C
I
I sink source
V out
= V
CC
, T = 25 °C
V out
= V
CC
, -40 °C < T < 125 °C
V out
= 0 V, T = 25 °C
V out
= 0 V, -40 °C < T < 125 °C
Supply current (per channel)
V out
= V
CC
/2, R
L
> 1 M Ω
T = 25 °C
-40 °C < T < 125 °C
51
47
91
63
20
17
19
17
3
0.3
1
1
1
1
73
106
3
7
31
27
32
32
600
2400
1.3
3.1
18
10
10
35
50
35
50
55
55
µV mV
µV/°C
μ
V month pA dB mV mA
µA
6/27 DocID022743 Rev 3
TSV52x, TSV52xA Electrical characteristics
Table 5. Electrical characteristics at V
CC+
= +3.3 V with V
CC-
R
L
= 10 k
Ω
connected to V
CC
= 0 V, V icm
= V
CC
/2, T = 25 °C, and
/2 (unless otherwise specified) (continued)
Symbol Parameter Conditions Min.
Typ.
Max.
Unit
AC performance
GBP Gain bandwidth product
F u
Φ m
G m
Unity gain frequency
Phase margin
Gain margin
SR Slew rate
R
L
= 10 k Ω , C
L
= 100 pF e n
Equivalent input noise voltage
THD+N
Total harmonic distortion + noise
R
L
= 10 k Ω, C
L
= 100 pF,
V out
= 0.5 V to V
CC
- 0.5 V f = 1 kHz f = 10 kHz
Follower configuration, f
R
L
= 100 k Ω , V icm
= V
CC in
= 1 kHz,
/2,
BW = 22 kHz, V out
= 1 V pp
0.64
1
900
55
7
0.75
60
42
0.003
MHz kHz degrees dB
V/ μ s
Hz
%
Table 6. Electrical characteristics at V
CC+
= +5 V with V
CC-
= 0 V, V icm
= V
CC
/2, T = 25 °C, and R
L
= 10 k Ω connected to V
CC
/2 (unless otherwise specified)
Symbol Parameter Conditions Min.
Typ.
Max.
Unit
DC performance
V io
Offset voltage
Δ V io
/ Δ T Input offset voltage drift
Δ V io
Long term input offset voltage drift
I
I io ib
CMR1
CMR2
Input offset current
(V out
= V
CC
/2)
Input bias current
(V out
= V
CC
/2)
Common-mode rejection ratio 20 log ( Δ V ic
/ Δ V io
)
V ic
V
= -0.1 V to V out
= V
CC
/2, R
CC
+0.1 V,
L
= 1 M Ω
Common-mode rejection ratio 20 log ( Δ V ic
/ Δ V io
)
V ic
V
= 1 V to V out
= V
CC
CC
-1 V,
/2, R
L
= 1 M Ω
TSV52xA, T = 25 °C
TSV52xA, -40 °C < T < 125 °C
TSV52x, T = 25 °C
TSV52x, -40 °C < T < 125 °C
-40 °C < T < 125 °C
(1)
T = 25 °C
(2)
T = 25 °C
-40 °C < T < 125 °C
T = 25 °C
-40 °C < T < 125 °C
T = 25 °C
-40 °C < T < 125 °C
T = 25 °C
-40 °C < T < 125 °C
54
50
63
58
3
0.7
1
1
1
1
76
84
600
2400
1
2.8
18
10
(3)
µV mV
µV/°C
μ
V month pA dB
DocID022743 Rev 3 7/27
27
Electrical characteristics TSV52x, TSV52xA
Table 6. Electrical characteristics at V
CC+
= +5 V with V
CC-
= 0 V, V and R
L
= 10 k
Ω
connected to V
CC icm
= V
CC
/2, T = 25 °C,
/2 (unless otherwise specified) (continued)
Symbol Parameter Conditions Min.
Typ.
Max.
Unit
65 87
SVR
A vd
V
OH
V
OL
I out
I
CC
Supply voltage rejection ratio 20 log ( Δ V
CC
/ Δ V io
)
V
CC
= 2.7 V to 5.5 V,
V out
= V
CC
/2
Large signal voltage gain
V out
R
L
= 0.5 V to (V
= 1 M Ω
CC
- 0.5 V),
T = 25 °C
-40 °C < T < 125 °C
T = 25 °C
-40 °C < T < 125 °C
High level output voltage
T = 25 °C
-40 °C < T < 125 °C
Low level output voltage
T = 25 °C
-40 °C < T < 125 °C
V out
= V
CC
, T = 25 °C
I
I sink source
V out
= V
CC
, -40 °C < T < 125 °C
V out
= 0 V, T = 25 °C
V out
= 0 V, -40 °C < T < 125 °C
Supply current (per channel)
V out
= V
CC
/2, R
L
> 1 M Ω
T = 25 °C
-40 °C < T < 125 °C
60
94
68
36
27
36
27
109
5
9
55
55
45
45
35
50
35
50
60
60 dB mV mA
µA
AC performance
GBP
F u
Φ m
G m
SR
Gain bandwidth product
Unity gain frequency
Phase margin
Gain margin
Slew rate
R
L
= 10 k Ω , C
L
= 100 pF
R
L
= 10 k Ω , C
L
= 100 pF
R
L
= 10 k Ω , C
L
= 100 pF
R
L
= 10 k Ω , C
L
= 100 pF
R
L
= 10 k
Ω,
C
L
= 100 pF,
V out
= 0.5 V to V
CC
- 0.5V
0.73
1.15
900
55
7
0.89
MHz kHz degrees dB
V/ μ s
e n
Low-frequency peak-topeak input noise
Bandwidth: f = 0.1 to 10 Hz 14 µV pp e n
THD+N
Equivalent input noise voltage
Total harmonic distortion + noise f = 1 kHz f = 10 kHz
Follower configuration, f
R
L
= 100 k
Ω
, V icm
= V
CC in
= 1 kHz,
/2,
BW = 22 kHz, V out
= 1 V pp
57
39
0.002
Hz
%
1.
See
Section 4.6: Input offset voltage drift over temperature .
2.
Typical value is based on the V io
drift observed after 1000 h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration.
3.
Guaranteed by design.
8/27 DocID022743 Rev 3
TSV52x, TSV52xA Electrical characteristics
Figure 2. Supply current vs. supply voltage at
V icm
= V
CC
/2
Figure 3. Input offset voltage distribution at
V
CC
= 5 V, V icm
= 2.5 V
9LRGLVWULEXWLRQDW7 &IRU9&& 99LFP 9
Figure 4. Input offset voltage temperature coefficient distribution
$0
Figure 5. Input offset voltage vs. input
Common-mode voltage at V
CC
= 5 V
9LFP 9&&
9&& 9
7 &
7 &
7 &
9&& 9
9LFP9
/LPLWIRU769[$
/LPLWIRU769;
$0
$0
Figure 6. Input offset voltage vs. temperature at
V
CC
= 5 V
Figure 7. Output current vs. output voltage at
V
CC
= 2.7 V
7 &
7 &
7 &
9&& 99LFP 9
$0
DocID022743 Rev 3
7 &
7 &
7 &
2XWSXWYROWDJH9
9&& 9
$0
9/27
27
Electrical characteristics
Figure 8. Output current vs. output voltage at
V
CC
= 5.5 V
7 &
7 &
7 &
TSV52x, TSV52xA
Figure 9. Bode diagram at V
CC
R
L
= 10 k Ω
= 2.7 V,
7 & 7 &
7 &
2XWSXWYROWDJH9
9&& 9
$0
Figure 10. Bode diagram at V
CC
R
L
= 2 k Ω
= 2.7 V,
7 &
7 &
7 &
*DLQ
3KDVH
7 &
7 &
7 &
*DLQ
3KDVH
9&& 99LFP 9*
&/ S)9UO 9&&
)UHTXHQF\N+]
$0
Figure 11. Bode diagram at V
CC
R
L
= 10 k Ω
= 5.5 V,
7 &
7 &
7 &
*DLQ
3KDVH
9&& 99LFP 9*
&/ S)9UO 9&&
)UHTXHQF\N+]
$0
Figure 12. Bode diagram at V
CC
R
L
= 2 k Ω
= 5.5 V,
7 &
7 &
7 &
*DLQ
3KDVH
9&& 99LFP 9*
&/ S)9UO 9&&
)UHTXHQF\N+]
Figure 13. Noise vs. frequency
$0
9&& 99LFP 9
7DPE &
9&& 99LFP 9*
&/ S)9UO 9&&
)UHTXHQF\N+]
)UHTXHQF\+]
10/27
$0
DocID022743 Rev 3
$0
TSV52x, TSV52xA Electrical characteristics
Figure 14. Positive slew rate vs. supply voltage Figure 15. Negative slew rate vs. supply voltage
&/ S)
9LQIURP9WR9&&9
65FDOFXODWHGIURPWR
7 &
7 &
7 &
6XSSO\YROWDJH9
$0
Figure 16. THD+N vs. frequency at V
CC
= 2.7 V Figure 17. THD+N vs. frequency at V
CC
= 5.5 V
9LQ 9SS
*DLQ
9LFP 9&&
9LQ 9SS
*DLQ
9LFP 9&&
(
)UHTXHQF\+]
$0
Figure 18. THD+N vs. output voltage at
V
CC
= 2.7 V
(
)UHTXHQF\+]
$0
Figure 19. THD+N vs. output voltage at
V
CC
= 5.5 V
(
I N+]
*DLQ
%: N+]
9LFP 9&&
2XWSXWYROWDJH9SS
$0
(
I N+]
*DLQ
%: N+]
9LFP 9&&
2XWSXWYROWDJH9SS
$0
DocID022743 Rev 3 11/27
27
Electrical characteristics TSV52x, TSV52xA
Figure 20. Output impedance versus frequency in closed-loop configuration
9&& 9WR9
2VFOHYHO 9506
*
7 &
)UHTXHQF\N+]
$0
Figure 21. Response to a 100 mV input step for gain = 1 at V
CC
= 5.5 V rising edge
Figure 22. Response to a 100 mV input step for gain = 1 at V
CC
= 5.5 V falling edge
V
CC
= 5.5 V, V icm
= 2.75 V
R
L
= 10 k Ω , C
L
= 100 pF
0.5 µs/div., 20 mV/div.
V
CC
= 5.5 V, V icm
= 2.75 V
R
L
= 10 k Ω , C
L
= 100 pF
0.5 µs/div., 20 mV/div.
Figure 23. PSRR vs. frequency at V
CC
= 2.7 V Figure 24. PSRR vs. frequency at V
CC
= 5.5 V
12/27
9&& 99LFP 9*
&/ S)9ULSSOH P9SS
)UHTXHQF\+]
$0
DocID022743 Rev 3
9&& 99LFP 9*
&/ S)9ULSSOH P9SS
)UHTXHQF\+]
$0
TSV52x, TSV52xA Application information
The amplifiers of the TSV52x, TSV52xA series can operate from 2.7 V to 5.5 V. Their parameters are fully specified for 2.7 V, 3.3 V and 5 V power supplies. However, the parameters are very stable in the full V
CC
range and several characterization curves show the TSV52x, TSV52xA device characteristics at 2.7 V. Additionally, the main specifications are guaranteed in extended temperature ranges from -40 to +125 °C.
4.2 Common-mode voltage range
The TSV52x, TSV52xA devices are built with two complementary PMOS and NMOS input differential pairs. The devices have a rail-to-rail input and the input Common-mode range is extended from V
CC-
- 0.1 V to V
CC+
+ 0.1 V.
The N channel pair is active for input voltage close to the positive rail typically (V
CC+
- 0.7 V) to 100 mv above the positive rail.
The P channel pair is active for input voltage close to the negative rail typically 100 mV below the negative rail to V
CC-
+ 0.7 V.
And between V
CC-
+ 0.7 V and V
CC+
- 0.7 V the both N and P pairs are active.
When the both pairs work together it allows to increase the speed of the TSV52x, TSV52xA devices. This architecture improves the merit factor of the whole device. In the transition region, the performance of CMR, SVR, V io degraded.
(
Figure 25 and Figure 26 ) and THD is slightly
Figure 25. Input offset voltage vs. input common-mode at V
CC
= 2.7 V
Figure 26. Input offset voltage vs. input common-mode at V
CC
= 5.5 V
9LFP9
$0
9LFP9
$0
DocID022743 Rev 3 13/27
27
Application information TSV52x, TSV52xA
The TSV52x, TSV52xA series are guaranteed without phase reversal as shown in
.
It is extremely important that the current flowing in the input pin does not exceed 10 mA. In order to limit this current, a serial resistor can be added on the V in
path.
Figure 27. Phase reversal test schematic Figure 28. No phase reversal
9LQS
B
9
9&&
9&&
9RXW
9
$0
9LQS9
9&& 9
9LQQ 9
$0
4.5
The operational amplifier output levels can go close to the rails: 35 mV maximum above and below the rail when connected to a 10 k
Ω
resistive load to V
CC
/2.
Driving resistive and capacitive loads
To drive high capacitive loads, adding an in series resistor at the output can improve the
stability of the device (see Figure 29 for the recommended in series value). Once the in
series resistor has been selected, the stability of the circuit should be tested on the bench and simulated with simulation models. The R load
is placed in parallel with the capacitive load. The R load
and the in series resistor create a voltage divider which introduces an error proportional to the ratio R s
/R load
. By keeping R s as low as possible, this error is generally negligible.
14/27 DocID022743 Rev 3
TSV52x, TSV52xA Application information
Figure 29. In series resistor versus capacitive load
6WDEOH
4.6
8QVWDEOH
9&& 99LFP 97 &5ORDG
0LQLPXPVHULDOUHVLVWRUWREHDGGHGWRDJLYHQ
FDSDFLWLYHORDGLQRUGHUWRHQVXUHVWDELOLW\
&DSDFLWLYHORDGQ)
$0
Input offset voltage drift over temperature
The maximum input voltage drift over the temperature variation is defined as the offset variation related to offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift over temperature enables the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1
.
Equation 1
Δ V
Δ T io
= max
V io
T – V io
( 25 ° C
T 25 ° C
)
--------------------------------------------------
– with T = -40 °C and 125 °C.
The datasheet maximum value is guaranteed by a measurement on a representative sample size ensuring a C pk
(process capability index) greater than 1.33.
DocID022743 Rev 3 15/27
27
Application information
4.7
TSV52x, TSV52xA
Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
•
Voltage acceleration, by changing the applied voltage
• Temperature acceleration, by changing the die temperature (below the maximum junction temperature allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using
Equation 2
A
FV
= e
β ⋅ (
V
S
– V
U
)
Where:
A
FV
is the voltage acceleration factor
β
is the voltage acceleration constant in 1/V, constant technology parameter (
β
= 1)
V
S
is the stress voltage used for the accelerated test
V
U
is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in Equation 3 .
Equation 3
A
FT
= e
E a
-----k
⋅
T
U
– ------
T
S
Where:
A
FT
is the temperature acceleration factor
E a
is the activation energy of the technology based on the failure rate k is the Boltzmann constant (8.6173 x 10
-5
eV.K
-1
)
T
U
is the temperature of the die when V
U
is used (K)
T
S
is the temperature of the die under temperature stress (K)
The final acceleration factor, A
F
, is the multiplication of the voltage acceleration factor and the temperature acceleration factor (
).
Equation 4
A
F
= A
FT
× A
FV
A
F is calculated using the temperature and voltage defined in the mission profile of the product. The A
F
value can then be used in
Equation 5 to calculate the number of months of
use equivalent to 1000 hours of reliable stress duration.
16/27 DocID022743 Rev 3
TSV52x, TSV52xA Application information
Equation 5
Months = A
F
×
1000 h
×
12 months
⁄ (
24 h
×
365.25 days
)
To evaluate the op-amp reliability, a follower stress condition is used where V
CC
is defined as a function of the maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules).
The V io
drift (in µV) of the product after 1000 h of stress is tracked with parameters at different measurement conditions (see
Equation 6
V
CC
= maxV op
with V icm
= V
CC
⁄ 2
The long term drift parameter ( Δ V io
), estimating the reliability performance of the product, is obtained using the ratio of the V io
(input offset voltage value) drift over the square root of the calculated number of months (
).
Equation 7
Δ V io
=
(
V io drift
-----------------------------months ) where V io
drift is the measured drift value in the specified test conditions after 1000 h stress duration.
For correct operation, it is advised to add 10 nF decoupling capacitors as close as possible to the power supply pins.
4.9 Macromodel
Accurate macromodels of the TSV52x, TSV52xA devices are available on
STMicroelectronics™ website at www.st.com
. These models are a trade-off between accuracy and complexity (that is, time simulation) of the TSV52x, TSV52xA operational amplifiers. They emulate the nominal performance of a typical device within the specified operating conditions mentioned in the datasheet. They also help to validate a design approach and to select the appropriate operational amplifier, but they do not replace onboard measurements .
DocID022743 Rev 3 17/27
27
Package information TSV52x, TSV52xA
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK is an ST trademark.
18/27 DocID022743 Rev 3
TSV52x, TSV52xA
5.1 SC705 package information
Figure 30. SC70-5 package outline
SIDE VIEW
DIMENSIONS IN MM
Package information
GAUGE PLANE
COPLANAR LEADS
SEATING PLANE
Ref c
D
E
E1
A
A1
A2 b
L
< e e1
TOP VIEW
Min.
0.10
1.80
1.80
1.15
0.80
0
0.80
0.15
0.26
0°
Table 7. SC70-5 package mechanical data
Dimensions
Millimeters
Typ.
0.90
2.00
2.10
1.25
0.65
1.30
0.36
Max.
0.22
2.20
2.40
1.35
1.10
0.10
1.00
0.30
0.46
8°
Min.
0.032
0.032
0.006
0.004
0.071
0.071
0.045
0.010
Inches
Typ.
0.035
0.079
0.083
0.049
0.025
0.051
0.014
Max.
0.043
0.004
0.039
0.012
0.009
0.087
0.094
0.053
0.018
DocID022743 Rev 3 19/27
27
Package information TSV52x, TSV52xA
Figure 31. DFN8 2x2x0.6, 8 pitch, 0.5 mm package outline
20/27
Ref.
D
D2
E
E2
A
A1
A3 b e
L ddd
Table 8. DFN8 2x2x0.6, 8 pitch, 0.5 mm package mechanical data
Dimensions
Min.
0.51
Millimeters
Typ.
0.55
Max.
0.60
0.05
Min.
0.020
Inches
Typ.
0.022
0.18
1.85
1.45
1.85
0.75
0.15
0.25
2.00
1.60
2.00
0.90
0.50
0.30
2.15
1.70
2.15
1.00
0.007
0.073
0.057
0.073
0.030
0.006
0.010
0.079
0.063
0.079
0.035
0.020
0.425
0.08
Max.
0.024
0.002
0.012
0.085
0.067
0.085
0.039
0.017
0.003
DocID022743 Rev 3
TSV52x, TSV52xA Package information
Figure 32. DFN8 2x2x0.6, 8 pitch, 0.5 mm footprint recommendation
DocID022743 Rev 3 21/27
27
Package information
5.3 MiniSO8 package information
Figure 33. MiniSO8 package outline
TSV52x, TSV52xA
22/27 e
L
L1
L2 k ccc c
D
E
E1
A
A1
A2 b
Symbol
0LQL62/
Table 9. MiniSO8 package mechanical data
Dimensions
Millimeters
Min. Typ. Max. Min.
1.10
0 0.15
0.75
0.85
0.95
0.22 0.40
0.08
2.80
3.00
4.65
4.90
2.80 3.00
0.23
3.20
5.15
3.10
0.65
0.40 0.60
0.95
0.25
0°
0.80
8°
0.10
0.016
0°
0
0.030
0.009
0.003
0.11
0.183
0.11
Inches
0.118
0.193
0.118
0.026
0.024
0.037
0.010
Typ. Max.
0.033
0.043
0.006
0.037
0.016
0.009
0.126
0.203
0.122
0.031
8°
0.004
DocID022743 Rev 3
TSV52x, TSV52xA
5.4 QFN16 3x3 package information
Package information
Figure 34. QFN16 3x3x0.9 mm, pad 1.7 package outline
9)431/
DocID022743 Rev 3 23/27
27
Package information TSV52x, TSV52xA
Symbol
Table 10. QFN16 3x3x0.9 mm, pad 1.7 package mechanical data
Dimensions
Millimeters Inches
Nom.
0.90
Min.
Max.
0.80 1.00
0.00
0.05
Nom.
0.035
Min.
0.032
0.000
b
D
D2
E
E2
A
A1
A3 e
L
0.20
3.00
3.00
0.50
0.18
2.90
1.50
2.90
1.50
0.30
0.30
3.10
1.80
3.10
1.80
0.50
0.008
0.118
0.118
0.020
0.007
0.114
0.061
0.114
0.061
0.012
Max.
0.039
0.002
0.012
0.122
0.071
0.122
0.071
0.020
Figure 35. QFN16 3x3x0.9 mm, pad 1.7 footprint recommendation
24/27 DocID022743 Rev 3
4)1)3
TSV52x, TSV52xA
5.5 TSSOP14 package information
Package information
Figure 36. TSSOP14 body 4.40 mm, lead pitch 0.65 mm package outline
DDD c
D
E
E1
A
A1
A2 b e
L
L1 k aaa
Table 11. TSSOP14 body 4.40 mm, lead pitch 0.65 mm package mechanical data
Dimensions
Symbol Millimeters Inches
Min.
Typ. Max. Min. Typ. Max.
1.20 0.047
0.05 0.15 0.006
0.80
1.00
1.05
0.031 0.039 0.041
0.012
4.90
6.20
4.30
0.45
5.00
6.40
4.40
0.60
1.00
5.10 0.193
0.197 0.201
6.60
0.244 0.252 0.260
4.50 0.169 0.173 0.176
0.75
0.10 0.018 0.024 0.030
DocID022743 Rev 3 25/27
27
Ordering information TSV52x, TSV52xA
Order code Temperature range
Table 12. Order codes
Package Packing Marking
TSV521ICT
TSV522IQ2T
TSV522IST
TSV524IQ4T
TSV524IPT
TSV522IYST
TSV524IYPT
TSV521AICT
TSV522AIQ2T
TSV522AIST
TSV524AIQ4T
TSV524AIPT
TSV522AIYST
TSV524AIYPT
-40 to 125 °C
-40 to 125 °C
Automotive grade
(1)
-40 to 125 °C
-40 to 125 °C
SC70-5
DFN8 2 x 2
MiniSO8
QFN16 3 x 3
TSSOP14
MiniSO8
TSSOP14
SC70-5
DFN8 2 x 2
MiniSO8
QFN16 3 x 3
TSSOP14
MiniSO8
TSSOP14
Tape and reel
1.
Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC
Q001 and Q 002 or equivalent.
K1G
K1G
K1G
K1G
TSV524
K1H
TSV524Y
K1K
K1K
K1K
K1K
TSV524A
K1L
TSV524AY
Date
19-Jun-2012
31-Jan-2014
12-Apr-2017
Revision
1
2
3
Table 13. Document revision history
Changes
Initial release.
Updated information of “ Related products”
“ Figure 1: Pin connections for each package (top view)”
“ Section 4: Application information” : updated text to make it more readable
“Table 12” : updated automotive footnotes.
: “L” dimension changed from 0.5 mm to 0.425 mm.
26/27 DocID022743 Rev 3
TSV52x, TSV52xA
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
DocID022743 Rev 3 27/27
27
Download
Public link updated
The public link to your chat has been updated. You may view and manage your chat links after registration here.
Document public link
Advertisement