STMicroelectronics TSV732 Datasheet
Pubblicità
Pubblicità
TSV731, TSV732, TSV734
High accuracy (200
μ
V) micropower 60
μ
A, 900 kHz
5 V CMOS operational amplifiers
Datasheet
-
preliminary data
Single (TSV731)
SC70-5
Dual (TSV732)
Benefits
• Higher accuracy without calibration
• Energy saving
• Guaranteed operation on low-voltage battery
Related products
• See the TSV71 series (150 kHz for 14 μ A) for more power savings
DFN8 2x2
QFN16 3x3
MiniSO-8
Quad (TSV734)
TSSOP14
Features
• Low offset voltage: 200 µV max.
• Low power consumption: 60 µA at 5 V
• Low supply voltage: 1.5 V to 5.5 V
• Gain bandwidth product: 900 kHz typ.
• Low input bias current: 1 pA typ.
• Rail-to-rail input and output
• EMI hardened operational amplifiers
• High tolerance to ESD: 4 kV HBM
• Extended temperature range: -40 to +125 °C
Applications
• Battery powered applications
• Portable devices
• Signal conditioning
• Active filtering
• Medical instrumentation
Description
The TSV73x series of single, dual, and quad operational amplifiers offer low-voltage operation, rail-to-rail input and output, and excellent accuracy (V io
lower than 200 μ V at 25 ° C).
These devices benefit from STMicroelectronics ®
5 V CMOS technology and offer an excellent speed/power consumption ratio (900 kHz typical gain bandwidth) while consuming 60 μ A typical at
5 V. The TSV73x series also feature an ultra-low input bias current.
The single version (TSV731), the dual version
(TSV732), and the quad version (TSV734) are housed in the smallest industrial packages.
These characteristics make the TSV73x family ideal for sensor interfaces, battery-powered and portable applications, and active filtering.
March 2013 DocID023708 Rev 2
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/29 www.st.com
29
Contents
Contents
TSV731, TSV732, TSV734
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 4
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input offset voltage drift over temperature . . . . . . . . . . . . . . . . . . . . . . . . 16
Long-term input offset voltage drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SC70-5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DFN8 2x2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MiniSO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
QFN16 3x3 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TSSOP14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/29 DocID023708 Rev 2
TSV731, TSV732, TSV734 Pin connections
287
,1
,1
9&&
Figure 1. Pin connections (top view)
Single
,1
9&&
,1
SC70-5 (TSV731)
9&&
287
Dual
DFN8 2x2 (TSV732)
9&&
287
,1
,1
287
,1
,1
9&&
MiniSO-8 (TSV732)
9&&
287
,1
,1
Quad
,1
9&&
1&
,1
1&
,1
9&&
1&
,1
QFN16 3x3 (TSV734) TSSOP14 (TSV734)
1. The exposed pads of the QFN16 3x3 can be connected to VCC- or left floating.
DocID023708 Rev 2 3/29
Absolute maximum ratings and operating conditions
2
TSV731, TSV732, TSV734
Absolute maximum ratings and operating conditions
Symbol
V
CC
V id
V in
I in
T stg
R thja
R thjc
T j
ESD
Table 1. Absolute maximum ratings (AMR)
Parameter
Supply voltage
(1)
Differential input voltage
(2)
Input voltage
(3)
Input current
(4)
Storage temperature
Thermal resistance junction-to-ambient
(5)(6)
SC70-5
DFN8 2x2
MiniSO8
QFN16 3x3
TSSOP14
Thermal resistance junction-to-case
DFN8 2x2
Maximum junction temperature
HBM: human body model
(7)
MM: machine model for TSV731
(8)
MM: machine model for TSV732
MM: machine model for TSV734
CDM: charged device model except MiniSO8
(9)
CDM: charged device model for MiniSO8
Latchup immunity
Value
6
±V
CC
V
CC-
- 0.2 to V
CC+
+ 0.2
10
-65 to +150
200
300
1.5
1.3
200
33
150
4
150
205
120
190
45
100
Unit
V mA
°C
°C/W
°C kV
V kV mA
1. All voltage values, except the differential voltage are with respect to the network ground terminal.
2. The differential voltage is a non-inverting input terminal with respect to the inverting input terminal. The
TSV732 and TSV734 devices include an internal differential voltage limiter that clamps internal differential voltage at 0.5 V.
3.
V
CC
- V in
must not exceed 6 V, V in
must not exceed 6 V.
4. Input current must be limited by a resistor in series with the inputs.
5. Short-circuits can cause excessive heating and destructive dissipation.
6. R th
are typical values.
7. Human body model: 100 pF discharged through a 1.5 k all couples of pin combinations with other pins floating.
Ω resistor between two pins of the device, done for
8. Machine model: a 200 pF cap is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 combinations with other pins floating.
Ω ), done for all couples of pin
9. Charged device model: all pins plus package are charged together to the specified voltage and then discharged directly to ground.
4/29 DocID023708 Rev 2
TSV731, TSV732, TSV734 Absolute maximum ratings and operating conditions
Symbol
V
CC
V icm
T oper
Table 2. Operating conditions
Parameter
Supply voltage
Common mode input voltage range
Operating free air temperature range
Value
1.5 to 5.5
V
CC-
- 0.1 to V
CC+
+ 0.1
-40 to +125
Unit
V
°C
DocID023708 Rev 2 5/29
Electrical characteristics TSV731, TSV732, TSV734
Table 3. Electrical characteristics at V
R
L
CC+
= 1.8 V with V
= 10 k Ω connected to V
CC
CC-
= 0 V, V icm
= V
CC
/2, T = 25 °C, and
/2 (unless otherwise specified)
Symbol Parameter Conditions Min.
Typ.
Max.
Unit
DC performance
V
Δ V io
I
I
A io io ib
/ vd
Δ
CMR
T
Input offset voltage
(V
(V icm out
= 0 V)
Input offset current
= V
CC
/2)
Input offset voltage drift
Input bias current (V out
= V
CC
/2)
Common mode rejection ratio
20 log ( Δ V
V
V icm out
= 0 V to V
= V
CC icm
/ Δ V
/2, R io
)
CC
,
L
> 1 M Ω
Large signal voltage gain
V out
= 0.5 V to (V
CC
- 0.5 V)
T = 25 °C
-40 °C < T< 85 °C
-40 °C < T< 125 °C
-40 °C < T< 125 °C
(1)
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
V
V
I
I
OH
OL out
CC
I
I
High level output voltage
(V
OH
= V
CC
- V out
)
Low level output voltage sink (
V source out
(V
= V out
CC)
= 0 V)
Supply current (per channel,
V out
= V
CC
/2, R
L
> 1 M Ω)
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
72
66
105
90
6
4
5
3
1
1
1
1
90
12
7
58
75
80
40
60
200
500
650
4.5
10
(2)
300
300
70
85
μ V
μ V/°C pA dB mV mA
µA
6/29 DocID023708 Rev 2
TSV731, TSV732, TSV734 Electrical characteristics
Table 3. Electrical characteristics at V
R
L
= 10 k Ω connected to V
CC+
CC
= 1.8 V with V
CC-
= 0 V, V icm
= V
CC
/2, T = 25 °C, and
/2 (unless otherwise specified) (continued)
Symbol Parameter Conditions Min.
Typ.
Max.
Unit
AC performance
GBP
F u
Φ m
G m
Gain bandwidth product
Unity gain frequency
Phase margin
Gain margin
SR Slew rate
(3)
R
L
= 10 k Ω , C
L
= 100 pF
700 850
650
45
12 kHz
Degrees dB
R
L
= 10 k Ω, C
L
= 100 pF,
V out
= 0.5 V to V
CC
- 0.5 V f = 1 kHz
0.35
35
V/ μ s e n
Equivalent input noise voltage f = 10 kHz 32
Hz t init
Initialization time
(4)
T = 25 °C
-40 °C < T< 125 °C
5
60 ms
1. See
Section 4.4: Input offset voltage drift over temperature .
2. Guaranteed by characterization.
3. Slew rate value is calculated as the average between positive and negative slew rates.
4. Initialization time is defined as the delay after power-up to guarantee operation within specified performances. Guaranteed by design. See
Section 4.6: Initialization time
.
DocID023708 Rev 2 7/29
Electrical characteristics TSV731, TSV732, TSV734
Table 4. Electrical characteristics at V
R
L
CC+
= 3.3 V with V
= 10 k Ω connected to V
CC
CC-
= 0 V, V icm
= V
CC
/2, T = 25 °C, and
/2 (unless otherwise specified)
Symbol Parameter Conditions Min.
Typ.
Max.
Unit
DC performance
I out
I sink (
V out
= V
CC)
I source
(V out
= 0 V)
T = 25 °C
V io
Input offset voltage -40 °C < T< 85 °C
-40 °C < T< 125 °C
-40 °C < T< 125 °C
(1) Δ V io
/ Δ T Input offset voltage drift
Δ V io
Long-term input offset voltage drift
I
I
CMR
A
V
V io ib vd
OH
OL
T = 25 °C
(2)
Input offset current
(V
Input bias current
(V out out
= V
= V
CC
CC
/2)
/2)
High level output voltage
(V
OH
T = 25 °C
Common mode rejection ratio
20 log ( Δ V icm
V
R icm
L
= 0 V to V
> 1 M Ω
/ Δ V io
CC
)
, V out
= V
CC
/2,
T = 25 °C
-40 °C < T< 125 °C
Large signal voltage gain
V out
= 0.5 V to (V
CC
- 0.5 V)
T = 25 °C
-40 °C < T< 125 °C
= V
CC
- V out
)
Low level output voltage
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
I
CC
Supply current (per channel,
V out
= V
CC
/2, R
L
> 1 M Ω)
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
83
76
105
90
25
15
20
15
0.3
1
1
1
1
100
40
28
59
75
80
40
60
200
500
650
4.5
10 (3)
300
300
70
85
μ V
μ V/°C
μ
V month pA dB mV mA
µA
8/29 DocID023708 Rev 2
TSV731, TSV732, TSV734 Electrical characteristics
Table 4. Electrical characteristics at V
R
L
= 10 k Ω connected to V
CC
CC+
= 3.3 V with V
CC-
= 0 V, V icm
= V
CC
/2, T = 25 °C, and
/2 (unless otherwise specified) (continued)
Symbol Parameter Conditions Min.
Typ.
Max.
Unit
AC performance
GBP
F u
Φ m
G m
Gain bandwidth product
Unity gain frequency
Phase margin
Gain margin
SR Slew rate
(4)
R
L
= 10 k Ω , C
L
= 100 pF
700 850
650
45
15 kHz
Degrees dB
R
L
= 10 k Ω, C
L
= 100 pF,
V out
= 0.5 V to V
CC
- 0.5 V f = 1 kHz
0.35
35
V/ μ s e n
Equivalent input noise voltage f = 10 kHz 32
Hz t init
Initialization time
(5)
T = 25 °C
-40 °C < T< 125 °C
5
50 ms
1. See
Section 4.4: Input offset voltage drift over temperature .
2. Typical value is based on the V io
drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration. See
Long-term input offset voltage drift
.
3. Guaranteed by characterization.
4. Slew rate value is calculated as the average between positive and negative slew rates.
5. Initialization time is defined as the delay after power-up which guarantees operation within specified performances.
Guaranteed by design.
See
Section 4.6: Initialization time .
DocID023708 Rev 2 9/29
Electrical characteristics TSV731, TSV732, TSV734
Table 5. Electrical characteristics at V
CC+
= 5 V with V and R
L
= 10 k Ω connected to V
CC
CC-
= 0 V, V icm
= V
CC
/2, T = 25 °C,
/2 (unless otherwise specified)
Symbol Parameter Conditions Min.
Typ.
Max.
Unit
DC performance
T = 25 °C
V io
Input offset voltage -40 °C < T< 85 °C
-40 °C < T< 125 °C
-40 °C < T< 125 °C
(1) Δ V io
/ Δ T Input offset voltage drift
Δ V io
Long-term input offset voltage drift io ib
CMR
SVR
A
EMIRR
V
I
I vd
OH
T = 25 °C
(2)
Input offset current
(V out
= V
CC
/2)
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
Input bias current
(V out
= V
CC
/2)
-40 °C < T< 125 °C
Common mode rejection ratio 20 log ( Δ V icm
/ Δ V io
)
V icm
= 0 V to V
V out
= V
CC
CC
/2, R
L
,
> 1 M Ω
Supply voltage rejection ratio
20 log ( Δ V
V
CC
CC
/ Δ V io
)
= 1.5 to 5.5 V, V ic
= 0 V
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
Large signal voltage gain
V out
EMIRR = 20 log (V
RFpeak
/ Δ V io
)
(V
= 0.5 V to (V
OH
= V
CC
EMI rejection ratio
CC
- V out
)
- 0.5 V)
High level output voltage
R
L
= 10 k Ω , T = 25 °C
R
L
= 10 k Ω , -40 °C < T< 125 °C
V
RF
= 100 mV
RFpeak, f = 400 MHz
V
RF
= 100 mV
RFpeak, f = 900 MHz
V
RF
= 100 mV
RFpeak
, f = 1800 MHz
V
RF
= 100 mV
RFpeak
, f = 2400 MHz
T = 25 °C
-40 °C < T< 125 °C
V
I
OL out
I
I
Low level output voltage sink (
V source out
(V
= V out
CC)
= 0 V)
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
I
CC
Supply current (per channel,
V out
= V
CC
/2, R
L
> 1 M Ω)
T = 25 °C
-40 °C < T< 125 °C
80
78
76
74
105
90
40
25
40
25
0.7
1
1
1
1
94
90
41
(4)
51
61
66
68
52
60
75
80
40
60
200
500
650
4.5
10 (3)
70
85
μ V
μ V/°C
μ
V month pA dB mV mA
µA
10/29 DocID023708 Rev 2
TSV731, TSV732, TSV734 Electrical characteristics
Table 5. Electrical characteristics at V
CC+ and R
L
= 10 k Ω connected to V
CC
= 5 V with V
CC-
= 0 V, V icm
= V
CC
/2, T = 25 °C,
/2 (unless otherwise specified) (continued)
Symbol Parameter Conditions Min.
Typ.
Max.
Unit
AC performance
GBP
F u
Φ m
G m
∫
SR e n
Gain bandwidth product
Unity gain frequency
Phase margin
R
L
= 10 k Ω , C
L
= 100 pF
Gain margin
Slew rate
(5)
R
L
= 10 k Ω, C
L
= 100 pF,
V out
= 0.5 V to V
CC
- 0.5 V
Low-frequency peak-to-peak input noise
Bandwidth: f = 0.1 to 10 Hz
700 900
700
48
15
0.35
7 kHz
Degrees dB
V/ μ s
µV pp e n
Equivalent input noise voltage f = 1 kHz f = 10 kHz
35
32
Hz
THD+N t init
Total harmonic distortion + noise
Initialization time
(6) f in
R
L
= 1 kHz, A
CL
= 100 k Ω , V
= 1, icm
= (V
BW = 22 kHz, V out
CC
- 1 V)/2,
= 0.5 V pp
T = 25 °C
-40 °C < T< 125 °C
0.002
5
50
% ms
1. See
Section 4.4: Input offset voltage drift over temperature .
2. Typical value is based on the V io
drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
Long-term input offset voltage drift
.
3. Guaranteed by characterization.
4. Tested on SC70-5 package.
5. Slew rate value is calculated as the average between positive and negative slew rates.
6. Initialization time is defined as the delay after power-up to guarantee operation within specified performances. Guaranteed by design. See
Section 4.6: Initialization time
.
DocID023708 Rev 2 11/29
Electrical characteristics
Figure 2. Supply current vs. supply voltage at V icm
= V
CC
/2
80
70
60
50
40
30
20
T = 125 ˚C
T = 25 ˚C
T = -40 ˚C
10
Vicm = VCC/2
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Supply voltage (V)
Figure 4. Input offset voltage distribution at V
CC
= 3.3 V, V icm
= V
CC
/2
9&& 9
9LFP 9
7 &
Figure 3. Input offset voltage distribution at V
CC
= 5 V, V icm
= V
CC
/2
9&& 9
9LFP 9
7 &
TSV731, TSV732, TSV734
,QSXWRIIVHWYROWDJH9
Figure 5. Input offset voltage temperature coefficient distribution
9&& 9
9LFP 9
7 &
,QSXWRIIVHWYROWDJH9 9LR
Figure 6. Input offset voltage vs. input common mode voltage
Figure 7. Input offset voltage vs. temperature
7 & 7 &
7 &
0D[LPXP9LR
12/29
9&& 9
,QSXWFRPPRQPRGHYROWDJH9
DocID023708 Rev 2
9&& 9
7HPSHUDWXUH&
TSV731, TSV732, TSV734
Figure 8. Output current vs. output voltage at V
CC
= 1.5 V
6LQN
9LG 9
7 &
7 &
7 &
9&& 9
Electrical characteristics
Figure 9. Output current vs. output voltage at V
CC
= 5 V
6LQN
9LG 9
7 &
7 &
7 &
9&& 9
6RXUFH
9LG 9
2XWSXWYROWDJH9
Figure 10. Output current vs. supply voltage
6LQN
9LG 9
7 &
7 &
7 &
9LFP 9&&
7 &
6RXUFH
9LG 9
7 &
7 &
6XSSO\YROWDJH9
Figure 12. Bode diagram at V
CC
= 5 V
*DLQ
7 &
7 &
N
9&& 9
9LFP 9
&O S)
*DLQ
7 &
N
)UHTXHQF\+]
0
3KDVH
N
DocID023708 Rev 2
2XWSXWYROWDJH9
6RXUFH
9LG 9
Figure 11. Bode diagram at V
CC
= 1.5 V
*DLQ
7 &
7 &
N
9&& 9
9LFP 9
&O S)
*DLQ
7 &
N
)UHTXHQF\+]
0
3KDVH
Figure 13. Closed-loop gain diagram vs. capacitive load
)ROORZHUFRQILJXUDWLRQ
9&& 9
9LFP 9 &O S) &O S)
7 &
&O S)
N N
)UHTXHQF\+]
0 0
13/29
Electrical characteristics
Figure 14. Positive slew rate
7 &
7 &
7 &
9&& 9
9LFP 9FF
&O S)
7LPHV
Figure 16. Slew rate vs. supply voltage
7 &
7 &
7 &
7 &
7 &
&O S)
9LFP 9&&
9ORDG 9&&
7 &
6XSSO\YROWDJH9
Figure 18. 0.1 Hz to 10 Hz noise
9&& 9
9LFP 9
7 &
TSV731, TSV732, TSV734
Figure 15. Negative slew rate
7 &
9&& 9
9LFP 9&&
&O S)
5O N
7 &
7 &
7LPHV
Figure 17. Noise vs. frequency
9&& 9
9LFP 9&&
7 &
)UHTXHQF\+]
Figure 19. THD+N vs. frequency
9&& 9
%: N+]
9LQ 9SS
*DLQ
9LFP 9&&
7 &
14/29
7LPHV
(
DocID023708 Rev 2
)UHTXHQF\+]
TSV731, TSV732, TSV734
Figure 20. THD+N vs. output voltage
Electrical characteristics
Figure 21. Output impedance vs. frequency in closed-loop configuration
9&& 9
9LFP 9
*DLQ
9RVF P9
506
7 &
(
(
9&& 9
*DLQ
I N+]
%: N+]
9LFP 9&&
7 &
2XWSXWYROWDJH9SS
N N N
)UHTXHQF\+]
0 0
DocID023708 Rev 2 15/29
Application information TSV731, TSV732, TSV734
The TSV73x series of devices can operate from 1.5 V to 5.5 V. The parameters are fully specified for 1.8 V, 3.3 V, and 5 V power supplies. However, they are very stable in the full
V
CC
range and several characterization curves show TSV73x device characteristics at 1.5 V.
In addition, the main specifications are guaranteed in the extended temperature range from
-40 °C to +125 °C.
The TSV731, TSV732, and TSV734 devices have a rail-to-rail input, and the input common mode range is extended from V
CC-
- 0.1 V to V
CC+
+ 0.1 V.
4.4
The output levels of the TSV73x operational amplifiers can go close to the rails: to a maximum of 40 mV below the upper rail and to a maximum of 75 mV above the lower rail when a 10 k Ω resistive load is connected to V
CC
/2.
Input offset voltage drift over temperature
The maximum input voltage drift over the temperature variation is defined as the offset variation related to offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift over temperature enables the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1
.
Equation 1
Δ
Δ
V
T
= max
V io
T
–
V ( 25 ° C )
T 25 ° C with T = -40 °C and 125 °C.
The datasheet maximum value is guaranteed by a measurement on a representative sample size ensuring a C pk
(process capability index) greater than 1.33.
16/29 DocID023708 Rev 2
TSV731, TSV732, TSV734 Application information
To evaluate product reliability, two types of stress acceleration are used:
• Voltage acceleration, by changing the applied voltage
• Temperature acceleration, by changing the die temperature (below the maximum junction temperature allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using
Equation 2
A
FV
= e
β ⋅ ( V
S
– V
U
)
Where:
A
FV
is the voltage acceleration factor
β
is the voltage acceleration constant in 1/V, constant technology parameter (
β
= 1)
V
S
is the stress voltage used for the accelerated test
V
U
is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in Equation 3 .
Equation 3
A
FT
= e
E k
⋅
⎛
⎝ T
1
U
–
T
1
S
⎞
⎠
Where:
A
FT
is the temperature acceleration factor
E a
is the activation energy of the technology based on the failure rate k is the Boltzmann constant (8.6173 x 10 -5 eV.K
-1 )
T
U
is the temperature of the die when V
U
is used (K)
T
S
is the temperature of the die under temperature stress (K)
The final acceleration factor, A
F
, is the multiplication of the voltage acceleration factor and the temperature acceleration factor (
).
Equation 4
A
F
=
A
FT
× A
FV
A
F is calculated using the temperature and voltage defined in the mission profile of the product. The A
F
value can then be used in
Equation 5 to calculate the number of months of
use equivalent to 1000 hours of reliable stress duration.
DocID023708 Rev 2 17/29
Application information TSV731, TSV732, TSV734
Equation 5
Months
=
A
F
× 1000 h × 12 months ⁄ ( 24 h × 365.25 days )
To evaluate the op-amp reliability, a follower stress condition is used where V
CC
is defined as a function of the maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules).
The V io
drift (in µV) of the product after 1000 h of stress is tracked with parameters at different measurement conditions (see
Equation 6
V
CC
=
maxV op
with V icm
=
V
CC
⁄ 2
The long term drift parameter ( Δ V io obtained using the ratio of the V io
), estimating the reliability performance of the product, is
(input offset voltage value) drift over the square root of the calculated number of months (
).
Equation 7
Δ V io
=
(
V io drift
-----------------------------months ) where V io duration.
drift is the measured drift value in the specified test conditions after 1000 h stress
18/29 DocID023708 Rev 2
TSV731, TSV732, TSV734 Application information
The TSV73x series of devices use a proprietary trimming topology that is initiated at each device power-up and allows excellent V io
performance to be achieved. The initialization time is defined as the delay after power-up which guarantees operation within specified
( performances. During this period, the current consumption ( I
CC
V io
) can be different to the typical ones.
) and the input offset voltage
Figure 22. Initialization phase
, &&
,QLWLDOL]DWLRQWLPH
9&&
3KDVH 3KDVH 9&& 9
9LFP 9
7 &
7\SLFDO,&&
7LPHPV
The initialization time is V
CC
and temperature dependent.
measurement results for different supply voltages and for temperatures varying from -40 °C to 125 °C.
V
CC
(V)
1.8
3.3
5
Table 6. Initialization time measurement results
Temperature: -40 °C Temperature: 25 °C Temperature: 125 °C
T init
(ms) I
CC phase 1 (mA) T init
(ms) I
CC
phase 1 (mA) T init
(ms) I
CC
phase 1 (mA)
37
2.9
2.4
0.33
1.4
3.2
3.2
0.95
0.85
0.40
1.3
2.4
0.35
0.34
0.31
0.46
1.2
2.9
For correct operation, it is advised to add a 10 nF decoupling capacitors as close as possible to the power supply pins.
DocID023708 Rev 2 19/29
Application information TSV731, TSV732, TSV734
4.8 Macromodel
Accurate macromodels of the TSV73x devices are available on the STMicroelectronics’ website at www.st.com
. These model are a trade-off between accuracy and complexity (that is, time simulation) of the TSV73x operational amplifiers. They emulate the nominal performance of a typical device within the specified operating conditions mentioned in the datasheet. They also help to validate a design approach and to select the right operational amplifier, but they do not replace on-board measurements .
20/29 DocID023708 Rev 2
TSV731, TSV732, TSV734 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
DocID023708 Rev 2 21/29
Package information
5.1 SC70-5 package information
TSV731, TSV732, TSV734
Figure 23. SC70-5 package mechanical drawing
S IDE VIEW
DIMEN S ION S IN MM
GAUGE PLANE
COPLANAR LEAD S
S EATING PLANE
22/29
Symbol c
D
E
E1
A
A1
A2 b
L
< e e1
TOP VIEW
Min.
0.10
1.80
1.80
1.15
0.80
0
0.80
0.15
0.26
0°
Table 7. SC70-5 package mechanical data
Dimensions
Millimeters
Typ.
0.90
2.00
2.10
1.25
0.65
1.30
0.36
Max.
0.22
2.20
2.40
1.35
1.10
0.10
1.00
0.30
0.46
8°
Min.
0.032
0.032
0.006
0.004
0.071
0.071
0.045
0.010
0°
Inches
Typ.
0.035
0.079
0.083
0.049
0.025
0.051
0.014
DocID023708 Rev 2
Max.
0.043
0.004
0.039
0.012
0.009
0.087
0.094
0.053
0.018
8°
TSV731, TSV732, TSV734 Package information
Figure 24. DFN8 2x2 package mechanical drawing
'
%
3,1,1'(;$5($
& [
7239,(:
&
&
3,1,1'(;$5($
6,'(9,(:
H
6($7,1*
3/$1(
&
ESOFV
& $ %
3LQ,'
Ref.
e
L
D
E
N
A
A1 b
%277209,(:
*$06&%
Min.
0.70
0.00
0.15
0.045
Table 8. DFN8 2x2 package mechanical data
Dimensions
Millimeters Inches
Typ.
0.75
0.02
0.20
2.00
2.00
0.50
0.55
8
Max.
0.80
0.05
0.25
0.65
Min.
0.028
0.000
0.006
0.018
Typ.
0.030
0.001
0.008
0.079
0.079
0.020
0.022
8
Max.
0.031
0.002
0.010
0.026
DocID023708 Rev 2 23/29
Package information TSV731, TSV732, TSV734
Figure 25. MiniSO-8 package mechanical drawing
24/29
Ref.
L2 k ccc
E1 e
L
L1
D
E b c
A
A1
A2
Min.
0
0.75
0.22
0.08
2.80
4.65
2.80
0.40
Table 9. MiniSO-8 package mechanical data
Dimensions
Millimeters Inches
Typ.
0.85
3.00
4.90
3.00
0.65
0.60
0.95
0.25
Max.
1.1
0.15
0.95
0.40
0.23
3.20
5.15
3.10
0.80
Min.
0
0.030
0.009
0.003
0.11
0.183
0.11
0.016
Typ.
0.033
0.118
0.193
0.118
0.026
0.024
0.037
0.010
0 ° 8 °
0.10
0 °
DocID023708 Rev 2
Max.
0.043
0.006
0.037
0.016
0.009
0.126
0.203
0.122
0.031
8 °
0.004
TSV731, TSV732, TSV734
5.4 QFN16 3x3 package information
Package information
Figure 26. QFN16 3x3 package mechanical drawing
DocID023708 Rev 2
4)1B[B9BB&
25/29
Package information TSV731, TSV732, TSV734 e
L
D
D2
E
E2
A
A1
A3 b
Ref.
Table 10. QFN16 3x3 mm package mechanical data (pitch 0.5 mm)
Dimensions
Min.
0.80
0
Millimeters
Typ.
0.90
Max.
1.00
0.05
Min.
0.031
0
Inches
Typ.
0.035
Max.
0.039
0.002
0.20
0.008
0.18
2.90
1.50
2.90
1.50
3.00
3.00
0.30
3.10
1.80
3.10
1.80
0.007
0.114
0.059
0.114
0.059
0.118
0.118
0.012
0.122
0.071
0.122
0.071
0.50
0.020
0.30
0.50
0.012
0.020
Figure 27. QFN16 3x3 footprint recommendation
26/29 DocID023708 Rev 2
4)1B[B9BIRRWSULQWBB&
TSV731, TSV732, TSV734
5.5 TSSOP14 package information
Package information
Figure 28. TSSOP14 package mechanical drawing
Ref.
c
D
E
E1
A
A1
A2 b
L1 k e
L aaa
Min.
0.05
0.80
0.19
0.09
4.90
6.20
4.30
0.45
Table 11. TSSOP14 package mechanical data
Dimensions
Millimeters
Typ.
Min.
1.00
5.00
6.40
4.40
0.65
0.60
1.00
Max.
0.20
5.10
6.60
4.50
1.20
0.15
1.05
0.30
0.75
0.002
0.031
0.007
0.004
0.193
0.244
0.169
0.018
Inches
Typ.
0.004
0.039
0.197
0.252
0.173
0.0256
0.024
0.039
0 ° 8 °
0.10
0 °
Max.
0.047
0.006
0.041
0.012
0.0089
0.201
0.260
0.176
0.030
8 °
0.004
DocID023708 Rev 2 27/29
Ordering information TSV731, TSV732, TSV734
Order code
TSV731ICT
TSV732IQ2T
TSV732IST
TSV734IQ4T
TSV734IPT
Temperature range
Table 12. Order codes
Package
-40° C to +125° C
SC70-5
DFN8 2x2
MiniSO8
QFN16 3x3
TSSOP14
Packaging
Tape and reel
Marking
K1X
K1X
V732
K1X
TSV734IP
Date
24-Sep-2012
26-Mar-2013
Table 13. Document revision history
Revision Changes
1
2
Initial internal release
Initial public release.
Datasheet updated for two new products: TSV732 and
TSV734.
Four new packages added: DFN8 2x2, MiniSO-8,
QFN16 3x3, and TSSOP14.
,
, and
Section 4: Application information : re-written
28/29 DocID023708 Rev 2
TSV731, TSV732, TSV734
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DocID023708 Rev 2 29/29
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