STMicroelectronics RF3L05150CB4 Datasheet
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RF3L05150CB4
Datasheet
150 W, 28/32 V, HF to 1 GHz RF power LDMOS transistor
5
4
LBB
1
3
4
5
Pin
1
2
Pin connection
Connection
Drain A
Drain B
Source (bottom side)
Gate B
Gate A
2
3
Features
Order code
RF3L05150CB4
Frequency
520 MHz
V
DD
28 V
P
OUT
150 W
Gain
23 dB
Efficiency
60 %
• High efficiency and linear gain operations
• Integrated ESD protection
• Large positive and negative gate-source voltage range for improved class C operation
• In compliance with the european directive 2002/95/EC
Applications
• 2-30 MHz HF or short wave communication
• 30-88 MHz ground communication
• 118-140 MHz Avionics
• 136-174 MHz commercial ground communication
• 30-512 MHz Jammer, ground/air communication
• HF to 1000 MHz ISM - instrumentation
Description
The RF3L05150CB4 is a 150 W, 28/32 V LDMOS FET designed for wide-band communication and ISM applications with frequencies from HF to 1 GHz. It can be used in class AB, B or C for all typical modulation formats.
Product status link
RF3L05150CB4
Product summary
Order code RF3L05150CB4
Marking
Package
3L05150
LBB
Packing
Base/bulk quantity
Tape and reel 13"
100/100
DS13358 - Rev 3 - March 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
RF3L05150CB4
Electrical ratings
Electrical ratings
Symbol
V
DS
V
GS
V
DD
T
STG
T
J
Table 1. Absolute maximum ratings (T
C
= 25 °C)
Parameter
Drain-source voltage
Gate-source voltage
Maximum operating voltage
Storage temperature range
Maximum junction temperature
Table 2. Thermal data
Symbol
R thJC
1. T
C
= 85 °C , T
J
= 200 °C, DC test.
Parameter
Thermal resistance, junction-to-case
Symbol
HBM
CDM
Table 3. ESD protection
Test methodology
Human body model (according to ANSI/ESDA/JEDEC JS001-2017)
Charge device model (according to ANSI/ESDA/JEDEC JS-002-2014)
Value
90
-8 to 10
36
-65 to 150
200
V
°C
°C
Unit
V
V
Value
0.4
Class
2
C3
Unit
°C/W
DS13358 - Rev 3 page 2/16
2
Note:
RF3L05150CB4
Electrical characteristics
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
V
GS(Q)
V
DS(on)
I
DS(on)
R
DS(on)
C
ISS
C
RSS
C
OSS
Table 4. Static
Parameter Test conditions
Drain-source breakdown voltage V
GS
= 0 V, I
DS
= 100 µA
Zero gate voltage drain leakage current
V
GS
= 0 V, V
DS
= 75 V
Gate-source leakage current
Gate threshold voltage
Gate quiescent voltage
Static drain-source on-voltage
Static drain-source on-current
V
GS
= -8/10 V, V
DS
= 0 V
V
DS
= 42 V, I
DS
= 600 µA
V
DS
= 1 V, I
DS
= 800 mA
V
GS
= 10 V, I
DS
= 2 A
V
GS
= 10 V, V
DS
= 100 mV
Drain-source on-state resistance V
GS
= 10 V, V
DS
= 100 mV
Common source input capacitance
Common source feedback capacitance
V
GS
= 0 V, V
DD
= 28 V, f = 1 MHz
Common source output capacitance
Symbol f
P
OUT
G
PS
η
D
VSWR
Parameter
Frequency
Output power
Power gain
Drain efficiency
Load mismatch
Table 5. Dynamic
Test conditions f = 520 MHz
1 dB compression, pulsed CW
At 150 W pulsed CW output power, all phase angles
V
DD
= 28 V, I
DQ
= 500 mA, pulse width = 20 μs, duty cycle = 10%.
Min.
Typ.
Max.
Unit
90 V
1 μA
1.75
2.0
70
±100 nA
2.50
5.0
650
V
V mV
2.5
1
A
Ω pF
1.1
30 pF pF
Min.
Typ.
Max.
1000
150
23
60
20:1
Unit
MHz
W dB
%
DS13358 - Rev 3 page 3/16
3
Note:
Note:
RF3L05150CB4
Typical performances
Typical performances
Figure 1. Power gain and drain efficiency vs output power (f = 520 MHz)
26
GADG101120200749GT
65
25
24
55
23
22
45
35
21
20
0 20 40 60 80 100
P
OUT
(W)
G
PS
η
D
120 140 160 180
25
V
DD
= 28 V, I
DQ
= 500 mA, pulsed CW, pulse width = 20 μs, duty cycle = 10%.
Figure 2. Power gain and drain efficiency vs output power (f = 860 MHz)
22
GADG101120200806GT
75
21 65
18
17
20
19
16
0 20 40 60 80 100 120 140 160 180 200
15
P
OUT
(W)
G
PS
η
D
V
DD
= 32 V, I
DQ
= 400 mA, pulsed CW, pulse width = 20 μs, duty cycle = 10%.
35
25
55
45
DS13358 - Rev 3 page 4/16
Note:
RF3L05150CB4
Typical performances
-16
-18
-20
-22
-24
-26
-28
-30
0
100
90
80
70
60
50
40
30
0
Figure 3. Gain, efficiency and P
1dB
vs frequency (typical broadband data)
110
GADG101120200817GT
20
100 200 300
P
1dB
(W)
400 500 600
Frequency (MHz)
η
D
(%)
700
G
PS
(dB)
800
13
900 1000
12
19
18
17
16
15
14
Figure 4. IMD3 versus Frequency (2 tones test, 200 kHz spacing)
GADG101120200817GT
100 200 300 400 500 600
Frequency (MHz)
700 800 900 1000
V
DD
= 28 V, I
DQ
= 400 mA, pulsed CW, pulse width = 20 μs, duty cycle = 10%.
DS13358 - Rev 3 page 5/16
4
Test circuits
Figure 5. Test circuit layout (f = 520 MHz)
RF3L05150CB4
Test circuits
Figure 6. Test circuit photo (f = 520 MHz)
DS13358 - Rev 3 page 6/16
Component
C1~C7
C8~C11
C12, C13, 14
C15
C16, C17
C18
C19
C20
C21
C22~C25
C26, C27
R1, R2
R3, R4
L1, L2
T1, T2, T3, T4
PCB
RF3L05150CB4
Test circuits
Table 6. Components list (f = 520 MHz)
Value
47 pF
68 pF
18 pF
20 pF
1000 pF
2.2 pF
5.6 pF
12 pF
5.6 pF
10 µF
470 µF
200 Ω
15 Ω ɸ 0.5, 30 mm, enameled wire
25 Ω, 50 mm
30 mils Rogers 4350B
Reference
DLC70B
ATC800B
DLC70B
DLC70B
DLC70B
DLC70B
DLC70B
DLC70B
DLC70B
100 V multilayer ceramic capacitor
63 V Aluminum electrolytic capacitor
0805 chip resistor
SF-086-1.5
DS13358 - Rev 3 page 7/16
DS13358 - Rev 3
Figure 7. Test circuit photo (f = 860 MHz)
RF3L05150CB4
Test circuits
Figure 8. Test circuit schematic (f = 860 MHz) page 8/16
DS13358 - Rev 3
RF3L05150CB4
Test circuits
Component
R1, R3
R2,R4
R5,R6
FB1,FB2
C1,C3,C7,C9
C2,C4,C5,C6
C8,C10
C11,C12
C13, C14
C15
C16
C17
C18
C19, C20
B1, B2
TL1, TL5
TL2, TL6
TL3, TL7
TL4, TL8, TL9, TL13
TL10, TL14
TL11, TL15
TL12, TL16
Board 3X5
2743021447
ATC100B910XXXX
C1812X7R501-104KNE
ATC100B620XXXX
ATC100B151XXXX
ATC100B110XXXX
ATC100B7R5XXXX
ATC100B1R1XXXX
27291PC
ATC100B101XXXX
EZ 141
Table 7. Components list (f = 860 MHz)
Value
CR1206-8W-130JB
CR1206-8W-122JB
CR1206-8W-250JB
Reference
Venkel
Venkel
Venkel
FAIR-RITE
CORP
Description
13 Ω, 1/8W surfacr mount chip resistor
1.2 kΩ, 1/8W surfacr mount chip resistor
25 Ω, 1/8W surfacr mount chip resistor
Surface mount EMI sheild bead
ATC
Venkel
ATC
ATC
ATC
ATC
ATC
Johanson
ATC
Huber-Suhner
100 µF, 63 V electrolytic capacitor
91 pF chip capacitor
0.1 µF 500 V surface mount ceramic chip capacitor
62 pF chip capacitor
150 pF chip capacitor
11pF chip capacitor
7.5pF chip capacitor
1.1pF chip capacitor
0.8-8pF giga trim variable capacitor
100 pF chip capacitor
Balun , 50 Ω sucoform, od 0.141. 2.37 lg coaxial cable or equivalent
L = 0.250 in [6.35 mm] W = 0.214 in [5.44 mm]
L = 0.182 in [4.62 mm] W = 0.284 in [7.21 mm]
L = 0.318 in [8.08 mm] W = 0.284 in [7.21 mm]
L = 2.37 in [60.19 mm] W = 0.082 in [2.08 mm]
L = 0.314 in [7.97 mm] W = 0.230 in [5.84 mm]
L = 0.460 in [11.68 mm] W = 0.230 in [5.84 mm]
L = 0.280 in [7.11 mm] W = 0.230 in [5.84 mm]
Rogers Corp εr = 2.55 t = 0.0026 in h = 0.030 in page 9/16
Figure 9. Test circuit photo (broadband)
RF3L05150CB4
Test circuits
DS13358 - Rev 3
Reference
C1
C2
C3
C4
C5
C6
C7, C8
C9,C10
C11,C12
R1, R2, R3
T1, T2
T3, T4
T5, T6
L1
PCB
Table 8. Components list (broadband)
Value
12 pF
15 pF
18 pF
8.2 pF
1 pF
120 pF
220 pF
1 nF
10 µF
300 Ω
17 Ω - 65 mm
25 Ω - 65 mm
50 Ω - 65 mm
8 turns - diameter = 7 mm
30 mils Rogers4350B
Reference
ATC600F
ATC600F
ATC600F
ATC800B
ATC600F
ATC100B
ATC100B
ATC100B
BN-61-202
BN-61-202
BN-61-202 page 10/16
5
5.1
RF3L05150CB4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
LBB package information
Figure 10. LBB package outline
N Ex4
A
B
C
M
G
S
L I H
F
CH2 x 45°
R2 x 4
D
R1 x 2
CH1 x 45°
T
S R
P
Q
DM00666717_2
DS13358 - Rev 3 page 11/16
DS13358 - Rev 3
Symbol
P
Q
R
S
T
CH1
CH2
R1
R2
H
I
L
M
N
A
B
C
E
F
Min.
28.82
22.73
16.87
5.32
1.01
5.72
5.72
17.65
1.02
4.72
16.38
1.37
1.97
Table 9. LBB mechanical data
Millimeters
Typ.
4.85
16.51
1.50
2.10
6.60
2.72
1.02
1.65
0.50
5.85
5.85
17.78
1.15
0.10
28.95
22.86
17.00
5.45
1.14
RF3L05150CB4
LBB package information
Max.
29.08
22.99
17.13
5.58
1.27
5.98
5.98
17.91
1.28
4.98
16.64
1.63
2.23
page 12/16
5.2
RF3L05150CB4
Marking information
Marking information
PACKAGE FACE : TOP
C
E
D
A B
F G H
Figure 11. Marking composition
LEGEND
Unmarkable Surface
Marking Composition Field
A - STANDARD ST LOGO
B - ECO level
(e4)
C
D
- MARKING AREA
- ADDITIONAL
INFORMATION
(MAX CHAR ALLOWED = 7)
E - COUNTRY OF ORIGIN
(MAX CHAR ALLOWED = 3)
F - Assy Plant
(PP)
G - Assy Year
(Y)
H - Assy Week
(WW)
GADG040220211644GT
DS13358 - Rev 3 page 13/16
RF3L05150CB4
Revision history
Date
08-Jun-2020
12-Nov-2020
16-Mar-2021
Version
1
2
3
Table 10. Document revision history
Changes
First release
Updated Features.
Updated Table 5. Dynamic.
Updated Section 3 Typical performances.
Updated Test circuit (f = 650 MHz).
Minor text changes.
Updated title and table product summary in cover page.
Updated Table 3. ESD protection
, Section 2 Electrical characteristics ,
Section 3 Typical performances and
.
Added
Section 5.2 Marking information
.
Minor text changes.
DS13358 - Rev 3 page 14/16
RF3L05150CB4
Contents
Contents
DS13358 - Rev 3 page 15/16
RF3L05150CB4
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DS13358 - Rev 3 page 16/16
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