STH2N120K5-2AG
Datasheet
Automotive-grade N-channel 1200 V, 7.25 Ω typ., 1.5 A, MDmesh K5
Power MOSFET in an H²PAK-2 package
G(1)
TAB
Features
Order code
STH2N120K5-2AG
V
DS
1200 V
R
DS(on)
max.
10 Ω
I
D
1.5 A
P
TOT
60 W
2
1
3
H2PAK-2
S(2, 3)
D(TAB)
• AEC-Q101 qualified
• Industry’s lowest R
DS(on)
x area
• Industry’s best FoM (figure of merit)
• Ultra-low gate charge
• 100% avalanche tested
Applications
• Switching applications
DTG1S23NZ
Description
This very high voltage N-channel Power MOSFET is designed using MDmesh K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
Product status
STH2N120K5-2AG
Product summary
(1)
Order code
Marking
STH2N120K5-2AG
2N120K5
Package
Packing
H²PAK-2
Tape and reel
1. HTRB test was performed at 80% of
V
(BR)DSS
according to AEC-Q101 rev.
C. All other tests were performed according to AEC-Q101 rev. D.
DS12486 - Rev 5 - June 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
STH2N120K5-2AG
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
I
GS
D
Parameter
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
I
DM
(1)
P
TOT
dv/dt (2) dv/dt (3)
T stg
T
J
Drain current (pulsed)
Total power dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Storage temperature range
Operating junction temperature range
1. Pulse width is limited by safe operating area.
2. I
SD
≤ 1.5 A, di/dt = 100 A/μs, V
DS
(peak) < V
(BR)DSS
, V
DD
= 80% V
(BR)DSS
.
3. V
DS
≤ 960 V.
Table 2. Thermal data
Symbol
R thj-case
R thj-pcb
(1)
Thermal resistance junction-case
Thermal resistance junction-pcb
Parameter
1. When mounted on an 1-inch² FR-4, 2 Oz copper board.
Table 3. Avalanche characteristics
Symbol
I
AR
(1)
E
AS
(2)
Single pulse avalanche energy
Parameter
Avalanche current, repetitive or not repetitive
1. Pulse width is limited by T
J
max.
2. Starting T
J
= 25 °C, I
D
= I
AR
, V
DD
= 50 V.
Value
±30
1.5
1
2.5
60
4.5
50
-55 to 150
Unit
V
A
A
W
V/ns
V/ns
°C
Value
2.08
30
Unit
°C/W
Value
0.5
80
Unit
A mJ
DS12486 - Rev 5 page 2/14
2
STH2N120K5-2AG
Electrical characteristics
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Table 4. Static
Symbol
V
(BR)DSS
V
R
I
I
DSS
GSS
GS(th)
DS(on)
Parameter Test conditions
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 1200 V
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 1200 V, T
C
= 125 °C (1)
Gate-body leakage current
Gate threshold voltage
V
DS
= 0 V, V
GS
= ±20 V
V
DS
= V
GS
, I
D
= 100 µA
Static drain-source on-resistance
V
GS
= 10 V, I
D
= 0.5 A
1. Defined by design, not subject to production test.
Min.
Typ.
Max.
Unit
1200 V
0.5
µA
100
2 3
±100 nA
4 V
7.25
10 Ω
Table 5. Dynamic
Symbol
C iss
C oss
C rss
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
V
DS
Test conditions
= 100 V, f = 1 MHz, V
GS
= 0 V
Min.
-
-
-
Typ.
124
13
0.5
Max.
-
-
-
C
C o(tr)
(1)
o(er)
(2)
Time-related equivalent capacitance
Energy-related equivalent capacitance
V
GS
= 0 V, V
DS
= 0 to 960 V
-
15
5 -
-
R
G
Q g
Q gs
Q gd
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge f = 1 MHz, I
V
DD
D
= 0 A
= 960 V, I
(see
D
= 1.5 A, V
GS
= 0 to 10 V
Figure 13. Test circuit for gate charge behavior )
-
-
-
16
5.3
0.8
3.5
-
-
-
-
1. C o(tr)
is a constant capacitance value giving the same charging time as C oss
while V
DS
is rising from 0 to 80% V
DSS
.
2. C o(er)
is a constant capacitance value giving the same stored energy as C oss
while V
DS
is rising from 0 to 80% V
DSS
.
Unit pF pF
Ω nC
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
V
DD
= 600 V, I
D
= 0.75 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see
Figure 12. Test circuit for resistive load switching times
and
Figure 17. Switching time waveform )
Min.
Typ.
Max.
Unit
10.3
-
-
-
-
7.8
34
39
-
-
ns
DS12486 - Rev 5 page 3/14
STH2N120K5-2AG
Electrical characteristics
Table 7. Source-drain diode
Symbol
I
SD
I
SDM
(1)
V
I
I
SD
(2)
t
Q
RRM t
Q rr rr rr rr
RRM
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Test conditions
V
GS
= 0 V, I
SD
= 1.5 A
I
SD
= 1.5 A, di/dt = 100 A/µs,
V
DD
= 60 V
(see
Figure 14. Test circuit for inductive load switching and diode recovery times )
I
SD
= 1.5 A, di/dt = 100 A/µs,
V
DD
= 60 V, T
J
= 150 °C
(see
Figure 14. Test circuit for inductive load switching and diode recovery times )
1. Pulse width is limited by safe operating area.
2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
-
-
-
-
-
-
-
Min.
Typ.
Max.
Unit
1.5
A
2.5
A
1.5
350
1.35
V ns
µC
7.7
600
2.09
7.7
A ns
µC
A
DS12486 - Rev 5 page 4/14
STH2N120K5-2AG
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 1. Safe operating area
I
D
(A)
GADG050320181141SOA
Operation in this area is limited by R
DS(on)
10 0 t p
= 10 µs t p
= 100 µs
10 -1
10 -2
Single pulse,
T
C
= 25 °C
T
J
≤150 °C t p
= 1 ms
10 -3
10 -1 10 0 10 1 10 2 10 3 t p
= 10 ms
V
DS
(V)
I
D
(A)
2.5
Figure 3. Output characteristics
GADG050320181127OCH
V
GS
= 8, 9, 10 V
2
1.5
V
GS
= 7 V
V
GS
= 6 V
1
V
GS
= 5 V
0.5
0
0 8 16 24 V
DS
(V)
Figure 5. Gate charge vs gate-source voltage
0
0
I I
Q
0 0
(nC)
Figure 2. Thermal impedance
1.5
1
0.5
0
0
I
D
(A)
Figure 4. Transfer characteristics
GADG050320181127TCH
2.5
2
V
DS
= 30 V
2 4 6 8 V
GS
(V)
Figure 6. Static drain-source on-resistance
R
DS(on)
(Ω)
GADG050320181140RID
8.5
V
GS
= 10 V
8
7.5
7
6.5
0 0.5
1 1.5
I
D
(A)
DS12486 - Rev 5 page 5/14
STH2N120K5-2AG
Electrical characteristics (curves)
C
(pF)
Figure 7. Capacitance variations
GADG050320181128CVR
10 3
10 2
10 1
10 0
10 -1
10 -1 f = 1 MHz
10 0 10 1 10 2
C
ISS
C
OSS
C
RSS
V
DS
(V)
Figure 9. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
GADG050320181128RON
2.5
2
V
GS
= 10 V
1.5
1
0.5
0
-75 -25 25 75 125 T j
(°C)
Figure 8. Normalized gate threshold voltage vs temperature
V
GS(th)
(norm.)
GADG050320181127VTH
1.2
I
D
= 100 µA
1
0.8
0.6
0.4
-75 -25 25 75 125 T j
(°C)
Figure 10. Normalized V
(BR)DSS
vs temperature
V
(BR)DSS
(norm.)
GADG050320181129BDV
1.08
1
I
D
= 1 mA
0.92
0.84
-75 -25 25 75 125 T j
(°C)
Figure 11. Source- drain diode forward characteristics
V
SD
(V)
GADG050320181128SDF
1 T
J
= -55 °C
0.8
T
J
= 25 °C
T
J
= 150 °C
0.6
0.4
0 0.5
1 1.5
I
SD
(A)
DS12486 - Rev 5 page 6/14
STH2N120K5-2AG
Test circuits
3
Test circuits
Figure 12. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF V
DD
D.U.T.
Figure 13. Test circuit for gate charge behavior
V
DD
RL
V
GS pulse width
2200
μF
+
1 kΩ
I
G
= CONST
2.7 kΩ
47 kΩ
100 Ω D.U.T.
V
G
AM01469v10
AM01468v1
Figure 14. Test circuit for inductive load switching and diode recovery times
Figure 15. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
A A fast diode
B
B
G
+
_
R
G
100 µH
D
D.U.T.
S
3.3
µF +
1000
µF
V
DD
AM01470v1
Figure 16. Unclamped inductive waveform
V
(BR)DSS
V
D
I
DM
I
D
V
DD
V
DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF V
DD
D.U.T.
AM01471v1
0
Figure 17. Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
V
GS
V
DS
90%
10%
0 10%
AM01473v1
DS12486 - Rev 5 page 7/14
4
4.1
STH2N120K5-2AG
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
H²PAK-2 package information
Figure 18. H²PAK-2 package outline
DS12486 - Rev 5
8159712_9 page 8/14
Dim.
F
F2
H
H1
J1
L
L1
A
A1
C
D e
E
M
R
V
L2
L3
L4
Table 8. H²PAK-2 package mechanical data mm
Typ.
4.93
6.85
1.50
2.60
0.20
0°
10.00
7.40
2.49
15.30
1.27
8.95
4.98
0.50
0.78
1.14
Min.
4.30
0.03
1.17
-
Figure 19. H²PAK-2 recommended footprint
STH2N120K5-2AG
H²PAK-2 package information
5.23
7.25
1.70
2.90
0.60
8°
10.40
7.80
2.69
15.80
1.40
9.35
5.18
0.90
0.85
1.70
Max.
4.70
0.20
1.37
Note: Dimensions are in mm.
DS12486 - Rev 5
8159712_9 page 9/14
STH2N120K5-2AG
Packing information
4.2
Packing information
T
Top cover tape
K0
B0
Figure 20. Tape outline
10 pitches cumulative tolerance on tape +/- 0.2 mm
P0 D P2
A0 P1
User direction of feed
D1
F
E
W
User direction of feed
R
Bending radius
AM08852v2
DS12486 - Rev 5 page 10/14
DS12486 - Rev 5
A
REEL DIMENSIONS
D
Figure 21. Reel outline
40 mm min.
Access hole
At slot location
B
C
Full radius
Tape slot
In core for
Tape start
STH2N120K5-2AG
Packing information
T
N
G measured
At hub
Dim.
K0
P0
P1
E
F
A0
B0
D
D1
P2
R
T
W
Table 9. Tape and reel mechanical data
Tape
4.8
3.9
11.9
1.9
50
0.25
23.7
Min.
10.5
15.7
1.5
1.59
1.65
11.4
mm
Max.
10.7
15.9
1.6
1.61
1.85
11.6
5.0
4.1
12.1
2.1
0.35
24.3
Dim.
G
N
T
A
B
C
D
Base quantity
Bulk quantity
Reel
Min.
1.5
12.8
20.2
24.4
100 mm
Max.
330
13.2
26.4
30.4
1000
1000 page 11/14
STH2N120K5-2AG
Revision history
Date
23-Mar-2018
30-Jul-2018
31-Jul-2018
05-Sep-2018
16-Jun-2020
Version
1
2
3
4
5
Table 10. Document revision history
Changes
Initial release. The document status is preliminary data.
The document status was promoted from preliminary to production data.
Updated title and features on cover page.
Updated the current table. The date for revision 2 was erroneously reported as "19-Jun-2018" instead of "30-Jul-2018".
Updated I
DSS
parameter in Table 4. Static .
Updated Section 4 Package information .
DS12486 - Rev 5 page 12/14
STH2N120K5-2AG
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
H²PAK-2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
DS12486 - Rev 5 page 13/14
STH2N120K5-2AG
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© 2020 STMicroelectronics – All rights reserved
DS12486 - Rev 5 page 14/14
