STB45N40DM2AG
Datasheet
Automotive-grade N-channel 400 V, 0.063 Ω typ., 38 A, MDmesh™ DM2
Power MOSFET in a D
2
PAK package
G(1)
TAB
2
1
3
D²PAK
D(2, TAB)
S(3)
AM01475V1
Features
Order code
STB45N40DM2AG
V
DS
400 V
R
DS(on)
max.
0.072 Ω
I
D
38 A
P
TOT
250 W
• AEC-Q101 qualified
• Fast-recovery body diode
• Extremely low gate charge and input capacitance
• Low on-resistance
• 100% avalanche tested
• Extremely high dv/dt ruggedness
• Zener-protected
Applications
• Switching applications
Description
This high-voltage N-channel Power MOSFET is part of the MDmesh™ DM2 fastrecovery diode series. It offers very low recovery charge (Q rr
) and time (t rr
) combined with low R
DS(on)
, rendering it suitable for the most demanding high-efficiency converters and ideal for bridge topologies and ZVS phase-shift converters.
Product status
STB45N40DM2AG
Product summary
Order code
Marking
Package
Packing
STB45N40DM2AG
45N40DM2
D 2 PAK
Tape and reel
DS11238 - Rev 4 - October 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
STB45N40DM2AG
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
GS
Parameter
Gate-source voltage
I
D
Drain current (continuous) at T case
= 25 °C
Drain current (continuous) at T case
= 100 °C
I
DM
(1)
P
TOT
dv/dt (2)
Drain current (pulsed)
Total power dissipation at T case
= 25 °C
dv/dt (3)
T stg
T j
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Storage temperature range
Operating junction temperature range
1. Pulse width is limited by safe operating area.
2. I
SD
≤ 38 A, di/dt = 800 A/μs, V
DS
peak < V
(BR)DSS
,V
DD
= 80% V
(BR)DSS
3. V
DS
≤ 320 V
Table 2. Thermal data
Symbol
R thj-case
R thj-pcb
(1)
Parameter
Thermal resistance junction-case
Thermal resistance junction-pcb
1. When mounted on an 1-inch² FR-4, 2 Oz copper board.
Table 3. Avalanche characteristics
Symbol
I
AR
(1)
E
AS
(2)
Parameter
Avalanche current, repetitive or not repetitive
Single pulse avalanche energy
1. Pulse width is limited by T jmax
.
2. starting T j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V
Value
±25
38
24
110
250
50
50
-55 to 150
Unit
V
A
A
W
V/ns
°C
Value
0.5
30
Unit
°C/W
Value
7
1100
Unit
A mJ
DS11238 - Rev 4 page 2/15
2
STB45N40DM2AG
Electrical characteristics
Electrical characteristics
(T case
= 25 °C unless otherwise specified)
Table 4. Static
Symbol
V
(BR)DSS
Parameter
Drain-source breakdown voltage
Test conditions
V
GS
= 0 V, I
D
= 1 mA
V
R
I
I
DSS
GSS
GS(th)
DS(on)
Zero gate voltage drain current
Gate-body leakage current
Gate threshold voltage
Static drain-source onresistance
V
GS
= 0 V, V
DS
= 400 V
V
T
GS
= 0 V, V
DS
= 400 V, case
= 125 °C
(1)
V
V
V
1. Defined by design, not subject to production test.
DS
DS
GS
= 0 V, V
GS
= V
GS
, I
D
= 10 V, I
= ±25 V
= 250 µA
D
= 19 A
Min.
400
3
Typ.
4
0.063
Max.
10
100
±5
5
0.072
Unit
V
µA
µA
V
Ω
Table 5. Dynamic
Symbol
C iss
C oss
C rss
C oss eq.
(1)
R
G
Q g
Q gs
Q gd
Parameter
Input capacitance
Test conditions
Output capacitance
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
Reverse transfer capacitance
Equivalent output capacitance V
DS
= 0 to 320 V, V
GS
= 0 V
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge f = 1 MHz, I
D
= 0 A
V
DD
V
GS
= 320 V, I
D
= 0 to 10 V
= 38 A,
(see Figure 14. Test circuit for gate charge behavior
)
Min.
-
-
-
-
-
-
-
-
Typ.
2600
180
3.5
300
4
56
13
28
Max.
-
-
-
-
-
-
-
-
Unit pF pF
Ω nC
1. C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS
increases from 0 to 80% V
DSS
.
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
V
DD
= 200 V, I
D
= 19 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see
Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform )
Min.
-
-
-
-
Typ.
20
6.7
68
9.8
Max.
-
-
-
-
Unit ns
DS11238 - Rev 4 page 3/15
DS11238 - Rev 4
STB45N40DM2AG
Electrical characteristics
Table 7. Source-drain diode
Symbol
I
SD
I
SDM
(1)
V
SD
(2)
I
I t
Q
RRM t
Q rr rr rr rr
RRM
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Test conditions
V
GS
= 0 V, I
SD
= 38 A
I
SD
=38 A, di/dt = 100 A/µs,
V
DD
= 60 V
(see
Figure 15. Test circuit for inductive load switching and diode recovery times )
I
SD
= 38 A, di/dt = 100 A/µs,
V
DD
= 60 V, T j
= 150 °C
(see
Figure 15. Test circuit for inductive load switching and diode recovery times )
1. Pulse width is limited by safe operating area.
2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
-
-
-
Min.
-
-
-
-
-
-
Symbol
V
(BR)GSO
Parameter
Gate-source breakdown voltage
Table 8. Gate-source Zener diode
Test conditions
I
GS
= ±250 µA, I
D
= 0 A
Min.
±30
Typ.
95
0.4
8.5
185
1.62
17.5
Typ.
-
Max.
38
110
1.6
Max.
-
A ns
µC
Unit
A
A
V ns
µC
A
Unit
V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device.
The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry.
page 4/15
STB45N40DM2AG
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 1. Safe operating area
I
D
(A)
GADG231020181004SOA
Operation in this area is limited by R
DS(on)
10 2 t p
= 1µs
10 1 t p
= 10µs
10 0
10 -1
10 -1
T j
≤150 °C
T c
= 25°C single pulse
10 0 10 1 t p
= 10ms
10 2 t p
= 100µs t p
= 1ms
V
DS
(V)
60
40
20
0
0
I
D
(A)
100
Figure 3. Output characteristics
GIPG270815FQ4LBOCH
V
GS
= 9,10 V
V
GS
= 8 V
80
4 8
V
GS
= 7 V
V
GS
= 6 V
12
V
GS
= 5 V
16 V
DS
(V)
Figure 5. Gate charge vs gate-source voltage
V
GS
(V) V
DS
12
GIPG270815FQ4LBQVG V
(V)
DS
V
DD
= 320 V, I
D
= 38 A
300
6
4
10
8
2
0
0
250
200
150
100
10 20 30 40 50 60
50
0
Q g
(nC)
Figure 2. Thermal impedance
80
60
40
20
0
2
I
D
(A)
100
Figure 4. Transfer characteristics
GIPG270815FQ4LBTCH
V
DS
= 20 V
4 6 8 V
GS
(V)
Figure 6. Static drain-source on-resistance
R
DS(on)
(Ω)
GIPG270815FQ4LBRID
V
GS
= 10 V
0.071
0.067
0.063
0.059
0.055
0 8 16 24 32 I
D
(A)
DS11238 - Rev 4 page 5/15
STB45N40DM2AG
Electrical characteristics (curves)
C
(pF)
Figure 7. Capacitance variations
GIPG270815FQ4LBCVR
10 4
C
ISS
10 3
10 2
C
OSS
10 1
10 0
10 -1 10 0 f = 1 MHz
10 1 10 2
C
RSS
V
DS
(V)
Figure 9. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
GIPG190815FQ75A1BRON
V
GS
= 10 V
2.2
1.8
1.4
1.0
0.6
0.2
-75 -25 25 75 125 T j
(°C)
Figure 11. Output capacitance stored energy
E
OSS
(µJ)
12
GIPG270815FQ4LBEOS
10
8
6
4
2
0
0 100 200 300 400 V
DS
(V)
Figure 8. Normalized gate threshold voltage vs temperature
V
GS(th)
(norm.)
GIPG270815FQ4LBVTH
I
D
= 250 µA
1.1
1.0
0.9
0.8
0.7
0.6
-75 -25 25 75 125 T j
(°C)
Figure 10. Normalized V
(BR)DSS
vs temperature
V
(BR)DSS
(norm.)
1.12
GIPG270815FQ4LBBDV
I
D
= 1 mA
1.08
1.04
1.00
0.96
0.92
0.88
-75 -25 25 75 125 T j
(°C)
Figure 12. Source- drain diode forward characteristics
V
SD
(V)
GIPG270815FQ4LBSDF
T j
= -50 °C
1.0
T j
= 25 °C
0.8
T j
= 150 °C
0.6
0.4
0.2
0 10 20 30 I
SD
(A)
DS11238 - Rev 4 page 6/15
STB45N40DM2AG
Test circuits
3
Test circuits
Figure 13. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF V
DD
D.U.T.
Figure 14. Test circuit for gate charge behavior
V
DD
RL
V
GS pulse width
2200
μF
+
I
G
= CONST
2.7 kΩ
47 kΩ
1 kΩ
100 Ω D.U.T.
V
G
AM01469v10
AM01468v1
Figure 15. Test circuit for inductive load switching and diode recovery times
Figure 16. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
A A fast diode
B
B
G
+
_
R
G
100 µH
D
D.U.T.
S
3.3
µF
+
1000
µF
V
DD
AM01470v1
Figure 17. Unclamped inductive waveform
V
(BR)DSS
V
D
I
DM
I
D
V
DD
V
DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF
V
DD
D.U.T.
AM01471v1
0
Figure 18. Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
V
GS
V
DS
90%
10%
0 10%
AM01473v1
DS11238 - Rev 4 page 7/15
4
STB45N40DM2AG
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
DS11238 - Rev 4 page 8/15
4.1
STB45N40DM2AG
D²PAK (TO-263) type A2 package information
D²PAK (TO-263) type A2 package information
Figure 19. D²PAK (TO-263) type A2 package outline
DS11238 - Rev 4
0079457_A2_25 page 9/15
DS11238 - Rev 4
STB45N40DM2AG
D²PAK (TO-263) type A2 package information
Dim.
e1
H
J1
L
L1
L2
R
V2
D
D1
D2
E
E1
E2 e
A
A1 b b2 c c2
Table 9. D²PAK (TO-263) type A2 package mechanical data mm
Typ.
1.14
0.45
1.23
8.95
7.50
Min.
4.40
0.03
0.70
1.10
10.00
8.70
7.30
7.75
1.30
8.90
7.50
2.54
4.88
15.00
2.49
2.29
1.27
1.30
0.40
0°
5.28
15.85
2.69
2.79
1.40
1.75
8°
1.70
0.60
1.36
9.35
8.00
Max.
4.60
0.23
0.93
1.50
10.40
9.10
7.70
Figure 20. D²PAK (TO-263) recommended footprint (dimensions are in mm)
Footprint page 10/15
4.2
D²PAK packing information
Figure 21. D²PAK tape outline
STB45N40DM2AG
D²PAK packing information
DS11238 - Rev 4 page 11/15
DS11238 - Rev 4
A
STB45N40DM2AG
D²PAK packing information
D
B
Full radius
Figure 22. D²PAK reel outline
T
40mm min. access hole at slot location
Tape slot in core for tape start
2.5mm min.width
C
N
G measured at hub
Dim.
E
F
K0
P0
P1
P2
R
T
W
A0
B0
D
D1
Min.
1.65
11.4
4.8
3.9
11.9
1.9
50
0.25
23.7
10.5
15.7
1.5
1.59
Tape
Table 10. D²PAK tape and reel mechanical data
Reel mm
Dim.
Max.
10.7
15.9
1.6
1.61
1.85
11.6
5.0
4.1
12.1
2.1
C
D
A
B
G
N
T
Base quantity
Bulk quantity
Min.
1.5
12.8
20.2
24.4
100
0.35
24.3
mm
AM06038v1
Max.
330
13.2
26.4
30.4
1000
1000 page 12/15
STB45N40DM2AG
Revision history
Date
27-Aug-2015
04-Aug-2016
14-Feb-2018
23-Oct-2018
Table 11. Document revision history
Revision
1
2
3
4
Changes
Initial version
Updated Figure 2: "Safe operating area" .
Minor text changes.
Removed maturity status indication from cover page.
Updated Section 4.1 D²PAK (TO-263) type A2 package information.
Minor text changes
Updated
Table 1. Absolute maximum ratings
and Table 7. Sourcedrain diode
.
Updated
Figure 1. Safe operating area and
Figure 14. Test circuit for gate charge behavior .
Minor text changes.
DS11238 - Rev 4 page 13/15
STB45N40DM2AG
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
[Package name] package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
D²PAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
DS11238 - Rev 4 page 14/15
STB45N40DM2AG
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© 2018 STMicroelectronics – All rights reserved
DS11238 - Rev 4 page 15/15
