STL33N65M2
Nchannel 650 V, 0.124 Ω typ., 20 A MDmesh™ M2
Power MOSFET in a PowerFLAT™ 8x8 HV package
Datasheet - production data
4
3
2
1
5
PowerFLA
T™ 8x8 HV
Figure 1: Internal schematic diagram
Features
Order code V
DS
R
DS(on) max I
D
STL33N65M2 650 V 0.154 Ω 20 A
Extremely low gate charge
Excellent output capacitance (C
OSS
) profile
100% avalanche tested
Zener-protected
Applications
Switching applications
Description
This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology.
Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters.
Order code
STL33N65M2
Marking
33N65M2
Table 1: Device summary
Package
PowerFLAT™ 8x8 HV
Packing
Tape and reel
April 2016 DocID026089 Rev 3
This is information on a product in full production.
1/15 www.st.com
Contents
Contents
STL33N65M2
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
4.2
PowerFLAT™ 8x8 HV package information .................................... 10
PowerFLAT™ 8x8 HV packing information ..................................... 12
5 Revision history ............................................................................ 14
2/15 DocID026089 Rev 3
STL33N65M2
1
Electrical ratings
Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
GS
I
D
I
D
I
DM
(1)
P
TOT
dv/dt (2) dv/dt (3)
T stg
T j
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Storage temperature range
Operating junction temperature range
Value
± 25
20
12.6
80
150
15
50
- 55 to 150
Notes:
(1)
Pulse width limited by safe operating area.
(2)
I
SD
≤ 20 A, di/dt ≤ 400 A/µs, V
DS(peak)
< V
(BR)DSS
, V
DD
= 400 V.
(3)
V
DS
≤ 520 V.
Symbol
Table 3: Thermal data
Parameter
R thj-case
Thermal resistance junction-case max
R
thj-pcb
(1)
Thermal resistance junction-pcb max
Value
0.83
45
Unit
°C/W
°C/W
Notes:
(1)
When mounted on FR-4 board of inch², 2oz Cu.
Symbol
Table 4: Avalanche characteristics
Parameter
I
AR
E
AS
Avalanche current, repetitive or notrepetitive (pulse width limited by T jmax
)
Single pulse avalanche energy (starting T j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Value Unit
2.2
600
A mJ
Unit
V
A
A
A
W
V/ns
V/ns
°C
°C
DocID026089 Rev 3 3/15
Electrical characteristics
2 Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Symbol Parameter
Table 5: On /off states
Test conditions
V
(BR)DSS
Drain-source breakdown voltage
V
GS
= 0 V, I
D
= 1 mA
I
DSS
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 650 V
V
GS
= 0 V,
V
DS
= 650 V, T
C
=125 °C (1)
I
GSS
Gate-body leakage current
V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source on- resistance
V
DS
= 0 V, V
GS
= ± 25 V
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 10 A
STL33N65M2
Min. Typ. Max. Unit
650
1
V
µA
100 µA
±10 µA
3 4 V
0.124 0.154 Ω
2
Notes:
(1)
Defined by design, not subject to production test.
Symbol Parameter
Table 6: Dynamic
Test conditions
C
C
C iss oss rss
Input capacitance
Output capacitance
Reverse transfer capacitance
C
oss eq.
(1)
Equivalent output capacitance
Q g
Q gs
Total gate charge
Gate-source charge
Q gd
Gate-drain charge
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0
V
DS
= 0 to 520 V, V
GS
= 0
V
DD
= 520 V, I
D
= 24 A
V
GS
= 10 V
(see Figure 15: "Gate charge test circuit" )
-
-
-
-
Min. Typ. Max. Unit
-
-
1790
75
-
- pF pF
- 2 - pF
380
41.5
6.8
18
-
-
-
-
Notes:
(1)
Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80%
V
DSS
.
Symbol Parameter
Table 7: Switching times
Test conditions Min. Typ. Max. Unit t d(on)
Turn-on delay time t r
Voltage rise time t d(off)
Turn-off delay time t f
Current fall time
V
DD
= 325 V, I
D
= 12 A
R
G
= 4.7 Ω, V
GS
= 10 V
(see Figure 14: "Switching times test circuit for resistive load" and
Figure 19: "Switching time waveform" )
-
-
-
-
13.5
11.5
72.5
11.5
-
-
-
- ns ns ns ns pF nC nC nC
4/15 DocID026089 Rev 3
STL33N65M2
Symbol Parameter
I
SD
Source-drain current
I
SDM
(1)
Source-drain current
(pulsed)
V
SD
(2)
Forward on voltage t
Q rr rr
Reverse recovery time
Reverse recovery charge
I
I
RRM t
Q rr rr
RRM
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Table 8: Source drain diode
Test conditions
I
SD
= 24 A, V
GS
= 0 V
I
SD
= 24 A, di/dt = 100 A/µs
V
DD
= 60 V (see Figure 16: " Test circuit for inductive load switching and diode recovery times" )
I
SD
= 24 A, di/dt = 100 A/µs
V
DD
= 60 V, T j
= 150 °C
(see Figure 16: " Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
- 20 A
- 80 A
- 1.6 V
- 426 ns
- 7 µC
- 33.5 A
- 544 ns
- 10 µC
- 36.5 A
Notes:
(1)
Pulse width limited by safe operating area.
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%.
DocID026089 Rev 3 5/15
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STL33N65M2
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
6/15 DocID026089 Rev 3
STL33N65M2
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Output capacitance stored energy
Figure 10: Normalized gate threshold voltage vs temperature
Figure 11: Normalized on-resistance vs temperature
Figure 12: Source-drain diode forward characteristics
Figure 13: Normalized V
(BR)DSS
vs temperature
DocID026089 Rev 3 7/15
Test circuits
3 Test circuits
Figure 14: Switching times test circuit for resistive load
STL33N65M2
Figure 15: Gate charge test circuit
R L
+
2200
µF
3.3
µF
V
DD
V
GS
V D
R
G
D.U.T.
P
W
GND1
(driver signal)
GND2
(power)
Figure 16: Test circuit for inductive load switching and diode recovery times
Figure 17: Unclamped inductive load test circuit
25Ω
G
A
D
D.U.T.
S
B
R
G
A
FAST
DIODE
A
B
B
D
L=100µH
G
S
D.U.T.
3.3
µF
+
1000
µF
V
DD
V
D
I
D
L
+
2200
µF
3.3
µF
V
DD
V i D.U.T.
GND1 GND2
Figure 18: Unclamped inductive waveform
P w
GND1 GND2
AM15858v1
Figure 19: Switching time waveform
8/15 DocID026089 Rev 3
STL33N65M2
4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
DocID026089 Rev 3 9/15
Package information
4.1 PowerFLAT™ 8x8 HV package information
Figure 20
: PowerFLAT™ 8x8 HV package outline
STL33N65M2
10/15 DocID026089 Rev 3
8222871_Rev_3_ A
STL33N65M2
Dim.
D
E
D2
E1
A
A1
A3 b
E2 e
L
Table 9: PowerFLAT™ 8x8 HV mechanical data
Package information mm
Min. Typ. Max.
0.75
0.00
0.10
0.90
7.90
7.90
7.10
2.65
4.25
0.40
0.85
0.20
1.00
8.00
8.00
7.20
2.75
4.35
2.00
0.50
0.95
0.05
0.30
1.10
8.10
8.10
7.30
2.85
4.45
0.60
Figure 21 : PowerFLAT™ 8x8 HV footprint
All dimensions are in millimeters.
DocID026089 Rev 3 11/15
Package information
4.2 PowerFLAT™ 8x8 HV packing information
Figure 22
: PowerFLAT™ 8x8 HV tape
STL33N65M2
All dimensions are in millimeters.
Figure 23
: PowerFLAT™ 8x8 HV package orientation in carrier tape
12/15 DocID026089 Rev 3
STL33N65M2
Figure 24
: PowerFLAT™ 8x8 HV reel
Package information
All dimensions are in millimeters.
DocID026089 Rev 3 13/15
Revision history
5
STL33N65M2
Revision history
Date Revision
Table 10: Document revision history
Changes
26-Jun-2013
23-Jul-2014
13-Apr-2016
1
2
3
First release.
Text edits throughout document.
On cover page, updated title, features and description.
Updated Table 2: Absolute maximum ratings.
Updated Table 3: Thermal data.
Added Table 4: Avalanche characteristics.
Updated Table 5: On /off states.
Updated Table 6: Dynamic.
Updated Table 7: Switching times.
Updated Table 8: Source drain diode.
Updated cover image and Figure 1: "Internal schematic diagram" .
Updated Section 3: "Test circuits" .
Added footnote in Table 5: "On /off states" .
Removed footnote in Table 8: "Source drain diode" .
Updated Section 4: "Package information" .
Minor text changes.
14/15 DocID026089 Rev 3
STL33N65M2
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