STB20N90K5
Datasheet
N-channel 900 V, 0.21 Ω typ., 20 A MDmesh™ K5 Power MOSFET in a D²PAK package
G(1)
TAB
2
1
3
D²PAK
D(2, TAB)
S(3)
AM01475V1
Features
Order code
STB20N90K5
V
DS
900 V
• Industry’s lowest R
DS(on)
x area
• Industry’s best FoM (figure of merit)
• Ultra-low gate charge
• 100% avalanche tested
• Zener-protected
R
DS(on )
max.
0.25 Ω
I
D
20 A
Applications
• Switching applications
Description
This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
Product status link
STB20N90K5
Product summary
Order code STB20N90K5
Marking
Package
Packing
20N90K5
D²PAK
Tape and reel
DS11568 - Rev 4 - October 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
1
STB20N90K5
Electrical ratings
Electrical ratings
Table 1. Absolute maximum ratings
Symbol Parameter
V
GS
I
D
I
D
I
D
(1)
P
TOT dv/dt
(2)
Gate-source voltage
Drain current (continuous) at T
C
Drain current (continuous) at T
C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
= 25 °C
= 100 °C dv/dt
(3)
T j
T stg
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Operating junction temperature range
Storage temperature range
1. Pulse width limited by safe operating area.
2. I
SD
≤ 20 A, di/dt ≤ 100 A/μs; V
DS
peak ≤ V
(BR)DSS
, V
DD
= 450 V.
3. V
DS
≤ 720 V.
Table 2. Thermal data
Symbol
R thj-case
Thermal resistance junction-case
R thj-pcb
(1)
Thermal resistance junction-pcb
Parameter
1. When mounted on a 1-inch² FR-4, 2 Oz copper board.
Symbol
I
AR
E
AS
Table 3. Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive (pulse width limited by T jmax
)
Single pulse avalanche energy (starting T j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Value
±30
20
13
80
250
4.5
50
-55 to 150
Unit
V
A
A
A
W
V/ns
°C
Value
0.5
30
Unit
°C/W
°C/W
Value
6.5
500
Unit
A mJ
DS11568 - Rev 4 page 2/15
2
STB20N90K5
Electrical characteristics
Electrical characteristics
T
C
= 25 °C unless otherwise specified
Table 4. On/off-state
Symbol
V
(BR)DSS
Parameter
Drain-source breakdown voltage
V
GS
Test conditions
= 0 V, I
D
= 1 mA
I
DSS
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 900 V
V
GS
= 0 V, V
DS
= 900 V
T
C
= 125 °C (1)
V
R
I
GSS
GS(th)
DS(on)
Gate body leakage current
Gate threshold voltage
Static drain-source on-resistance
V
V
V
DS
DS
GS
= 0 V, V
GS
= V
GS
1. Defined by design, not subject to production test.
, I
D
= 10 V, I
D
= ±20 V
= 100 µA
= 10 A
Min.
900
3
Typ.
4
0.21
Max.
1
50
±10
5
0.25
Table 5. Dynamic
Symbol
C
C
C iss
C oss
C rss o(er) o(tr)
R g
Q g
Q gs
Q gd
(1)
(2)
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent capacitance energy related
Equivalent capacitance time related
Total gate charge
Gate-source charge
Gate-drain charge
V
V
V
V
DS
GS
GS
DS
V
DD
Test conditions
= 100 V, f = 1 MHz,
= 0 V
= 0 V,
= 0 to 720 V
Intrinsic gate resistance f = 1 MHz , I
D
= 0 A
= 720 V, I
D
V
GS
= 0 to 10 V
= 20 A
(see Figure 14. Test circuit for gate charge behavior
)
Min.
-
-
-
-
-
-
-
-
Typ.
1500
120
1
78
220
3.7
40
14
17
Max.
-
-
-
-
-
-
-
-
-
Unit pF pF pF pF pF
Ω nC nC nC
1. C o(er)
is a constant capacitance value that gives the same stored energy as C oss
while V
DS
is rising from 0 to 80% V
DSS
.
2. C o(tr)
is a constant capacitance value that gives the same charging time as C oss
while V
DS
is rising from 0 to 80% V
DSS
.
Unit
V
µA
µA
µA
V
Ω
DS11568 - Rev 4 page 3/15
DS11568 - Rev 4
STB20N90K5
Electrical characteristics
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
V
DD
= 450 V, I
D
= 10 A,
R
G
= 4.7 Ω
V
GS
= 10 V
(see Figure 13. Test circuit for resistive load switching times
and
Figure 18. Switching time waveform
)
Min.
-
-
-
-
Typ.
20.2
13.5
64.7
16
Max.
-
-
-
-
Unit ns ns ns ns
Table 7. Source-drain diode
Symbol
I
I
SD
SDM
(1)
Parameter
Source-drain current
Source-drain current
(pulsed)
Test conditions
V
SD
I
I
Q rr
RRM t t rr
Q rr rr
(2)
RRM
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 20 A, V
GS
= 0 V
I
SD
= 20 A, di/dt = 100 A/µs,
V
DD
= 60 V
(see Figure 15. Test circuit for inductive load switching and diode recovery times
)
I
SD
= 20 A, di/dt = 100 A/µs,
V
DD
= 60 V,
T j
= 150 °C
(see Figure 15. Test circuit for inductive load switching and diode recovery times
)
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Min.
-
-
-
-
-
-
-
-
-
Symbol
V
(BR)GSO
Parameter
Gate-source breakdown voltage
Table 8. Gate-source Zener diode
Test conditions Min.
I
GS
= ±1 mA, I
D
= 0 A 30
517
11.4
44
674
14
41.6
Typ.
Max.
20
80
1.5
V ns
µC
A
Unit
A
A ns
µC
A
Typ.
-
Max.
-
Unit
V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device.
The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry.
page 4/15
STB20N90K5
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
I
D
(A)
Figure 1. Safe operating area
GIPG301120161112SOA
10 1
Operation in this area is limited by R
DS(on)
10 0
T
T j
≤150 °C c
= 25°C single pulse
10 -1
10 -1 10 0 10 1 10 2 t p t p t t p p
=10 µs
=100 µs
=1 ms
=10 ms
V
DS
(V)
20
10
0
0
I
D
(A)
50
Figure 3. Output characteristics
GIPG291120161015OCH
V
GS
=10, 11 V
40
V
GS
=9 V
30
V
GS
=8 V
4
V
GS
=7 V
8 12
V
GS
=6 V
16 V
DS
(V)
Figure 5. Normalized V
(BR)DSS
vs temperature
V
(BR)DSS
(norm.)
1.12
I
D
= 1 mA
GIPG291120161015BDV
1.08
1.04
1.00
0.96
0.92
0.88
-50 0 50 100 T j
(°C)
Figure 2. Thermal impedance
30
20
10
0
5
Figure 4. Transfer characteristics
I
D
(A)
50
V
DS
= 20 V
GIPG291120161014TCH
40
6 7 8 9 10 V
GS
(V)
Figure 6. Static drain-source on-resistance
R
DS(on)
(Ω)
0.23
GIPG291120161014RID
V
GS
=10 V
0.22
0.21
0.20
0.19
0.18
0 5 10 15 I
D
(A)
DS11568 - Rev 4 page 5/15
STB20N90K5
Electrical characteristics (curves)
V
GS
(V)
14
12
10
4
2
0
0
8
6
Figure 7. Gate charge vs gate-source voltage
10
V
DS
GIPG291120161013QVG V
DS
(V)
700
V
DD
I
D
= 720 V
= 20 A
600
500
400
300
20 30 40
200
100
Q
0 g
(nC)
Figure 9. Normalized gate threshold voltage vs temperature
V
GS(th)
(norm.)
1.2
GIPG291120161016VTH
I
D
= 100 µA
1.0
0.8
0.6
0.4
0.2
-50 0 50 100 T j
(°C)
C
(pF)
Figure 8. Capacitance variation
GIPG291120161011CVR
10 4
10 3
C
ISS
10 2
10 1
10 0
10 -1 f = 1 MHz
10 0 10 1 10 2
C
OSS
C
RSS
V
DS
(V)
Figure 10. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
2.6
GIPG291120161017RON
V
GS
= 10 V
2.2
1.8
1.4
1.0
0.6
0.2
-50 0 50 100 T j
(°C)
Figure 11. Maximum avalanche energy vs. starting T
J
E
AS
(mJ)
500
GIPG291120161018EAS
400
Single pulse
I
D
= 6.5 A
V
DD
= 50 V
300
200
100
0
-50 -25 0 25 50 75 100 125 T
J
(°C)
Figure 12. Source-drain diode forward characteristics
V
SD
(V)
1.1
1
Tj = -50 °C
0.9
0.8
Tj = 25 °C
0.7
Tj = 150 °C
0.6
0.5
0.4
5 10
GIPD280920181027SDF
15 I
SD
(A)
DS11568 - Rev 4 page 6/15
STB20N90K5
Test circuits
3
Test circuits
Figure 13. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF V
DD
D.U.T.
Figure 14. Test circuit for gate charge behavior
V
DD
RL
V
GS pulse width
2200
μF
+
I
G
= CONST
2.7 kΩ
47 kΩ
1 kΩ
100 Ω D.U.T.
V
G
AM01469v10
AM01468v1
Figure 15. Test circuit for inductive load switching and diode recovery times
Figure 16. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
A A fast diode
B
B
G
+
_
R
G
100 µH
D
D.U.T.
S
3.3
µF
+
1000
µF
V
DD
AM01470v1
Figure 17. Unclamped inductive waveform
V
(BR)DSS
V
D
I
DM
I
D
V
DD
V
DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF
V
DD
D.U.T.
AM01471v1
0
Figure 18. Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
V
GS
V
DS
90%
10%
0 10%
AM01473v1
DS11568 - Rev 4 page 7/15
4
STB20N90K5
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
DS11568 - Rev 4 page 8/15
4.1
STB20N90K5
D²PAK (TO-263) type A2 package information
D²PAK (TO-263) type A2 package information
Figure 19. D²PAK (TO-263) type A2 package outline
DS11568 - Rev 4
0079457_A2_25 page 9/15
DS11568 - Rev 4
STB20N90K5
D²PAK (TO-263) type A2 package information
Dim.
e1
H
J1
L
L1
L2
R
V2
D
D1
D2
E
E1
E2 e
A
A1 b b2 c c2
Table 9. D²PAK (TO-263) type A2 package mechanical data mm
Typ.
1.14
0.45
1.23
8.95
7.50
Min.
4.40
0.03
0.70
1.10
10.00
8.70
7.30
7.75
1.30
8.90
7.50
2.54
4.88
15.00
2.49
2.29
1.27
1.30
0.40
0°
5.28
15.85
2.69
2.79
1.40
1.75
8°
1.70
0.60
1.36
9.35
8.00
Max.
4.60
0.23
0.93
1.50
10.40
9.10
7.70
Figure 20. D²PAK (TO-263) recommended footprint (dimensions are in mm)
Footprint page 10/15
4.2
D²PAK packing information
Figure 21. D²PAK tape outline
STB20N90K5
D²PAK packing information
DS11568 - Rev 4 page 11/15
DS11568 - Rev 4
A
STB20N90K5
D²PAK packing information
D
B
Full radius
Figure 22. D²PAK reel outline
T
40mm min. access hole at slot location
Tape slot in core for tape start
2.5mm min.width
C
N
G measured at hub
Dim.
E
F
K0
P0
P1
P2
R
T
W
A0
B0
D
D1
Min.
1.65
11.4
4.8
3.9
11.9
1.9
50
0.25
23.7
10.5
15.7
1.5
1.59
Tape
Table 10. D²PAK tape and reel mechanical data
Reel mm
Dim.
Max.
10.7
15.9
1.6
1.61
1.85
11.6
5.0
4.1
12.1
2.1
C
D
A
B
G
N
T
Base quantity
Bulk quantity
Min.
1.5
12.8
20.2
24.4
100
0.35
24.3
mm
AM06038v1
Max.
330
13.2
26.4
30.4
1000
1000 page 12/15
STB20N90K5
Revision history
Date
19-May-2016
01-Dec-2016
24-Jan-2017
04-Oct-2018
Revision
1
2
3
4
Table 11. Document revision history
Changes
First release.
Modified title and R
DS(on)
in features table
Modified Table 4: "Avalanche characteristics" , Table 5: "On/off-state" , Table 6: "Dynamic" ,
Table 7: "Switching times" , Table 8: "Source-drain diode"
Added Section 2.1: "Electrical characteristics (curves)"
Modified Section 3: "Test circuits"
Datasheet promoted from preliminary data to production data
Minor text changes
Modified Table 7: "Switching times".
Minor text changes.
Removed maturity status indication from cover page.
Added
Figure 12. Source-drain diode forward characteristics .
Minor text changes.
DS11568 - Rev 4 page 13/15
STB20N90K5
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
D²PAK (TO-263) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
D²PAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
DS11568 - Rev 4 page 14/15
STB20N90K5
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS11568 - Rev 4 page 15/15
