G(1)
TAB
2
1
3
D(2, TAB)
STB23N80K5
Datasheet
N-channel 800 V, 0.23 Ω typ., 16 A MDmesh K5 Power MOSFET in a D²PAK package
S(3)
NG1D2TS3Z
Features
Order code
STB23N80K5
V
DS
800 V
R
DS(on)
max.
0.28 Ω
• Industry’s lowest R
DS(on)
x area
• Industry’s best FoM (figure of merit)
• Ultra-low gate charge
• 100% avalanche tested
• Zener-protected
I
D
16 A
P
TOT
190 W
Applications
• Switching applications
Description
This very high voltage N-channel Power MOSFET is designed using MDmesh
K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
Product status link
STB23N80K5
Product summary
Order code STB23N80K5
Marking
Package
Packing
23N80K5
D²PAK
Tape and reel
DS11240 - Rev 2 - May 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
STB23N80K5
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
I
GS
D
Parameter
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed) I
DM
(1)
P
TOT dv/dt
(2)
Total power dissipation at T
C
= 25 °C
Peak diode recovery voltage slope dv/dt
(3)
T stg
T
J
MOSFET dv/dt ruggedness
Storage temperature range
Operating junction temperature range
1. Pulse width is limited by safe operating area.
2. I
SD
≤ 16 A, di/dt=100 A/μs; V
DS(peak)
< V
(BR)DSS
, V
DD
= 80% V
(BR)DSS
.
3. V
DS
≤ 640 V
Table 2. Thermal data
Symbol
R thJC
R thJA
(1)
Parameter
Thermal resistance, junction-to-ambient
Thermal resistance, junction-to-board
1. When mounted on 1-inch² FR-4, 2 Oz copper board.
Table 3. Avalanche characteristics
Symbol
I
AR
(1)
E
AS
(2)
Single pulse avalanche energy
Parameter
Avalanche current, repetitive or not repetitive
1. Pulse width limited by T
Jmax
.
2. Starting T
J
= 25 °C, I
D
= I
AR
, V
DD
= 50 V.
Value
±30
16
10
64
190
4.5
50
-55 to 150
Unit
V
A
A
W
V/ns
°C
Value
0.66
30
Unit
°C/W
Value
5
400
Unit
A mJ
DS11240 - Rev 2 page 2/19
2
STB23N80K5
Electrical characteristics
Electrical characteristics
T
C
= 25 °C unless otherwise specified.
Table 4. Static
Symbol
V
(BR)DSS
I
DSS
Parameter
I
GSS
V
GS(th)
R
DS(on)
1. Defined by design, not subject to production test.
Test conditions
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 800 V
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 800 V, T
C
= 125 °C (1)
Gate-body leakage current
Gate threshold voltage
V
DS
= 0 V, V
GS
= ±20 V
V
DS
= V
GS
, I
D
= 100 µA
Static drain-source on-resistance V
GS
= 10 V, I
D
= 8 A
Min.
Typ.
Max.
Unit
800 V
1
50
µA
3 4
±10
5
0.23
0.28
µA
V
Ω
Table 5. Dynamic
Symbol
C iss
C oss
C rss
C
O(tr)
(1)
C
O(er)
(2)
R
G
Q g
Q gs
Q gd
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent output capacitance
Equivalent output capacitance
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
V
V
DS f = 1 MHz, I
D
V
DS
DS
DD
10 V (see
Test conditions
= 100 V, f = 1 MHz, V
= 0 to 640 V, V
= 0 A
= 640 V, I
D
charge behavior )
GS
= 0 to 640 V, V
GS
GS
= 0 V
= 0 V
= 16 A, V
GS
= 0 V
= 0 to
Figure 13. Test circuit for gate
Min.
-
-
-
-
-
-
-
-
-
Typ.
1000
65
1.5
165
59
4.7
33
6
25
Max.
-
-
-
-
-
-
-
-
-
Unit pF pF
Ω nC
1. Time related is defined as a constant equivalent capacitance giving the same charging time as C
OSS from 0 to 80% V
DSS
.
when V
DS
increases
2. Energy related is defined as a constant equivalent capacitance giving the same stored energy as C
OSS
when V from 0 to 80% V
DSS
DS
increases
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
V
DD
= 400 V, I
D
= 8 A, R
G
= 4.7 Ω,
V
GS
= 10 V (see Figure 12. Test circuit for resistive load switching times and
Figure 17. Switching time waveform )
Min.
Typ.
Max.
Unit
14 -
9 ns
-
48
9 -
-
DS11240 - Rev 2 page 3/19
DS11240 - Rev 2
STB23N80K5
Electrical characteristics
Table 7. Source-drain diode
Symbol
I
SD
I
SDM
(1)
V
SD
(2)
t rr
Q rr
I
RRM t rr
Q rr
I
RRM
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
I
V
T j
GS
SD
SD
1. Pulse width is limited by safe operating area.
2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
Test conditions
= 0 V, I
SD
= 16 A
= 16 A, di/dt = 100 A/µs, V
DD
(see
= 16 A, di/dt = 100 A/µs, V
recovery times )
DD
= 60 V
Figure 14. Test circuit for inductive load switching and diode recovery times
= 60 V,
= 150 °C (see
Figure 14. Test circuit for inductive load switching and diode
)
-
-
-
-
-
-
Min.
Typ.
Max.
Unit
16 A
-
64
1.5
A
V
410
7
34
650
10
32 ns
µC
A ns
µC
A
Symbol
V
(BR)GSO
Table 8. Gate-source Zener diode
Parameter Test conditions
Gate-source breakdown voltage I
GS
= ±1 mA, I
D
= 0 A
Min.
Typ.
Max.
Unit
±30 V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device.
The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry.
page 4/19
STB23N80K5
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
I
D
(A)
Figure 1. Safe operating area
GIPG280815VK86BSOA
10 1
Operation in this area is limited by R
DS(on)
10 µs
100 µs
1 ms
10 ms 10 0
10 -1
10 -1 10 0
T j
= 150 °C
T c
= 25 °C single pulse
10 1 10 2
V
DS
(V)
Figure 2. Normalized transient thermal impedance
GC20540
Figure 3. Typical output characteristics
I
D
(A)
GIPG130815VK86WOCH
40
30
V
GS
= 11 V
V
GS
= 10 V
V
GS
= 9 V
20
V
GS
= 8 V
10
0
0 4 8 12
V
GS
= 7 V
V
GS
= 6 V
16 V
DS
(V)
Figure 4. Typical transfer characteristics
I
D
(A)
GIPG130815VK86WTCH
V
DS
= 20 V
40
30
20
10
0
5 6 7 8 9 10 V
GS
(V)
Figure 5. Typical gate charge characteristics
V
GS
(V) V
DS
12
GIPG130815VK86WQVG V
DS
(V)
V
DD
= 640 V, I
D
= 16 A
600
6
4
10
8
2
0
0 10 20 30
500
400
300
200
100
Q
0 g
(nC)
Figure 6. Typical drain-source on-resistance
R
DS(on)
(Ω)
GIPG130815VK86WRID
V
GS
= 10 V
0.35
0.30
0.25
0.20
0.15
0 10 20 30 I
D
(A)
DS11240 - Rev 2 page 5/19
STB23N80K5
Electrical characteristics (curves)
Figure 7. Typical capacitance characteristics
C
(pF)
GIPG130815VK86WCVR
10 3
C
ISS
10 2
10 1 f = 1 MHz
10 0
10 -1 10 0 10 1 10 2
C
C
OSS
RSS
V
DS
(V)
Figure 8. Normalized gate threshold vs temperature
V
GS(th)
(norm.)
1.2
GIPG130815VK86WVTH
I
D
= 100 µA
1.0
0.8
0.6
0.4
0.2
-50 0 50 100 T j
(°C)
Figure 9. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
2.6
GIPG130815VK86WRON
V
GS
= 10 V
2.2
1.8
1.4
1.0
0.6
0.2
-50 0 50 100 T j
(°C)
Figure 10. Normalized breakdown voltage vs temperature
V
(BR)DSS
(norm.)
1.08
GIPG130815VK86WBDV
I
D
= 1 mA
1.04
1.00
0.96
0.92
0.88
-50 0 50 100 T j
(°C)
Figure 11. Maximum avalanche energy vs temperature
E
AS
(mJ)
GIPG130815VK86WEAS50
Single pulse, I
D
= 5 A, V
DD
= 50 V
400
300
200
100
0
-50 0 50 100 T
C
(°C)
DS11240 - Rev 2 page 6/19
STB23N80K5
Test circuits
3
Test circuits
Figure 12. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF
D.U.T.
V
DD
AM01468v1
Figure 14. Test circuit for inductive load switching and diode recovery times
Figure 13. Test circuit for gate charge behavior
12 V
V
GS pulse width
2200
μF
+
1 kΩ
I
G
= CONST
2.7 kΩ
47 kΩ
47 kΩ
100 nF
100 Ω
V
DD
1 kΩ
D.U.T.
V
G
AM01469v1
Figure 15. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
+
_
R
G
A A fast diode
B
B
G
100 µH
D
D.U.T.
S
3.3
µF +
1000
µF
V
DD
AM01470v1
Figure 16. Unclamped inductive waveform
V
(BR)DSS
V
D
I
DM
I
D
V
DD
V
DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF V
DD
D.U.T.
AM01471v1
0
Figure 17. Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
V
GS
V
DS
90%
10%
0 10%
AM01473v1
DS11240 - Rev 2 page 7/19
4
4.1
STB23N80K5
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
D²PAK (TO-263) type A package information
Figure 18. D²PAK (TO-263) type A package outline
DS11240 - Rev 2
0079457_26 page 8/19
DS11240 - Rev 2
Dim.
L2
R
V2
J1
L
L1
E1
E2 e e1
H c2
D
D1
D2
E
A
A1 b b2 c
STB23N80K5
D²PAK (TO-263) type A package information
Table 9. D²PAK (TO-263) type A package mechanical data mm
Typ.
Min.
1.23
8.95
7.50
1.10
10.00
8.30
6.85
4.40
0.03
0.70
1.14
0.45
7.75
1.30
8.50
7.05
2.54
4.88
15.00
2.49
2.29
1.27
1.30
0.40
0°
Max.
1.36
9.35
8.00
1.50
10.40
8.70
7.25
4.60
0.23
0.93
1.70
0.60
5.28
15.85
2.69
2.79
1.40
1.75
8° page 9/19
4.2
D²PAK packing information
Figure 19. D²PAK tape outline
STB23N80K5
D²PAK packing information
DS11240 - Rev 2 page 10/19
DS11240 - Rev 2
A
STB23N80K5
D²PAK packing information
D
B
Full radius
Figure 20. D²PAK reel outline
T
40mm min. access hole at slot location
Tape slot in core for tape start
2.5mm min.width
C
N
G measured at hub
Dim.
K0
P0
P1
E
F
A0
B0
D
D1
P2
R
T
W
4.8
3.9
11.9
1.9
50
0.25
23.7
Min.
10.5
15.7
1.5
1.59
1.65
11.4
Tape
Table 10. D²PAK tape and reel mechanical data
Reel mm
Dim.
Max.
10.7
15.9
1.6
1.61
1.85
11.6
5.0
4.1
12.1
2.1
G
N
T
A
B
C
D
Base quantity
Bulk quantity
Min.
1.5
12.8
20.2
24.4
100
0.35
24.3
mm
AM06038v1
Max.
330
13.2
26.4
30.4
1000
1000 page 11/19
4.3
STB23N80K5
D²PAK (TO-263) type B package information
D²PAK (TO-263) type B package information
Figure 21. D²PAK (TO-263) type B package outline
DS11240 - Rev 2
0079457_26_B page 12/19
DS11240 - Rev 2
Dim.
E
E1 e
H
L
L1
L2
L3
L4 c c1 c2
D
D1
A
A1 b b1 b2
STB23N80K5
D²PAK (TO-263) type B package information
Table 11. D²PAK (TO-263) type B mechanical data mm
Typ.
Min.
0.38
0.38
1.19
8.60
6.90
10.15
8.10
4.36
0
0.70
0.51
1.17
2.54 BSC
15.00
1.90
4.78
0.25
15.60
2.50
1.65
1.78
5.28
Max.
0.694
0.534
1.34
9.00
7.50
10.55
8.70
4.56
0.25
0.90
0.89
1.37
page 13/19
DS11240 - Rev 2
STB23N80K5
D²PAK (TO-263) type B package information
Figure 22. D²PAK (TO-263) recommended footprint (dimensions are in mm)
0079457_Rev26_footprint page 14/19
4.4
D²PAK type B packing information
Figure 23. D²PAK type B tape outline
STB23N80K5
D²PAK type B packing information
DS11240 - Rev 2
A
Figure 24. D²PAK type B reel outline
D
B
Full radius
T
40mm min. access hole at slot location
Tape slot in core for tape start
2.5mm min.width
C
N
G measured at hub
AM06038v1 page 15/19
Dim.
N
T
D
G
A
B
C
Table 12. D²PAK type B reel mechanical data mm
Min.
1.5
12.8
20.2
24.4
100
STB23N80K5
D²PAK type B packing information
Max.
330
13.2
26.4
30.4
DS11240 - Rev 2 page 16/19
Revision history
Date
28-Aug-2015
21-May-2021
Revision
1
2
Table 13. Document revision history
Changes
First release.
Updated Section 4.1 D²PAK (TO-263) type A package information .
Added
Section 4.3 D²PAK (TO-263) type B package information
.
Minor text changes.
STB23N80K5
DS11240 - Rev 2 page 17/19
STB23N80K5
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
D²PAK (TO-263) type A package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
D²PAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3
D²PAK (TO-263) type B package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4
D²PAK type B packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
DS11240 - Rev 2 page 18/19
STB23N80K5
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS11240 - Rev 2 page 19/19
