STF18N60M2
Datasheet
N-channel 600 V, 0.255 Ω typ., 13 A MDmesh M2
Power MOSFET in a TO-220FP package
Features
1
2
3
TO-220FP
Order code
VDS @TJmax
RDS(on) max.
ID
STF18N60M2
650 V
0.280 Ω
13 A
•
•
Extremely low gate charge
Excellent output capacitance (COSS) profile
•
•
100% avalanche tested
Zener-protected
D(2)
Applications
•
•
•
G(1)
Switching applications
LCC converters
Resonant converters
Description
S(3)
AM15572v1_no_tab
This device is an N-channel Power MOSFET developed using MDmesh M2
technology. Thanks to its strip layout and an improved vertical structure, the device
exhibits low on-resistance and optimized switching characteristics, rendering it
suitable for the most demanding high efficiency converters.
Product status link
STF18N60M2
Product summary
Order code
STF18N60M2
Marking
18N60M2
Package
TO-220FP
Packing
Tube
DS9710 - Rev 4 - June 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
STF18N60M2
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
Value
Unit
Gate-source voltage
±25
V
Drain current (continuous) at TC = 25 °C
13
A
Drain current (continuous) at TC = 100 °C
8
A
Drain current (pulsed)
52
A
Total power dissipation at TC = 25 °C
25
W
Peak diode recovery voltage slope
15
V/ns
MOSFET dv/dt ruggedness
50
V/ns
VISO
Insulation withstand voltage (RMS) from all three leads to external heat
sink (t = 1 s; TC = 25 °C)
2.5
kV
Tstg
Storage temperature range
-55 to 150
°C
Value
Unit
5
°C/W
62.5
°C/W
Value
Unit
3
A
135
mJ
VGS
ID (1)
IDM
(2)
PTOT
dv/dt (3)
dv/dt
(4)
Tj
Parameter
Operating junction temperature range
1. Limited by maximum junction temperature.
2. Pulse width limited by safe operating area.
3. ISD ≤ 13 A, di/dt ≤ 400 A/µs; VDS(peak) < V(BR)DSS, VDD = 400 V
4. VDS ≤ 480 V
Table 2. Thermal data
Symbol
Parameter
Rthj-case
Thermal resistance junction-case
Rthj-amb
Thermal resistance junction-ambient
Table 3. Avalanche characteristics
Symbol
IAR
EAS
DS9710 - Rev 4
Parameter
Avalanche current, repetitive or not repetitive
(pulse width limited by Tjmax)
Single pulse avalanche energy (starting Tj=25 °C, ID= IAR, VDD=50 V)
page 2/12
STF18N60M2
Electrical characteristics
2
Electrical characteristics
(TC = 25 °C unless otherwise specified).
Table 4. On /off states
Symbol
V(BR)DSS
IDSS
IGSS
VGS(th)
RDS(on)
Parameter
Drain-source breakdown
voltage
Zero gate voltage
drain current
Gate-body leakage
current
Gate threshold voltage
Static drain-source
on-resistance
Test conditions
ID = 1 mA, VGS = 0 V
Min.
Typ.
Max.
600
Unit
V
VGS = 0 V, VDS = 600 V
1
µA
VGS = 0 V, VDS = 600 V,
TC = 125 °C (1)
100
µA
VDS = 0 V, VGS = ± 25 V
±10
µA
3
4
V
0.255
0.280
Ω
Min.
Typ.
Max.
Unit
-
791
-
pF
-
40
-
pF
-
1.3
-
pF
-
164.5
-
pF
VDS = VGS, ID = 250 µA
2
VGS = 10 V, ID = 6.5 A
1. Defined by design, not subject to production test.
Table 5. Dynamic
Symbol
Parameter
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer capacitance
Coss eq. (1)
Test conditions
VDS = 100 V, f = 1 MHz,
VGS = 0 V
Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V
RG
Intrinsic gate resistance
f = 1 MHz, ID = 0 A
-
5.6
-
Ω
Qg
Total gate charge
VDD = 480 V, ID = 13 A,
-
21.5
-
nC
Qgs
Gate-source charge
-
3.2
-
nC
Qgd
Gate-drain charge
VGS = 0 to 10 V (see
Figure 14. Test circuit for gate
charge behavior)
-
11.3
-
nC
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0
to 80% VDSS.
Table 6. Switching times
Symbol
td(on)
tr
td(off)
tf
DS9710 - Rev 4
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Turn-on delay time
VDD = 300 V, ID = 6.5 A,
-
12
-
ns
Rise time
RG = 4.7 Ω, VGS = 10 V
-
9
-
ns
Turn-off delay time
(see Figure 13. Test circuit for
resistive load switching times
and Figure 18. Switching time
waveform)
-
47
-
ns
-
10.6
-
ns
Fall time
page 3/12
STF18N60M2
Electrical characteristics
Table 7. Source-drain diode
Symbol
ISD
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Source-drain current
-
13
A
ISDM (1)
Source-drain current (pulsed)
-
52
A
VSD (2)
Forward on voltage
ISD = 13 A, VGS = 0 V
-
1.6
V
trr
Reverse recovery time
ISD = 13 A, di/dt = 100 A/µs
-
305
ns
Qrr
Reverse recovery charge
-
3.3
µC
IRRM
Reverse recovery current
VDD = 60 V (see
Figure 15. Test circuit for
inductive load switching and
diode recovery times)
-
22
A
trr
Reverse recovery time
ISD = 13 A, di/dt = 100 A/µs
-
417
ns
Qrr
Reverse recovery charge
VDD = 60 V, Tj = 150 °C
-
4.6
µC
IRRM
Reverse recovery current
(see Figure 15. Test circuit for
inductive load switching and
diode recovery times)
-
22
A
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration = 300 μs, duty cycle 1.5%.
DS9710 - Rev 4
page 4/12
STF18N60M2
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 1. Safe operating area
Figure 2. Thermal impedance
AM15834v1
ID
(A)
s
ai
re on)
si a DS(
th R
in ax
n
it o by m
ra
pe ed
O imit
L
10
1
10µs
K
GC20940
10 -1
100µs
1ms
10ms
Tj=150°C
Tc=25°C
0.1
10 -2
Single
pulse
0.01
10
1
0.1
100
10 -3
10 -4
VDS(V)
Figure 3. Output characteristics
VGS=7, 8, 9, 10V
30
25
25
6V
15
10
10
VDS = 18V
5V
5
5
4V
0
0
5
15
10
20
VDS(V)
Figure 5. Gate charge vs gate-source voltage
12
t p (s)
10 0
20
15
VGS
(V)
10 -1
AM15838v1
ID
(A)
30
20
10 -2
Figure 4. Transfer characteristics
AM15837v1
ID
(A)
10 -3
AM15839v1
VDS
VDD = 480 V
ID = 13 A
10
0
0
2
4
10
8
6
VGS(V)
Figure 6. Static drain-source on-resistance
VDS
(V)
RDS(on)
(Ω)
500
0.270
400
0.265
300
0.260
200
0.255
100
0.250
0
Qg (nC)
0.245
0
AM15840v1
VGS=10V
8
6
4
2
0
0
DS9710 - Rev 4
5
10
15
20
25
2
4
6
8
10
12
ID(A)
page 5/12
STF18N60M2
Electrical characteristics (curves)
Figure 8. Normalized gate threshold voltage vs.
temperature
Figure 7. Capacitance variations
AM15841v1
C
(pF)
VGS(th)
(norm.)
GIPG070815BQ6KLVTH
ID = 250 µA
1.1
1000
Ciss
1.0
100
0.9
Coss
0.8
10
0.7
1
0.1
1
10
100
Crss
VDS (V)
Figure 9. Normalized on-resistance vs temperature
RDS(on)
(norm.)
GIPG070815BQ6KLRON
VGS = 10 V
2.4
0.6
-75
-25
25
75
125
TJ (°C)
Figure 10. Source-drain diode forward characteristics
AM15842v1
VSD(V)
1.4
1.2
2.0
TJ=-50°C
1.0
1.6
0.8
1.2
0.6
0.8
0.4
0.4
0.2
0.0
-75
-25
25
75
125
TJ (°C)
Figure 11. Normalized V(BR)DSS vs temperature
V(BR)DSS
(norm.)
GIPG070815BQ6KLBDV
ID = 1 mA
1.12
0.0
4
6
8
12
10
ISD(A)
AM15843v1
Eoss
(µJ)
6
5
1.04
4
1.00
3
0.96
2
1
0.92
DS9710 - Rev 4
2
TJ=25°C
Figure 12. Output capacitance stored energy
1.08
0.88
-75
0
TJ=150°C
-25
25
75
125
TJ (°C)
0
0
100 200
300
400
500
600 VDS (V)
page 6/12
STF18N60M2
Test circuits
3
Test circuits
Figure 13. Test circuit for resistive load switching times
Figure 14. Test circuit for gate charge behavior
VDD
12 V
2200
+ μF
3.3
μF
VDD
VD
VGS
1 kΩ
100 nF
RL
IG= CONST
VGS
RG
47 kΩ
+
pulse width
D.U.T.
2.7 kΩ
2200
μF
pulse width
D.U.T.
100 Ω
VG
47 kΩ
1 kΩ
AM01469v1
AM01468v1
Figure 15. Test circuit for inductive load switching and
diode recovery times
D
G
A
D.U.T.
S
25 Ω
A
L
A
B
B
3.3
µF
D
G
+
VD
100 µH
fast
diode
B
Figure 16. Unclamped inductive load test circuit
RG
1000
+ µF
2200
+ µF
VDD
3.3
µF
VDD
ID
D.U.T.
S
D.U.T.
Vi
_
pulse width
AM01471v1
AM01470v1
Figure 18. Switching time waveform
Figure 17. Unclamped inductive waveform
ton
V(BR)DSS
td(on)
VD
toff
td(off)
tr
tf
90%
90%
IDM
VDD
10%
0
ID
VDD
AM01472v1
VGS
0
VDS
10%
90%
10%
AM01473v1
DS9710 - Rev 4
page 7/12
STF18N60M2
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
4.1
TO-220FP package information
Figure 19. TO-220FP package outline
7012510_Rev_13_B
DS9710 - Rev 4
page 8/12
STF18N60M2
TO-220FP package information
Table 8. TO-220FP package mechanical data
Dim.
mm
Min.
Max.
A
4.40
4.60
B
2.50
2.70
D
2.50
2.75
E
0.45
0.70
F
0.75
1.00
F1
1.15
1.70
F2
1.15
1.70
G
4.95
5.20
G1
2.40
2.70
H
10.00
10.40
L2
DS9710 - Rev 4
Typ.
16.00
L3
28.60
30.60
L4
9.80
10.60
L5
2.90
3.60
L6
15.90
16.40
L7
9.00
9.30
Dia
3.00
3.20
page 9/12
STF18N60M2
Revision history
Table 9. Document revision history
Date
Revision
04-Jun-2013
1
Changes
First release.
– Added: note 2 in Table 2
05-Jun-2013
2
– Modified: typical value for Ciss, Coss eq., Qg, Qgs, Qgd
– Modified: Figure 10 and 11
– Minor text changes
– Modified: note 1 in Table 2
28-Feb-2014
3
– Rthj-case value in Table 3
– Minor text changes
19-Jun-2019
4
Modified Figure 8. Normalized gate threshold voltage vs. temperature,
Figure 9. Normalized on-resistance vs temperature and Figure 11. Normalized
V(BR)DSS vs temperature.
Minor text changes.
DS9710 - Rev 4
page 10/12
STF18N60M2
Contents
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
TO-220FP package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
DS9710 - Rev 4
page 11/12
STF18N60M2
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DS9710 - Rev 4
page 12/12
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