STD5N80K5
Datasheet
N-channel 800 V, 1.50 Ω typ., 4 A MDmesh K5 Power MOSFET in a DPAK package
G(1)
TAB
DPAK
1
2 3
D(2, TAB)
S(3)
AM01475V1
Features
Order code
STD5N80K5
V
DS
800 V
• Industry’s lowest R
DS(on)
x area
• Industry’s best FoM (figure of merit)
• Ultra-low gate charge
• 100% avalanche tested
• Zener-protected
R
DS(on)
max.
1.75 Ω
I
D
4 A
Applications
• Switching applications
Description
This very high voltage N-channel Power MOSFET is designed using MDmesh K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
Product status link
STD5N80K5
Product summary
Order code
Marking
Package
Packing
STD5N80K5
5N80K5
DPAK
Tape and reel
DS11344 - Rev 4 - July 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
1
STD5N80K5
Electrical ratings
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
GS
I
D
I
D
I
DM
(1)
P
TOT dv/dt
(2)
dv/dt
(3)
T
J
T stg
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total power dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Operating junction temperature range
Storage temperature range
Parameter
1. Pulse width limited by safe operating area.
2. I
SD
≤ 4 A, di/dt =100 A/μs; V
DS
(peak) < V
(BR)DSS
, V
DD
= 640 V.
3. V
DS
≤ 640 V.
Table 2. Thermal data
Symbol
R thj-case
R thj-pcb
(1)
Thermal resistance junction-case
Thermal resistance junction-pcb
Parameter
1. When mounted on FR-4 board of 1 inch², 2 oz Cu.
Symbol
I
AR
E
AS
Table 3. Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive (pulse width limited by T
J
max)
Single pulse avalanche energy (starting T
J
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Value
±30
4
2.3
16
60
4.5
50
- 55 to 150
Unit
V
A
A
A
W
V/ns
°C
Value
2.08
50
Value
1.2
165
Unit
°C/W
°C/W
Unit
A mJ
DS11344 - Rev 4 page 2/18
2
STD5N80K5
Electrical characteristics
Electrical characteristics
T
C
= 25 °C unless otherwise specified
Table 4. On/off-state
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Parameter Test conditions
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 800 V
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 800 V, T
C
= 125 °C (1)
Gate-body leakage current
Gate threshold voltage
V
DS
= 0 V, V
GS
= ±20 V
V
DD
= V
GS
, I
D
= 100 µA
Static drain-source on-resistance V
GS
= 10 V, I
D
= 2 A
1. Defined by design, not subject to production test.
Min.
Typ.
Max.
Unit
800 V
1
µA
50
3
±10
4 5
1.50
1.75
µA
V
Ω
Table 5. Dynamic
Symbol
C iss
C oss
C rss
Parameter
Input capacitance
Output capacitance V
DS
Test conditions
= 100 V, f = 1 MHz, V
GS
= 0 V
Min.
-
-
Typ.
177
15
Max.
-
-
Unit pF pF
C
C o(tr) o(er)
(1)
(2)
Reverse transfer capacitance
Equivalent capacitance time related
Equivalent capacitance energy related
V
DS
= 0 to 640 V, V
GS
= 0 V
-
-
0.3
33
12 -
-
pF nC nC
R g
Q g
Q gs
Q gd
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
V
DD
GS
= 640 V, I
= 0 to 10 V
(see
D
charge behavior
= 4 A,
Figure 14. Test circuit for gate
)
-
-
-
-
16
5
1.7
2.9
-
-
-
nC nC nC nC
1. C o(tr)
is a constant capacitance value that gives the same charging time as C oss
while V
DS
is rising from 0 to 80% V
DSS
.
2. C o(er)
is a constant capacitance value that gives the same stored energy as C oss
while V
DS
is rising from 0 to 80% V
DSS
.
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
V
DD
= 400 V, I
D
= 2 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see
Figure 13. Test circuit for resistive load switching times
and
Figure 18. Switching time waveform )
Min.
Typ.
Max.
Unit
-
12.7
11.7
-
ns ns
-
23
14.8
-
ns ns
DS11344 - Rev 4 page 3/18
DS11344 - Rev 4
STD5N80K5
Electrical characteristics
Table 7. Source-drain diode
Symbol
I
SD
I
SDM
(1)
V
SD
(2)
t rr
Q rr
I
RRM t rr
Q rr
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
I
RRM
Reverse recovery current
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration = 300 μs, duty cycle 1.5%.
I
I
SD
SD
Test conditions
= 4 A, V
GS
= 0 V
= 4 A, di/dt = 100 A/μs, V
DD
(see
= 60 V
Figure 15. Test circuit for inductive load switching and diode recovery times
I
SD
= 4 A, di/dt = 100 A/μs, V
DD
= 60 V,
T
J
= 150 °C
(see
Figure 15. Test circuit for inductive load switching and diode recovery times )
)
-
-
-
-
-
Min.
Typ.
Max.
Unit
4 A
16 A
1.5
265
1.59
12
386
V ns
μC
A ns
-
2.18
11.3
μC
A
Symbol
V
(BR)GSO
Table 8. Gate-source Zener diode
Parameter Test conditions
Gate-source breakdown voltage I
GS
= ±1 mA, I
D
= 0 A
Min.
Typ.
Max.
Unit
30 V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device.
The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry.
page 4/18
STD5N80K5
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 1. Safe operating area
I
D
(A)
GIPG270420161532SOA
Operation in this area is limited by R
DS(on)
10 1
10 0 t p
=10 µs t p
=100 µs t p
=1 ms t p
=10 ms
10 -1
10 -2
10 -1 10 0
T
T j
≤150 °C c
= 25°C single pulse
10 1 10 2
V
DS
(V)
Figure 2. Thermal impedance
3
2
1
0
0
I
D
(A)
6
Figure 3. Output characteristics
V
GS
=7, 8, 9, 10 V
GIPG210420161528OCH
V
GS
=11 V
V
GS
=10 V
5
V
GS
=9 V
4
V
GS
=8 V I
D
(A)
6
Figure 4. Transfer characteristics
V
DS
=20 V
GIPG210420161528TCH
5
4 8 12
V
GS
=8 V
V
GS
=7 V
V
GS
=6 V
16 V
DS
(V)
2
1
0
4
4
3
5 6 7 8 9 10 11 V
GS
(V)
Figure 5. Gate charge vs gate-source voltage
V
GS
(V)
12
10
V
DS
GIPG210420161527QVG V
(V)
DS
600
V
DD
I
D
= 640 V
=4 A
500
8
6
4
2
0
0
Q gs
1 2 3
Q gd
4 5
400
300
200
100
0
Q g
(nC)
Figure 6. Static drain-source on-resistance
R
DS(on)
(Ω)
1.8
V
GS
=10 V
GIPG210420161528RID
1.7
1.6
1.5
1.4
1.3
1.2
0 1 2 3 4 I
D
(A)
DS11344 - Rev 4 page 5/18
STD5N80K5
Electrical characteristics (curves)
C
(pF)
Figure 7. Capacitance variations
GIPG210420161526CVR
10 3
C
ISS
10 2
10 1
10 0
10 -1
10 -1 f = 1 MHz
10 0 10 1 10 2
C
OSS
C
RSS
V
DS
(V)
Figure 9. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
2.6
GIPG210420161531RON
V
GS
= 10 V
2.2
1.8
1.4
1.0
0.6
0.2
-75 -25 25 75 125 T j
(°C)
Figure 11. Maximum avalanche energy vs starting T
J
E
AS
(mJ)
150
GIPG210420161532EAS
Single pulse
I
D
V
=1.2 A
DD
=50 V
120
90
60
30
0
-75 -25 25 75 125 T
J
(°C)
Figure 8. Normalized gate threshold voltage vs temperature
V
GS(th)
(norm.)
GIPG210420161529VTH
1.2
I
D
= 100 µA
1.0
0.8
0.6
0.4
0.2
-75 -25 25 75 125 T j
(°C)
Figure 10. Normalized V
(BR)DSS
vs temperature
V
(BR)DSS
(norm.)
1.08
I
D
= 1 mA
GIPG210420161529BDV
1.04
1.00
0.96
0.92
0.88
-75 -25 25 75 125 T j
(°C)
Figure 12. Source-drain diode forward characteristics
V
SD
(V)
1.0
GIPG210420161530SDF
T j
= -50 °C
0.9
0.8
0.7
0.6
0.5
0 1 2
T j
= 25 °C
T j
= 150 °C
3 4 I
SD
(A)
DS11344 - Rev 4 page 6/18
STD5N80K5
Test circuits
3
Test circuits
Figure 13. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF V
DD
D.U.T.
Figure 14. Test circuit for gate charge behavior
V
DD
RL
V
GS pulse width
2200
μF
+
1 kΩ
I
G
= CONST
2.7 kΩ
47 kΩ
100 Ω D.U.T.
V
G
AM01469v10
AM01468v1
Figure 15. Test circuit for inductive load switching and diode recovery times
Figure 16. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
A A fast diode
B
B
G
+
_
R
G
100 µH
D
D.U.T.
S
3.3
µF +
1000
µF
V
DD
AM01470v1
Figure 17. Unclamped inductive waveform
V
(BR)DSS
V
D
I
DM
I
D
V
DD
V
DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF V
DD
D.U.T.
AM01471v1
0
Figure 18. Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
V
GS
V
DS
90%
10%
0 10%
AM01473v1
DS11344 - Rev 4 page 7/18
4
STD5N80K5
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
DS11344 - Rev 4 page 8/18
4.1
STD5N80K5
DPAK (TO-252) type A package information
DPAK (TO-252) type A package information
Figure 19. DPAK (TO-252) type A package outline
DS11344 - Rev 4
0068772_A_26 page 9/18
DS11344 - Rev 4
Dim.
c2
D
D1
E
E1 e e1
A
A1
A2 b b4 c
L2
L4
R
V2
H
L
(L1)
STD5N80K5
DPAK (TO-252) type A package information
Table 9. DPAK (TO-252) type A mechanical data mm
Typ.
9.35
1.00
2.60
0.65
0.60
4.95
6.40
4.60
2.159
4.445
0.64
5.20
0.45
0.48
6.00
Min.
2.20
0.90
0.03
5.10
4.70
2.286
4.572
2.80
0.80
0.20
0°
10.10
1.50
3.00
0.95
1.00
5.25
6.60
4.80
2.413
4.699
0.90
5.40
0.60
0.60
6.20
Max.
2.40
1.10
0.23
8° page 10/18
4.2
STD5N80K5
DPAK (TO-252) type C package information
DPAK (TO-252) type C package information
Figure 20. DPAK (TO-252) type C package outline
DS11344 - Rev 4
0068772_C_26 page 11/18
DS11344 - Rev 4
Dim.
L
L1
L2
L3
L4
L6
θ1
θ2
V2 c2
D
D1
E
E1 e
H
A
A1
A2 b b4 c
STD5N80K5
DPAK (TO-252) type C package information
Table 10. DPAK (TO-252) type C mechanical data
0.72
5.13
0.47
0.47
6.00
Min.
2.20
0.90
0.00
5.25
6.50
4.70
2.186
9.80
1.40
mm
Typ.
2.30
1.01
5.33
6.10
6.60
2.286
10.10
1.50
2.90 REF
0.90
0.60
5°
5°
0°
0.51 BSC
0.80
1.80 BSC
7°
7°
6.70
2.386
10.40
1.70
1.25
0.85
5.46
0.60
0.60
6.20
Max.
2.38
1.10
0.10
1.00
9°
9°
8° page 12/18
DS11344 - Rev 4
STD5N80K5
DPAK (TO-252) type C package information
Figure 21. DPAK (TO-252) recommended footprint (dimensions are in mm)
FP_0068772_26 page 13/18
4.3
DPAK (TO-252) packing information
Figure 22. DPAK (TO-252) tape outline
T
Top cover tape
10 pitches cumulative tolerance on tape +/- 0.2 mm
P0 D P2
B1
K0
For machine ref. only including draft and radii concentric around B0
B0
A0 P1
User direction of feed
D1
STD5N80K5
DPAK (TO-252) packing information
F
E
W
User direction of feed
R
Bending radius
AM08852v1
DS11344 - Rev 4 page 14/18
DS11344 - Rev 4
A
D
B
Figure 23. DPAK (TO-252) reel outline
STD5N80K5
DPAK (TO-252) packing information
T
40mm min. access hole at slot location
C
N
G measured at hub
Full radius
Tape slot in core for tape start
2.5mm min.width
Dim.
E
F
K0
P0
P1
P2
R
T
W
A0
B0
B1
D
D1
AM06038v1
1.5
1.5
1.65
7.4
2.55
3.9
7.9
1.9
40
0.25
15.7
Table 11. DPAK (TO-252) tape and reel mechanical data
Tape Reel mm
Dim.
Min.
6.8
10.4
Max.
7
10.6
12.1
1.6
N
T
D
G
A
B
C
Min.
1.5
12.8
20.2
16.4
50 1.85
7.6
2.75
4.1
8.1
2.1
0.35
16.3
Base qty.
Bulk qty.
mm
Max.
330
13.2
18.4
22.4
2500
2500 page 15/18
STD5N80K5
Revision history
Table 12. Document revision history
Date
08-Jan-2016
09-May-2016
Revision Changes
1 First release.
2
Modified: title
Modified: Table 1. Absolute maximum ratings , Table 2. Thermal data , Table 4. On/off-state , Table 5.
Dynamic , Table 6. Switching times and Table 7. Source-drain diode .
Added: Section 2.1 Electrical characteristics (curves) .
Modified: Section 3 Test circuits.
Minor text changes
03-Apr-2019
05-Jul-2019
3
4
Updated Section 4 Package information .
Minor text changes.
Updated
Section 4 Package information
.
Minor text changes.
DS11344 - Rev 4 page 16/18
STD5N80K5
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
DPAK (TO-252) type A package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
DPAK (TO-252) type C package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3
DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
DS11344 - Rev 4 page 17/18
STD5N80K5
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
DS11344 - Rev 4 page 18/18
