STMicroelectronics STGIPS15C60 Datasheet
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STGIPS15C60
SLLIMM™ small low-loss intelligent molded module
IPM, 3-phase inverter - 15 A, 600 V short-circuit rugged IGBT
Datasheet
-
production data
Applications
• 3-phase inverters for motor drives
• Home appliance, air conditioners
SDIP-25L
Description
This intelligent power module provides a compact, high performance AC motor drive in a simple, rugged design. Combining ST proprietary control ICs with the most advanced short-circuitrugged IGBT system technology, this device is ideal for 3-phase inverters in applications such as motor drives and air conditioners. SLLIMM™ is a trademark of STMicroelectronics.
Features
• IPM 15 A, 600 V 3-phase IGBT inverter bridge including control ICs for gate driving and freewheeling diodes
• Short-circuit rugged IGBTs
• 3.3 V, 5 V, 15 V CMOS/TTL inputs comparators with hysteresis and pull-down / pull-up resistors
• Undervoltage lockout
• Internal bootstrap diode
• Interlocking function
• Smart shutdown function
• Comparator for fault protection against overtemperature and overcurrent
• DBC leading to low thermal resistance
• Isolation rating of 2500 V rms
/min
• UL recognized: UL1557 file E81734
Order code
STGIPS15C60
Table 1. Device summary
Marking Package
GIPS15C60 SDIP-25L
Packing
Tube
April 2015
This is information on a product in full production.
DocID025060 Rev 3 1/20 www.st.com
4
Contents
Contents
STGIPS15C60
Internal block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . 3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2
Waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SDIP-25L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/20 DocID025060 Rev 3
STGIPS15C60
1
Internal block diagram and pin configuration
Internal block diagram and pin configuration
Figure 1. Internal block diagram
Pin 1
OUT U
VBOOT U
LIN-U
HIN-U
VCC
LIN Vboot
SD/OD HVG
OUT HIN
VCC
DT
LVG
CP+
GND
Pin 25
P
U
NU
OUT V
VBOOT V
GND
LIN-V
HIN-V
LIN
HIN
Vboot
SD/OD HVG
OUT
VCC
DT
LVG
CP+
GND
P
V
NV
OUT W
VBOOT W
LIN-W
HIN-W
SD/OD
CIN
Pin 16
HIN
VCC
DT
LIN
SD/OD
Vboot
HVG
OUT
LVG
CP+
GND
P
W
NW
Pin 17
DocID025060 Rev 3
AM05002v1
3/20
20
Pin n°
14
15
16
17
18
19
8
9
10
11
12
13
20
21
22
23
24
25
5
6
7
3
4
1
2
Internal block diagram and pin configuration STGIPS15C60
Symbol
LIN
V
HIN
V
OUT
W
V boot W
LIN
W
HIN
W
SD / OD
CIN
OUT
U
V bootU
LIN
U
HIN
U
V
CC
OUT
V
V boot V
GND
N
W
W
P
N
V
V
P
N
U
U
P
Table 2. Pin description
Description
High-side reference output for U phase
Bootstrap voltage for U phase
Low-side logic input for U phase
High-side logic input for U phase
Low voltage power supply
High-side reference output for V phase
Bootstrap voltage for V phase
Ground
Low-side logic input for V phase
High-side logic input for V phase
High-side reference output for W phase
Bootstrap voltage for W phase
Low-side logic input for W phase
High-side logic input for W phase
Shutdown logic input (active low) / open-drain (comparator output)
Comparator input
Negative DC input for W phase
W phase output
Positive DC input
Negative DC input for V phase
V phase output
Positive DC input
Negative DC input for U phase
U phase output
Positive DC input
Figure 2. Pin layout (bottom view)
0$5.,1*$5($
4/20 DocID025060 Rev 3
STGIPS15C60 Electrical ratings
Symbol
Table 3. Inverter part
Parameter
V
PN
Supply voltage applied between P - N
U
, N
V
, N
W
V
PN(surge)
V
CES
± I
C
Supply voltage (surge) applied between P - N
U
,
N
V
, N
W
Each IGBT collector emitter voltage (V
IN
(1)
= 0)
Each IGBT continuous collector current at T
C
= 25°C
Each IGBT pulsed collector current ± I
CP
(2)
P t
TOT scw
Each IGBT total dissipation at T
C
= 25°C
Short circuit withstand time, V
CE
= 0.5 V
(BR)CES
T
J
= 125 °C, V
CC
= V boot
= 15 V, V
IN (1)
= 0 - 5 V
1.
Applied between HIN i
, LIN i and
GND for i = U, V, W
2.
Pulse width limited by max junction temperature
Value
450
500
600
15
30
42
5
Symbol
Table 4. Control part
Parameter
V
OUT
Output voltage applied between
OUT
U,
OUT
V,
OUT
W
- GND
Low voltage power supply V
CC
V
V
CIN boot
V
IN
Comparator input voltage
Bootstrap voltage applied between
V boot i
- OUT i
for i = U, V, W
Logic input voltage applied between HIN, LIN and
GND
V
SD/OD
Open drain voltage dV
OUT
/dt Allowed output slew rate
Value
V boot
- 21 to V boot
+ 0.3
- 0.3 to +21
- 0.3 to V
CC
+0.3
- 0.3 to 620
- 0.3 to 15
- 0.3 to 15
50
Symbol
V
ISO
T j
T
C
Table 5. Total system
Parameter
Isolation withstand voltage applied between each pin and heatsink plate (AC voltage, t = 60 s)
Power chips operating junction temperature
Module case operation temperature
Value
2500
- 40 to 150
- 40 to 125
Unit
V
V
V
V
V
V
V/ns
Unit
V
°C
°C
Unit
V
V
V
A
A
W
µs
DocID025060 Rev 3 5/20
20
Electrical ratings
Symbol
R thJC
Table 6. Thermal data
Parameter
Thermal resistance junction-case single IGBT
Thermal resistance junction-case single diode
STGIPS15C60
Value
3
5.5
Unit
°C/W
°C/W
6/20 DocID025060 Rev 3
STGIPS15C60 Electrical characteristics
T
J
= 25 °C unless otherwise specified.
Table 7. Inverter part
Symbol Parameter Test conditions
V
CE(sat)
Collector-emitter saturation voltage
V
CC
= V boot
= 15 V, V
IN
(1)
= 0 - 5 V,
I
C
= 15 A
V
CC
= V boot
= 15 V, V
IN
(1)
= 0 - 5 V,
I
C
= 15 A, T
J
= 125 °C
I
CES
V
F
Collector-cut off current
(V
IN
(1)
= 0 “logic state”)
Diode forward voltage
V
V
CE
= 550 V, V
IN
(1)
Inductive load switching time and energy
CC
= V
Boot
= 0 “logic state”, I
C
= 15 V
= 15 A t on t c(on) t off t c(off) t rr
E on
E off
Turn-on time
Crossover time (on)
Turn-off time
Crossover time (off)
Reverse recovery time
Turn-on switching losses
Turn-off switching losses
V
PN
= 300 V,
V
CC
= V boot
= 15 V,
V
IN
(1)
= 0 - 5 V,
I
C
= 15 A
(see
)
1.
Applied between HIN i
, LIN i and
GND for i = U, V, W. (LIN inputs are active-low).
Min.
-
-
-
-
-
-
-
-
-
-
-
Note:
Value
Typ.
1.6
1.7
330
150
925
135
190
385
294
Max.
2
100
2.3
-
-
-
-
-
-
-
Unit
V
µA
V ns
µJ t
ON
and t
OFF
include the propagation delay time of the internal drive. t
C(ON)
and t
C(OFF)
are the switching time of IGBT itself under the internally given gate driving condition.
DocID025060 Rev 3 7/20
20
Electrical characteristics
Figure 3. Switching time test circuit
INPUT
+5V
VCC
RSD
/Lin
/SD
Hin
Vcc
DT
GND
BOOT
HVG
OUT
LVG
CP+
VBOOT>VCC
L
IC
VCE
STGIPS15C60
BUS
V
0
1
Figure 4. Switching time definition
100% I
C
100% I
C t rr
CE
I
C
I
C
V
CE
AM17099v1
Note:
V
IN
V
IN(ON) t
ON t
C(ON)
10% I
C
90% I
C
10% V
CE
V
IN t
OFF
V
IN(OFF)
10% V
CE t
C(OFF)
10% I
C
(a) turn-on (b) turn-off
AM09223V1
Figure 4 "Switching time definition" refers to HIN inputs (active high). For LIN inputs (active low), V
IN
polarity must be inverted for turn-on and turn-off.
8/20 DocID025060 Rev 3
STGIPS15C60 Electrical characteristics
Symbol
Table 8. Low voltage power supply (V
CC
= 15 V unless otherwise specified)
Parameter Test conditions Min.
Typ.
Max.
Unit
V cc_hys
V cc_thON
V cc_thOFF
V cc
UV hysteresis
V cc
UV turn ON threshold
V cc
UV turn OFF threshold
1.2
11.5
10
1.5
12
10.5
1.8
12.5
11
V
V
V
I qccu
I qcc
Undervoltage quiescent supply current
Quiescent current
V
CC
= 10 V
SD/OD = 5 V; LIN = 5 V;
H
IN
= 0, C
IN
= 0
V
CC
= 15 V
SD/OD= 5 V; LIN = 5 V
H
IN
= 0, C
IN
= 0
450
3.5
µA mA
V ref
Internal comparator (CIN) reference voltage
0.5
0.54
0.58
V
V ih
I
HINh
I
HINl
I
LINl
I
LINh
I
SDh
I
SDl
Dt
Table 9. Bootstrapped voltage (V
CC
= 15 V unless otherwise specified)
Parameter Test conditions Min.
Typ.
Max.
Symbol
V
BS_hys
V
BS
UV hysteresis
V
BS_thON
V
BS
UV turn ON threshold
V
BS_thOFF
V
BS
UV turn OFF threshold
I
R
I
QBSU
QBS
DS(on)
Undervoltage V current
BS
quiescent
V
BS
< 9 V
SD/OD = 5 V; LIN and
HIN = 5 V; C
IN
= 0
V
BS
quiescent current
V
BS
= 15 V
SD/OD = 5 V; LIN and
HIN = 5 V; C
IN
= 0
Bootstrap driver on resistance LIN= 5 V; HIN= 0 V
1.2
11.1
9.8
1.5
11.5
10
70
200
120
1.8
12.1
10.6
110
300
Symbol
V il
Table 10. Logic inputs (V
CC
= 15 V unless otherwise specified)
Parameter Test conditions Min.
Typ.
Low level logic threshold voltage
High level logic threshold voltage
HIN logic “1” input bias current HIN = 15 V
HIN logic “0” input bias current HIN = 0 V
LIN logic “1” input bias current LIN = 0 V
LIN logic “0” input bias current LIN = 15 V
SD logic “0” input bias current SD = 15 V
SD logic “1” input bias current SD = 0 V
Dead time see Figure 5 and
0.8
1.9
110
3
30
175
6
120
1.2
Max.
1.1
2.25
260
1
20
1
300
3
Unit
V
V
µA
µA
µA
µs
µA
µA
µA
Unit
V
V
V
µA
µA
Ω
DocID025060 Rev 3 9/20
20
Electrical characteristics STGIPS15C60
Table 11. Sense comparator characteristics (V
CC
= 15 V unless otherwise specified)
Symbol Parameter Test conditions Min.
Typ.
Max.
Unit
I ib
3 µA
V ol t d_comp
SR t sd t isd
Input bias current
Open-drain low-level output voltage
I
V
CIN od
= 1 V
= 3 mA
Comparator delay
Slew rate
Shut down to high / low side driver propagation delay
Comparator triggering to high / low side driver turn-off propagation delay
SD/OD pulled to 5 V through
100 k
Ω
resistor
C
L
= 180 pF; R pu
= 5 k Ω
V
OUT
= 0, V boot
= V
CC
,
V
IN
= 0 to 3.3 V
Measured applying a voltage step from 0 V to 3.3 V to pin
CIN
-
-
-
50
50
90
60
125
200
0.5
130
200
250
V ns
V/µsec ns
Condition
Shutdown enable half-bridge tri-state
Interlocking half-bridge tri-state
0 ‘’logic state” half-bridge tri-state
1 “logic state” low side direct driving
1 “logic state” high side direct driving
Note: X: don’t care
SD/OD
L
H
H
H
H
Table 12. Truth table
Logic input (V
I
)
LIN HIN
X X
L
H
L
H
L
H
H
L
LVG
L
L
L
H
L
Output
HVG
L
L
L
L
H
10/20 DocID025060 Rev 3
STGIPS15C60 Electrical characteristics
Figure 5. Dead time and interlocking waveforms definition
LIN
CONTROL SIGNAL EDGES
OVERLAPPED:
INTERLOCKING + DEAD TIME
HIN
LVG
HVG gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DT LH gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
G
DT HL
CONTROL SIGNALS EDGES
SYNCHRONOUS (*):
DEAD TIME
LIN
HIN
LVG
HVG gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DT
LH gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DT
HL
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:
DEAD TIME
LIN
HIN
LVG
HVG gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DT
LH
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:
DIRECT DRIVING
LIN
HIN
LVG
HVG gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DT
LH gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DT
HL gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DT HL
DocID025060 Rev 3 11/20
20
Smart shutdown function
4 Smart shutdown function
STGIPS15C60
The STGIPS15C60 integrates a comparator for fault sensing purposes. The comparator has an internal voltage reference V ref connected to the inverting input, while the non-inverting input, available on pin (C
IN
), can be connected to an external shunt resistor in order to implement a simple over-current protection function. When the comparator triggers, the device is set in shutdown state and both its outputs are set to low-level leading the halfbridge in tri-state. In the common overcurrent protection architectures the comparator output is usually connected to the shutdown input through a RC network, in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition.
Our smart shutdown architecture allows to immediately turn-off the output gate driver in case of overcurrent, the fault signal has a preferential path which directly switches off the outputs. The time delay between the fault and the outputs turn-off is no more dependent on the RC values of the external network connected to the shutdown pin. At the same time the
DMOS connected to the open-drain output (pin SD/OD) is turned on by the internal logic which holds it on until the shutdown voltage is lower than the logic input lower threshold
(V il
). Finally the smart shutdown function provides the possibility to increase the real disable time without increasing the constant time of the external RC network.
12/20 DocID025060 Rev 3
STGIPS15C60 Smart shutdown function comp Vref
Figure 6. Smart shutdown timing waveforms
CP+
HIN/LIN
HVG/LVG
SD/OD
PROTECTION open drain gate
(internal) disable time
Fast shut down
: the driver outputs are set in SD state immediately after the comparator triggering even if the SD signal has not yet reach the lower input threshold
An approximation of the disable time is given by:
V
BIAS
SHUT DOWN CIRCUIT
FROM/TO
CONTROLLER
R
SD
SD/OD
C
SD
R
ON_OD
R
PD_SD
SMART
SD
LOGIC where:
AM12947v1
Please refer to Table 11 for internal propagation delay time details.
DocID025060 Rev 3 13/20
20
Application information
Figure 7. Typical application circuit
STGIPS15C60
14/20
CONTROLLER
DocID025060 Rev 3
AM05001v2
STGIPS15C60 Application information
5.1 Recommendations
•
Input signal HIN is active high logic. A 85 k
Ω
(typ.) pull down resistor is built-in for each high side input. If an external RC filter is used, for noise immunity, pay attention to the variation of the input signal level.
• Input signal LIN is active low logic. A 720 k Ω (typ.) pull-up resistor, connected to an internal 5 V regulator through a diode, is built-in for each low side input.
•
To prevent the input signals oscillation, the wiring of each input should be as short as possible.
•
By integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler is possible.
• Each capacitor should be located as nearby the pins of IPM as possible.
•
Low inductance shunt resistors should be used for phase leg current sensing.
•
Electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. Additional high frequency ceramic capacitor mounted close to the module pins will further improve performance.
• The SD/OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see
Section 4: Smart shutdown function for detailed info).
Symbol
V
PN
V
CC
V
BS t dead f
PWM
T
C
Table 13. Recommended operating conditions
Value
Parameter Conditions
Supply Voltage
Blanking time to prevent Arm-short
Applied between P-Nu,Nv,Nw
Control supply voltage Applied between V
CC
-GND
High side bias voltage
Applied between V
BOOTi
-OUT i
for i=U,V,W
For each input signal
PWM input signal
-40°C < T c
< 100°C
-40°C < T j
< 125°C
Case operation temperature
Min.
Typ.
Max.
300 400
13.5
15 18
13
1.5
18
20
100
Unit
V
V
V
µs kHz
°C
Note: For further details refer to AN3338.
DocID025060 Rev 3 15/20
20
Package information STGIPS15C60
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
Please refer to dedicated technical note TN0107 for mounting instructions.
Figure 8. SDIP-25L package outline
16/20 DocID025060 Rev 3
B
STGIPS15C60
Dim.
F
F1
R
T
V
D1
E
E1
C3 e e1 e2 e3
D
B
B1
B2
C
C1
C2
A
A1
A2
A3
Package information
0.85
0.35
1.55
0.45
0°
Table 14. SDIP-25L mechanical data mm
Min.
43.90
1.15
1.40
38.90
21.50
11.25
24.83
5.00
6.50
11.20
2.90
2.15
3.40
4.50
6.30
Typ.
5.55
11.20
1.40
1.00
0.50
1.75
0.55
3.00
2.35
3.60
4.70
6.50
33.30
44.40
1.35
1.60
39.40
22.00
11.85
25.23
5.40
7.00
11.70
Max.
44.90
1.55
1.80
39.90
22.50
12.45
25.63
6.00
7.50
12.20
3.10
2.55
3.80
4.90
6.70
1.15
0.65
1.95
0.65
6°
DocID025060 Rev 3 17/20
20
Package information
Figure 9. SDIP-25L packing information
STGIPS15C60
18/20 DocID025060 Rev 3
STGIPS15C60 Revision history
Date
19-Aug-2013
16-May-2014
09-Apr-2015
Table 15. Document revision history
Revision Changes
1
2
3
Initial release.
Updated
,
,
and Section 6.2: Packing information .
Minor text changes.
Text edits and formatting changes throughout document
Updated
Figure 2: Pin layout (bottom view)
Updated
Section 6: Package information
DocID025060 Rev 3 19/20
20
STGIPS15C60
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
20/20 DocID025060 Rev 3
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