STMicroelectronics STDRIVE601 Datasheet
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STDRIVE601
Datasheet
Triple half-bridge high-voltage gate driver
SO-28
Product status link
STDRIVE601
Order code
Package
Packing
Product summary
STDRIVE601 STDRIVE601TR
SO-28
Tube Tape & Reel
Product label
Features
• High voltage rail up to 600 V
• Driver current capability:
– 200 mA source current @ 25 °C
– 350 mA sink current @ 25 °C
• dV/dt transient immunity ±50 V/ns
• Gate driving voltage range from 9 V to 20 V
• Overall input-output propagation delay: 85 ns
• Matched propagation delay for all channels
• 3.3 V, 5 V TTL/CMOS inputs with hysteresis
• Integrated bootstrap diodes
• Comparator for fast overcurrent protection
• Smart shutdown function
• Interlocking and deadtime function
• Dedicated Enable pin
• UVLO function on low-side and high-sides
Applications
• 3-phase motor drives
• Inverters
Description
The STDRIVE601 is a high voltage device manufactured with BCD6s offline technology. It is a single-chip with three half-bridge gate drivers for N-channel power
MOSFETs or IGBTs suitable for 3-phase applications.
All device outputs can sink and source 350 mA and 200 mA respectively. Prevention from cross conduction is ensured by interlocking and deadtime function.
The device has dedicated input pins for each output and a shutdown pin. The logic inputs are CMOS/TTL compatible down to 3.3 V for easy interfacing with control devices. Matched delays between low-side and high-side sections guarantee no cycle distortion and allow high frequency operation.
The STDRIVE601 embeds a comparator featuring advanced SmartSD function also integrated in the device, ensuring fast and effective protection against fault events like overcurrent, overtemperature, etc.
Dedicated UVLO protection on the low-sides and each of the high-side driving sections allow to prevent the power switches from operating in low efficiency or dangerous conditions.
The integrated bootstrap diodes as well as all of the integrated features of this IC make the application PCB design easier, more compact and simpler, thus reducing the overall bill of material.
The device is available in SO-28 package.
DS12949 - Rev 2 - April 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
STDRIVE601
Block diagram
Block diagram
VCC
+5V
HIN1
+5V
HIN2
+5V
HlN3
LIN1
+5V
LIN2
+5V
Figure 1. Block diagram
VCC
D1
VCC UVLO
DETECTION
VCC UVLO
Input noise filter
VBO UVLO &
Level Shifter
Floating structure
VCC
D2
Input noise filter
Input noise filter
Input noise filter
LOGIC
SHOOT
THROUGH
PREVENTION
DEADTIME
VBO UVLO &
Level Shifter
Floating structure
D3
VCC
VBO UVLO &
Level Shifter
Floating structure
VCC
Input noise filter
+5V
VCC
LlN3
EN
Input noise filter
EN Input noise filter
VCC
FAULT
VCC UVLO
+5V
I
OD
OD
SMART
SD
CIN
+
V
REF
-
+
+5V
Comparator input filter
SGND
BOOT1
HVG1
OUT1
BOOT2
HVG2
OUT2
BOOT3
HVG3
OUT3
LVG1
LVG2
LVG3
PGND
DS12949 - Rev 2 page 2/26
2
STDRIVE601
Pin description and connection diagram
Pin description and connection diagram
3
4
5
6
1
2
7
8
9
10
11
12
13
14
FAULT
CIN
EN
OD
SGND
PGND
LVG3
VCC
HIN1
HIN2
HIN3
LIN1
LIN2
LIN3
Figure 2. Pin connection (top view)
BOOT1
HVG1
OUT1
NC
BOOT2
HVG2
OUT2
NC
BOOT3
HVG3
OUT3
NC
LVG1
LVG2
19
18
17
16
15
25
24
23
22
21
20
28
27
26
14
15
16
17, 21 25
18
19
20
22
Pin #
6
7
8
9
10
11
12
13
1
2
3
4
5
LVG3
LVG2
LVG1
N.C.
OUT3
BOOT3
OUT2
Pin Name
LIN2
LIN3
FAULT
CIN
EN
VCC
HIN1
HIN2
HIN3
LIN1
OD
SGND
PGND
Table 1. Pin description
Type Function
Power Supply Low-side and logic supply voltage
Logic Input
Logic Input
High-side driver logic input 1
High-side driver logic input 2
Logic Input
Logic Input
High-side driver logic input 3
Low-side driver logic input 1
Logic Input
Logic Input
OD Output
Analog Input
Logic Input
Low-side driver logic input 2
Low-side driver logic input 3
Fault output
Comparator positive input
Enable input, active high
OD Output SmartSD timing Open Drain output, unlatch and restart input
Power Supply Signal ground
Power Supply Low-side driver ground
Analog Output Low-side driver output 3
Analog Output Low-side driver output 2
Analog Output Low-side driver output 1
Not Connected
Power Supply High-side (floating) common voltage driver 3
Analog Output High-side driver output 3
Power Supply Bootstrap supply voltage 3
Power Supply High-side (floating) common voltage driver 2
DS12949 - Rev 2 page 3/26
STDRIVE601
Pin description and connection diagram
Pin #
23
24
26
27
28
Pin Name
BOOT2
OUT1
BOOT1
Type
Analog Output High-side driver output 2
Function
Power Supply Bootstrap supply voltage 2
Power Supply High-side (floating) common voltage driver 1
Analog Output High-side driver output 1
Power Supply Bootstrap supply voltage 1
1. The circuit guarantees less than 1 V on the LVG and HVG pins (at Isink = 10 mA), with VCC > 3 V. This allows omitting the
“bleeder” resistor connected between the gate and the source of the external MOSFETs normally used to hold the pin low.
DS12949 - Rev 2 page 4/26
3
3.1
3.2
STDRIVE601
Electrical data
Electrical data
Absolute maximum ratings
Table 2. Absolute maximum ratings
Note: Each voltage referred to SGND unless otherwise specified.
Symbol Parameter Min.
VCC
V
PGND
V
PS
V
OUT
V
BOOT
V
HVG
V
LVG
V
CIN
V i
V
OD
V
FAULT dV
OUT
/dt
T
J
T
S
ESD
Logic supply voltage
Low-side driver ground
Low-side drivers ground
Output voltage
Bootstrap voltage
High-side gate output voltage
Low-side gate output voltage
Comparator input voltage
Logic input voltage
OD pin voltage
FAULT pin voltage
Common mode transient Immunity
Junction temperature
Storage temperature
Human body model
-0.3
VCC - 21
-21
V
BOOT
- 21
- 0.3
V
OUT
- 0.3
V
PGND
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
-40
-50
1. V
PS
= PGND - SGND.
2. EN, LINx, HINx.
3. Pins 18 to 28 have HBM ESD rating 1C conforming to ANSI/ESDA/JEDEC JS-001-2014.
50
150
150
20
15
21
21
Max.
21
VCC + 0.3
21
V
BOOT
+ 0.3
620
V
BOOT
+ 0.3
VCC + 0.3
Thermal data
Symbol
R th(JA)
1. JEDEC 2s2p PCB in still air.
Table 3. Thermal data
Parameter
Thermal resistance junction to ambient
Value
52
Unit
°C/W
V
V
V
V
V
V
V
V/ns
°C
°C kV
Unit
V
V
V
V
DS12949 - Rev 2 page 5/26
3.3
STDRIVE601
Recommended operating conditions
Recommended operating conditions
Table 4. Recommended operating conditions
Note: Each voltage referred to SGND unless otherwise specified.
Symbol Parameter Test conditions
Logic supply voltage VCC
V
LS
V
PS
V
BO
V
OUT
V
CIN
V i
V
OD
V
FAULT
F
SW
PW
T
J
Low-side drivers supply voltage
Low-side drivers ground
DC Output voltage
Comparator input voltage
Logic input voltage
OD pin voltage
FAULT pin voltage
Maximum switching frequency
Minimum input pulse width
Junction temperature -
-
-
-
-
-
-
-
-
-
-
1. V
LS
= VCC - PGND
2. V
PS
= PGND - SGND.
3. V
BO
= BOOT - OUT.
4. VCC = 9 V, LVG off. Logic is operational if V
BOOT
> 5 V.
5. Actual maximum F
SW
depends on power dissipation.
6. Pulse width on LIN or HIN pins. See
Figure 3. Propagation delay timing definition .
8.5
0
0
0
0
Min.
9
4
-5
-
100
-40
V
V
V
V
V kHz ns
°C
Unit
V
V
V
V
580
15
15
20
20
800
-
125
Max.
20
20
5
20
DS12949 - Rev 2 page 6/26
4
DS12949 - Rev 2
STDRIVE601
Electrical characteristics
Electrical characteristics
Table 5. Electrical characteristics
Note: VCC = 15 V; PGND = SGND; T
J
= +25 °C, unless otherwise specified. HIN is referred to channels HIN1, HIN2,
HIN3; LIN is referred to channels LIN1, LIN2, LIN3.
Symbol Pin Parameter Test conditions Min. Typ. Max. Unit
Low-side section supply
VCC
THON
VCC UVLO turn-on threshold
VCC
THOFF
VCC
HYS
VCC UVLO turn-off threshold
-
VCC UVLO hysteresis
I
QCCU
VCC undervoltage quiescent supply current
I
QCC
VCC quiescent supply current
-
-
-
VCC = 7 V; EN = 5 V; CIN = SGND
LVG & HVG: OFF
EN = 5 V; CIN = SGND
LVG & HVG: OFF
8 8.5
7.5
8
9 V
8.5
V
0.4
0.5
0.6
V
430 744 μA
950 1450 μA
High-side floating section supply
V
BOTHON
V
BOTHOFF
V
BOHYS
I
QBOU
20 - 18
24 - 22
28 - 26
V
V
V
V
BO
BO
BO
BO
UVLO turn-on threshold
UVLO turn-off threshold
UVLO hysteresis
undervoltage quiescent supply current
-
-
7.5
8
7 7.5
0.4
0.5
0.6
V
-
8.5
V
8 V
25 62 μA
I
QBO
I
LK
-
V
BO quiescent supply current
High voltage leakage current
R
Dboot
-
Output driving buffers
Bootstrap Diode on resistance
VCC = V
BO
= 6.5 V; EN = 5 V;
CIN = SGND
LVG OFF; HVG = ON
-
VBO = 15 V EN = 5 V; CIN = SGND
LVG OFF; HVG = ON
BOOT = HVG = OUT
= 620V
-
-
84 150 μA
15 μA
215 Ω
I
SO
High/Low-side source peak current
T
J
= 25°C
T
J
= 25°C
I = 10 mA
160 200 300 mA
130 350
230 350 430 mA
200 500
24 35 46
-
-
Ω
I
SI
R
DSonON
R
DSonOFF
Logic Inputs
14, 15,
16, 19,
23, 27
High/Low-side sink peak current
High/Low-side source RDSon
High/Low-side sink RDSon
V il
V
V
V
V ih hyst
SSDh
SSDl
I
LINh
I
LINl
2, 3, 4,
5, 6, 7,
10
Low level logic threshold voltag
High level logic threshold voltage
2, 3, 4,
5, 6, 7,
10
Logic input threshold hysteresis
SmartSD restart threshold
11
SmartSD unlatch threshold
5, 6, 7
LIN logic “1” input bias current
LIN logic “0” input bias current
-
-
-
-
-
I = 10 mA
V
LINx
= 15 V
V
LINx
= 0 V
11 16 21
0.8
1.8
0.8
-
-
-
-
3.5
4
Ω
1.4
V
2.3
V
1.2
V
4.3
V
0.56 0.75
V
1 μA
28 43 58 μA page 7/26
DS12949 - Rev 2
STDRIVE601
Electrical characteristics
Symbol Pin Parameter Test conditions
I
HINh
I
HINl
2, 3, 4
HIN logic “1” input bias current
HIN logic “0” input bias current
V
HINx
= 15 V
V
HINx
= 0
R t t t
PU_IN
OD
CIN-F
CINoff
2, 3, 4,
5, 6, 7
Logic input pull-up resistor
8
8
11
11
11
FAULT ON resistance
FAULT low level sink current
Comparator propagation delay
Comparator triggering to FAULT
Comparator triggering to high/lowside driver propagation delay
-
I
ENh
I
ENl
R
PD_EN
10
10
EN logic “1” input bias current
EN logic "0" input bias current
EN pull-down resistor
Sense comparator
V
V
REF
C
INhyst
C
IN_PD
I
OD
R
ON_OD
I
OL_OD
I
SAT_OD
FLOAT_OD
-
9
9
11
11
11
11
11
Internal voltage reference
Comparator input hysteresis
-
V
EN
V
EN
= 15 V
= 0 V
Comparator input pull- down current V
CIN
= 1 V
OD internal current source
OD On resistance
OD low level sink current
OD saturation current
OD floating voltage level
I
-
-
-
OD
V
OD
V
OD
= 16 mA
= 400 mV
= 5 V
OD connected only to an external capacitance
R
ON_F
I
OL_F
I
FAULT
= 8 mA
V
FAULT
= 400 mV
Rpu = 100 kΩ to 5 V; voltage step on CIN = 0 to 3.3 V;
50% CIN to 90% OD voltage step on CIN = 0 to 3.3 V;
50% CIN to 90% FAULT voltage step on CIN = 0 to 3.3 V;
50% CIN to 90% LVG/HVG t
FCIN
11 Comparator input filter time -
SR 11 OD Slew rate
C
L
= 1 nF;
R pu
= 33 kΩ to 5 V;
90% to 10% OD
Dynamic characteristics t on
2 vs. 27 vs 23 vs 19
High/Low-side driver turn-on propagation delay t t t off
EN
FIN
5 vs. 16
6 vs. 15
7 vs. 14
High/Low-side driver turn-off propagation delay
10 vs.
14, 15,
16, 19,
23, 27
2,3,4,
5,6,7
Enable to high/low- side driver propagation delay
LIN HIN input filter time t
FEN
10 EN input filter time -
-
OUT = 0 V BOOT = VCC C
Vin = 0 to 3.3 V
L
= 1 nF
Min. Typ. Max. Unit
1 μA
28 43 58 μA
75 100 125 kΩ
110 150 200 μA
1 μA
75 100 125 kΩ
410 460 510 mV
40 70
7 10
-
13 mV
μA
2.5
5 7.5
μA
-
4
19 25 36 Ω
11 16 21 mA
95 mA
4.4
4.8
5.2
V
-
-
50
8
350
350
100
12
500
500
Ω mA ns ns
360 510 ns
200 300 400 ns
20
45
45
245 385
30
60
85
85
40
200 300
100 V/μs
120
120
520
50
400 ns ns ns ns ns page 8/26
DS12949 - Rev 2
STDRIVE601
Electrical characteristics
Symbol t t r f
MT
Pin Parameter
14, 15,
16, 19,
23, 27
Rise time
Fall time
-
Delay matching high/low side turn-
-
C
C
L
L
= 1 nF
= 1 nF
Test conditions Min. Typ. Max. Unit
-
-
120
50
0
160
75
30 ns ns ns
DT
MDT -
Deadtime
Matching deadtime
C
L
= 1 nF
C
L
= 1 nF
200 300
-
1. V
BO
= BOOT - OUT.
2. Values provided by characterization, not tested.
3. Comparator is disabled when VCC is in UVLO condition.
4. MT = max. (|ton(LVG) - toff(LVG)|, |ton(HVG) - toff(HVG)|, |toff(LVG) - ton(HVG)|, |toff(HVG) - ton(LVG)|).
5. MDT = | DTLH - DTHL |, refer to Section 4 Electrical characteristics
0
400
50 ns ns
LIN
HIN
50% t > DT
Figure 3. Propagation delay timing definition
50% t > DT
50%
50%
50%
LVG
t on
10% t r
90% 90% t f t off
10%
HVG
t on
10% t r
90% t off
90% t f
10%
EN
LVG/HVG
50% t
EN
90%
50% t
EN
10% page 9/26
STDRIVE601
Electrical characteristics
Figure 4. Deadtime timing definitions t > DT
50%
LIN
50%
HIN
50%
HVG
LVG
t
90% t f off
10%
DT
LH
10% t r
90%
50%
90% t f t off
10%
DT
HL
10%
DS12949 - Rev 2 page 10/26
DS12949 - Rev 2
STDRIVE601
Electrical characteristics
CONTROL SIGNAL EDGES
OVERLAPPED FOR
MORE THAN DEAD TIME:
INTERLOCKING
Figure 5. Deadtime and interlocking waveforms definition
LIN
INTERLOCKING
HIN
LVG
HVG gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DT
LH gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
INTERLOCKING
DT
HL
LIN
CONTROL SIGNAL EDGES
OVERLAPPED:
INTERLOCKING + DEAD TIME
HIN
LVG
HVG gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
INTERLOCKING
DT
LH gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
INTERLOCKING
DT
HL
CONTROL SIGNALS EDGES
SYNCHRONOUS (*):
DEAD TIME
LIN
HIN
LVG
HVG gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DT
LH gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DT
HL
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:
DEAD TIME
LIN
HIN
LVG
HVG gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DT
LH
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:
DIRECT DRIVING
LIN
HIN
LVG
HVG gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DT
LH gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DT
HL gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
DT
HL page 11/26
5
5.1
5.2
5.3
STDRIVE601
Functional description
Functional description
Inputs and outputs
•
•
The devices are controlled through the following logic inputs:
• EN: Enable input, active high;
LIN: low-side driver inputs, active low;
HIN: high-side driver inputs, active low.
Table 6. Inputs truth table
Note: Applicable when device is not in UVLO or SmartSD protection
Input pins
EN
L
H
H
H
LIN
X
H
L
H
HIN
X
H
H
L
LVG
Low
Low
High
Low
Interlocking
H L L Low
Output pins
HVG
Low
Low
Low
High
Low
The FAULT and OD pins are open-drain outputs.
The FAULT signal is set low in case VCC UVLO is detected, or in case the SmartShutDown comparator triggers an event. It is only used to signal a UVLO or SmartSD activation to external circuits, and its state does not affect the behavior of other functions or circuits inside the driver. The OD behavior is explained in
Section 5.5 Comparator and smart shutdown
.
When EN is set low, gate driver outputs are forced low and assure low impedance.
Deadtime
The deadtime feature, in companion with interlocking feature, guarantees that driver outputs of the same channel are not high simultaneously and at least a DT time passes between the turn-off of one driver's output and the turn-on of the companion output of the same channel. If a deadtime longer than the internal DT is applied to
LIN and HIN inputs by the external controller, the internal DT is ignored, and the outputs follow the deadtime determined by the inputs.
Refer to
Figure 4. Deadtime timing definitions for the dead time and interlocking waveforms.
VCC UVLO protection
Undervoltage protection is available on VCC and BOOT supply pins. In order to avoid intermittent operation, a hysteresis set the turn-off threshold with respect to the turn-on threshold.
When VCC voltage goes below VCC
THOFF
threshold all the outputs are switched off, both LVG and HVG. When
VCC voltage reaches VCC
THON
threshold the driver returns to normal operation and sets the LVG outputs according to actual input pins status; HVG is also set according to input pin status if the corresponding V
BO section is not in UVLO condition.
The FAULT output is kept low when VCC is in UVLO condition. The following figures show some examples of typical operation conditions.
DS12949 - Rev 2 page 12/26
5.4
STDRIVE601
VBO UVLO protection
Figure 6. VCC power ON and UVLO, LVG timing
Fault pin connected to external pull-up.
VCC
FAULT
UVLO VCC
LIN
V
CCthON
V
CCthOFF
0 V
0 V
0 V
LVG
Figure 7. VCC power ON and UVLO, HVG timing
Fault pin connected to external pull-up.
0 V
VCC
FAULT
V
CCthON
V
CCthOFF
0 V
0 V
UVLO VCC
HIN
0 V
V
BOthON
V
BOthOFF
0 V
V
BO
HVG-OUT
VBO UVLO protection
Dedicated undervoltage protection is available on each bootstrap section between BOOTx and OUTx supply pins. In order to avoid intermittent operation, a hysteresis sets the turn-off threshold with respect to the turn-on threshold.
When V
BO
voltage goes below V switched off. When V
BO
BOTHOFF
threshold, the HVG output of corresponding bootstrap section is
voltage reaches V
BOTHON
threshold device returns to normal operation and the output remains off up to the next input pins transition that requests HVG to turn on.
DS12949 - Rev 2 page 13/26
5.5
STDRIVE601
Comparator and smart shutdown
Figure 8. V
BO
power-ON and UVLO timing
VCC
FAULT
V
CCthON
V
CCthOFF
0 V
0 V
HIN
0 V
V
BOthON
V
BOthOFF
0 V V
BO
HVG-OUT
0 V
Comparator and smart shutdown
This device integrates a comparator committed to the fault protection function, thanks to the SmartShutDown
(SmartSD) circuit.
The SmartSD architecture allows immediate turn-off of the gate driver outputs in the case of overload or overcurrent condition, by minimizing the propagation delay between the fault detection event and the actual output switch-off. In fact, the time delay between the fault detection and the output turn-off is not dependent on the value of the external components connected to the OD pin, which are only used to set the duration of disable time after the fault.
This provides the possibility to increase the duration of the output disable time after the fault event up to very large values without increasing the delay time of the protection. The duration of the disable time is determined by the values of the external capacitor C
OD
and of the optional pull-up resistor connected to OD pin.
The comparator has an internal voltage reference V
REF
connected to the inverting input, while the non-inverting input is available on the CIN pin. The comparator CIN input can be connected to an external shunt resistor in order to implement a fast and simple overcurrent protection function. The output signal of the comparator is filtered from glitches shorter than t
FCIN
and then fed to the SmartSD logic.
If the impulse on CIN pin is higher than V
REF
and wider than t
FCIN
, the SmartSD logic is triggered and immediately sets all of the driver outputs to low-level (OFF).
At the same time, FAULT is forced low to signal the event (for example to an MCU input) and OD starts to discharge the external C
OD
capacitor used to set the duration of the output disable time of the fault event.
The FAULT pin is released and driver outputs restart following the input pins as soon as the output disable time expires.
The overall disable time is composed of two phases:
•
•
The OD unlatch time (t
1
in
Figure 9. Smart shutdown timing waveforms ), which is the time required to
discharge C
OD
capacitor down to V
SSDl
threshold. The discharge starts as soon as the SmartSD comparator is triggered.
The OD restart time (t
2
in Figure 9. Smart shutdown timing waveforms , which is the time required to
recharge the C
OD
capacitor up to the V
SSDh
threshold. The recharge of C
OD
starts when the OD internal
MOSFET is turned-off, which happens when the fault condition has been removed (CIN < V
REF
- C
INhyst
) and the voltage on OD reaches the V
SSDl
threshold. This time normally covers most of the overall output disable time.
DS12949 - Rev 2 page 14/26
STDRIVE601
Comparator and smart shutdown
If no external pull-up is connected to OD, the external C
OD
capacitor is discharged with a time constant defined by
C
OD
and the internal MOSFET's characteristic ( Eq. (1) ), and the
Restart time is determined by the internal current source I
OD
and by C
OD
t1 ≅ RON_OD ⋅ COD ⋅ ln t2 ≅
COD ⋅ VSSDℎ
IOD
⋅ ln
VOD
VSSDl
VSSDl − VOD
VSSDℎ − VOD
In case the OD pin is connected to VCC by an external pull-up resistor R
OD_ext
, the OD discharge time is determined by the external network R
OD_ext
C
OD
and by the internal MOSFET's R
ON_OD
(
), while the
Restart time is determined by current in R
OD_ext
(
).
(1)
(2) t1 ≅ COD ⋅ ROD_ext//RON_OD ⋅ ln t1 ≅ COD ⋅ ROD_ext ⋅ ln
VOD − Von
VSSDl − Von
VSSDl − VOD
VSSDℎ − VOD
(3)
(4)
Where:
Von =
RON_OD
RON_ext + RON_OD; VOD = VCC
DS12949 - Rev 2 page 15/26
DS12949 - Rev 2
Figure 9. Smart shutdown timing waveforms
STDRIVE601
Comparator and smart shutdown
V
REF
CIN t
FCIN
LVG/HVG
OD
OD gate
(internal)
V
OD
V
SSDh
V
SSDl
1 t
FCIN t
CINoff
Fast shut down the driver outputs are switched off immediately after the comparator triggering t
1 disable time t
2
2
FAULT
I OD
5 V
C
OD
OD
R
ON_OD
SMART SHUTDOWN CIRCUIT
SMART
SD
LOGIC
VCC
R
OD_ext
OD
C
OD
R
ON_OD external pull-up
I OD
5 V
SMART
SD
LOGIC page 16/26
6
STDRIVE601
Typical application diagram
Typical application diagram
Figure 10. Typical application diagram
VCC
D1
V
CC
+
VCC
C VCC1
+5V
HIN1
+5V
VCC UVLO
DETECTION
VCC UVLO
Input noise filter
VBO UVLO &
Level Shifter
Floating structure
D2
VCC
FROM CONTROLLER
FROM CONTROLLER
HIN
LIN
HIN2
+5V
HlN3
+5V
LIN1
+5V
Input noise filter
Input noise filter
Input noise filter
3x Half-Bridge Inputs
LIN2
+5V
Input noise filter
LlN3
VDD
TO
CONTROLLER
R FAULT
FROM
CONTROLLER
C
SD
Vcc
R
OD
EN
FAULT
OD
I OD
C OD
CIN
C LP
R LP
SGND
Input noise filter
EN input noise filter
VCC UVLO
+
V
REF
-
+
+5V
Comparator input filter
SMART
SD
LOGIC
SHOOT
THROUGH
PREVENTION
DEADTIME
VBO UVLO &
Level Shifter
Floating structure
VCC
D3
VBO UVLO &
Level Shifter
Floating structure
VCC
VCC
VCC
BOOT1
HVG1
OUT1
BOOT2
HVG2
OUT2
BOOT3
HVG3
OUT3
LVG1
LVG2
LVG3
PGND
V CC
C
VCC2
BOOT
HVG
C
BOOT
R GH_ON
D H R GH_OFF
OUT
HS
LVG
R
GL_ON
D L R GL_OFF
LS
3x Power Half-Bridge
R S
HV
IGBT
IGBT
+
C HV
THREE-PHASE
MOTOR
M
DS12949 - Rev 2 page 17/26
7
7.1
STDRIVE601
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
SO-28 package information
Dim.
e
H h
D
E
A
A1
B
C
L k ddd
-
10.00
0.25
0.40
0°
-
Min.
2.35
0.10
0.33
0.23
17.70
7.40
Table 7. SO-28 package dimensions
Mm
-
-
-
1.27
-
-
Typ.
-
-
-
-
-
-
-
10.65
0.75
1.27
8°
0.10
Max.
2.65
0.30
0.51
0.32
18.10
7.60
DS12949 - Rev 2 page 18/26
DS12949 - Rev 2
28
D
Figure 11. SO-28 mechanical data
STDRIVE601
SO-28 package information
hx45°
B
15
SEATING
PLANE
1
L e
14 page 19/26
DS12949 - Rev 2
Figure 12. SO-28 suggested land pattern
11.50
2.00
STDRIVE601
SO-28 package information
7.50
page 20/26
STDRIVE601
Ordering information
8
Ordering information
Order code
STDRIVE601
STDRIVE601TR
Package
SO-28
SO-28
Table 8. Order codes
Package marking
STDRV601
STDRV601
Packaging
Tube
Tape and reel
DS12949 - Rev 2 page 21/26
Revision history
Date
21-May-2019
02-Apr-2021
Revision
1
2
Table 9. Document history
Changes
Initial release.
Throughout document:
- updated template
- minor text edits
In Table 2. Absolute maximum ratings :
- updated ESD value and added footnote
In Table 5. Electrical characteristics
:
- updated V
SSDh
Typ. and Max. values
- updated V
FLOAT_OD
Min., Typ., and Max. values
STDRIVE601
DS12949 - Rev 2 page 22/26
STDRIVE601
Contents
Contents
DS12949 - Rev 2 page 23/26
STDRIVE601
List of figures
List of figures
DS12949 - Rev 2 page 24/26
STDRIVE601
List of tables
List of tables
DS12949 - Rev 2 page 25/26
STDRIVE601
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS12949 - Rev 2 page 26/26
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