STMicroelectronics STP80N240K6 Datasheet
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STP80N240K6
Datasheet
N-channel 800 V, 197 mΩ typ., 16 A MDmesh K6
Power MOSFET in a TO-220 package
G(1)
TAB
TO-220
1
2
3
D(2, TAB)
S(3)
Features
Order code
STP80N240K6
V
DS
800 V
• Worldwide best R
DS(on)
x area
• Worldwide best FOM (figure of merit)
• Ultra low gate charge
• 100% avalanche tested
• Zener-protected
R
DS(on)
max.
220 mΩ
I
D
16 A
Applications
• Recommended for flyback topology, based applications such as LED lighting, chargers and adapters. Provide more power density reducing both BOM cost and size of the board.
AM01476v1_tab
Description
This very high voltage N-channel Power MOSFET is designed using the ultimate
MDmesh K6 technology based on 20 years STMicroelectronics experience on super junction technology. The result is the best-in-class on-resistance per area and gate charge for applications requiring superior power density and high efficiency.
Product status link
STP80N240K6
Product summary
Order code
Marking
Package
Packing
STP80N240K6
80N240K6
TO-220
Tube
DS13772 - Rev 1 - June 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
STP80N240K6
Electrical ratings
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
GS
I
D
I
D
I
DM
P
TOT dv/dt
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Parameter
Total power dissipation at T
C
= 25 °C
Peak diode recovery voltage slope dv/dt
dv/dt
T stg
T
J
Peak diode recovery current slope
MOSFET dv/dt ruggedness
Storage temperature range
Operating junction temperature range
1. Pulse width limited by safe operating area.
2. I
SD
≤ 4 A; V
DS
(peak) = 400 V
3. V
DS
≤ 640 V
Symbol
R thJC
R thJA
Table 2. Thermal data
Parameter
Thermal resistance, junction-to-case
Thermal resistance, junction-to-ambient
Symbol
I
AR
E
AS
Table 3. Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive (pulse width limited by T
J
max.)
Single pulse avalanche energy (starting T
J
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Value
±30
16
10
35
140
5
100
120
-55 to 150
Unit
V
A
A
A
W
V/ns
A/µs
V/ns
°C
Value
0.89
62.5
Value
3.3
200
Unit
°C/W
°C/W
Unit
A mJ
DS13772 - Rev 1 page 2/13
2
STP80N240K6
Electrical characteristics
Electrical characteristics
T
C
= 25 °C unless otherwise specified.
Table 4. On/off-state
Symbol
V
(BR)DSS
I
DSS
Parameter
I
GSS
V
GS(th)
R
DS(on)
1. Defined by design, not subject to production test.
Test conditions
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 800 V
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 800 V, T
C
= 125 °C
Gate body leakage current
Gate threshold voltage
V
DS
= 0 V, V
GS
= ±20 V
V
DS
= V
GS
, I
D
= 100 µA
Static drain-source on-resistance V
GS
= 10 V, I
D
= 7 A
Min.
Typ.
Max.
Unit
800 V
1
50
µA
µA
3 3.5
±1
4
197 220
µA
V mΩ
Table 5. Dynamic
Symbol
C iss
C oss
Parameter
Input capacitance
Output capacitance
V
DS
Test conditions
= 100 V, f = 1 MHz, V
GS
= 0 V
Min.
-
-
Typ.
1350
22
Max.
-
-
Unit pF pF
C
C o(er) o(tr)
R g
Q g
Q gs
Q gd
Equivalent capacitance time related
Equivalent capacitance energy related
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V f = 1 MHz , I
V
DS
DD
= 0 to 640 V, V
(see
D
= 640 V, I
= 0 A
D
GS
= 0 V
= 7 A, V
GS
= 0 to 10 V
Figure 19. Test circuit for gate
-
-
-
-
-
-
25
139
1.8
25.9
6.9
8.4
-
-
-
-
-
pF pF
Ω nC nC nC
1. C o(er)
is a constant capacitance value that gives the same stored energy as C oss
while V
DS
is rising from 0 to 80% V
DSS
.
2. C o(tr)
is a constant capacitance value that gives the same stored energy as C oss
while V
DS
is rising from 0 to 80% V
DSS
.
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
V
DD
= 400 V, I
D
=7 A, R
G
= 4.7 Ω
V
GS
= 10 V see (
Figure 17. Test circuit for resistive load switching times and
Figure 18. Switching time waveform )
Min.
Typ.
Max.
Unit
16 ns
5.3
ns
-
47.8
12 -
ns ns
DS13772 - Rev 1 page 3/13
STP80N240K6
Electrical characteristics
Table 7. Source-drain diode
Symbol
I
SD
I
SDM
V
SD
t rr
Q rr
I
RRM t rr
I
Q rr
RRM
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
I
I
SD
SD
Test conditions
= 14 A, V
GS
= 0 V
= 14 A, di/dt = 100 A/µs, V
DD
(see
= 60 V
Figure 20. Test circuit for inductive load switching and diode recovery times
I
SD
= 14 A, di/dt = 100 A/µs, V
DD
= 60 V,
T
J
= 150 °C
(see
Figure 20. Test circuit for inductive load switching and diode recovery times )
-
-
-
-
-
Min.
Typ.
Max.
Unit
14 A
-
35
1.5
A
V
335
5.4
27.5
430
7.4
ns
µC
A ns
µC
28 A
DS13772 - Rev 1 page 4/13
STP80N240K6
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
I
D
(A)
Figure 1. Safe operating area
GADG250620210921SOA
I
DM
10 1
in
this area
R
DS(on)
max.
t p
=1μs t p
=10μs
V
(BR)DSS t p
=100μs
10 0
10 -1
10 -1 10 0
T
C
T
J
= 25 °C
≤ 150 °C single pulse
10 1 10 2 10 3 t p
=1ms t p
=10ms
V
DS
(V)
20
15
10
Figure 3. Typical output characteristics
I
D
(A)
30
V
GS
=7, 8, 9, 10 V
GADG240620211241OCH
25
V
GS
=6 V
5
0
0 4 8 12
V
GS
=5 V
16 V
DS
(V)
Figure 5. Typical gate charge characteristics
V
DS
(V)
600
500
400
300
Q gs
I
V
DD
D
GADG240620211243QVG
= 640 V
= 7 A
V
GS
(V)
12
Q g
V
GS
10
8
Q gd
6
200
100
0
0
V
DS
5 10 15 20 25 30
4
2
Q
0 g
(nC)
Figure 2. Maximum transient thermal impedance
GADG240620211255ZTH Z thJC
(°C/W) duty=0.5
10 -1
0.05
4
3
2
10 -2
Single pulse
R thJC
= 0.89 °C/W duty = t on
/ T t on
T
10 -3
10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 t p
(s)
20
15
10
Figure 4. Typical transfer characteristics
I
D
(A)
30
V
DS
= 20 V
GADG240620211242TCH
25
5
0
4 5 6 7 V
GS
(V)
Figure 6. Typical drain-source on-resistance
R
DS(on)
(mΩ)
GADG240620211242RID
V
GS
= 10 V
210
200
190
180
0 2 4 6 8 10 12 I
D
(A)
DS13772 - Rev 1 page 5/13
STP80N240K6
Electrical characteristics (curves)
Figure 7. Typical capacitance characteristics
C
(pF)
10 4
GADG240620211244CVR
10 3
C
ISS
10 2
10 1
10 0
10 -1
10 -2
10 -1 f = 1 MHz
10 0 10 1 10 2
C
OSS
C
RSS
V
DS
(V)
Figure 9. Normalized gate threshold vs temperature
V
GS(th)
(norm.)
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
-75
I
D
= 100 μA
-25 25
GADG240620211244VTH
75 125 T j
(°C)
Figure 8. Typical output capacitance stored energy
E
OSS
(µJ)
GADG240620211245EOS
6
4
2
0
0 100 200 300 400 500 600 700 V
DS
(V)
Figure 10. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
2.2
V
GS
= 10 V
GADG240620211243RON
1.8
1.4
1.0
0.6
0.2
-75 -25 25 75 125 T j
(°C)
Figure 11. Normalized breakdown voltage vs temperature
V
(BR)DSS
(norm.)
1.08
I
D
= 1 mA
GADG240620211245BDV
1.04
Figure 12. Typical reverse diode forward characteristics
V
SD
(V)
1.0
GADG240620211247SDF
T j
= -50 °C
0.9
1.00
0.8
T j
= 25 °C
0.96
0.7
T j
= 150 °C
0.92
0.88
-75 -25 25 75 125 T j
(°C)
0.6
0.5
2 4 6 8 10 12 14 I
SD
(A)
DS13772 - Rev 1 page 6/13
DS13772 - Rev 1
Figure 13. Maximum avalanche energy vs temperature
E
AS
(mJ)
200
GADG240620211246EAS
I
Single pulse
D
V
= 3.3 A
DD
=50 V
160
120
80
40
0
-75 -25 25 75 125 T
J
(°C)
STP80N240K6
Electrical characteristics (curves)
Figure 14. Typical output capacitance stored energy
E
OSS
(µJ)
GADG240620211245EOS
6
4
2
0
0 100 200 300 400 500 600 700 V
DS
(V)
Figure 15. Inductive load: energy losses vs I
D
E
(μJ)
GADG240620211251SLI
R
G
= 4.7 Ω
90
ON
60
30
OFF
0
0 3 6 9 12 I
D
(A)
Figure 16. Inductive load: energy losses vs Rg
E
(μJ)
GADG240620211252SLG
I
D
= 7 A
ON
120
80
OFF
40
0
0 9 18 27 36 45 R
G
(Ω) page 7/13
STP80N240K6
Test circuits
3
Test circuits
Figure 17. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF
D.U.T.
V
DD
AM01468v1
Figure 19. Test circuit for gate charge behavior
V
DD
RL
V
GS pulse width
2200
μF
+
1 kΩ
I
G
= CONST
2.7 kΩ
47 kΩ
100 Ω D.U.T.
V
G
AM01469v10
Figure 18. Switching time waveform
V
DS
90%
V
GS
10% t d(on) t r t d(off) t f
GADG280620211209SA
Figure 20. Test circuit for inductive load switching and diode recovery times
G
D
A
D.U.T.
S
B
25 Ω
+
_
R
G
A A fast diode
B
B
G
100 µH
D
D.U.T.
3.3
µF
S
+
1000
µF
V
DD
Figure 21. Unclamped inductive load test circuit
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF
V
DD
D.U.T.
AM01470v1
Figure 22. Unclamped inductive waveform
V
(BR)DSS
V
D
I
DM
I
D
V
DD
V
DD
AM01472v1
AM01471v1
DS13772 - Rev 1 page 8/13
4
4.1
STP80N240K6
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
TO-220 type A package information
Figure 23. TO-220 type A package outline
DS13772 - Rev 1
0015988_typeA_Rev_23 page 9/13
DS13772 - Rev 1
Dim.
H1
J1
L
L1
L20
L30
øP
Q
Slug flatness
D1
E e e1
F
A b b1 c
D
STP80N240K6
TO-220 type A package information
Table 8. TO-220 type A package mechanical data mm
Typ.
Min.
4.40
0.61
1.14
0.48
15.25
1.27
10.00
2.40
4.95
1.23
6.20
2.40
13.00
3.50
16.40
28.90
3.75
2.65
0.03
3.85
2.95
0.10
Max.
4.60
0.88
1.55
0.70
15.75
10.40
2.70
5.15
1.32
6.60
2.72
14.00
3.93
page 10/13
STP80N240K6
Revision history
Date
30-Jun-2021
Table 9. Document revision history
Revision
1 Initial release.
Changes
DS13772 - Rev 1 page 11/13
STP80N240K6
Contents
Contents
DS13772 - Rev 1 page 12/13
STP80N240K6
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DS13772 - Rev 1 page 13/13
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