STL34N65M5
*
6
6
6
N-channel 650 V, 0.099
Ω
typ., 22.5 A MDmesh™ V
Power MOSFET in PowerFLAT™ 8x8 HV package
Datasheet
-
production data
%RWWRPYLHZ
'
3RZHU)/$7[+9
Features
Order code
STL34N65M5
V
DS
@
T
Jmax
710 V
R
DS(on) max
I
D
0.120 Ω 22.5 A
(1)
1.
The value is rated according to R package.
thj-case and limited by
• 100% avalanche tested
• Low input capacitance and gate charge
• Low gate input resistance
Figure 1. Internal schematic diagram
Applications
•
Switching applications
*
Order code
STL34N65M5
'
6
$0Y
Description
This device is an N-channel MDmesh™ V Power
MOSFET based on an innovative proprietary vertical process technology, which is combined with STMicroelectronics’ well-known
PowerMESH™ horizontal layout structure. The resulting product has extremely low onresistance, which is unmatched among siliconbased Power MOSFETs, making it especially suitable for applications which require superior power density and outstanding efficiency.
Table 1. Device summary
Marking Package
34N65M5 PowerFLAT™ 8x8 HV
Packaging
Tape and reel
April 2014
This is information on a product in full production.
DocID023325 Rev 1 1/15 www.st.com
5
6
3
4
1
2
Contents
Contents
STL34N65M5
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/15 DocID023325 Rev 1
STL34N65M5 Electrical ratings
Symbol
Table 2. Absolute maximum ratings
Parameter
V
DS
V
GS
I
D
(1)
I
D
(1)
I
DM
(1),(2)
I
D
(3)
I
D
(3)
P
TOT
(3)
P
TOT
(1)
I
E
AR
AS dv/dt
(4)
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
C
Drain current (continuous) at T
C
Drain current (pulsed)
Drain current (continuous) at T
= 25 °C
= 100 °C amb
= 25 °C
Drain current (continuous) at T amb
= 100 °C
Total dissipation at T amb
= 25 °C
Total dissipation at T
C
= 25 °C
Avalanche current, repetitive or notrepetitive (pulse width limited by T j
max)
Single pulse avalanche energy
(starting T j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Peak diode recovery voltage slope
T stg
T j
Storage temperature
Max. operating junction temperature
1.
The value is rated according to R thj-case and limited by package.
2.
Pulse width limited by safe operating area.
3.
When mounted on FR-4 board of inch², 2oz Cu.
4.
I
SD
≤
22.5 A, di/dt
≤
400 A/µs, V
DS(peak)
< V
(BR)DSS,
V
DD
= 400 V.
Value
6
510
15
- 55 to 150
150
650
± 25
22.5
15
90
3.2
2
2.8
150
Symbol
Table 3. Thermal data
Parameter
R thj-case
R thj-amb
(1)
Thermal resistance junction-case max
Thermal resistance junction-ambient max
1.
When mounted on FR-4 board of inch², 2oz Cu.
Value
0.83
45
Unit
°C/W
°C/W mJ
V/ns
°C
°C
Unit
A
A
A
V
V
A
A
W
W
A
DocID023325 Rev 1 3/15
15
Electrical characteristics STL34N65M5
(T
C
= 25 °C unless otherwise specified)
Symbol Parameter
Table 4. On /off states
Test conditions
V
(BR)DSS
V
R
I
I
DSS
GSS
GS(th)
DS(on)
Drain-source breakdown voltage
I
D
= 1 mA, V
GS
= 0
Zero gate voltage drain current (V
GS
= 0)
V
DS
= 650 V
V
DS
= 650 V, T
C
=125 °C
Gate-body leakage current (V
DS
= 0)
V
GS
= ± 25 V
Gate threshold voltage V
DS
= V
GS
, I
D
= 250 µA
Static drain-source on- resistance
V
GS
= 10 V, I
D
= 12 A
Min.
Typ.
Max.
Unit
650
3
1
100
±100 nA
V
µA
µA
4 5 V
0.099
0.120
Ω
Symbol Parameter
Table 5. Dynamic
Test conditions Min.
Typ.
Max.
Unit
C
C
C iss oss rss
Input capacitance
Output capacitance
Reverse transfer capacitance
V
V
DS
GS
= 100 V, f = 1 MHz,
= 0
-
-
-
2700
75
6.3
-
-
pF pF pF
C
C o(er)
(1) o(tr)
(2)
Equivalent output capacitance energy related
Equivalent output capacitance time related
V
V
GS
DS
= 0,
= 0 to 80% V
(BR)DSS
-
63
220 -
pF pF
R
G
Intrinsic gate resistance f = 1 MHz open drain 1.95
Ω
Q g
Q gs
Q gd
Total gate charge
Gate-source charge
Gate-drain charge
V
DD
V
GS
= 520 V, I
= 10 V
(see
Figure 15
D
)
= 14 A,
-
-
62.5
17
28 -
-
nC nC nC
1.
C o(er) is a constant capacitance value that gives the same stored energy as C oss to 80% V
DSS
while V
DS
is rising from 0
2.
C o(tr) is a constant capacitance value that gives the same charging time as C oss to 80% V
DSS
while V
DS
is rising from 0
4/15 DocID023325 Rev 1
STL34N65M5 Electrical characteristics
Symbol t d(v) t r(v) t f(i) t c(off)
Parameter
Voltage delay time
Voltage rise time
Current fall time
Crossing time
Table 6. Switching times
Test conditions
V
DD
= 400 V, I
D
= 18 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see Figure 19
)
Min.
Typ.
Max. Unit
-
-
-
59
8.7
7.5
12
-
-
-
ns ns ns ns
Table 7. Source drain diode
Symbol Parameter Test conditions
I
SD
(1)
I
SDM
(1),(2)
V
SD
(3) t rr
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
I
I
Q rr
RRM t rr
Q rr
RRM
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
I
SD
= 22.5 A, V
GS
= 0
I
SD
= 22.5 A, di/dt = 100 A/µs
V
DD
= 100 V (see Figure 16
)
SD
= 22.5 A, di/dt = 100 A/µs
V
DD
= 100 V, T j
= 150 °C
(see
Figure 16 )
Min.
Typ.
Max.
Unit
-
-
-
-
-
-
-
-
-
330
5.3
32.5
412
7.3
35.5
22.5
90
1.5
A
A
V ns
µC
A ns
µC
A
1.
The value is rated according to R thj-case and limited by package.
2.
Pulse width limited by safe operating area.
3.
Pulsed: pulse duration = 300 µs, duty cycle 1.5%.
DocID023325 Rev 1 5/15
15
Electrical characteristics STL34N65M5
2.1 Electrical characteristics (curves)
I
D
(A)
Figure 2. Safe operating area
AM14974v1
Tj=150°C
Tc=25°C
Single pulse
DS(on)
10
10µs y max R ation in this area is
Oper
Limited b
100µs
Figure 3. Thermal impedance
Zth PowerFLAT 8x8 HV
K
δ
=0.5
10
-1
0.2
0.1
0.02
0.05
1 1ms
0.01
Single pulse
10ms
0.1
0.1
1 10 100 V
DS
(V)
10
-2
10
-5
10
-4
10
-3
10
-2 t p
(s)
50
40
30
20
10
0
0
Figure 4. Output characteristics
AM14975v1
I
D
(A)
V
GS
=10V
80
8V
70
60
5 10 15
7V
20
6V
25 V
DS
(V)
Figure 5. Transfer characteristics
AM14976v1
I
D
(A)
V
DS
=25V
80
70
60
50
40
30
20
10
0
0 2 4 6 8 10 12 V
GS
(V)
Figure 6. Gate charge vs gate-source voltage
V
GS
(V)
12
V
DD
=520V
I
D
=14A
AM14978v1
V
DS
(V)
V
DS
500
Figure 7. Static drain-source on-resistance
R
DS(on)
(
Ω
)
0.115
V
GS
=10V
AM14977v1
10 0.110
400
8 0.105
300
6 0.100
200
4 0.095
2
100
0.090
0
0 10 20 30 40 50 60 70
0
Q g
(nC)
0.085
0 5 10 15 20 I
D
(A)
6/15 DocID023325 Rev 1
STL34N65M5 Electrical characteristics
Figure 8. Capacitance variations
C
(pF)
AM14979v1
Figure 9. Output capacitance stored energy
AM14980v1
E oss
(µJ)
12
10000
10
Ciss
1000
8
6
100
Coss
10
Crss
1
0.1
1 10 100 V
DS
(V)
Figure 10. Normalized gate threshold voltage vs temperature
AM05459v1 V
GS(th)
(norm)
1.10
I
D
= 250 µA
1.00
0.90
0.80
0.70
-50 -25 0 25 50 75 100 T
J
(°C)
4
2
0
0 100 200 300 400 500 600 V
DS
(V)
Figure 11. Normalized on-resistance vs temperature
R
DS(on)
(norm)
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
-50 -25
V
GS
= 10 V
I
D
= 12 A
0
AM05460v1
25 50 75 100 T
J
(°C)
Figure 12. Switching losses vs gate resistance
(1)
AM14981v1
E
(
μ
J)
Eon
500
I
D
=18A
V
DD
=400V
V
GS
=10V
400
Figure 13. Normalized V
DS
vs temperature
V
DS
(norm)
1.08
1.06
1.04
I
D
= 1mA
AM10399v1
300
1.02
1.00
200 0.98
0.96
100
Eoff
0
0 10 20 30 40
1.
Eon including reverse recovery of a SiC diode
R
G
(
Ω
)
0.94
0.92
-50 -25 0 25 50 75 100 T
J
(°C)
DocID023325 Rev 1 7/15
15
Test circuits
3 Test circuits
STL34N65M5
Figure 14. Switching times test circuit for resistive load
Figure 15. Gate charge test circuit
V
DD
12V
47k
Ω
100nF
1k Ω
V
GS
V
D
R
G
R
L
D.U.T.
2200
μ
F
3.3
μ
F
V
DD
V i
=20V=V
GMAX
2200
μ F
I
G
=CONST
2.7k
Ω
100 Ω
D.U.T.
V
G
P
W
47k
Ω
AM01468v1
Figure 16. Test circuit for inductive load switching and diode recovery times
P
W
1k
Ω
AM01469v1
Figure 17. Unclamped inductive load test circuit
25 Ω
G
A
D
D.U.T.
S
B
R
G
A
FAST
DIODE
A
B
B
G
D
S
L=100 μ H
3.3
μ F
1000
μ F
V
DD
V i
V
D
I
D
L
2200
μ F
3.3
μ F
V
DD
D.U.T.
P w
AM01470v1
Figure 18. Unclamped inductive waveform
V
(BR)DSS
V
D
Id
90%Vds
AM01471v1
Figure 19. Switching time waveform
Concept waveform for Inductive Load Turn-off
90%Id
I
DM
V
DD
I
D
V
DD
Vgs
90%Vgs
Vds
10%Vds
AM01472v1
10%Id
AM05540v2
8/15 DocID023325 Rev 1
STL34N65M5
4 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
DocID023325 Rev 1 9/15
15
Package mechanical data
Figure 20. PowerFLAT™ 8x8 HV drawing mechanical data
STL34N65M5
10/15 DocID023325 Rev 1
8222871_REV_C
STL34N65M5
Dim.
D
E
D2
E2 e
L
A
A1 b
Package mechanical data
Table 8. PowerFLAT™ 8x8 HV mechanical data mm
Min.
0.80
0.00
0.95
7.05
4.15
0.40
Typ.
0.90
0.02
1.00
8.00
8.00
7.20
4.30
2.00
0.50
Max.
1.00
0.05
1.05
7.30
4.40
0.60
Figure 21. PowerFLAT™ 8x8 HV recommended footprint
7.30
2.00
1.05
Footprin
DocID023325 Rev 1 11/15
15
Packaging mechanical data
5 Packaging mechanical data
Figure 22. PowerFLAT™ 8x8 HV tape
P2 (2.0±0.1) P0 (4.0±0.1)
D0 ( 1.55±0.05) T (0.30±0.05)
D1 ( 1.5 Min)
STL34N65M5
E (1.75±0.1)
P1 (12.00±0.1) A0 (8.30±0.1)
K0 (1.10±0.1)
Note: Base and Bulk quantity 3000 pcs
8229819_Tape_revA
Figure 23. PowerFLAT™ 8x8 HV package orientation in carrier tape.
12/15 DocID023325 Rev 1
STL34N65M5 Packaging mechanical data
Figure 24. PowerFLAT™ 8x8 HV reel
8229819_Reel_revA
DocID023325 Rev 1 13/15
15
Revision history
Date
07-Apr-2014
Revision
Table 9. Document revision history
Changes
1 First release.
STL34N65M5
14/15 DocID023325 Rev 1
STL34N65M5
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