STD4NK100Z
Automotive-grade N-channel 1000 V, 5.6
Ω
typ., 2.2 A
SuperMESH™ Power MOSFET Zener-protected in a DPAK
Datasheet
-
production data
7$%
'3$.
Features
Order code
STD4NK100Z
V
DSS
1000 V
R
DS(on)max
6.8 Ω
I
D
2.2 A
• Designed for automotive applications and
AEC-Q101 qualified
• Extremely high dv/dt capability
• 100% avalanche tested
• Gate charge minimized
• Very low intrinsic capacitance
• Zener-protected
Figure 1. Internal schematic diagram
'7$%
Applications
•
Switching application
*
6
$0YBWDE
Description
This device is an N-channel Zener-protected
Power MOSFET developed using
STMicroelectronics’ SuperMESH™ technology, achieved through optimization of ST’s well established strip-based PowerMESH™ layout. In addition to a significant reduction in onresistance, this device is designed to ensure a high level of dv/dt capability for the most demanding applications.
Note:
Order code
STD4NK100Z
Table 1. Device summary
Marking
4NK100Z
Package
DPAK
Packaging
Tape and reel
HTRB test has been performed at 80% of V
(BR)DSS
according to AEC-Q101 rev. C. All the other tests have been done according to the new rev. D.
April 2015
This is information on a product in full production.
DocID022821 Rev 2 1/16 www.st.com
5
6
3
4
1
2
Contents
Contents
STD4NK100Z
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/16 DocID022821 Rev 2
STD4NK100Z Electrical ratings
Symbol
Table 2. Absolute maximum ratings
Parameter
V
DS
V
GS
I
D
I
D
I
DM
(1)
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
Drain current (continuous) at T
Drain current (pulsed)
C
C
= 25 °C
=100 °C
P
TOT
V
ESD(G-S) d v
/d t
(2)
Total dissipation at T
C
= 25 °C
Gate source ESD (HBM-C=100pF, R=1.5 k
Ω
)
Peak diode recovery voltage slope
T
J
T stg
Operating junction temperature
Storage temperature
1.
Pulse width limited by safe operating area
2.
I
SD
≤
2.2 A, di/dt
≤
200 A/µs, V
DD
≤
V
(BR)DSS
, T j
≤
T
JMAX.
Value
-55 to 150
1000
± 30
2.2
1
8.8
90
3000
4.5
Symbol
Table 3. Thermal data
Parameter
R thj-case
R thj-pcb
(1)
Thermal resistance junction-case max
Thermal resistance junction-pcb max
1.
When mounted on 1inch² FR-4 board, 2 oz Cu
Value
1.39
50
Symbol
I
AR
E
AS
Table 4. Avalanche characteristics
Parameter
Avalanche current, repetitive or not-repetitive
(pulse width limited by T
JMAX
)
Single pulse avalanche energy
(starting T
J
=25 °C, I
D
=I
AR
, V
DD
=50 V)
Value
2.2
110
Unit
°C/W
°C/W
Unit
A
A
W
V
V
A
V
V/ns
°C
Unit
A mJ
DocID022821 Rev 2 3/16
16
Electrical characteristics STD4NK100Z
(T
CASE
=25 °C unless otherwise specified)
Symbol Parameter
Table 5. On/off states
Test conditions
V
(BR)DSS
V
R
I
I
DSS
GSS
GS(th)
DS(on)
Drain-source breakdown voltage
I
D
= 1 mA, V
GS
= 0
Zero gate voltage drain current (V
GS
= 0)
V
DS
= 1000 V,
V
DS
= 1000 V, Tc = 125 °C
Gate body leakage current
(V
GS
= 0)
V
GS
= ± 20 V
Gate threshold voltage V
DS
= V
GS
, I
D
= 50 µA
Static drain-source on-resistance
V
GS
= 10 V, I
D =
1.1 A
Min.
Typ.
Max.
Unit
1000
3 3.75
5.6
1
50
± 10
4.5
6.8
V
µA
µA
µA
V
Ω
Table 6. Dynamic
Test conditions Symbol Parameter Min.
Typ.
Max.
Unit
C iss
C
C oss rss
Input capacitance
Output capacitance
Reverse transfer capacitance
V
V
DS
GS
=25 V, f=1 MHz,
=0
-
-
-
601
53
12
-
-
pF pF pF
C oss. eq
(1)
Equivalent output capacitance
V
GS
=0, V
DS
=0 V to 800 V 15 pF t d(on) t r t d(off) t f
Q g
Q gs
Q gd
Turn-on delay time
Rise time
Off-voltage rise time
Fall time
Total gate charge
Gate-source charge
Gate-drain charge
V
DD
R
G
(see
V
=4.7 Ω, V
GS
DD
V
GS
=500 V, I
D
= 1.25 A,
Figure 16
=800 V, I
D
(see
=10 V
Figure 15
)
)
=10 V
= 2.5 A
-
-
-
-
-
-
15
7.5
32
39
18
3.6
9.2
-
-
-
-
-
-
ns ns ns ns nC nC nC
1.
C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss increases from 0 to 80% V
DSS
when V
DS
4/16 DocID022821 Rev 2
STD4NK100Z Electrical characteristics
Symbol Parameter
Table 7. Source drain diode
Test conditions
I
SD
I
SDM
(1)
V
SD
(2) t rr
Q rr
I
RRM t rr
Q rr
I
RRM
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
1.
Pulse width limited by safe operating area
2.
Pulsed: pulse duration=300 µs, duty cycle 1.5%
I
SD
= 2.2 A, V
GS
=0
I
SD
= 2.5 A, di/dt = 100 A/µs,
V
DD
=100 V
(see
Figure 14 )
I
SD
= 2.5 A, di/dt = 100 A/µs,
V
DD
=100 V, T j
=150 °C
(see
Figure 14 )
-
-
-
-
-
-
-
-
-
Min.
Typ.
Max.
Unit
2.2
8.8
1.6
584
2.3
A
A
V ns
µC
8
628
2.5
8.1
A ns
µC
A
Table 8. Gate-source Zener diode
Parameter Test conditions Symbol
V
(BR)GSO
Gate-source breakdown voltage I gs
=± 1 mA, I
D
=0
Min.
Typ.
Max.
Unit
30 V
The built-in back-to-back Zener diodes have specifically been designed to enhance the device's ESD capability. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated
Zener diodes thus avoid the usage of external components.
DocID022821 Rev 2 5/16
16
Electrical characteristics STD4NK100Z
2.1 Electrical characteristics (curves)
Figure 3. Thermal impedance
,
'
$
Figure 2. Safe operating area
*,3')65
'6RQ
V
V
PV
PV
7M &
7F &
6LQJOHSXOVH
9
'6
9
Figure 4. Output characteristics Figure 5. Transfer characteristics
Figure 6. Normalized V
(BR)DSS
vs. temperature Figure 7. Static drain-source on-resistance
6/16 DocID022821 Rev 2
STD4NK100Z
Figure 8. Gate charge vs. gate-source voltage
Electrical characteristics
Figure 9. Capacitance variations
Figure 10. Normalized gate threshold voltage vs. temperature
Figure 11. Normalized on-resistance vs. temperature
Figure 12. Source-drain diode forward characteristics
Figure 13. Maximum avalanche energy vs Tj
DocID022821 Rev 2 7/16
16
Test circuits
3 Test circuits
STD4NK100Z
Figure 14. Switching times test circuit for resistive load
Figure 15. Gate charge test circuit
V
DD
12V
47k
Ω
100nF
1k Ω
V
GS
V
D
R
G
R
L
D.U.T.
2200
μ
F
3.3
μ
F
V
DD
V i
=20V=V
GMAX
2200
μ F
I
G
=CONST
2.7k
Ω
100
Ω
D.U.T.
V
G
P
W
AM01468v1
Figure 16. Test circuit for inductive load switching and diode recovery times
47k
Ω
P
W
1k
Ω
AM01469v1
Figure 17. Unclamped inductive load test circuit
25 Ω
G
D
A
D.U.T.
S
B
R
G
A
FAST
DIODE
A
B
B
G
D
S
L=100 μ H
3.3
μ F
1000
μ F
V
DD
V i
AM01470v1
Figure 18. Unclamped inductive waveform
V
(BR)DSS
V
D
V
D
I
D
L
2200
μ F
3.3
μ F
V
DD
D.U.T.
P w
AM01471v1
Figure 19. Switching time waveform t on td on t r t off td off t f
I
DM
90%
90%
10%
I
D 0
10% V
DS
V
DD
V
DD
90%
V
GS
AM01472v1
0
10%
AM01473v1
8/16 DocID022821 Rev 2
STD4NK100Z Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
DocID022821 Rev 2 9/16
16
Package information
Figure 20. DPAK (TO-252) type A2 outline
STD4NK100Z
10/16 DocID022821 Rev 2
BW\SH$BUHY
STD4NK100Z
Dim.
e e1
H
L
D
D1
E
E1
L1
L2
L4
R
V2 b4 c c2
A
A1
A2 b
Package information
Table 9. DPAK (TO-252) type A2 mechanical data mm
Typ.
Min.
2.16
4.40
9.35
1.00
6.00
4.95
6.40
5.10
2.20
0.90
0.03
0.64
5.20
0.45
0.48
2.60
0.65
0.60
5.10
5.20
2.28
2.80
0.80
0.20
0°
Max.
6.20
5.25
6.60
5.30
2.40
4.60
10.10
1.50
2.40
1.10
0.23
0.90
5.40
0.60
0.60
3.00
0.95
1.00
8°
DocID022821 Rev 2 11/16
16
Package information
Figure 21. DPAK (TO-252) footprint
(a)
STD4NK100Z
)3BB5
12/16 a.
All dimensions are in millimeters
DocID022821 Rev 2
STD4NK100Z Packing information
Dim.
P0
P1
P2
R
T
W
D1
E
F
K0
A0
B0
B1
D 1.5
1.5
1.65
7.4
2.55
3.9
7.9
1.9
40
0.25
15.7
Table 10. DPAK (TO-252) tape and reel mechanical data
Tape Reel mm mm
Dim.
Min.
6.8
10.4
Max.
7
10.6
12.1
1.6
G
N
T
A
B
C
D
Min.
1.5
12.8
20.2
16.4
50 1.85
7.6
2.75
4.1
8.1
2.1
0.35
16.3
Base qty.
Bulk qty.
Max.
330
13.2
18.4
22.4
2500
2500
DocID022821 Rev 2 13/16
16
Packing information
T
Top cover tape
Figure 22. Tape for DPAK (TO-252)
10 pitches cumulative tolerance on tape +/- 0.2 mm
P0 D P2
B1
K0
For machine ref. only including draft and radii concentric around B0
B0
A0 P1
User direction of feed
D1
STD4NK100Z
F
E
W
14/16
R
A
User direction of feed
REEL DIMENSIONS
Figure 23. Reel for DPAK (TO-252)
40mm min.
Access hole
At sl ot location
B
D
C
Bending radius
AM08852v1
T
N
Full radius
DocID022821 Rev 2
Tape slot in core for tape start 25 mm min.
width
G measured at hub
AM08851v2
STD4NK100Z Revision history
Date
01-Oct-2013
13-Apr-2015
Table 11. Document revision history
Revision Changes
1
2
First release.
Document status promoted from preliminary to production data.
Updated title and features in cover page.
Updated Section 2.1: Electrical characteristics (curves)
and
Section 4: Package information
.
Minor text changes.
DocID022821 Rev 2 15/16
16
STD4NK100Z
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
16/16 DocID022821 Rev 2
