STMicroelectronics STTD6050H-12M2Y Datasheet
Advertisement
Advertisement
STTD6050H-12M2Y
Datasheet
60 A 1200 V half-controlled bridge rectifier in ACEPACK SMIT module
Product status
Internal
Product summary
I
T(RMS)
, I
F(RMS)
I
OUT(AV)
V
DRM
/V
RRM
V
DSM
/V
RSM
I
GT
T j
max.
60 A
75 A
1200 V
1400 V
50 mA
150 °C
Features
• AEC-Q101 qualified
• 1200 V symmetrical blocking voltage
• High junction temperature: 150 °C
• High noise immunity, static dV/dt: 1000 V/μs
• Embed two TN6050HP-12 and two STBR6012 dies
• Module qualified according to AQG324 recommendation
• SMD with isolated top cooled tab
• Terminal pins opposite to cooling side
– Fully automatic PCB mounting to heat sink
• Moisture Sensitivity Level : Level 3
– IPC/JEDEC J-STD-033
• 4000 V insulated tab-to-lead package
– UL recognized, File E81734
• Large creepage distance to meet IEC 60664-1
– 250 V
AC
, material group 2, pollution degree 3
– 600 V
AC
, material group 2, pollution degree 2
• Smaller footprint than four TO-247
• ECOPACK2 compliant component
Applications
• Single-phase controlled bridge rectifier
• On-board and stationary chargers
• AC DC converter for motor drive, UPS and SMPS
• AC input converter current up to 85 A
RMS
• Output full wave DC current up to 75 A
AV
Description
The STTD6050H-12M2Y is a top cooled surface mount module that integrates a single-phase half-controlled bridge rectifier. It is rated at 1200 V and delivers an output full wave DC current up to 75 A
AV current of 60 A
RMS
. Each single embedded device has a rated
and a symmetric blocking voltage of 1200 V.
With its top cooling pad opposite to the printed circuit board this device allows the
PCB-module-heat sink stack to be automatically assembled.
This provides a low profile and compact converter in the field of on-board charger, charging station, motor drive, UPS and AC-DC power supplies.
Based on the ST high temperature automotive planar technology, it offers higher specified noise immunity of 1000 V/µs up to the 150 °C junction temperature T j
, and an over-voltage robustness V
DSM
up to 1400 V.
DS13702 - Rev 2 - April 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
DS13702 - Rev 2
STTD6050H-12M2Y
Characteristics
Characteristics
Table 1. Diode and SCR absolute maximum ratings (limiting values)
Symbol
I
T(RMS)
, I
F(RMS)
I
T(AV)
, I
F(AV)
I
OUT(AV)
Parameter
RMS on-state current, sine half wave
Average on-state current, sine half wave
Average output current, sine full wave
T
T
T
C_SCR
C(AV)
= 106 °C
C_DIODE
= 110 °C
= 106 °C
V
V
I
TSM
DRM
DSM
I
, I
2 t
FSM dl/dt
/ V
/ V
V
GM
I
GM
V
RGM
P
G(AV)
T stg
T j
V
INS
RRM
RSM
I
Non repetitive surge peak on-state current,
V
R
= 0 V, I
G
= 100 mA
2 t value for fusing t p
= 8.3 ms
T j
initial = 25 °C t p
= 10 ms t p
= 10 ms T j
= 25 °C
I
Critical rate of rise of on-state SCR current
G
= 2 x I
GT
, tr ≤ 100 ns f = 100 Hz T j
= 150 °C
Repetitive off-state voltage
T j
= -40 °C to 150 °C
Non repetitive surge peak off-state voltage
t p
= 10 ms T j
= 25 °C
Peak forward SCR gate voltage
Peak forward SCR gate current
Peak SCR gate voltage
Average SCR gate power dissipation
Storage junction temperature range
Operating junction temperature range
RMS tab-to-leads insulation voltage, 1 minute, f = 50 - 60 Hz
1. V
DRM
and V
DSM
apply to SCR only.
t p
= 20 µs T j
= 150 °C t p
= 20 µs T j
= 150 °C
T j
= 25 °C
T j
= 150 °C
200
1200
1400
10
8
5
1
-40 to +150
-40 to +150
4
Value
60
38
75
525
500
1250
Unit
A
A
A
A
A 2 s
A/µs
V
V
W
°C
°C kV
V
A
V
Symbol
SCR triggering characteristics
Table 2. SCR electrical characteristics, per single SCR
Test Conditions
I
GT
V
D
= 12 V, R
L
= 33 Ω
V
V
GT
GD
V
D
= 12 V, R
L
= 33 Ω
V
D
= 2/3 V
DRM
, R
L
= 3.3 kΩ
I
T
= 500 mA, gate open I
H
I
L
I
G
= 1.2 x I
SCR dynamic characteristics
GT t t
GT
Q dV/dt
I
T
= 60 A , V
D
= 800 V, I
G
= 100 mA, dI
G
/dt = 0.2 A/µs
I
T
= 38 A, V
D
= 800 V, dI
T
/dt = 10 A/µs,
V
R
= 75 V, dV
D
/dt = 20 V/µs, t p
= 100 µs
V
D
= 800 V, gate open
T j
= 25 °C
T j
= 25 °C
T j
= 150 °C
T j
= 25 °C
T j
= 25 °C
T j
= 25 °C
T j
= 150 °C
T j
= 150 °C
Value Unit
Min.
Max.
Max.
Min.
Max.
Max.
0.2
100
125
10
50
1.3
mA
V
V mA mA
Typ.
1 µs
Typ.
150 µs
Min.
1000 V/µs page 2/18
DS13702 - Rev 2
STTD6050H-12M2Y
Characteristics
Symbol
SCR static characteristics
Test Conditions
V
TM
V
TOT
R
DT
I
DRMT
/I
RRMT
I
TM
= 60 A, t
P
= 380 µs
SCR on-state threshold voltage
SCR on-state dynamic resistance
V
D
= V
DRM
, V
R
= V
RRM
I
DSMT
/I
RSMT
SCR losses evaluation
V
D
= V
DSM
, V
R
= V
RSM
P
LT
V
TOT
x I
T(AV)
+ R
DT
x I
T(RMS)
2
1. Refer to application note AN4608 for parameter definition
T j
= 25 °C
T j
= 150 °C
T j
= 150 °C
T j
= 150 °C
T j
= 25 °C
T j
= 150 °C
T j
= 25 °C
Value Unit
Max.
1.3
Max.
1.3
V
V
Max.
0.8
V
Max.
7.45
mΩ
Max.
5 µA
Max.
7.5
Max.
10 mA
µA
W
Symbol
Diode static characteristics
Table 3. Diode Electrical Characteristics, per single diode
Test Conditions
V
F
V
TOD
R
DD
I
RRMD
I
F
= 60 A, t
P
= 380 µs, duty cycle δ < 2%
On-state rectifier threshold
On-state rectifier dynamic resistance
V
R
= V
RRM
, t p
= 5 ms, duty cycle δ < 2%
I
RSMD
V
Diode losses evaluation
R
= V
RSM
P
LD
V
TOD
x I
T(AV)
+ R
DD
x I
T(RMS)
2
T j
= 25 °C
T j
= 150 °C
T j
= 150 °C
T j
= 150 °C
T j
= 25 °C
T j
= 150 °C
T j
= 25 °C
Value Unit
Max.
Max.
1.3
1.2
Max.
0.96
Max.
Max.
Max.
Max.
4
5
250
25
V
V
V mΩ
µA
µA
W
Table 4. Thermal characteristics
Symbol
R th(j-c) T
R th(j-c) D
Junction to case (DC), per SCR (1)
Junction to case (DC), per diode (1)
Parameter
1. The case temperature is measured right underneath the device die on cooling pad
Value Unit
Max.
0.75
°C/W
Max.
0.75
°C/W
For more information, please refer to the following application note related to the thermal management:
• AN5384 : ACEPACK SMIT module package guidelines for mounting and thermal management page 3/18
STTD6050H-12M2Y
Characteristics (curves)
1.1
Characteristics (curves)
Figure 1. Diode forward on-state characteristics
(maximum value), T j
= 25 °C and 150 °C
1.0E+03
I
F
(A)
1.0E+02
1.0E+01
1.0E+00
1.0E-01
1.0E-02
0.0
T j
= 150 °C
0.5
T j
= 25 °C
1.0
1.5
V
F
(V)
2.0
On-state characteristics (maximum value)
Figure 2. SCR on-state characteristics (maximum values),
T j
= 25 °C and 150 °C
I
TM
(A)
1000
Tj max:
V
R T0
D
= 0.8 V
= 7.45 mΩ Tj = 150 °C
100
10
1
0 0.5
1
Tj = 25 °C
1.5
2 2.5
3 3.5
V
TM
(V)
4 4.5
Figure 3. Diode maximum average power dissipation versus average half-wave on-state current, a = 30 ° to
180 °
55
50
P(W)
45
40
35
30
25
20
15
10
5
0
0 10
α = 30 °
α = 60 °
α = 90 °
α = 180 °
α = 120 °
20
360 °
α
30
IT
(AV)
(A)
40
Figure 4. SCR maximum average power dissipation versus average half-wave on-state current, a = 30 ° to
180 °
65
60
55
50
45
40
35
30
25
20
15
10
5
0
0
P(W)
10
α = 180 °
α = 90 °
α = 120 °
α = 30 °
α = 60 °
20
360 °
α
30 40
IT
(AV)
(A)
50
Figure 5. Diode average on-state current versus case temperature
50
IT
(AV)
(A)
360 °
40 α = 180 °
α
30
α = 120 °
α = 90 °
α = 60 °
20
α = 30 °
10
0
0 25 50
T c
(°C)
75 100 125 150
Figure 6. SCR average on-state current versus case temperature
50
IT
(AV)
(A)
40 α = 180 °
30
α = 120 °
α = 90 °
α = 60 °
20
α = 30 °
10
0
0 25 50
T c
(°C)
75 100 125 150
DS13702 - Rev 2 page 4/18
STTD6050H-12M2Y
Characteristics (curves)
Figure 7. Diode relative variation of thermal impedance junction to case versus pulse duration, 1 ms to 1 s
1.0
Zth(j-c) / Rth(j-c)
Single pulse
Figure 8. SCR relative variation of thermal impedance junction to case versus pulse duration, 1 ms to 1 s
K = [Zth/ Rth]
1.0E+00
Zth(j-c)
0.1
1.E-03 1.E-02 tP(s)
1.E-01 1.E+00
1.0E-01
1.0E-03 1.0E-02 tp(s)
1.0E-01 1.0E+00
Figure 9. SCR relative variation of gate trigger current and gate trigger voltage versus junction temperature (typical values)
2.0
IGT, VGT [ Tj ] / IGT, VGT [ Tj = 25 °C]
Figure 10. SCR relative variation of holding and latching current versus junction temperature (typical values)
2.0
IH, IL [ Tj ] / IH, IL [ Tj = 25 °C]
1.6
IH
1.5
IGT
1.2
IL
1.0
0.8
VGT
0.5
0.4
0.0
-50 -25 0 25
T j
(°C)
50 75 100 125 150
0.0
-50 -25 0 25
T j
(°C)
50 75 100 125 150
Figure 11. Diode non repetitive surge peak on-state current for a sinusoidal pulse (t p
< 10 ms) , V r
= 0 V
4.0
I FSM (t p ) / I FSM (10ms)
3.5
3.0
2.5
2.0
1.5
1.0
0.1
t
P
(ms)
1.0
10.0
Figure 12. SCR non repetitive surge peak on-state current for a sinusoidal pulse (t p
< 10 ms) , V r
= 0 V
10000
I
TSM
(A)
T j
initial = 25 °C
1000 dl/dt limitation: 200 A/µs
100
10
1.E-02 1.E-01 t p
(ms)
I
TSM
1.E+00 1.E+01
DS13702 - Rev 2 page 5/18
STTD6050H-12M2Y
Characteristics (curves)
Figure 13. SCR and diode surge peak forward current versus number of half cycles, V r
= 0 V and
T j
initial = 25 °C
550
500
450
400
350
300
250
200
150
100
50
0
1
I
TSM
(A)
Non repetitive Tj = 25 °C
Repetitive Tc = 107 °C
10
Number of cycles
100
One cycle
1000
Figure 14. SCR and Diode junction capacitance versus reverse voltage applied, gate open, in discrete package
(typical values)
1000
C(pF)
100
10
10
Diode
SCR
100
F = 1 MHz
V osc
T
= 30 mV j
RMS
= 25 °C
V
R
(V)
1000
Figure 15. SCR relative variation of the static dV/dt immunity versus junction temperature (typical values)
2
1
0
25
5
4
3
6 dV/dt [T j
] / dV/dt [T j
=150 °C]
50 75 100
V
D
=V
R
= 2/3 V
DRM
125
Tj(°C)
150
DS13702 - Rev 2 page 6/18
STTD6050H-12M2Y
Application
2
Application
2.1
Solid state Inrush current limitation topologies using STTD6050H-12M2Y
As illustrated here below, bypass and mixed bridge rectifiers are two topologies dedicated to the AC line voltage rectification which include the solid-state inrush current limitation feature.
Figure 16. Bypass function ensured by SCR Figure 17. Soft start / mixed control bridge rectifier
In the bypass topology, at system start-up both T1 and T2 SCRs are OFF. The output bulk capacitor is then charged through the D3, D4, D2, D1 diodes and the current is limited by the R_limit resistor placed in the current path.
At steady state, R_limit power losses are cut by switching ON alternatively the T1 and T2 SCRs according to line polarity which are then bypassing R_limit.
Figure 18. Bypass topology waveform working principle
DS13702 - Rev 2 page 7/18
STTD6050H-12M2Y
Solid state Inrush current limitation topologies using STTD6050H-12M2Y
In the mixed bridge topology, SCRs are controlled in phase angle to smoothly increase the PFC output capacitor voltage up to peak AC line voltage. The pre-charging peak current value is controlled by a microcontroller which smartly synchronizes the SCRs gate driving signal angle step (referred as Δt in the figure here below). Limiting resistor is no more needed.
Figure 19. Mixed bridge phase angle principle
DS13702 - Rev 2
For more information, refer to the application note:
• AN4606 tips.
: Inrush-current limiter circuits (ICL) with Triacs and Thyristors (SCR) and controlled bridge design
Those two robust solid-state topologies allow the applications to easily comply to the following standards:
1.
IEC61000-3-3 (voltage fluctuations and flicker in public low-voltage supply systems, for equipment with rated current ≤ 16 A). the high current powered from the grid may lead to voltage fluctuations and drops due to the line impedance. Those mains voltage disturbances have an impact on any other equipment connected to the same circuit and cause undesired brightness variation of lamps or displays (commonly called flickering phenomenon).
2.
IEC61000-4-11 (voltage dips, short interruptions, and voltage variations immunity tests) As any appliance connected to the mains can be subject to line voltage dips or interruptions, a high input current may occur when the line voltage suddenly comes back to its nominal value. This high current may damage the front-end circuit components and can trigger an AC fuse for example.
page 8/18
STTD6050H-12M2Y
Dissipated power and junction temperature calculation at steady state
2.2
Dissipated power and junction temperature calculation at steady state
In below example, STTD6050H-12M2Y is placed upstream from PFC stage. I
T
and I
F
define respectively SCR and diode current value. Therefore, the current taken from the line and flowing through the mixed bridge is a sinus waveform.
Figure 20. Soft start / mixed control bridge rectifier Figure 21. SCR / diode current waveform (sinusoidal half wave)
2.2.1
Note:
Dissipated power into SCRs and diodes
Dissipated power into SCRs and diodes is defined by the following equation:
(1)
V
T0X
and R
DX
are given in
Eq. (1) and Eq. (4) where X = T for the SCR and F for the diode.
IT AV =
IP
π ; Ip = ILine RMS × 2 = > IT AV =
2
π × IL RMS
=
IL RMS
2
Using equations (1), (2) and (3), dissipated power can directly be calculated from AC line RMS current value
I
L(RMS)
for a single SCR or diode in the mixed bridge:
Pd = × IL RMS +
2
2 × IL RMS
(2)
(3)
(4)
DS13702 - Rev 2 page 9/18
2.2.2
STTD6050H-12M2Y
Dissipated power and junction temperature calculation at steady state
Junction temperature calculation
Figure 22. Die assembly representation
Note:
When Tc value is known, silicon junction temperature can be calculated as follows:
Tj = TC + PD × RTH j − c
Otherwise, starting from ambient temperature measurement, junction temperature can be calculated as follows:
Tj = TA + PD × RTH j − a
•
•
•
R th(j-c)
and R th(j-a)
values are given in the datasheet.
with:
RTH j − a = RTH j − c + RTH c − ℎ + RTH ℎ − a and where R
TH(c-h)
is the thermal interface resistance (grease or foil) and R
TH(h-a)
is the heatsink thermal resistance.
For more information about the thermal management and power dissipation calculation, refer to the application note:
AN533 : SCRs, TRIACs, and AC switches, thermal management precautions for handling and mounting
AN604 : Calculation of conduction losses in a power rectifier
AN4021 : Calculation of reverse losses in a power diode
DS13702 - Rev 2 page 10/18
3
3.1
STTD6050H-12M2Y
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
•
•
ACEPACK SMIT package information
Lead-free package leads finishing
Halogen-free molding compound resin meets UL94 standard level V0
Figure 23. ACEPACK SMIT package outline
DS13702 - Rev 2
DM00447519_Rev.5
page 11/18
Dim.
m1
V aaa bbb
L
L1 m c1 d d1 e e1 b b1 b2 b3 c
A
B
C
D
E
STTD6050H-12M2Y
ACEPACK SMIT package information
Min.
19.50
21.50
22.80
24.80
32.20
1.30
4.65
3.95
5.40
1.30
0.95
1.95
0.00
0.45
1.30
0°
0.01
0.00
Table 5. ACEPACK SMIT package mechanical data
0.55
1.50
4.85
4.00
5.50
1.50
1.50
2° mm
Typ.
9.00
4.00
6.75
9.50
1.00
2.00
20.00
22.00
23.00
25.00
32.70
1.70
5.05
4.05
5.60
1.80
1.10
2.10
0.15
0.65
1.80
4°
0.05
0.10
Max.
20.50
22.50
23.20
25.20
33.20
Min.
0.7677
0.8465
0.8976
0.9764
1.2677
0.0374
0.0768
0.0000
0.0177
0.0512
0.1831
0.1555
0.2126
0.0512
0.0512
0°
Inches (for reference only)
Typ.
0.0787
0.0000
0.0217
0.0591
0.1909
0.1575
0.2165
0.0591
0.0591
2°
0.0004
0.0000
0.7874
0.8661
0.9055
0.9843
1.2874
0.3543
0.1575
0.2657
0.3740
0.0394
Figure 24. ACEPACK SMIT recommended footprint (dimensions are in mm)
0.0433
0.0827
0.0059
0.0256
0.0669
0.1988
0.1594
0.2205
0.0709
0.0709
4°
0.0020
0.0039
Max.
0.8071
0.8858
0.9134
0.9921
1.3071
4.00 (x9)
Note:
30.10
DM00447519_FP_Rev.5
Recommended pressing force on package to the heatsink: 50 N as described in application note AN5384 .
DS13702 - Rev 2 page 12/18
3.2
STTD6050H-12M2Y
ACEPACK SMIT package insulation information
ACEPACK SMIT package insulation information
Figure 25. ACEPACK SMIT package insulation information
Note:
Table 6. ACEPACK SMIT package insulation characteristics
Symbol
L2
L3
I
INS
Pin-to-pin creepage distance
Pin-to-backside creepage distance
RMS tab-to-pin lead insulation current
Parameter
Terminal to terminal: 3 to 4, 7 to 8, 8 to 9
Duration = 1 s., V
INS
= 4.8 kV
Min.
Min.
Max.
Value Unit
6.6
4
1 mm mm mA
Recommended pressing force on package to the heatsink: 50 N as described in application note AN5384 .
DS13702 - Rev 2 page 13/18
3.3
STTD6050H-12M2Y
ACEPACK SMIT terminal description
ACEPACK SMIT terminal description
Pin #
1
2
3
4
5
6
7
8
9
Table 7. ACEPACK SMIT STTD6050H-12M2Y module pinout description
Name
NC
G1
G2
D-
D-
D-
L2
L1
D+
Description
Not connected
Gate SCR1
Gate SCR2
Output minus
Output minus
Output minus
AC line 2
AC line 1
Output plus
Figure 26. ACEPACK SMIT STTD6050H-12M2Y module pinout
DS13702 - Rev 2 page 14/18
3.4
STTD6050H-12M2Y
ACEPACK SMIT packing information
ACEPACK SMIT packing information
Figure 27. ACEPACK SMIT carrier tape outline, bottom view
Table 8. ACEPACK SMIT carrier tape dimensions
A
0
B
0
C D
0
D
1
26.00
33.30
0.40
2.00
1.50
Carrier tape typical dimension (mm)
E
1
F G K
0
K
1
P
0
P
1
P
2
T W
1.75
26.20
24.10
7.10
5.80
4.00
36.00
2.00
0.35
56.00
Figure 28. ACEPACK SMIT reel outline
DS13702 - Rev 2
Base qty.
200
A
16.4 ±0.3
B (max.)
22.4
Table 9. ACEPACK SMIT reel dimensions
C
13.2 ±0.2
Reel dimension (mm)
D (min.) E (max.)
20.2 ±0.25
330
F (min.)
20.2
G
2.0 ±0.5
T
1
(max.)
0.1
page 15/18
4
STTD6050H-12M2Y
Ordering information
Ordering information
ST
Figure 29. Ordering information scheme
T D 60 50 H 12 M2 Y
Devices Type
T = Thyristor SCR, ; D = Diode
RMS SCR / Diode current
60 = 60 A
Gate triggering Current
50 = 50 mA
High Temperature
H = 150°C rated
Blocking Voltage
12 = 1200 V
Package
M2 = ACEPACK SMIT module with two embedded legs
Quality grade
Comply with automotive AQG324
Order code
STTD6050H-12M2Y
Table 10. Ordering information
Marking
STTD6050H12M2Y
Package
ACEPACK SMIT
Weight
8.1 g
Base qty.
200
Delivery mode
Tape and reel
DS13702 - Rev 2 page 16/18
STTD6050H-12M2Y
Revision history
Date
14-Apr-2021
22-Apr-2021
Table 11. Document revision history
Version
1
2
Changes
Initial release.
Confidentiality level changed from ST Resctricted to public.
DS13702 - Rev 2 page 17/18
STTD6050H-12M2Y
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS13702 - Rev 2 page 18/18
Download
Public link updated
The public link to your chat has been updated. You may view and manage your chat links after registration here.
Document public link
Advertisement