STMicroelectronics STP16DP05 Datasheet

STP16DP05

Low voltage 16-bit constant current LED sink driver with outputs error detection

Datasheet - production data

Features



Low voltage power supply down to 3 V



16 constant current output channels



Adjustable output current through external resistor



Short and open output error detection



Serial data IN/Parallel data OUT



3.3 V micro driver-able





Output current: 5-100 mA

30 MHz clock frequency



Available in high thermal efficiency TSSOP exposed pad



ESD protection 2.5 kV HBM, 200 V MM

LED panel displays. The device contains a 16-bit serial-in, parallel-out shift register that feeds a

16-bit D-type storage register. In the output stage, sixteen regulated current sources were designed to provide 5-100 mA constant current to drive the LEDs. The STP16DP05 features open and short LED detections on the outputs. The

STP16DP05 is backward compatible with

STP16C/L596. The detection circuit checks

3 different conditions that can occur on the output line: short to GND, short to V

O

or open line. The data detection results are loaded in the shift register and shifted out via the serial line output.

The detection functionality is implemented without increasing the pin count number, through a secondary function of the output enable and latch pin (DM1 and DM2 respectively), a dedicated logic sequence allows the device to enter or leave from detection mode. Through an external resistor, users can adjust the

STP16DP05 output current, controlling in this way the light intensity of LEDs, in addition, user can adjust LED’s brightness intensity from 0 % to

100 % via OE/DM2 pin. The STP16DP05 guarantees a 20 V output driving capability, allowing users to connect more LEDs in series.

The high clock frequency, 30 MHz, makes the device suitable for high data rate transmission.

The 3.3 V voltage supply is well useful for

Description

The STP16DP05 is a monolithic, low voltage, low current power 16-bit shift register designed for applications that interface any 3.3 V micro.

Compared with a standard TSSOP package, the

TSSOP exposed pad increases heat dissipation capability by a 2.5 factor.

Table 1: Device summary

Order code Package Packing

STP16DP05MTR

STP16DP05TTR

STP16DP05XTTR

STP16DP05PTR

SO-24 (tape and reel)

TSSOP24 (tape and reel)

TSSOP24 exposed pad (tape and reel)

QSOP-24

1000 parts per reel

2500 parts per reel

2500 parts per reel

2500 parts per reel

November 2017 DocID13093 Rev 8

This is information on a product in full production.

1/34 www.st.com

Contents

Contents

STP16DP05

1 Summary description ...................................................................... 3

1.1

Pin connection and description ......................................................... 3

2 Electrical ratings ............................................................................. 4

2.1

2.2

2.3

Absolute maximum ratings ................................................................ 4

Thermal data ..................................................................................... 4

Recommended operating conditions ................................................. 5

3 Electrical characteristics ................................................................ 6

4 Equivalent circuit and outputs ....................................................... 8

5 Timing diagrams ............................................................................ 11

6 Typical characteristics .................................................................. 14

7 Detection mode functionality ....................................................... 17

7.1

7.2

7.3

Phase one: “entering in detection mode“ ........................................ 17

Phase two: “error detection” ............................................................ 18

Phase three: “resuming to normal mode” ........................................ 20

7.4

Error detection conditions ............................................................... 20

8 Package information ..................................................................... 23

8.1

8.2

8.3

8.4

8.5

QSOP-24 package information ....................................................... 24

SO-24 package information ............................................................ 26

TSSOP24 package information ....................................................... 27

TSSOP24 exposed pad package information ................................. 29

TSSOP24, TSSOP24 exposed pad and SO-24 packing information31

9 Revision history ............................................................................ 33

2/34 DocID13093 Rev 8

STP16DP05 Summary description

1 Summary description

Output voltage

Table 2: Typical current accuracy

Current accuracy

Output current

Between bits Between ICs

≥ 1.3 V ±1.5 % ±5 % 20 to 100 mA

V

DD

3.3 V to 5 V

1.1 Pin connection and description

Figure 1: Pin connection

Temperature

25 °C

The exposed pad should be electrically connected to a metal land electrically isolated or connected to ground

Pin n° Symbol

Table 3: Pin description

Name and function

1

2

3

4

GND

SDI

Ground terminal

Serial data input terminal

CLK Clock input terminal

LE-DM1 Latch input terminal - detect mode 1 (see operation principle)

5-20 OUT 0-15 Output terminal

21 OE-DM2 Input terminal of output enable (active low) - detect mode 1 (see operation principle)

22

23

SDO

R-EXT

Serial data out terminal

Input terminal of an external resistor for constant current programing

24 V

DD

Supply voltage terminal

DocID13093 Rev 8 3/34

Electrical ratings

2

2.1

2.2

Electrical ratings

STP16DP05

Absolute maximum ratings

St ressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 4: Absolute maximum ratings

Parameter Value Unit

V

DD

V

O

I

O

V

I

I

GND f

CLK

Supply voltage

Output voltage

Output current

Input voltage

GND terminal current

Clock frequency

0 to 7

-0.5 to 20

100

-0.4 to V

DD

1600

50

V

V mA

V mA

MHz

Thermal data

Symbol

T

OPR

T

STG

R thJA

Table 5: Thermal data

Parameter

Operating temperature range

Storage temperature range

Thermal resistance junctionambient

SO-24

TSSOP24

TSSOP24 exposed pad (1)

QSOP-24

Value Unit

-40 to +125 °C

-55 to +150 °C

42.7 °C/W

55

37.5

°C/W

°C/W

55 °C/W

Notes:

(1)

The exposed pad should be soldered directly to the PCB to realize the thermal benefits.

4/34 DocID13093 Rev 8

STP16DP05

2.4 Recommended operating conditions

Symbol

Electrical ratings

Table 6: Recommended operating conditions

Parameter Test condition Min. Typ. Max. Unit

V

DD

V

O

I

O

Supply voltage

Output voltage

Output current OUTn

3.0

5

-

-

-

5.5

20

100

V

V mA

I

OH

I

OL

V

IH

V

IL

Output current

Output current

Input voltage

Input voltage

SERIAL-OUT

SERIAL-OUT

0.7 V

DD

-0.3

-

-

-

-

+1

-1

V

DD

+0.3

0.3 V

DD t wLAT t wCLK

LE\DM1 pulse width

CLK pulse width

6

8

-

- t wEN

OE/DM2 pulse width 100 -

V

DD

= 3.0 V to 5.0 V t

SETUP(D)

Setup time for DATA 10

5

10

- t

HOLD(D)

Hold time for DATA t

SETUP(L)

Setup time for LATCH f

CLK

Clock frequency

Cascade operation (1)

-

-

- 30

Notes:

(1)

If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please consider the timings carefully.

mA mA

V

V ns ns ns ns ns ns

MHz

DocID13093 Rev 8 5/34

Electrical characteristics STP16DP05

3 Electrical characteristics

Symbol

V

DD

= 3.3 V to 5 V, T = 25 °C, unless otherwise specified

Parameter

Table 7: Electrical characteristics

Test conditions Min.

V

IH

V

IL

Input voltage high level

Input voltage low level

I

OH

Output leakage current V

OH

= 20 V

V

OL

Output voltage (serial-OUT) I

OL

= 1 mA

0.7 V

DD

GND

I

V

OH

Output voltage (serial-OUT) I

OH

= -1 mA

I

OL1

V

O

= 0.3 V

R

EXT

= 3.9 kΩ

I

I

OL2

OL3

Output current

V

O

= 0.3 V

R

EXT

= 970 Ω

V

O

= 1.3 V

R

EXT

= 190 Ω

∆I

∆I

∆I

OL1

OL2

OL3

Output current error between bit (all output ON)

V

O

= 0.3 V

R

EXT

= 3.9 kΩ

V

O

= 0.3 V

R

EXT

= 970 Ω

V

O

= 1.3 V

R

EXT

=190 Ω

R

SIN(up)

Pull-up resistor

R

SIN(down)

Pull-down resistor

I

DD(OFF1)

DD(OFF2)

Supply current (OFF)

I

DD(ON1)

Supply current (ON)

I

DD(ON2)

Thermal Thermal protection (1)

R

EXT

= 970 OUT 0 to 15 = OFF

R

EXT

= 240 OUT 0 to 15 = OFF

R

EXT

= 970 OUT 0 to 15 = ON

R

EXT

= 240 OUT 0 to 15 = ON

V

OH

-V

DD

= -0.4 V

4.25

19

96

150

100

Notes:

(1)

Guaranteed by design (not tested). The thermal protection switches OFF only the outputs current.

5

Typ. Max. Unit

V

DD

V

0.3 V

DD

V

1

0.4

µA

V

V

5.75

20

100

± 5

21

104

± 8

± 1.5 ± 3

± 1.2 ± 3

300

200

5

13

6

600

400

6

14

7

13.5 14.5

170 mA

%

KΩ

KΩ mA

°C

6/34 DocID13093 Rev 8

STP16DP05

V

DD

= 5 V, T = 25 °C, unless otherwise specified.

Symbol Parameter

Table 8: Switching characteristics

Test conditions t

PLH1

Propagation delay time,

CLK - OUTn , LE/DM1 = H,

V

DD

= 3.3 V

V

DD

= 5 V

Electrical characteristics

Min. Typ. Max. Unit

- 40 65

- 20 30 ns

OE/DM2 = L

V

DD

= 3.3 V - 51 77 t

PLH2 t

PLH3 t

PLH t

PHL1 t

PHL2

Propagation delay time,

LE/DM1 - OUTn , OE/DM2

= L

Propagation delay time,

OE/DM2 - OUTn ,

LE/DM1 = H

Propagation delay time,

CLK-SDO

Propagation delay time,

CLK - OUTn , LE/DM1 = H,

OE/DM2 = L

Propagation delay time,

LE/DM1 - OUTn ,

V

DD

= 5 V

V

DD

= 3.3 V

V

DD

= 5 V

V

DD

= 3.3 V

V

DD

= 5 V

V

DD

= 3.3 V

V

IH

= V

DD

V

IL

= GND

C

L

= 10 pF I

O

= 20 mA

V

L

= 3.0 V R

EXT

= 1 KΩ

R

L

= 60 Ω

V

DD

= 5 V

V

DD

= 3.3 V

-

-

-

-

-

-

-

-

32

49

27

47

77

41

21.5 32

14.5 21.5

15 25

11 14.5

13 20 ns ns ns ns ns

V

DD

= 5 V - 9 12.5 t

PHL3 t

PHL t

ON t

OFF t r t f

OE/DM2 = L

Propagation delay time,

OE/DM2 - OUTn ,

LE/DM1 = H

Propagation delay time,

CLK-SDO

Output fall time 10~90 % of voltage waveform

Output rise time 90~10 % of voltage waveform

CLK rise time (1)

CLK fall time (1)

V

DD

= 3.3 V

V

DD

= 5 V

V

DD

= 3.3 V

V

DD

= 5 V

V

DD

= 3.3 V

V

DD

= 5 V

V

DD

= 3.3 V

V

DD

= 5 V

-

-

-

-

-

-

-

-

-

-

11.5 18

8.5 12 ns

25.5 38

17.5 25 ns

34 53.5

12.5 18.5 ns

5.5 8.5 ns

4.5 6.5

5000 ns

5000 ns

Notes:

(1)

In order to achieve high cascade data transfer, please consider tr/tf timings carefully.

DocID13093 Rev 8 7/34

Equivalent circuit and outputs

4 Equivalent circuit and outputs

Figure 2: OE\DM2 terminal

STP16DP05

Figure 3: LE\DM1 terminal

8/34 DocID13093 Rev 8

STP16DP05

Figure 4: CLK, SDI terminal

Equivalent circuit and outputs

Figure 5: SDO terminal

DocID13093 Rev 8 9/34

Equivalent circuit and outputs

Figure 6: Block diagram

STP16DP05

10/34 DocID13093 Rev 8

STP16DP05

5

Timing diagrams

Timing diagrams

CLOCK LE\DM1

Table 9: Truth table

OE/DM2 SERIAL-IN OUT0 .....OUT7.....OUT15

_|¯

_|¯

_|¯

¯|_

¯|_

H

L

H

X

X

L

L

L

L

H

Dn

Dn + 1

Dn + 2

Dn + 3

Dn + 3

Dn ..... Dn - 7 ..... Dn -15

No change

Dn + 2 ..... Dn - 5 ..... Dn -13

Dn + 2 ..... Dn - 5 ..... Dn -13

OFF

OUTn = ON when Dn = H OUTn = OFF when Dn = L

Figure 7: Timing diagram

SDO

Dn - 15

Dn - 14

Dn - 13

Dn - 13

Dn - 13

1 - Latch and output enable are level sensitive and ARE NOT synchronized with rising-or-falling edge of CLK signal.

2 - When LE terminal is low level, the latch circuits hold previous set of data.

3 - When LE terminal is at high level, the latch circuits refresh new set of data from SDI chain.

4 - When OE terminal is at low level, the output terminals - Out0 to Out15 respond to data in the latch circuits, either '1' for ON or '0' for OFF.

5 - When OE terminal is at high level, all output terminals will be switched OFF.

DocID13093 Rev 8 11/34

Timing diagrams

Figure 8: Clock, serial-in, serial-out

STP16DP05

12/34 DocID13093 Rev 8

STP16DP05

Figure 9: Clock, serial-in, latch, enable, outputs

Timing diagrams

Figure 10: Outputs

DocID13093 Rev 8 13/34

Typical characteristics

6 Typical characteristics

Figure 11: Output current-Rext resistor

STP16DP05

14/34

325

300

278

259

241

229

215

976

780

652

560

488

433

389

354

60

65

70

75

80

85

90

40

45

50

55

20

25

30

35

Conditions:

Temperature = 25 °C, V

DD

= 3.3 V; 5.0 V, I

SET

= 3 mA; 5 mA; 10 mA; 20 mA; 50 mA;

80 mA.

Rext (Ω)

Table 10: Output current-Rext resistor

Output current (mA)

DocID13093 Rev 8

STP16DP05

Figure 12: I

SET

vs drop out voltage (V drop

)

Typical characteristics

Iout (mA)

3

5

10

20

50

80

Table 11: I

SET

vs drop out voltage (V drop

)

Avg @ 3.0 V

19.33

36.67

77.33

158.67

406

692

Avg @ 5.0 V

22.66

40.33

80

157.33

406

668

Figure 13: I

DD

ON/OFF

DocID13093 Rev 8 15/34

Typical characteristics

Figure 14: Power dissipation vs temperature package

STP16DP05

The exposed pad should be soldered to the PBC to realize the thermal benefits.

16/34 DocID13093 Rev 8

STP16DP05

7

7.1

Detection mode functionality

Detection mode functionality

Phase one: “entering in detection mode“

Fr om the “normal mode” condition the device can switch to the “error mode” by a logic sequence on the OE/DM2 and LE/DM1 pins as showed in the following table and diagram:

CLK

Table 12: Entering in detection truth table

1° 2° 3° 4° 5°

OE/DM2 H L H H H

LE/DM1 L L L H L

Figure 15: Entering in detection timing diagram

After these five CLK cycles the device goes into the “error detection mode” and at the 6 th rise front of CLK the SDI data are ready for the sampling.

DocID13093 Rev 8 17/34

Detection mode functionality

7.2 Phase two: “error detection”

STP16DP05

The 16 data bits must be set “1” in order to set ON all the outputs during the detection. The data are latched by LE/DM1 and after that the outputs are ready for the detection process.

When the micro controller switches the OE/DM2 to LOW, the device drives the LEDs in order to analyze if an OPEN or SHORT condition has occurred.

Figure 16: Detection diagram

The LEDs status will be detected at least in 1 microsecond and after this time the microcontroller sets OE/DM2 in HIGH state and the output data detection result will go to the microprocessor via SDO.

Detection mode and normal mode use both the same format data. As soon as all the detection data bits are available on the serial line, the device may go back to normal mode of operation. To re-detect the status the device must go back in normal mode and reentering in error detection mode.

18/34 DocID13093 Rev 8

STP16DP05 Detection mode functionality

Figure 17: Timing example for open and/or short detection

DocID13093 Rev 8 19/34

Detection mode functionality

7.3 Phase three: “resuming to normal mode”

STP16DP05

The sequence for re-entering in normal mode is showed in the following table and diagram:

CLK

Table 13: Resuming to normal mode timing diagram

1° 2° 3° 4° 5°

OE/DM2 H L H H H

7.4

LE/DM1 L L L L L

For proper device operation the “Entering in detection” sequence must be follow by a “resume mode” sequence, it is not possible to insert consecutive equal sequence.

Error detection conditions

V

DD

= 3.3 to 5 V temperature range -40 to 125 °C

Table 14: Detection conditions

SW-1 or

SW-3b

Open line or output short to GND detected

==> I

ODEC

≤ 0.5 x I

O

No error detected

==> I

ODEC

≥ 0.5 x I

O

SW-2 or

SW-3a

Short on LED or short to V-LED detected

==> V

O

≥ 2.4 V

No error detected

==> V

O

≤ 2.2 V

Where: I

O

= the output current programmed by the R

EXT

, I

ODEC

= the detected output current in detection mode.

20/34 DocID13093 Rev 8

STP16DP05

Figure 18: Detection circuit

Detection mode functionality

DocID13093 Rev 8 21/34

Detection mode functionality

Figure 19: Error detection sequence

STP16DP05

22/34 DocID13093 Rev 8

STP16DP05

8

Package information

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK ® is an ST trademark.

DocID13093 Rev 8 23/34

Package information

8.1 QSOP-24 package information

Figure 20: QSOP-24 package outline

STP16DP05

24/34 DocID13093 Rev 8

STP16DP05

Dim. c

D

E

E1

A

A1

A2 b e

L h

<

Table 15: QSOP-24 mechanical data mm

Min. Typ.

1.54

0.10

1.62

0.15

1.47

0.20

0.17

8.56

5.80

3.80

0.40

0.25

0°

8.66

6.00

3.91

0.635

0.635

0.33

Package information

Max.

1.73

0.25

0.31

0.254

8.76

6.20

4.01

0.89

0.41

8°

DocID13093 Rev 8 25/34

Package information

8.2 SO-24 package information

Figure 21: SO-24 package outline

STP16DP05

26/34 DocID13093 Rev 8

STP16DP05

8.3

Dim.

D

E e

H

A

A1

B

C h

L k ddd

Table 16: SO-24 mechanical data mm

Min. Typ.

2.35

0.10

0.33

0.23

15.20

7.40

1.27

10.00

0.25

0.40

0

TSSOP24 package information

Figure 22: TSSOP24 package outline

Package information

Max.

2.65

0.30

0.51

0.32

15.60

7.60

10.65

0.75

1.27

8

0.10

DocID13093 Rev 8 27/34

Package information

Dim. c

D

E e

A

A1

A2 b

H

K

L

0.05

0.19

0.09

7.7

4.3

6.25

0°

0.50

Table 17: TSSOP24 mechanical data mm

Min. Typ.

0.9

0.65 BSC

STP16DP05

Max.

1.1

0.15

0.30

0.20

7.9

4.5

6.5

8°

0.70

28/34 DocID13093 Rev 8

STP16DP05

8.4 TSSOP24 exposed pad package information

Package information

Figure 23: TSSOP24 exposed pad package outline

DocID13093 Rev 8 29/34

Package information

Dim.

E1

E2 e

L

L1 k aaa c

D

D1

E

A

A1

A2 b

STP16DP05

Table 18: TSSOP24 exposed pad mechanical data mm

Min. Typ.

0.80

0.19

0.09

7.70

4.80

6.20

4.30

3.00

0.45

0°

1.00

7.80

5.00

6.40

4.40

3.20

0.65

060

1.00

Max.

1.20

0.15

1.05

0.30

0.20

7.90

5.2

6.60

4.50

3.40

0.75

8°

0.10

30/34 DocID13093 Rev 8

STP16DP05

8.5

Package information

TSSOP24, TSSOP24 exposed pad and SO-24 packing information

Figure 24: TSSOP24, TSSOP24 exposed pad and SO-24 reel outline

Table 19: TSSOP24 and TSSOP24 exposed pad tape and reel mechanical data mm

Dim.

Min. Typ. Max.

A

C

D

N

T

Ao

Bo

Ko

Po

P

12.8

20.2

60

6.8

8.2

1.7

3.9

11.9

-

-

-

-

-

-

-

-

-

-

330

13.2

22.4

7

8.4

1.9

4.1

12.1

DocID13093 Rev 8 31/34

Package information

Dim.

T

Ao

Bo

Ko

A

C

D

N

Po

P

Table 20: SO-24 tape and reel mechanical data mm

Min. Typ.

12.8

20.2

60

10.8

15.7

2.9

3.9

11.9

-

-

-

-

-

-

-

-

-

-

STP16DP05

Max.

330

13.2

30.4

11.0

15.9

3.1

4.1

12.1

32/34 DocID13093 Rev 8

STP16DP05

9

Revision history

Revision history

Date Revision

Table 21: Document revision history

Changes

9-Jan-2007

21-May-2007

10-Jul-2007

28-Feb-2008

23-Oct-2009

20-Jan-2010

17-Jun-2014

07-Nov-2017

1

2

3

4

5

6

7

8

First release

Updated Table 7 on page 7

Updated Table 9: Truth table on page 11

Updated Table 15: TSSOP24 exposed-pad on page 23

Added QSOP-24 package information Table 14 and Figure 21 on page 24

Updated Figure 7 on page 11, Chapter 3 on page 7

Updated Table 5 on page 5

Updated Section 8: Package mechanical data.

Added Section 9: Packaging mechanical data.

Minor text changes.

Updated Figure 5: "SDO terminal" ,

Figure 8: "Clock, serial-in, serial-out" ,

Figure 9: "Clock, serial-in, latch, enable, outputs"

and Section 8:

"Package information" .

Minor text changes.

DocID13093 Rev 8 33/34

STP16DP05

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34/34 DocID13093 Rev 8