STMicroelectronics STGIPN3H60-H Datasheet
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STGIPN3H60-H
SLLIMM™-nano small low-loss intelligent molded module
IPM, 3 A, 600 V, 3-phase IGBT inverter bridge
Datasheet - production data
Applications
3-phase inverters for motor drives
Dish washers, refrigerator compressors, heating systems, air-conditioning fans, draining and recirculation pumps
Description
Features
IPM 3 A, 600 V, 3-phase IGBT inverter bridge including control ICs for gate driving and freewheeling diodes
Optimized for low electromagnetic interference
V
CE(sat)
negative temperature coefficient
3.3 V, 5 V, 15 V CMOS/TTL inputs comparators with hysteresis and pull down/pull up resistors
Undervoltage lockout
Internal bootstrap diode
Interlocking function
Smart shutdown function
Comparator for fault protection against overtemperature and overcurrent
Op amp for advanced current sensing
Optimized pinout for easy board layout
Table 1: Device summary
This intelligent power module implements a compact, high performance AC motor drive in a simple, rugged design. It is composed of six
IGBTs with freewheeling diodes and three halfbridge HVICs for gate driving, providing low electromagnetic interference (EMI) characteristics with optimized switching speed. The package is optimized for thermal performance and compactness in built-in motor applications, or other low power applications where assembly space is limited. This IPM includes an operational amplifier, completely uncommitted, and a comparator that can be used to design a fast and efficient protection circuit. SLLIMM™ is a trademark of STMicroelectronics.
Order code Marking Package Packing
STGIPN3H60-H GIPN3H60-H NDIP-26L Tube
September 2016 DocID024132 Rev 4
This is information on a product in full production.
1/23 www.st.com
Contents
Contents
STGIPN3H60-H
1 Internal schematic diagram and pin configuration ....................... 3
2 Electrical ratings ............................................................................. 6
Absolute maximum ratings ................................................................ 6
Thermal data ..................................................................................... 7
3 Electrical characteristics ................................................................ 8
Waveform definitions ....................................................................... 13
4 Smart shutdown function ............................................................. 14
5 Application circuit example .......................................................... 16
6 Package information ..................................................................... 18
NDIP-26L type C package information ............................................ 19
NDIP-26L packing information ........................................................ 21
7 Revision history ............................................................................ 22
2/23 DocID024132 Rev 4
STGIPN3H60-H
1
Internal schematic diagram and pin configuration
Internal schematic diagram and pin configuration
Figure 1: Internal schematic diagram
DocID024132 Rev 4 3/23
Internal schematic diagram and pin configuration
Table 2: Pin description
Pin Symbol Description
1 GND Ground
2
8
9
10
11
12
13
14
3
4
5
6
7
15
STGIPN3H60-H
SD / OD Shut down logic input (active low) / open drain (comparator output)
V
CC
W
HIN W
LIN W
OP+
OP
OUT
OP-
V
CC
V
HIN V
LIN V
CIN
V
CC
U
HIN U
Low voltage power supply W phase
High side logic input for W phase
Low side logic input for W phase
Op amp non inverting input
Op amp output
Op amp inverting input
Low voltage power supply V phase
High side logic input for V phase
Low side logic input for V phase
Comparator input
Low voltage power supply for U phase
High side logic input for U phase
SD / OD Shut down logic input (active low) / open drain (comparator output)
24
25
26
20
21
22
23
16
17
18
19
LIN U
V
BOOT
U
P
U, OUT
U
N
U
V
BOOT
V
V, OUT
V
N
V
Low side logic input for U phase
Bootstrap voltage for U phase
Positive DC input
U phase output
Negative DC input for U phase
Bootstrap voltage for V phase
V phase output
Negative DC input for V phase
V
BOOT
W Bootstrap voltage for W phase
W, OUT
W
W phase output
N
W
Negative DC input for W phase
4/23 DocID024132 Rev 4
STGIPN3H60-H
PIN26
Internal schematic diagram and pin configuration
Figure 2: Pin layout (top view)
(*) (*)
PIN17
PIN #1 ID
PIN1
(*) Dummy pin internally connected to P (positive DC input).
PIN16
AM09368V1
DocID024132 Rev 4 5/23
Electrical ratings
2
2.1
Electrical ratings
Absolute maximum ratings
Symbol
V
CES
± I
± I
P
TOT
Table 3: Inverter part
Parameter
Each IGBT collector emitter voltage (V
Each IGBT continuous collector current at T
C
= 25°C
Each IGBT pulsed collector current
Each IGBT total dissipation at T
C
= 25°C
Notes:
(1)
Applied between HIN i
, LIN i
and G
ND
for i = U, V, W.
(2)
Calculated according to the iterative formula:
STGIPN3H60-H
Value
600
3
18
8
Unit
V
A
A
W
(3)
Pulse width limited by max junction temperature.
Symbol
Table 4: Control part
Parameter
V
OUT
V
CC
Output voltage applied between OUT
U
, OUT
V
, OUT
W
-
GND
Low voltage power supply
V
CIN
Comparator input voltage
V op+
OPAMP non-inverting input
V op-
OPAMP inverting input
V boot
Bootstrap voltage
V
V
IN
Logic input voltage applied between HIN, LIN and GND
Open drain voltage
∆V
OUT/dT
Allowed output slew rate
Symbol
Table 5: Total system
Parameter
V
ISO
T j
T
C
Isolation withstand voltage applied between each pin and heatsink plate (AC voltage, t = 60 s.)
Power chips operating junction temperature range
Module operation case temperature range
Min.
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
21
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
620
15
15
50
Value
1000
Max.
V boot
- 21 V boot
+ 0.3 V
-40 to 150
-40 to 125
Unit
Unit
V
°C
°C
V
V
V
V
V
V
V
V/ns
6/23 DocID024132 Rev 4
STGIPN3H60-H
2.2 Thermal data
Symbol
R thJA
Table 6: Thermal data
Parameter
Thermal resistance junction-ambient
Electrical ratings
Value
50
Unit
°C/W
DocID024132 Rev 4 7/23
Electrical characteristics STGIPN3H60-H
3 Electrical characteristics
3.1 Inverter part
Symbol
V
CE(sat)
T
J
= 25 °C unless otherwise specified.
Parameter
Collector-emitter saturation voltage
Table 7: Static
Test conditions Min. Typ. Max. Unit
V
CC
= V boot
= 15 V, V
C
= 1 A -
V
CC
= V boot
= 15 V, V
C
= 1 A,
T
J
= 125 °C
-
2.15
1.65
2.6
V
I
CES
V
F
Collector-cut off current
(V
= 0 “logic state”)
Diode forward voltage
V
CE
= 550 V, V
CC
= V
Boot
= 15 V
V
= 0 “logic state”, I
C
= 1 A
-
-
250 µA
1.7 V
Notes:
(1)
Applied between HIN i
, LIN i
and G
ND
for i = U, V, W.
Symbol Parameter t
Turn-on time t
Crossover time (on) t
Turn-off time t
Crossover time (off) t rr
E on
Reverse recovery time
Turn-on switching energy
E off
Turn-off switching energy
Table 8: Inductive load switching time and energy
Test conditions Min. Typ. Max. Unit
I
V
DD
= 300 V,
V
CC
= V boot
= 15 V,
V
C
= 1 A
(see Figure 4: "Switching time definition" )
-
-
-
-
-
-
-
275
90
890
125
50
18
13
-
-
-
-
-
-
- ns
µJ
Notes:
(1) t
ON
and t
OFF
include the propagation delay time of the internal drive. t
C(ON)
and t
C(OFF)
are the switching time of IGBT itself under the internally given gate driving condition.
(2)
Applied between HIN i
, LIN i
and G
ND
for i = U, V, W.
8/23 DocID024132 Rev 4
STGIPN3H60-H
+5V
VCC
RSD
INPUT
Figure 3: Switching time test circuit
Lin
/SD
Hin
Vcc
DT
GND
BOOT
HVG
OUT
LVG
CP+
VBOOT>VCC
Electrical characteristics
L
IC
VCE
BUS
0
1
Figure 4: Switching time definition (1)
AM06019v3
Notes:
(1) Figure 4: "Switching time definition" refers to HIN, LIN inputs (active high).
DocID024132 Rev 4 9/23
Electrical characteristics
3.2 Control part
Symbol
STGIPN3H60-H
Table 9: Low voltage power supply (V
CC
= 15 V unless otherwise specified)
Parameter Test conditions Min. Typ. Max. Unit
V
CC_hys
V
CC
UV hysteresis
V
CC_thON
V
CC
UV turn ON threshold
V
CC_thOFF
V
CC
UV turn OFF threshold
I qccu
Undervoltage quiescent supply current
V
CC
= 10 V, SD /OD = 5 V, LIN = 0,
H
IN
= 0, C
IN
= 0
1.2 1.5 1.8 V
11.5 12 12.5 V
10 10.5 11 V
150 µA
I qcc
V ref
I
QBSU
Quiescent current
V cc
= 15 V, SD /OD = 5 V, LIN = 0,
H
IN
= 0, C
IN
= 0
1 mA
Internal comparator (CIN) reference voltage
0.5 0.54 0.58 V
Table 10: Bootstrapped voltage (V
CC
= 15 V unless otherwise specified)
Parameter Test conditions Min. Typ. Max. Unit Symbol
V
BS_hys
V
BS
UV hysteresis
V
BS_thON
V
BS
UV turn ON threshold
V
BS_thOFF
V
BS
UV turn OFF threshold
Undervoltage V
BS
quiescent current
V
BS
< 9 V, SD /OD = 5 V, LIN = 0,
HIN=5 V, C
IN
= 0
1.2 1.5 1.8 V
11.1 11.5 12.1 V
9.8 10 10.6 V
70 110 µA
I
QBS
V
BS
quiescent current
V
BS
=15 V, SD /OD = 5 V, LIN = 0,
HIN=5 V, C
IN
= 0
150 210 µA
R
DS(on)
Bootstrap driver onresistance
LVG ON 120
Ω
10/23 DocID024132 Rev 4
STGIPN3H60-H
Symbol Parameter
Electrical characteristics
Table 11: Logic inputs (V
CC
= 15 V unless otherwise specified)
Test conditions Min. Typ. Max. Unit
V il
V ih
I
HINh
I
HINI
I
LINh
I
LINI
Low logic level voltage
High logic level voltage
HIN logic “1” input bias current
HIN logic “0” input bias current
LIN logic “1” input bias current
LIN logic “0” input bias current
HIN = 15 V
HIN = 0 V
LIN = 15 V
LIN = 0 V
0.8 V
2.25 V
20 40 100 µA
1
20 40 100 µA
1
µA
µA
I
SDh
SD logic “0” input bias current
SD = 15 V 30 120 300 µA
I
SDI
SD logic “1” input bias current
SD = 0 V 3 µA
D t
Dead time
see Figure 5: "Dead time and interlocking waveform definitions"
180 ns
Symbol Parameter
V io
Table 12: OPAMP characteristics (V
CC
= 15 V unless otherwise specified)
Test condition Min. Typ. Max. Unit
Input offset voltage V ic
= 0 V, V o
= 7.5 V
I
I io ib
V icm
V
V
I
OL
OH o
Input offset current
Input common mode voltage range
Low level output voltage
High level output voltage
Output short-circuit current
V ic
= 0 V, V o
= 7.5 V
R
L
= 10 kΩ to V
CC
R
L
= 10 kΩ to GND
Source, V id
= + 1 V; V o
= 0 V
Sink, V id
= -1 V; V o
= V
CC
SR
GBWP
A vd
Slew rate
Gain bandwidth product
Large signal voltage gain
V
R i
L
= 1 - 4 V; C
V o
= 7.5 V
= 2 kΩ
SVR Supply voltage rejection ratio vs. V
CC
L
= 100 pF; unity gain
CMRR Common mode rejection ratio
Notes:
(1)
The direction of input current is out of the IC.
6 mV
4 40 nA
100 200 nA
0 V
75 150 mV
14 14.7 V
16 30 mA
50 80 mA
2.5 3.8 V/µs
8 12 MHz
70 85 dB
60 75 dB
55 70 dB
DocID024132 Rev 4 11/23
Electrical characteristics STGIPN3H60-H
Table 13: Sense comparator characteristics (V
CC
= 15 V unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
I ib
V ol
Input bias current V
CIN
= 1 V
Open drain low level output voltage I od
= 3 mA
3
0.5
µA
V t d_comp
Comparator delay
SR t sd t isd
Slew rate
Shutdown to high / low side driver propagation delay
Comparator triggering to high / low side driver turn-off propagation delay
SD /OD pulled to 5 V through
100 kΩ resistor
C
L
= 180 pF; R pu
= 5 kΩ
V
OUT
= 0, V boot
= V
CC
, V
IN
= 0 to
3.3 V
Measured applying a voltage step from 0 V to 3.3 V to pin CIN
Table 14: Truth table
Logic input (V
I
)
Condition
SD /OD
90 130
60
50 125 200
50 200 250 ns
V/µsec ns
Output
LIN HIN LVG HVG
Shutdown enable half-bridge tri-state
Interlocking half-bridge tri-state
0 “logic state” half-bridge tri-state
1 “logic state” low side direct driving
1
“logic state” high side direct driving
L
H
H
H
H
H
L
H
L
H
L
L
H
L
L
L
H
L
L
L
L
L
H
Notes:
(1) X: don’t care.
12/23 DocID024132 Rev 4
STGIPN3H60-H
3.3 Waveform definitions
Electrical characteristics
Figure 5: Dead time and interlocking waveform definitions
DocID024132 Rev 4 13/23
Smart shutdown function
4 Smart shutdown function
STGIPN3H60-H
The STGIPN3H60-H integrates a comparator for fault sensing purposes. The comparator has an internal voltage reference V
REF
connected to the inverting input, while the noninverting input, available on pin (CIN), can be connected to an external shunt resistor in order to implement a simple over-current protection function. When the comparator triggers, the device is set in shutdown state and both its outputs are set to low-level leading the halfbridge in tri-state. In the common overcurrent protection architectures the comparator output is usually connected to the shutdown input through a RC network, in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. Our smart shutdown architecture allows to immediately turn-off the output gate driver in case of overcurrent, the fault signal has a preferential path which directly switches off the outputs. The time delay between the fault and the outputs turn-off is no more dependent on the RC values of the external network connected to the shutdown pin.
At the same time the DMOS connected to the open-drain output is turned on by the internal logic which holds it on until the shutdown voltage is lower than the logic input lower threshold (V il
). Finally, the smart shutdown function provides the possibility to increase the real disable time without increasing the constant time of the external RC network.
14/23 DocID024132 Rev 4
STGIPN3H60-H comp Vref
Smart shutdown function
Figure 6: Smart shutdown timing waveforms
C P+
H IN /LIN
H VG/LVG
SD /OD
PROTECTION open drain gate
(internal) disable tim e
Fast shut down : the driver outputs are set in SD state im m ediately after the com parator triggering even if the SD signal has not yet reach the low er input threshold
An approximation of the disable time is given by:
V
BIAS
SHUT DOW N CIRCUIT
F ROM /T O
CONT ROLLER
R
S D
SD/OD
C
S D
R
ON_OD
R
PD_SD
S M A RT
S D
LOGIC where:
AM12947v1
DocID024132 Rev 4 15/23
Application circuit example
5 Application circuit example
Figure 7: Application circuit example
STGIPN3H60-H
16/23
AM09367v1
Application designers are free to use a different scheme according with the specifications of the device.
DocID024132 Rev 4
STGIPN3H60-H
5.1 Guidelines
Application circuit example
Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull down resistor is builtin for each input. If an external RC filter is used, for noise immunity, pay attention to the variation of the input signal level.
To prevent input signal oscillation, the wiring of each input should be as short as possible.
By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals without an opto-coupler is possible.
Each capacitor should be located as close as possible to the pins of the IPM.
Low inductance shunt resistors should be used for phase leg current sensing.
Electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. Additional high frequency ceramic capacitors mounted close to the module pins will further improve performance.
The SD /OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see
Section 4: "Smart shutdown function" for detailed info).
These guidelines are useful for application design to ensure the specifications of the device. For further details, please refer to the relevant application note AN4043.
Symbol
Table 15: Recommended operating conditions
Parameter Test conditions Min. Typ. Max. Unit
V
PN
V
CC
V
BS
Supply voltage
Control supply voltage
High side bias voltage
Applied between P-Nu, Nv, Nw
Applied between V
CC
-GND
Applied between V
BOOTi
-OUT i for i = U, V, W
300 500
13.5 15 18
13 18
V
V
V t dead
Blanking time to prevent
Arm-short
For each input signal 1.5 µs f
PWM
PWM input signal
-40°C < T c
< 100 °C
-40°C < T j
< 125 °C
25 kHz
T
C
Case operation temperature
100 °C
DocID024132 Rev 4 17/23
Package information
6 Package information
STGIPN3H60-H
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
18/23 DocID024132 Rev 4
STGIPN3H60-H
6.1 NDIP-26L type C package information
Figure 8: NDIP-26L type C package outline
Package information
DocID024132 Rev 4
8278949_7
19/23
Package information
Dim. b3 c c1
D
D1
D2
D3
A4 b b1 b2
A
A1
A2
A3
E e e1 eB1 eB2
L
Table 16: NDIP-26L type C mechanical data mm
Min. Typ.
0.82
0.46
0.45
29.05
0.50
0.35
0.80
3.00
1.70
5.70
0.53
0.52
0.83
12.35
1.70
2.40
16.10
21.18
1.24
0.90
0.50
29.15
0.77
0.53
12.45
1.80
2.50
16.40
21.48
1.39
1.00
3.10
1.80
5.90
0.60
STGIPN3H60-H
Max.
0.98
0.59
0.55
29.25
1.00
0.70
29.55
4.40
1.20
3.20
1.90
6.10
0.72
0.68
1.02
12.55
1.90
2.60
16.70
21.78
1.54
20/23 DocID024132 Rev 4
STGIPN3H60-H
6.2 NDIP-26L packing information
Package information
Figure 9: NDIP-26L tube dimensions (dimensions are in mm)
Notes:
Parameter
Base quantity
Bulk quantity
Table 17: Shipping details
Value
17 pcs
476 pcs
8313150_3
DocID024132 Rev 4 21/23
Revision history
7
STGIPN3H60-H
Revision history
Date Revision
Table 18: Document revision history
Changes
15-Jan-2013
02-May-2013
14-Mar-2014
08-Sep-2016
1
2
3
4
Initial release.
Modified: Figure 3 on page 8 , Section 4 on page 14 and Figure 6 on page 15 .
Updated Figure 3: Switching time test circuit, Table 9: Bootstrapped voltage (VCC = 15 V unless otherwise specified) and Table 10: Logic inputs (VCC = 15 V unless otherwise specified).
Updated Section 6: Package mechanical data.
Updated Section 6.1: "NDIP-26L type C package information" and
Section 6.2: "NDIP-26L packing information"
Minor text changes
22/23 DocID024132 Rev 4
STGIPN3H60-H
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2016 STMicroelectronics
– All rights reserved
DocID024132 Rev 4 23/23
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