STI40N65M2, STP40N65M2
Nchannel 650 V, 0.087 Ω typ., 32 A MDmesh™ M2
Power MOSFET in I²PAK and TO-220 packages
Datasheet - production data
TAB
I²PAK
G(1)
TAB
1
2
3
TO-220
1
2
3
Figure 1: Internal schematic diagram
D(2, TAB)
Features
Order code V
DS
R
DS(on)
max. I
D
STI40N65M2
650 V
0.099 Ω
32 A
STP40N65M2
•
Extremely low gate charge
•
Excellent output capacitance (C
OSS
) profile
•
100% avalanche tested
•
Zener-protected
Applications
•
Switching applications
Description
These devices are N-channel Power MOSFETs developed using MDmesh™ M2 technology.
Thanks to their strip layout and improved vertical structure, the devices exhibit low on-resistance and optimized switching characteristics, rendering them suitable for the most demanding high efficiency converters.
Order code
STI40N65M2
STP40N65M2
S(3) AM15572v1_tab
Table 1: Device summary
Marking Package
40N65M2
I²PAK
TO-220
Packaging
Tube
February 2015 DocID027478 Rev 1
This is information on a product in full production.
1/14 www.st.com
Contents
Contents
STI40N65M2, STP40N65M2
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.2
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
4.2
I²PAK package information ............................................................... 9
TO-220 type A package information ................................................ 11
5 Revision history ............................................................................ 13
2/14 DocID027478 Rev 1
STI40N65M2, STP40N65M2
1 Electrical ratings
Symbol
V
GS
I
D
I
D
I
DM
(1)
P
TOT
dv/dt
(2) dv/dt
(3)
T stg
T j
Table 2: Absolute maximum ratings
Parameter
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Storage temperature
Max. operating junction temperature
Notes:
(1)
Pulse width limited by safe operating area.
(2)
I
SD
≤ 32 A, di/dt ≤ 400 A/µs; V
DS peak
< V
(BR)DSS
, V
DD
= 400 V
(3)
V
DS
≤ 520 V
Symbol
Table 3: Thermal data
Parameter
R thj-case
R thj-amb
Thermal resistance junction-case max
Thermal resistance junction-ambient max
Symbol
I
AR
E
AS
Table 4: Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive (pulse width limited by T jmax
)
Single pulse avalanche energy (starting T j
= 25 °C,
I
D
= I
AR
, V
DD
= 50 V)
Electrical ratings
Value
± 25
32
20
128
250
15
50
- 55 to 150
150
Unit
V
A
A
A
W
V/ns
V/ns
°C
Value
0.5
62.50
Value
3
820
Unit
°C/W
°C/W
Unit
A mJ
DocID027478 Rev 1 3/14
Electrical characteristics
2 Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Table 5: On/off states
Symbol Parameter Test conditions
V
(BR)DSS
V
GS
= 0 V, I
D
= 1 mA
I
DSS
Zero gate voltage Drain current
V
GS
= 0 V, V
DS
= 650 V
V
GS
= 0 V, V
DS
= 650 V,
T
C
= 125 °C
I
GSS
Gate-body leakage current V
DS
= 0 V, V
GS
= ± 25 V
V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source onresistance
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 16 A
Symbol
Drain-source breakdown voltage
Parameter
Table 6: Dynamic
Test conditions
C
C
C
R oss
Q
Q
Q iss rss
G g gs gd
C
oss eq.
(1)
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent output capacitance
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
V
DS
= 0 V to 520 V,
V
GS
= 0 V f = 1 MHz, open drain
V
DD
= 520 V, I
D
= 32 A,
V
GS
= 10 V (see Figure 15:
"Gate charge test circuit" )
STI40N65M2, STP40N65M2
Min
.
Typ. Max. Unit
650 V
1 µA
100 µA
3
±10 µA
4 V
0.087 0.099
Ω
2
Min. Typ. Max. Unit
-
-
2355
102
-
- pF pF
- 2.7 - pF
-
-
-
-
-
380
4.5
56.5
8
24
-
-
-
-
-
Notes:
(1)
C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to 80% V
DSS
Symbol Parameter
Table 7: Switching times
Test conditions Min. Typ. Max. Unit t d(on) t r t d(off) t f
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
V
DD
= 325 V, I
D
= 16 A
R
G
= 4.7
Ω, V
GS
= 10 V (see
Figure 14: "Switching times test circuit for resistive load" and Figure 19: "Switching time waveform" )
-
-
-
-
15
10
96.5
12
-
-
-
- ns ns ns ns pF
Ω nC nC nC
4/14 DocID027478 Rev 1
STI40N65M2, STP40N65M2
Symbol
I
RRM
Parameter
I
SD
I
SDM
(1)
Source-drain current
(pulsed)
V
SD
(2)
Forward on voltage t rr
Q rr
Source-drain current
Reverse recovery time
Reverse recovery charge
Table 8: Source drain diode
Test conditions
Reverse recovery current
V
GS
= 0 V, I
SD
= 32 A
I
SD
= 32 A, di/dt = 100 A/µs,
V
DD
= 60 V (see Figure 16: "
Test circuit for inductive load switching and diode recovery times" )
t rr
Q rr
I
RRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 32 A, di/dt = 100 A/µs,
V
DD
= 60 V, T j
= 150 °C (see
Figure 16: " Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
- 32 A
- 128 A
-
-
-
468
8.7
1.6 V ns
µC
- 37.5 A
-
-
610
11.7 ns
µC
- 39 A
Notes:
(1)
Pulse width is limited by safe operating area
(2)
Pulse test: pulse duration = 300 µs, duty cycle 1.5%
DocID027478 Rev 1 5/14
Electrical characteristics
2.2 Electrical characteristics (curves)
I
D
(A)
Figure 2: Safe operating area
GIPG090220151652ALS
STI40N65M2, STP40N65M2
K
Figure 3: Thermal impedance
GC20540
δ=0.5
100
10
1
0.1
0.1
s n t hi s ar ax
R ea i
S( on)
D at ion i
O per lim ited b y m
T j
= 150 °C
T c
= 25 °C
Single pulse
1 10 100
10µs
100µs
1ms
10ms
V
DS
(V)
I
D
(A)
70
Figure 4: Output characteristics
GIPG300120151500ALS
V
GS
= 6,7,8,9,10 V
V
GS
= 5 V
60
50
40
30
20
V
GS
= 4 V
10
0
0 4 8 12 16 20 24
Figure 6: Normalized gate threshold voltage vs temperature
0.2
0.1
10 -1
0.05
0.02
10 -2
10 -5
0.01
Single pulse
10 -4 10 -3 10 -2
Zth= K*Rthj-c
δ= tp/ Ƭ tp
Ƭ
10 -1 t
P
(s)
Figure 5: Transfer characteristics
I
D
(A)
70
GIPG300120151715ALS
60
50
40
30
20
10
0
0
V
GS
= 20 V
2 4 6 8 V
GS
(V)
Figure 7: Normalized V(BR)DSS vs temperature
6/14 DocID027478 Rev 1
STI40N65M2, STP40N65M2
Figure 8: Static drain-source on-resistance
Electrical characteristics
Figure 9: Normalized on-resistance vs. temperature
Figure 10: Gate charge vs. gate-source voltage
Figure 11: Capacitance variations
Figure 12: Output capacitance stored energy
Figure 13: Source-drain diode forward characteristics
DocID027478 Rev 1 7/14
Test circuits
3 Test circuits
Figure 14: Switching times test circuit for resistive load
STI40N65M2, STP40N65M2
Figure 15: Gate charge test circuit
12 V 47 k
Ω
100 nF
1 k
Ω
V
DD
V i
≤ V
GS
2200 μ F
I
G
= CONST
2.7 k
Ω
47 k
Ω
1 k
Ω
P
W
100 Ω
D.U.T.
V G
AM01469v 1
Figure 16: Test circuit for inductive load switching and diode recovery times
Figure 17: Unclamped inductive load test circuit
25
Ω
G
A
D
D.U.T.
S
B
R
G
A
FAST
DIODE
A
B
B
L=100 µH
G
D
D.U.T.
S
3.3
µF
1000
µF
V
DD
V
DD
I
D
AM01470v1
Figure 18: Unclamped inductive waveform
V
(BR)DSS
I
DM
V
D
V
DD
AM01472v 1
0
Figure 19: Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
10% V
DS
V
GS
90%
0
10% AM01473v 1
8/14 DocID027478 Rev 1
STI40N65M2, STP40N65M2
4
4.1
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
I²PAK package information
Figure 20: I²PAK package outline
0004982_Rev_H
DocID027478 Rev 1 9/14
Package information
Dim. e1
E
L
L1
L2 c c2
D e
A
A1 b b1
Table 9: I²PAK mechanical data mm
Min. Typ.
4.95
10
13
3.50
1.27
4.40
2.40
0.61
1.14
0.49
1.23
8.95
2.40
–
–
–
–
–
–
–
–
–
–
–
–
–
STI40N65M2, STP40N65M2
Max.
4.60
2.72
0.88
1.70
0.70
1.32
9.35
2.70
5.15
10.40
14
3.93
1.40
10/14 DocID027478 Rev 1
STI40N65M2, STP40N65M2
4.2 TO-220 type A package information
Figure 21: TO-220 type A package outline
Package information
DocID027478 Rev 1 11/14
Package information
Dim. e1
F
H1
J1
L
L1
L20
D
D1
E e
A b b1 c
L30
øP
Q
STI40N65M2, STP40N65M2
Table 10: TO-220 type A mechanical data mm
Typ. Min.
4.40
0.61
1.14
0.48
15.25
Max.
4.60
0.88
1.70
0.70
15.75
1.27
10
2.40
4.95
1.23
6.20
2.40
13
3.50
10.40
2.70
5.15
1.32
6.60
2.72
14
3.93
16.40
28.90
3.75
2.65
3.85
2.95
12/14 DocID027478 Rev 1
STI40N65M2, STP40N65M2
5
Revision history
Revision history
Date
09-Feb-2014
Table 11: Document revision history
Revision
1
Changes
First release.
DocID027478 Rev 1 13/14
STI40N65M2, STP40N65M2
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14/14 DocID027478 Rev 1
