STP10LN80K5
Nchannel 800 V, 0.55 Ω typ., 8 A MDmesh™ K5
Power MOSFET in a TO-220 package
Datasheet - production data
Figure 1: Internal schematic diagram
Features
Order code V
DS
R
DS(on)
max.
STP10LN80K5 800 V 0.63 Ω
Industry’s lowest R
DS(on)
x area
Industry’s best figure of merit (FoM)
Ultra-low gate charge
100% avalanche tested
Zener-protected
I
D
8 A
Applications
Switching applications
Description
This very high voltage N-channel Power
MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
Order code
STP10LN80K5
Table 1: Device summary
Marking
10LN80K5
Package
TO-220
Packing
Tube
December 2015 DocID027747 Rev 2
This is information on a product in full production.
1/14 www.st.com
Contents
Contents
STP10LN80K5
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 9
4 Package information ..................................................................... 10
4.1
TO-220 type A package information ................................................ 11
5 Revision history ............................................................................ 13
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STP10LN80K5
1
Electrical ratings
Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
GS
I
D
I
D
I
DM
(1)
P
TOT
dv/dt
(2) dv/dt
(3)
T j
T stg
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Operating junction temperature
Storage temperature
Notes:
(1)
Pulse width limited by safe operating area
(2)
I
SD
≤ 8 A, di/dt 100 A/μs; V
DS
peak < V
(BR)DSS
, V
DD
= 640 V
(3)
V
DS
≤ 640 V
Symbol
Table 3: Thermal data
Parameter
R thj-case
R thj-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
Symbol
I
AR
E
AS
Table 4: Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive (pulse width limited by T jmax
)
Single pulse avalanche energy (starting T j
= 25 °C, I
D
= I
AR
,
V
DD
= 50 V)
Value
± 30
8
5
32
110
4.5
50
- 55 to 150
Value
1.14
62.5
Value
2.7
240
°C
Unit
°C/W
°C/W
Unit
A mJ
Unit
V
A
A
A
W
V/ns
DocID027747 Rev 2 3/14
Electrical characteristics
2 Electrical characteristics
T
C
= 25 °C unless otherwise specified
Symbol Parameter
Table 5: On/off-state
Test conditions
V
(BR)DSS
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 1 mA
I
DSS
I
GSS
Zero gate voltage drain current
Gate body leakage current
V
GS(th)
Gate threshold voltage
V
GS
= 0 V, V
DS
= 800 V
V
GS
= 0 V, V
DS
= 800 V
T
C
= 125 °C
V
DS
= 0 V, V
GS
= ±20 V
V
DD
= V
GS
, I
D
= 100 µA
R
DS(on)
Static drain-source on-resistance V
GS
= 10 V, I
D
= 4 A
Symbol Parameter
Table 6: Dynamic
Test conditions
C iss
C oss
C rss
C
o(tr)
(1)
C
o(er)
(2)
R g
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent capacitance time related
Equivalent capacitance energy related
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
V
DS
= 0 to 640 V,
V
GS
= 0 V f = 1 MHz , I
D
= 0 A
V
DD
= 640 V, I
D
= 8 A
V
GS
= 10 V
See Figure 16: "Test circuit for gate charge behavior"
-
-
-
-
STP10LN80K5
Min. Typ. Max. Unit
800 V
1 µA
50 µA
±10 µA
4 5 V
0.55 0.63
Ω
3
Min. Typ. Max. Unit
-
-
-
427
43
0.25
-
-
- pF pF pF
-
72
27
7
15
4.2
9
-
-
-
-
-
- pF pF
Ω nC nC nC
Notes:
(1)
Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when V
DS increases from 0 to 80% V
DSS
(2)
Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when
V
DS
increases from 0 to 80% V
DSS
Symbol Parameter t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time t f
Fall time
Table 7: Switching times
Test conditions
V
DD
= 400 V, I
D
= 4 A, R
G
= 4.7 Ω
V
GS
= 10 V
See Figure 15: "Test circuit for resistive load switching times" and Figure 20: "Switching time waveform"
Min. Typ. Max. Unit
-
-
-
-
11.8
10
28
13
-
-
-
- ns ns ns ns
4/14 DocID027747 Rev 2
STP10LN80K5
Symbol Parameter
I
SD
Source-drain current
I
SDM
(1)
Source-drain current
(pulsed)
V
SD
(2)
Forward on voltage t rr
Q rr
Reverse recovery time
Reverse recovery charge
I
RRM
Reverse recovery current
Table 8: Source-drain diode
Test conditions
I
I
SD
= 8 A, V
GS
= 0 V
SD
= 8 A, di/dt = 100 A/µs,V
60 V
DD
=
See Figure 17: "Test circuit for inductive load switching and diode recovery times"
Electrical characteristics
Min. Typ. Max. Unit
- 8 A
- 32 A
- 1.5 V
-
-
-
350
3.9
22.5 ns
µC
A t rr
- 505 ns
Q rr
I
RRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 8 A, di/dt = 100 A/µs V
DD
=
60 V, T j
= 150 °C
See Figure 17: "Test circuit for inductive load switching and diode recovery times"
-
-
5
20
µC
A
Notes:
(1)
Pulse width limited by safe operating area
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Symbol
Table 9: Gate-source Zener diode
Parameter Test conditions Min. Typ. Max. Unit
V
(BR)GSO
Gate-source breakdown voltage I
GS
= ± 1mA,I
D
= 0 A 30 - - V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry.
DocID027747 Rev 2 5/14
Electrical characteristics
2.2 Electrical characteristics (curves)
Figure 2: Safe operating area
STP10LN80K5
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
6/14 DocID027747 Rev 2
STP10LN80K5
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs temperature
Figure 10: Normalized on-resistance vs temperature
Figure 11: Normalized V
(BR)DSS
vs temperature
Figure 12: Output capacitance stored energy Figure 13: Source-drain diode forward characteristics
DocID027747 Rev 2 7/14
Electrical characteristics
Figure 14: Output capacitance stored energy
STP10LN80K5
8/14 DocID027747 Rev 2
STP10LN80K5
3 Test circuits
Figure 15: Test circuit for resistive load switching times
Test circuits
Figure 16: Test circuit for gate charge behavior
Figure 17: Test circuit for inductive load switching and diode recovery times
Figure 18: Unclamped inductive load test circuit
Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform
DocID027747 Rev 2 9/14
Package information
4 Package information
STP10LN80K5
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
10/14 DocID027747 Rev 2
STP10LN80K5
4.1 TO-220 type A package information
Figure 21: TO-220 type A package outline
Package information
DocID027747 Rev 2 11/14
Package information
Dim. e1
F
H1
J1
L
L1
L20
D
D1
E e
A b b1 c
L30
øP
Q
Table 10: TO-220 type A mechanical data mm
Min. Typ.
4.40
0.61
1.14
0.48
15.25
1.27
10
2.40
4.95
1.23
6.20
2.40
13
3.50
16.40
28.90
3.75
2.65
STP10LN80K5
10.40
2.70
5.15
1.32
6.60
2.72
14
3.93
3.85
2.95
Max.
4.60
0.88
1.70
0.70
15.75
12/14 DocID027747 Rev 2
STP10LN80K5
5
Revision history
Revision history
Date Revision
Table 11: Document revision history
Changes
10-Jun-2015
14-Dec-2015
1
2
First release.
Datasheet promoted from preliminary data to production data
Modified: Table 2: "Absolute maximum ratings" , Table 3: "Thermal data" , Table 4: "Avalanche characteristics" ,
Table 5: "On/off-state" ,
Table 6: "Dynamic" ,
Figure 2: "Safe operating area" , Figure 3: "Thermal impedance" , Figure 4: "Output characteristics" and Figure 7: "Static drain-source on-resistance"
Minor text changes
DocID027747 Rev 2 13/14
STP10LN80K5
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14/14 DocID027747 Rev 2
