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STF17N80K5
Nchannel 800 V, 0.29 Ω typ., 14 A MDmesh™ K5
Power MOSFET in a TO-220FP package
Datasheet - production data
TO-220FP
Figure 1: Internal schematic diagram
D(2)
G(1)
Features
Order code V
DS
R
DS(on)
max.
STF17N80K5 800 V 0.34 Ω
Industry’s lowest R
DS(on)
x area
Industry’s best figure of merit (FoM)
Ultra-low gate charge
100% avalanche tested
Zener-protected
I
D
14 A
Applications
Switching applications
Description
This very high voltage N-channel Power
MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
Order code
STF17N80K5
S(3)
AM15572v1_no_tab
Table 1: Device summary
Marking Package
17N80K5 TO-220FP
Packing
Tube
January 2016 DocID027695 Rev 2
This is information on a product in full production.
1/13 www.st.com
Contents
Contents
STF17N80K5
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
Electrical characteristics (curves) ...................................................... 6
4 Package information ....................................................................... 9
TO-220 FP package information ..................................................... 10
5 Revision history ............................................................................ 12
2/13 DocID027695 Rev 2
STF17N80K5
1 Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
I
V
GS
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
I
Drain current (continuous) at T
C
= 100 °C
I
Drain current (pulsed)
P
TOT
Total dissipation at T
C
= 25 °C
V
ISO
Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1 s; T
C
=25 °C)
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
T
J
T stg
Operating junction temperature range
Storage temperature range
Notes:
(1)
Limited by maximum junction temperature.
(2)
Pulse width limited by safe operating area
(3)
I
SD
≤ 14 A, di/dt 100 A/μs; V
DS
peak < V
(BR)DSS,
V
DD
= 400 V
(4)
V
DS
≤ 640 V
Symbol
Table 3: Thermal data
Parameter
R thj-case
R thj-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
Symbol
I
AR
E
AS
Table 4: Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive (pulse width limited by T jmax
)
Single pulse avalanche energy (starting Tj = 25 °C, I
D
= I
AR
,
V
DD
= 50 V)
Electrical ratings
Value
± 30
14
9
56
30
2500
4.5
50
- 55 to 150
V/ns
°C
Unit
V
A
A
A
W
V
Value
4.2
62.5
Unit
°C/W
°C/W
Value
4.7
340
Unit
A mJ
DocID027695 Rev 2 3/13
Electrical characteristics
2 Electrical characteristics
T
C
= 25 °C unless otherwise specified
Symbol Parameter
Table 5: On/off-state
Test conditions
V
(BR)DSS
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 1 mA
I
DSS
I
GSS
Zero gate voltage drain current
Gate body leakage current
V
GS(th)
Gate threshold voltage
V
GS
= 0 V, V
DS
= 800 V
V
GS
= 0 V, V
DS
= 800 V
T
C
= 125 °C
V
DS
= 0 V, V
GS
= ±25 V
V
DD
= V
GS
, I
D
= 250 µA
R
DS(on)
Static drain-source on-resistance V
GS
= 10 V, I
D
= 7 A
Symbol Parameter
Table 6: Dynamic
Test conditions
C iss
C oss
C rss
C
C
R g
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent capacitance time related
Equivalent capacitance energy related
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
V
DS
= 0 to 640 V,
V
GS
= 0 V f = 1 MHz , I
D
= 0 A
V
DD
= 640 V, I
D
= 14 A
V
GS
= 10 V
See ( Figure 15: "Test circuit for gate charge behavior" )
STF17N80K5
Min. Typ. Max. Unit
800 V
1 µA
50 µA
±10 µA
4 5 V
0.29 0.34
Ω
3
Min. Typ. Max. Unit
-
-
-
866
64
0.42
-
-
- pF pF pF
-
-
-
-
-
-
142
51
5
26
7.2
15.2
-
-
-
-
-
- pF
Notes:
(1)
Time related is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to 80% V
DSS
(2)
Energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss
when V
DS increases from 0 to 80% V
DSS
Symbol Parameter
Table 7: Switching times
Test conditions t t d(on)
Turn-on delay time V
DD
= 400 V, I
D
=7 A, R
G
= 4.7 Ω t r
Rise time
V
GS
= 10 V d(off) t f
Turn-off delay time
Fall time
See ( Figure 14: "Test circuit for resistive load switching times" and
Figure 19: "Switching time waveform" )
Min. Typ. Max. Unit
-
-
-
-
14.8
10.8
84.3
10.1
-
-
-
- ns ns ns ns pF
Ω nC nC nC
4/13 DocID027695 Rev 2
STF17N80K5
Symbol t rr
Q rr
Parameter
I
SD
Source-drain current
I
Source-drain current
(pulsed)
V
Forward on voltage
Reverse recovery time
Reverrse recovery charge
I
RRM
Table 8: Source-drain diode
Test conditions
Reverse recovery current
I
I
SD
= 14 A, V
GS
= 0 V
SD
= 14 A, di/dt = 100 A/µs,V
= 60 V
DD
See Figure 16: "Test circuit for inductive load switching and diode recovery times"
Electrical characteristics
Min. Typ. Max. Unit
-
-
-
-
-
-
439
6.37
29
14
56
1.6
A
A
V ns
µC
A t rr
Q rr
I
RRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 14 A, di/dt = 100 A/µs V
DD
= 60 V, T j
= 150 °C
See Figure 16: "Test circuit for inductive load switching and diode recovery times"
-
-
-
626
8.36
26.7 ns
µC
A
Notes:
(1)
Pulse width limited by safe operating area
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Symbol
Table 9: Gate-source Zener diode
Parameter Test conditions Min. Typ. Max. Unit
V
(BR)GSO
Gate-source breakdown voltage I
GS
= ± 1mA, I
D
= 0 A 30 - - V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry.
DocID027695 Rev 2 5/13
Electrical characteristics
2.2 Electrical characteristics (curves)
Figure 2: Safe operating area
STF17N80K5
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
6/13
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
DocID027695 Rev 2
STF17N80K5
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs temperature
Figure 10: Normalized on-resistance vs temperature
Figure 11: Normalized V
(BR)DSS
vs temperature
Figure 12: Source-drain diode forward characteristics
Figure 13: Maximum avalanche energy vs starting T
J
DocID027695 Rev 2 7/13
Test circuits
3 Test circuits
Figure 14: Test circuit for resistive load switching times
STF17N80K5
Figure 15: Test circuit for gate charge behavior
Figure 16: Test circuit for inductive load switching and diode recovery times
Figure 17: Unclamped inductive load test circuit
Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform
8/13 DocID027695 Rev 2
STF17N80K5
4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
DocID027695 Rev 2 9/13
Package information
4.1 TO-220 FP package information
Figure 20: TO-220FP package outline
STF17N80K5
10/13 DocID027695 Rev 2
STF17N80K5
Dim.
G1
H
L2
L3
L4
L5
L6
L7
Dia
F
F1
F2
G
A
B
D
E
Table 10: TO-220FP package mechanical data mm
Min. Typ.
Package information
Max.
4.4
2.5
2.5
0.45
0.75
1.15
1.15
4.95
2.4
10
16
4.6
2.7
2.75
0.7
1
1.70
1.70
5.2
2.7
10.4
28.6
9.8
2.9
15.9
9
3
30.6
10.6
3.6
16.4
9.3
3.2
DocID027695 Rev 2 11/13
Revision history
5
STF17N80K5
Revision history
Date Revision
Table 11: Document revision history
Changes
31-Mar-2015
20-Jan-2016
1
2
First release.
Modified: Table 4: "Avalanche characteristics" ,
, and Table 8: "Source-drain diode"
Added: Section 3.1: "Electrical characteristics (curves)"
Minor text changes
12/13 DocID027695 Rev 2
STF17N80K5
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DocID027695 Rev 2 13/13
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