STF7N105K5
Nchannel 1050 V, 1.4 Ω typ., 4 A MDmesh™ K5
Power MOSFET in TO-220FP package
Datasheet - production data
TO-220FP
Figure 1: Internal schematic diagram
D(2)
G(1)
Features
Order code V
DS
R
DS(on)
max. I
D
P
TOT
STF7N105K5 1050 V 2.0 Ω 4 A 25 W
Industry’s lowest R
DS(on)
x area
Industry’s best FoM (figure of merit)
Ultra-low gate charge
100% avalanche tested
Zener-protected
Applications
Switching applications
Description
This very high voltage N-channel Power
MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
Order code
STF7N105K5
S(3)
AM15572v1_no_tab
Table 1: Device summary
Marking Package
7N105K5 TO-220FP
Packaging
Tube
June 2016 DocID026184 Rev 2
This is information on a product in full production.
1/14 www.st.com
Contents
Contents
STF7N105K5
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 9
4 Package information ..................................................................... 10
4.1
TO-220FP package information ...................................................... 11
5 Revision history ............................................................................ 13
2/14 DocID026184 Rev 2
STF7N105K5
1
Electrical ratings
Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
GS
E
AS
Gate- source voltage
I
D
Drain current (continuous) at T
C
= 25 °C
I
D
Drain current (continuous) at T
C
= 100 °C
I
DM
(2)
Drain current (pulsed)
P
TOT
Total dissipation at T
C
= 25 °C
I
AR
Max. current during repetitive or single pulse avalanche
Single pulse avalanche energy
(starting T
J
= 25 °C, I
D
=I
AR
, V
DD
= 50 V)
V
ISO
Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; T
C
= 25 °C)
dv/dt (3)
Peak diode recovery voltage slope
dv/dt (4)
MOSFET dv/dt ruggedness
T j
T stg
Operating junction temperature range
Storage temperature range
Notes:
(1)
Limited by package.
(2)
Pulse width limited by safe operating area.
(3)
I
SD
≤ 4 A, di/dt ≤ 100 A/µs, V
DS(peak)
≤ V
(BR)DSS
; V
SD
≤ 840 V
(4)
V
DS
≤ 840 V
Symbol
Table 3: Thermal data
Parameter
R thj-case
R thj-amb
Thermal resistance junction-case max
Thermal resistance junction-amb max
2500
4.5
50
- 55 to 150
Value
5
62.5
Value
± 30
4 (1)
3 (1)
16
25
1.5
132
V
V/ns
V/ns
°C
Unit
°C/W
°C/W
Unit
V
A
A
A
W
A mJ
DocID026184 Rev 2 3/14
Electrical characteristics
2 Electrical characteristics
(T
CASE
= 25 °C unless otherwise specified).
Symbol Parameter
Table 4: On/off states
Test conditions
V
(BR)DSS
I
DSS
Drain-source breakdown voltage
V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 1050 V
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 1050 V,
T
C
=125 °C (1)
Gate body leakage current V
DS
= 0, V
GS
= ± 20 V I
GSS
V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source on- resistance
V
V
DS
GS
= V
GS
, I
D
= 10 V, I
D
= 100 µA
= 2 A
STF7N105K5
Min. Typ. Max. Unit
3
1050
4
1.4
1
V
µA
50 µA
±10 µA
5 V
2 Ω
Notes:
(1)
Defined by design, not subject to production test.
Symbol Parameter
Table 5: Dynamic
Test conditions
C iss
C oss
C rss
C
o(tr)
(1)
C
o(er)
(2)
R
G
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent capacitance time related
Equivalent capacitance energy related
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
=100 V, f=1 MHz, V
GS
=0 V
V
GS
= 0 V, V
DS
= 0 to 840 V f = 1MHz open drain
V
DD
= 840 V, I
D
= 4 A
V
GS
=10 V
Figure 16: "Test circuit for gate charge behavior"
Min. Typ. Max. Unit
-
-
380
40
-
- pF pF
-
-
-
-
-
-
-
0.65
47
17
7
11
2.8
5.6
-
-
-
-
-
-
- pF pF pF
Ω nC nC nC
Notes:
(1)
Time related is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to 80% V
DSS
(2)
Energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss
when V
DS increases from 0 to 80% V
DSS
4/14 DocID026184 Rev 2
STF7N105K5
Symbol Parameter t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time t f
Fall time
Table 6: Switching times
Test conditions
V
DD
= 525 V, I
D
= 2 A, R
G
=4.7 Ω,
V
GS
=10 V
(see Figure 15: "Test circuit for resistive load switching times" and
Figure 20: "Switching time waveform" )
Electrical characteristics
Min. Typ. Max. Unit
-
-
-
-
17.5
7
43
25
-
-
-
- ns ns ns ns
Symbol
I
SD
Source-drain current
I
SDM
Source-drain current
(pulsed)
V
SD
(1)
Forward on voltage t rr
Q rr
Reverse recovery time
Reverse recovery charge
I
I
RRM t
Q rr rr
RRM
Parameter
Reverse recovery current
Reverse recovery time
Table 7: Source drain diode
Test conditions
Reverse recovery charge
Reverse recovery current
I
SD
= 4 A, V
GS
=0
I
SD
= 4 A, V
DD
= 60 V di/dt = 100 A/µs,
Figure 17: "Test circuit for inductive load switching and diode recovery times"
I
SD
= 4 A,V
DD
= 60 V di/dt=100 A/µs, Tj=150 °C
Figure 17: "Test circuit for inductive load switching and diode recovery times"
-
-
-
Min. Typ. Max. Unit
- 4 A
16 A
370
3
1.6 V ns
µC
-
-
-
-
16.5
600
4.4
14.5
A ns
µC
A
Notes:
(1)
Pulsed: pulse duration = 300µs, duty cycle 1.5%
Symbol
Table 8: Gate-source Zener diode
Parameter Test conditions Min Typ. Max. Unit
V
(BR)GSO
Gate-source breakdown voltage I
GS
= ± 1mA, I
D
=0 30 - -
The built-in back-to-back Zener diodes have been specifically designed to enhance the
ESD capability of the device. The Zener voltage is appropriate for efficient and costeffective intervention to protect the device integrity. These integrated Zener diodes thus eliminate the need for external components.
V
5/14 DocID026184 Rev 2
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STF7N105K5
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
6/14
Figure 6: Gate charge vs gate-source voltage
Figure 7: Static drain-source on-resistance
Ω
DocID026184 Rev 2
STF7N105K5
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Source-drain diode forward characteristics
Figure 10: Normalized gate threshold voltage vs temperature
µ
Figure 11: Normalized on-resistance vs temperature
Figure 12: Normalized V(BR)DSS vs temperature
GIPG210320141421S A
Figure 13: Maximum avalanche energy vs starting Tj
E
AS
(mJ)
120
I
D
=1.5 A
V
DD
=50 V
100
80
60
40
20
0
0 20 40 60 80 100 120 140 T
J
(°C)
DocID026184 Rev 2 7/14
Electrical characteristics
Figure 14: Output capacitance stored energy
µ
STF7N105K5
8/14 DocID026184 Rev 2
STF7N105K5
3 Test circuits
Figure 15: Test circuit for resistive load switching times
Test circuits
Figure 16: Test circuit for gate charge behavior
Figure 17: Test circuit for inductive load switching and diode recovery times
Figure 18: Unclamped inductive load test circuit
Figure 19: Unclamped inductive waveform
Figure 20: Switching time waveform
DocID026184 Rev 2 9/14
Package information
4 Package information
STF7N105K5
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
10/14 DocID026184 Rev 2
STF7N105K5
4.1 TO-220FP package information
Figure 21: TO-220FP package outline
Package information
DocID026184 Rev 2 11/14
Package information
Dim.
G1
H
L2
L3
L4
L5
L6
L7
Dia
F
F1
F2
G
A
B
D
E
Table 9: TO-220FP package mechanical data mm
Min. Typ.
4.4
2.5
2.5
0.45
0.75
1.15
1.15
4.95
2.4
10
16
28.6
9.8
2.9
15.9
9
3
STF7N105K5
Max.
4.6
2.7
2.75
0.7
1
1.70
1.70
5.2
2.7
10.4
30.6
10.6
3.6
16.4
9.3
3.2
12/14 DocID026184 Rev 2
STF7N105K5
5
Revision history
Revision history
Date Revision
Table 10: Document revision history
Changes
07-Apr-2014
07-Jun-2016
1
2
First release.
Updated Figure 6: "Gate charge vs gate-source voltage"
and Table 5:
"Dynamic" .
Minor text changes.
DocID026184 Rev 2 13/14
STF7N105K5
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14/14 DocID026184 Rev 2
