STU7LN80K5
Nchannel 800 V, 0.95 Ω typ., 5 A MDmesh™ K5
Power MOSFET in a IPAK package
Datasheet - production data
TAB
IPAK
1
2
3
Figure 1: Internal schematic diagram
Features
Order code
STU7LN80K5
V
DS
800 V
R
DS(on)
max.
1.15 Ω
•
Industry’s lowest R
DS(on)
x area
•
Industry’s best figure of merit (FoM)
•
Ultra-low gate charge
•
100% avalanche tested
•
Zener-protected
Applications
•
Switching applications
I
D
5 A
Description
This very high voltage N-channel Power
MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
Order code
STU7LN80K5
Table 1: Device summary
Marking Package
7LN80K5 IPAK
Packing
Tube
January 2016 DocID028830 Rev 1
This is information on a product in full production.
1/12 www.st.com
Contents
Contents
STU7LN80K5
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
IPAK type C package information ..................................................... 9
5 Revision history ............................................................................ 11
2/12 DocID028830 Rev 1
STU7LN80K5
1
Electrical ratings
Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
GS
I
D
I
D
I
D
(1)
P
TOT
dv/dt
(2) dv/dt
(3)
T stg
T j
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Storage temperature
Operating junction temperature
Notes:
(1)
Pulse width limited by safe operating area.
(2)
I
SD
≤ 5 A, di/dt ≤100 A/μs; V
DS peak ≤ V
(BR)DSS
, V
DD
= 400 V
(3)
V
DS
≤ 640 V
Symbol
Table 3: Thermal data
Parameter
R thj-case
R thj-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
Symbol
I
AR
E
AS
Table 4: Avalanche characteristics
Parameter
Avalanche current, repetetive or not repetetive (pulse width limited by T jmax
)
(Single pulse avalanche energy (starting T j
= 25 °C, I
D
= I
AR
;
V
DD
= 50 V)
Value
± 30
5
3.4
20
85
4.5
50
- 55 to 150
Value
1.47
100
Value
1.5
200
Unit
°C/W
°C/W
Unit
A mJ
Unit
V
A
A
A
W
V/ns
V/ns
°C
DocID028830 Rev 1 3/12
Electrical characteristics
2 Electrical characteristics
T
C
= 25 °C unless otherwise specified
Symbol Parameter
Table 5: On/off states
Test conditions
V
(BR)DSS
I
DSS
I
GSS
Drain-source breakdown voltage
V
GS
= 0 V, I
D
= 1 mA
Zero gate voltage Drain current
V
GS
= 0 V, V
DS
= 800 V
V
GS
= 0 V, V
DS
= 800 V,
T
C
= 125 °C
Gate-body leakage current V
DS
= 0 V, V
GS
= ±20 V
V
DS
= V
GS
, I
D
=100 µA V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source onresistance
V
GS
= 10 V, I
D
= 2.5 A
Symbol Parameter
Table 6: Dynamic
Test conditions
C iss
C oss
C rss
C
o(er)
(1)
C
o(tr)
(2)
R
G
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent capacitance energy related
Equivalent capacitance time related
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
V
DS
= 0 to 640 V, V
GS
= 0 V f = 1 MHz, open drain
V
DD
= 640 V, I
D
= 5 A,
V
GS
= 10 V (see Figure 15:
"Test circuit for gate charge behavior" )
-
-
-
-
-
STU7LN80K5
Min. Typ. Max. Unit
800 V
1 µA
50 µA
4
±10 µA
5 V
0.95 1.15
Ω
3
Min. Typ. Max. Unit
-
-
270
22
-
- pF pF
- 0.5 - pF
- 17
48
7.5
12
2.6
8.6
-
-
-
-
-
- nC
Notes:
(1)
Energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss
when V
DS increases from 0 to 80% V
DSS
(2)
Time related is defined as a constant equivalent capacitance giving the same stored energy as C oss
when V
DS increases from 0 to 80% V
DSS
Symbol Parameter t d(on)
Turn-on delay time t t r f
Rise time t d(off)
Turn-off-delay time
Fall time
Table 7: Switching times
Test conditions
V
DD
= 400 V, I
D
= 2.5 A, R
G
= 4.7
Ω,
V
GS
= 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform" )
Min. Typ. Max. Unit
-
-
9.3
6.7
- 23.6
- 17.4
-
-
-
- ns ns ns ns nC
Ω nC nC nC
4/12 DocID028830 Rev 1
STU7LN80K5
Symbol Parameter
I
SD
Source-drain current
I
SDM
(1)
Source-drain current
(pulsed)
V
SD
(2)
Forward on voltage t rr
I
Q rr
RRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current t rr
I
Q rr
RRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Table 8: Source drain diode
Test conditions
I
I
SD
SD
V
= 5 A, V
GS
= 0 V
= 5 A, di/dt = 100 A/µs,
DD
= 60 V (see circuit for inductive load switching and diode recovery times" )
Figure 16: "Test
I
SD
= 5 A, di/dt = 100 A/µs,
V
DD
= 60 V, T j
= 150 °C
(see Figure 16: "Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
- 5 A
- 20 A
-
- 276
1.6 V ns
- 2.13 µC
- 15.4
- 402
- 2.79
- 13.9
A ns
µC
A
Notes:
(1)
Pulse width is limited by safe operating area
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Symbol
Table 9: Gate-source Zener diode
Parameter Test conditions
V
(BR)GSO
Gate-source breakdown voltage I
GS
= ±1 mA, I
D
= 0 A
Min. Typ. Max. Unit
30 - V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry.
DocID028830 Rev 1 5/12
Electrical characteristics
2.2 Electrical characteristics (curves)
Figure 2: Safe operating area
STU7LN80K5
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
6/12 DocID028830 Rev 1
STU7LN80K5
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs temperature
Figure 10: Normalized V
(BR)DSS
vs temperature Figure 11: Normalized on-resistance vs temperature
Figure 12: Source-drain diode forward characteristics
Figure 13: Maximum avalanche energy vs starting T
J
DocID028830 Rev 1 7/12
Test circuits
3 Test circuits
Figure 14: Test circuit for resistive load switching times
STU7LN80K5
Figure 15: Test circuit for gate charge behavior
Figure 16: Test circuit for inductive load switching and diode recovery times
Figure 17: Unclamped inductive load test circuit
Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform
8/12 DocID028830 Rev 1
STU7LN80K5
4
4.1
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
IPAK type C package information
Figure 20: IPAK (TO-251) type C package outline
0068771_IK_typeC_rev13
DocID028830 Rev 1 9/12
Package information
Dim. e e1
H
L
L1
L2
θ1
θ2
D
D1
E
E1
A
A1 b b2 b4 c c2
STU7LN80K5
Table 10: IPAK (TO-251) type C package mechanical data mm
Min.
2.20
0.90
0.66
Typ.
2.30
1.00
5.33
2.20
4.40
16.18
9.00
0.90
0.90
3°
1°
5.23
0.46
0.46
6.00
5.20
6.50
4.60
6.10
5.37
6.60
4.78
2.25
4.50
16.48
9.30
1.00
1.08
5°
3°
6.20
5.55
6.70
4.95
2.30
4.60
16.78
9.60
1.20
1.25
7°
5°
Max.
2.35
1.10
0.79
0.90
5.43
0.59
0.59
10/12 DocID028830 Rev 1
STU7LN80K5
5
Revision history
Revision history
Date
08-Jan-2016
Table 11: Document revision history
Revision
1
Changes
First release.
DocID028830 Rev 1 11/12
STU7LN80K5
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12/12 DocID028830 Rev 1
