G(1)
STFH40N60M2
Nchannel 600 V, 0.078 Ω typ., 34 A MDmesh™ M2
Power MOSFET in a TO-220FP wide creepage package
Datasheet - preliminary data
Figure 1: Internal schematic diagram
D(2)
Features
Order codes V
DS
@ T
Jmax
R
DS(on)
max I
D
STFH40N60M2 650 V 0.088 Ω 34 A
Extremely low gate charge
Excellent output capacitance (C
OSS
) profile
100% avalanche tested
Zener-protected
Wide creepage distance of 4.25 mm between the pins
Applications
Switching applications
LLC converters, resonant converters
Description
This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology.
Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters.
The TO-220FP wide creepage package provides increased surface insulation for Power MOSFETs to prevent failure due to arcing, which can occur in polluted environments.
Order codes
STFH40N60M2
S(3)
AM15572v1_no_tab
Table 1: Device summary
Marking Package
40N60M2 TO-220FP wide creepage
June 2016 DocID029433 Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Packaging
Tube
1/12 www.st.com
Contents
Contents
STFH40N60M2
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
TO-220FP wide creepage package information ................................ 9
5 Revision history ............................................................................ 11
2/12 DocID029433 Rev 1
STFH40N60M2
1 Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
GS
Gate-source voltage
I
D
Drain current (continuous) at T
C
= 25 °C
I
D
Drain current (continuous) at T
C
= 100 °C
I
DM
(2)
Drain current (pulsed)
P
TOT
Total dissipation at T
C
= 25 °C
dv/dt (3)
Peak diode recovery voltage slope
dv/dt (4)
MOSFET dv/dt ruggedness
V
ISO
Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C)
T stg
T j
Storage temperature range
Operating junction temperature range
Electrical ratings
Value
± 25
34 (1)
22 (1)
136 (1)
40
15
50
2500
- 55 to 150
Unit
V
A
A
A
W
V/ns
V/ns
V
°C
Notes:
(1)
Limited by maximum junction temperature.
(2)
Pulse width limited by safe operating area.
(3)
I
SD
≤ 13 A, di/dt ≤ 400 A/µs; V
DSpeak
< V
(BR)DSS
, V
DD
= 400 V
(4)
V
DS
≤ 480 V
Symbol
Table 3: Thermal data
Parameter Value Unit
R thj-case
R thj-amb
Thermal resistance junction-case max
Thermal resistance junction-ambient max
3.13
62.5
Symbol
I
AR
E
AS
Table 4: Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive (pulse width limited by T jmax
)
Single pulse avalanche energy (starting T j
=25 °C, I
D
= I
AR
; V
DD
=50 V)
°C/W
°C/W
Value Unit
6 A
500 mJ
DocID029433 Rev 1 3/12
Electrical characteristics
2
4/12
STFH40N60M2
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Symbol Parameter
Table 5: On /off states
Test conditions
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
Min. Typ. Max. Unit
V
(BR)DSS
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 600 V
I
DSS
Zero gate voltage drain current
V
GS
= 0 V,
V
DS
= 600 V,
T
C
=125 °C (1)
I
GSS
Gate-body leakage current
V
GS(th)
Gate threshold voltage
V
DS
= 0 V, V
GS
= ±25 V
600
V
DS
= V
GS
, I
D
= 250 µA 2
R
DS(on)
Static drain-source on- resistance V
GS
= 10 V, I
D
= 17 A
Notes:
(1)
Defined by design, not subject to production test.
Symbol Parameter
Table 6: Dynamic
Test conditions
1
V
µA
100 µA
±10 µA
3 4 V
0.078 0.088
Ω
Min. Typ. Max. Unit
C iss
C oss
-
-
2500
117
-
- pF pF
C rss
C
oss eq.
(1)
R
G
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent output capacitance
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 0 to 480 V, V
GS
= 0 V f = 1 MHz, I
D
=0 A
V
DD
= 480 V, I
D
= 34 A,
V
GS
= 10 V
(see Figure 15: "Test circuit for gate charge behavior" )
-
-
-
-
-
-
2.4
342
4.4
57
10
25.5
-
-
-
-
-
- pF pF
Ω nC nC nC
Notes:
(1)
Coss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to 80% V
DSS
Symbol Parameter
Table 7: Switching times
Test conditions Min. Typ. Max. Unit t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time t f
Fall time
V
DD
= 300 V, I
D
= 34 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform" )
-
-
-
-
20.5
13.5
96.5
11
-
-
-
- ns ns ns ns
DocID029433 Rev 1
STFH40N60M2
Symbol Parameter
I
SD
(1)
Source-drain current
I
SDM
(2)
Source-drain current
(pulsed)
V
SD
(3)
Forward on voltage t rr
Q rr
Reverse recovery time
Reverse recovery charge
I
I
RRM t
Q rr rr
RRM
Table 8: Source drain diode
Test conditions
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 34 A, V
V
DD
= 60 V
GS
= 0 V
I
SD
= 34 A, di/dt = 100 A/µs
(see Figure 16: "Test circuit for inductive load switching and diode recovery times" )
I
SD
= 34 A, di/dt = 100 A/µs
V
DD
= 60 V, T j
= 150 °C
(see Figure 16: "Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
-
-
-
-
-
-
-
-
-
440
8.2
37
568
11.5
40.5
34
136
1.6
A
A
V ns
µC
A ns
µC
A
Notes:
(1)
The value is rated according to R thj-case and limited by package.
(2)
Pulse width limited by safe operating area.
(3)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
DocID029433 Rev 1 5/12
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STFH40N60M2
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
W
6/12 DocID029433 Rev 1
STFH40N60M2
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs. temperature
Figure 10: Normalized on-resistance vs temperature
I
D
=17 A
Figure 11: Source-drain diode forward characteristics
GIPD240920132025FSR
Figure 12: Normalized V(BR)DSS vs temperature Figure 13: Output capacitance stored energy
DocID029433 Rev 1 7/12
Test circuits
3 Test circuits
Figure 14: Test circuit for resistive load switching times
STFH40N60M2
Figure 15: Test circuit for gate charge behavior
8/12
Figure 16: Test circuit for inductive load switching and diode recovery times
Figure 17: Unclamped inductive load test circuit
Figure 18: Unclamped inductive waveform
Figure 19: Switching time waveform
DocID029433 Rev 1
STFH40N60M2
4
4.1
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
TO-220FP wide creepage package information
Figure 20: TO-220FP wide creepage package outline
DocID029433 Rev 1
DM00260252_1
9/12
Package information
Dim.
G1
H
L2
L3
L4
L5
L6
L7
Dia
F
F1
F2
G
A
B
D
E
Table 9: TO-220FP wide creepage package mechanical data mm
STFH40N60M2
Min. Typ. Max.
4.15
10.90
15.25
28.70
10.00
2.55
16.00
9.05
3.00
4.60
2.50
2.49
0.46
0.76
0.96
1.11
8.40
4.70
2.60
2.59
8.50
4.25
11.00
15.40
29.00
10.20
2.70
16.10
9.15
3.10
4.35
11.10
15.55
29.30
10.40
2.85
16.20
9.25
3.20
4.80
2.70
2.69
0.59
0.89
1.25
1.40
8.60
10/12 DocID029433 Rev 1
STFH40N60M2
5
Revision history
Revision history
Date
08-Jun-2016
Table 10: Document revision history
Revision
1
Changes
First release.
DocID029433 Rev 1 11/12
STFH40N60M2
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12/12 DocID029433 Rev 1
