USBULC6-2M6
Ultra large bandwidth ESD protection
Features
■
■
■
■
■
■
■
2 data line 15 kV ESD protection
Protects 5 V V
BUS
when applicable
Ultra low capacitance: 0.65 pF at F = 240 MHz
Very low leakage current: 0.5 µA max.
Fast response time compared with varistors
µQFN 6 lead package
RoHS compliant
Benefits
■
■
■
■
■
ESD protection of V
BUS
(when applicable)
High bandwidth to minimize impact on data signal quality
Low PCB space occupation
Low leakage current profides longer operation of battery powered devices
Higher reliability offered by monolithic integration
Complies with these standards:
■ IEC 61000-4-2 level 4
– 15 kV air discharge
– 8 kV contact discharge
Applications
■
■
■
■
USB 2.0 ports including Hi-Speed USB ports up to 480 Mb/s as well as full and low speed
USB ports
Ethernet port: 10/100/1000 Mb/s
Video line protection
Portable electronics
µQFN
(pin view)
Figure 1.
Functional diagram (top view)
Description
The USBULC6-2M6 is a monolithic, application specific discrete device dedicated to ESD protection of high speed interfaces.
Its ultra low line capacitance provides high bandwidth and secures a high level of signal integrity without compromizing the protection of downstream sensitive chips against the most stringent characterized ESD strikes.
November 2007 Rev 1 1/10 www.st.com
Characteristics
1 Characteristics
USBULC6-2M6
Table 1.
Symbol
V
PP
T stg
T j
T
L
Absolute ratings
Parameter
Peak pulse voltage
IEC 61000-4-2 air discharge
IEC 61000-4-2 contact discharge
MIL STD883G-Method 3015-7
Storage temperature range
Maximum junction temperature
Lead solder temperature (10 seconds duration)
Table 2.
Electrical characteristics (T amb
= 25 °C)
Value
±15
±15
±25
-55 to +150
150
260
Unit kV
°C
°C
°C
Symbol Parameter Test conditions
I
V
RM
BR
Leakage current
Breakdown voltage between V
BUS and GND
I
V
R
RM
= 5 V
= 1 mA
C
V
CL i/o-GND
Clamping voltage
I
PP
= 1 A, t p
= 8/20 µs
Any I/O pin to GND
I
PP
= 5 A, t p
= 8/20 µs
Any I/O pin to GND
Capacitance between I/O and GND
V
R
= 0 V, F = 1 MHz
Any I/O pin to ground
V
R
= 0 V, F = 240 MHz
Any I/O pin to ground
Δ C i/o-GND
Capacitance variation between I/O and GND
V
R
= 0 V, F = 1 MHz
Any I/O pin to ground
V
R
= 0 V, F = 1 MHz
Ground not connected
C i/o-i/o
Capacitance between I/O
V
R
= 0 V, F = 240 MHz
Ground not connected
Value
Min.
Typ.
Max
Unit
0.5
µA
6
0.95
0.65
0.020
0.5
0.35
12
17
1.1
0.85
0.55
0.4
V
V
V pF
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USBULC6-2M6 Characteristics
Figure 2.
Line capacitance versus frequency
(typical values)
Figure 3.
Relative variation of leakage current versus junction temperature (typical values)
1000.0
C(fF) I
RM
[T j
] / I
RM
[T j
=25°C]
5
900.0
800.0
4
700.0
600.0
500.0
400.0
300.0
200.0
100.0
0.0
0 1
F(GHz)
I/O - GND
I/O – I/O
2 3
3
2
1
25 50 75 100 125
Figure 4.
Attenuation measurement
0.00
S21(db)
Figure 5.
Crosstalk measurements
0.00
dB
- 30.00
- 4.00
- 8.00
- 60.00
- 12.00
- 90.00
F(Hz)
- 16.00
300.0k
1.0M
3.0M
10.0M
30.0M
100.0M
300.0M
1.0G
3.0G
F (Hz)
- 120.00
300.0k
1.0M
3.0M
10.0M
30.0M
100.0M
300.0M
1.0G
3.0G
Figure 6.
Remaing voltage on I/O1 after the
USBULC6-2M6 during positive
ESD surge (15 kV Air)
10V/Div
Figure 7.
Remaing voltage on I/O2 after the
USBULC6-2M6 during negative
ESD surge (15 kV Air)
10V/Div
100ns/Div 100ns/Div
3/10
4/10
Characteristics USBULC6-2M6
Figure 8.
Remaing voltage on V
BUS
after the
USBULC6-2M6 during positive
ESD surge (15 kV Air)
Figure 9.
Remaing voltage on V
BUS
after the
USBULC6-2M6 during negative
ESD surge (15 kV Air)
10V/Div 10V/Div
100ns/Div 100ns/Div
Figure 10.
Eye diagram PCB only
400 mV amplitude, F = 480 Mbps
Horiz: 350 ps/div
Vert: 100 mV/div
Figure 11.
Eye diagram PCB + USBULC6-2M6
400 mV amplitude, F = 480 Mbps
Horiz: 350 ps/div
Vert: 100 mV/div
Figure 12.
Eye diagram PCB + USBULC6-2M6, +5 V on V
BUS
decoupling capacitor
100 nF, 400 mV amplitude, F = 480 Mbps
Horiz: 350 ps/div
Vert: 100 mV/div
USBULC6-2M6 Application example
Figure 13.
One differential line
D+
I/O1
1
To GND plane
2
I/O2
3
D-
6
I/O1
5
4
I/O2
100 nF
3 Ordering information scheme
Figure 14.
Ordering information scheme
USB ULC 6 - 2 M6
Product Designation
Ultra low capacitance
Breakdown Voltage
6 = 6 Volts
Number of lines protected
2 = 2 lines
Package
µQFN - 6 leads
5/10
Package information USBULC6-2M6
Note:
● Epoxy meets UL94, V0
In order to meet environmental requirements, ST (also) offers these devices in ECOPACK® packages. ECOPACK® packages are Lead-free. The category of second level Interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Table 3.
Micro QFN 1.45x1.00 6L dimensions
Dimensions
D
N
Ref.
Millimeters Inches
E Min.
Typ.
Max.
Min.
Typ.
Max.
A
A1
1
1 e
2
2 b
L k
A 0.50
0.55
0.60
0.020 0.022 0.024
A1 0.00
0.02
0.05
0.000 0.001 0.002
b 0.18
0.25
0.30
0.007 0.010 0.012
D
(1)
1.45
0.057
E
(1)
e
(2)
1.00
0.50
0.039
0.020
K 0.20
0.008
L 0.30
0.35
0.40
0.012 0.014 0.016
1.
± 0.1 mm
2.
± 0.05 mm
Product marking may be rotated by 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin
1 mark is to be used for this purpose.
Figure 15.
Footprint dimensions in mm [inches]
0.50
[0.020]
0.25
[0.010]
0.65
[0.026]
0.30
[0.012]
1.60
[0.063]
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USBULC6-2M6
5
Recommendation on PCB assembly
Recommendation on PCB assembly
5.1 Stencil opening design
1.
General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness)
Figure 16.
Stencil opening dimensions.
L
T
W
Stencil thickness (T) = 75 ~ 125 µm
Aspect Ratio
Aspect Area
=
=
W
1.5
T
≥
L ×
2T L
W
+ W
)
≥
0.66
a) Stencil opening thickness: 100 µm b) Stencil opening for leads: Opening to footprint ratio is 90%.
1.
Halide-free flux qualification ROL0 according to ANSI/J-STD-004.
2. “No clean” solder paste is recommended.
3. Offers a high tack force to resist component movement during high speed
4. Solder paste with fine particles: powder particle size is 20-45 µm.
7/10
Recommendation on PCB assembly USBULC6-2M6
5.3 Placement
1.
Manual positioning is not recommended.
2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering
3. Standard tolerance of ± 0.05 mm is recommended.
4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages.
5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool.
6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
1.
To control the solder paste amount, the closed via is recommended instead of open vias.
2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
Figure 17.
ST ECOPACK
®
recommended soldering reflow profile for PCB mounting
3°C/s max
3°C/s max
2°C/s recommended
6°C/s max
Note: Minimize air convection currents in the reflow oven to avoid component movement.
8/10
USBULC6-2M6 Ordering information
Table 4.
Ordering information
Order code Package
USBULC6-2M6
Marking
T
(1)
µQFN
Weight
2.2 mg
1.
The marking can be rotated by 90° to diferentiate assembly location
Base qty
3000
Delivery mode
Tape and reel
Table 5.
Date
Document revision history
Revision
29-Nov-2007 1 First issue
Description of changes
9/10
USBULC6-2M6
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