ESDALC12-1T2
Single line transient surge voltage suppressor (TVS) for data and power line
Datasheet
−
production data
Features
■
■
■
■
■
■
■
■
Stand-off voltage 10 V
Unidirectional device
Low clamping factor V
CL
/V
BR
Breakdown voltage V
BR
= 12 V min.
Fast response time
Very thin package: 0.4 mm
Low leakage current
RoHS compliant
Benefits
■
■
High ESD robustness of the application
Suitable for high density boards
Complies with the following standards:
■
■
IEC 61000-4-2 level 4:
– 15 kV (air discharge)
– 8 kV (contact discharge)
MIL STD 883G - Method 3015-7: class 3B
SOD882T
Figure 1.
Functional diagram
I/O1
GND
Applications
Where transient overvoltage protection and electrical overstress protection in sensitive equipment are required, such as:
■
■
Computers
Printers
■
■
■
Communication systems
Cellular phone handsets and accessories
Video equipment
Description
The ESDALC12-1T2 is a unidirectional single line
Transil™ diode designed specially for protection of integrated circuits in portable equipment and miniaturized electronic devices subjected to ESD and EOS transient over voltages. Packed in
SOD882T, it minimizes PCB occupation.
June 2012
This is information on a product in full production.
TM: Transil is a trademark of STMicroelectronics
Doc ID 15025 Rev 3 1/11 www.st.com
11
Characteristics
1 Characteristics
ESDALC12-1T2
Table 1.
Symbol
Absolute maximum ratings (T amb
= 25 °C)
Parameter
V
PP
P
PP
I
PP
T j
T stg
Peak pulse voltage - IEC 61000-4-2
Air discharge
Contact discharge
Peak pulse power dissipation (8/20 µs)
Peak pulse current (8/20 µs)
Storage temperature range
(1)
Operating junction temperature range
(1)
T j initial
= T
1.
For a surge greater than the maximum values, the diode will fail in short-circuit amb
Figure 2.
Electrical characteristics (definitions)
Symbol
I
PP
I
R
α
T
V
F
V
BR
I
RM
V
RM
V
CL
R d
=
=
=
=
=
=
=
=
=
Parameter
Breakdown voltage
Leakage current @ V
RM
Stand-off voltage
Clamping voltage
Dynamic impedance
Peak pulse current
Breakdown current
Voltage temperature coefficient
Forward voltage drop
V
CL
V
BR
V
RM
I
F
I
I
RM
Slope = 1/Rd
I
PP
V
F
Value
25
20
50
2
- 40 to + 125
- 55 to +150
V
Table 2.
Symbol
V
BR
I
RM
R d
V
CL
C
Electrical characteristics (T amb
= 25 °C)
Test conditions
I
R
= 1 mA
V
RM
= 10 V
1 A to 3 A, 8/20 µs
I
PP
= 1 A, 8/20µs
V
R
= 0 V DC, F = 1 MHz, V
OSC
= 30 mV
RMS
Unit kV
W
A
°C
°C
Min.
12
Typ.
1.9
15
Max.
14
200
20
18
Unit
V nA
Ω
V pF
2/11 Doc ID 15025 Rev 3
ESDALC12-1T2 Characteristics
Figure 3.
Peak pulse power dissipation versus initial junction temperature
Figure 4.
Peak pulse power versus exponential pulse duration
100
90
80
70
60
50
40
30
20
10
0
0 25 50 75 100 125
8/20 µs
150 175
1000
100
10
1
1 10 100
Figure 5.
Clamping voltage versus peak pulse current (maximum values)
10.0
8/20 µs
1000
Figure 6.
Forward voltage drop versus peak
10.00
I
FM
(A) forward current (typical values)
1.00
1.0
0.10
0.01
0.1
12 14 16 18 20 22 24 26 28
0.00
0.0
0.5
1.0
1.5
2.0
2.5
V
FM
(V)
3.0
10
8
6
4
2
0
0
Figure 7.
Junction capacitance versus reverse applied voltage
(typical values)
16
C(pF)
14
F = 1 Mhz
V
OSC
= 30 mV
RMS
12
1 2 3 4 5
Figure 8.
Leakage current versus junction temperature (typical values)
10.00
1.00
0.10
0.01
25 50
V = V
RM
= 10 V
75 100 125
Doc ID 15025 Rev 3 3/11
Characteristics
Figure 9.
ESD response to IEC 61000-4-2
(+15 kV air discharge) on each channel
10 V/div
ESDALC12-1T2
Figure 10.
ESD response to IEC 61000-4-2
(-15 kV air discharge) on each channel
5 V/div
100 ns/div 100 ns/div
Figure 11.
S21 attenuation measurement
0.00
dB
-5.00
-10.00
-15.00
-20.00
-25.00
F (Hz)
-30.00
300.0k
1.0M
3.0M
10.0M 30.0M 100.0M 300.0M 1.0G
3.0G
4/11 Doc ID 15025 Rev 3
ESDALC12-1T2
2 Ordering information scheme
Figure 12.
Ordering information scheme
Ordering information scheme
ESDA LC 12 - 1 T2
ESD array
Low capacitance
Breakdown voltage
12 = 12 Volt min.
Number of lines
Package
T2 = SOD882T
Doc ID 15025 Rev 3 5/11
Package information ESDALC12-1T2
6/11
●
●
Epoxy meets UL94, V0
Lead-free package
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
Figure 13.
SOD882 dimension definitions
L1 L2 b1
PIN # 1 ID b2 e
A
A1
E
D
Table 3.
SOD882 dimension values
Ref.
b2
D
E e
A
A1 b1
L1
L2
Min.
0.40
0.00
0.45
0.45
0.55
0.95
0.60
0.20
0.20
Dimensions
Millimeters
Typ.
0.47
0.50
0.50
0.60
1.00
0.65
0.25
0.25
Max.
0.50
0.05
0.55
0.55
0.65
1.05
0.70
0.30
0.30
Min.
0.016
0.000
0.018
0.018
0.022
0.037
0.024
0.008
0.008
Inches
Typ.
0.019
0.020
0.020
0.024
0.039
0.026
0.010
0.010
Max.
0.020
0.002
0.022
0.022
0.026
0.041
0.028
0.012
0.012
Doc ID 15025 Rev 3
ESDALC12-1T2 Package information
Figure 14.
Footprint (dimensions in mm) Figure 15.
Marking
0.55
(0.022)
0.55
(0.022)
Pin1
I N
Pin 2
0.40
(0.016)
0.50
0.020
Note: Product marking may be rotated by multiples of 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a
PCB. Only pin 1 mark is to be used for this purpose.
Figure 16.
Tape and reel specifications
Cathode bar
Ø 1.55
2.0
4.0
0.20
0.6
All dimensions in mm
0.68
2.0
User direction of unreeling
Doc ID 15025 Rev 3 7/11
Recommendation on PCB assembly
4 Recommendation on PCB assembly
4.1 Stencil opening design
1.
General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 17.
Stencil opening dimensions
L
T
W
ESDALC12-1T2 b) General design rule
Stencil thickness (T) = 75 ~ 125 µm
Aspect Ratio =
Aspect Area =
W
1.5
T
≥
L
×
2T L
W
+ W
)
≥
0.66
a) Stencil opening thickness: 100 µm b) Stencil opening for leads: Opening to footprint ratio - between 60% and 65%.
Figure 18.
Recommended stencil windows position
Package footprint
Lead footprint on PCB 0.055 mm
Lead footprint on PCB
Stencil window position 0.39 mm
Stencil window position
0.45 mm
0.05 mm 0.05 mm
8/11
1.
Halide-free flux qualification ROL0 according to ANSI/J-STD-004.
2. “No clean” solder paste is recommended.
3. Offers a high tack force to resist component movement during high speed
4. Solder paste with fine particles: powder particle size is 20-45 µm.
Doc ID 15025 Rev 3
ESDALC12-1T2 Recommendation on PCB assembly
4.3 Placement
1.
Manual positioning is not recommended.
2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering
3. Standard tolerance of ± 0.05 mm is recommended.
4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages.
5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool.
6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
1.
To control the solder paste amount, the closed via is recommended instead of open vias.
2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
Figure 19.
ST ECOPACK® recommended soldering reflow profile for PCB mounting
150
100
50
250
Temperature (°C)
200
0 30
2 - 3 °C/s
240-245 °C
60 sec
(90 max)
-2 °C/s to
-3 °C/s
-6 °C/s max
0.9 °C/s
60 90 120 150 180 210
Time (s)
240 270 300
Note: Minimize air convection currents in the reflow oven to avoid component movement.
Doc ID 15025 Rev 3 9/11
Ordering information ESDALC12-1T2
Table 4.
Ordering information
Order code Package
ESDALC12-1T2
Marking
V
(1)
SOD882T
Weight
0.76 mg
Base qty
12000
1.
The marking can be rotated by multiples of 90° to differentiate assembly location
Delivery mode
Tape and reel
Table 5.
Date
Document revision history
Revision
16-Sep-2008
02-Nov-2010
13-Jun-2012
1
2
3
Changes
Initial release
Updated Table 1
, base quantity change on
Table 4 and updated
graphics.
Added Figure 13 , updated Table 3
and added note after
Figure 15 .
10/11 Doc ID 15025 Rev 3
ESDALC12-1T2
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Doc ID 15025 Rev 3 11/11
