EMIF03-SIM02M8
Datasheet
3 line IPAD, EMI filter for SIM card applications
8
7
6
5
GND
GND
11
2
3
4
V
CC
Micro QFN 1.7 mm x 1.5 mm
(bottom view)
Pin configuration (top view)
V
CC
RST
IN
CLK
IN
DATA
IN
RST
EXT
CLK
EXT
DATA
EXT
RST
IN
CLK
IN
DATA
IN
V
CC
Device configuration
100 Ω
R1
47Ω
R2
100 Ω
R3
RST
EXT
CLK
EXT
DATA
EXT
GND
Maximum line capacitance = 20 pF
Product status
EMIF03-SIM02M8
Features
• SIM card EMI low-pass filter
• High efficiency in EMI filtering
• Very low PCB space consuming: 1.7 mm x 1.5 mm
• Very thin package: 0.6 mm max.
• High efficiency in ESD suppression on external pins (IEC 61000-4-2 level 4)
• High reliability offered by monolithic integration
• High reduction of parasitic elements through integration and wafer level packaging
• Lead free package
• Easy layout and flexibility thanks to I/O topology
• Low clamping voltage
• Complies with following standards:
– IEC 61000-4-2 level 4 externals pins
◦ 15 kV (air discharge)
◦ 8 kV (contact discharge)
– IEC 61000-4-2 level 2 internal pins
◦ 2 kV (air discharge)
◦ 2 kV (contact discharge)
• MIL STD 883G - Method 3015-7 Class 3A (all pins)
Applications
Where EMI filtering in ESD sensitive equipment is required:
• Keyboard for mobile phones
• Computers and printers
• Communication systems
• MCU boards
Description
The EMIF03-SIM02M8 is a 3 line highly integrated device designed to suppress
EMI/RFI noise in all systems exposed to electromagnetic interference.
This filter includes ESD protection circuitry, which prevents damage to the application when subjected to ESD surges up to 15 kV on the external pins.
DS5513 - Rev 2 - January 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
1
EMIF03-SIM02M8
Characteristics
Characteristics
Symbol
V
PP
T j
T op
T stg
Table 1. Absolute maximum ratings (T amb
= 25 °C)
Parameter
Internal pins:
ESD discharge IEC 61000-4-2 air discharge
ESD discharge IEC 61000-4-2 contact discharge
External pins and V
CC
:
ESD discharge IEC 61000-4-2 air discharge
ESD discharge IEC 61000-4-2 contact discharge
Maximum junction temperature
Operating temperature range
Storage temperature range
Figure 1. Electrical characteristics (definitions)
I
I
F
Symbol Parameter
VBR Breakdown voltage
IRM
Leakage current at VRM
VRM Stand-off voltage
VCL Clamping voltage
Rd Dynamic resistance
IPP
RI/O
Cline
Peak pulse current
Series resistance between Input and Output
Input capacitance per line
V
BR
V
CL
V
RM
I
RM
I
R
V
F
Value
2
2
15
8
125
- 40 to + 85
- 55 to + 150
I
PP
Unit kV
V
°C
°C
°C
Symbol
V
BR
I
RM
R1, R3
R13
C line
Table 2. Electrical characteristics (T amb
= 25 °C)
Test conditions
I
R
= 1 mA
V
RM
= 3 V per line
Tolerance ±20%
Tolerance ±20%
V
R
= 0 V, V
OSC
= 30 mV, F = 1 MHz
Min.
6
Typ.
100
47
17
Max.
7.9
0.2
20
Unit
V
µA
Ω
Ω pF
DS5513 - Rev 2 page 2/13
EMIF03-SIM02M8
Characteristics (curves)
1.1
Characteristics (curves)
Figure 2. S21(db) attenuation (RST line)
0.00
dB
-5.00
-10.00
-15.00
-20.00
-25.00
-30.00
-35.00
300.0k
1.0M
3.0M
F (Hz)
10.0M
3 0.0M
1 00.0M
300.0M
1.0G
3.0G
Figure 4. S21(db) attenuation (DATA line)
0.00
dB
-5.00
-10.00
-15.00
-20.00
-25.00
-30.00
-35.00
300.0k
1.0M
3.0M
F (Hz)
10.0M
30.0M
100.0M
300.0M
1.0G
3.0G
Figure 6. ESD response to IEC 61000-4-2 (+15 kV air discharge) applied to external pin
Figure 3. S21(db) attenuation (CLK line)
0.00
dB
-5.00
-10.00
-15.00
-20.00
-25.00
-30.00
-35.00
300.0k
1.0M
3.0M
F (Hz)
10.0M
30.0M
100.0M
300.0M
1.0G
3.0G
Figure 5. Analog cross talk measurements
0.00
-10.00
dB
-20.00
-30.00
-40.00
-50.00
-60.00
-70.00
-80.00
-90.00
-100.00
-110.00
-120.00
300.0k
1.0M
3.0M
ClkIn-RstExt
F (Hz)
10.0M
30.0M
100.0M 300.0M
DataIn-Rst/Clk
1.0G
3.0G
Figure 7. ESD response to IEC 61000-4-2 (-15 kV air discharge) applied to external pin
200 ns/div
DS5513 - Rev 2
200 ns/div page 3/13
Figure 8. ESD response to IEC 61000-4-2 (+2 kV air discharge) applied to internal pin
EMIF03-SIM02M8
Characteristics (curves)
Figure 9. ESD response to IEC 61000-4-2 (-2 kV air discharge) applied to internal pin
20 ns/div
20 ns/div
DS5513 - Rev 2 page 4/13
2
Application information
Vcc
RST in
CLK in
Data in
Figure 10. Application schematic
Vcc
RST
CLK
Data
EXT
EXT
EXT
EMIF03-SIM02M8
Application schematic
DS5513 - Rev 2 page 5/13
3
3.1
EMIF03-SIM02M8
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
•
Micro QFN 1.7x1.5-8L package information
Epoxy meets UL94, V0
Figure 11. Micro QFN 1.7x1.5-8L package outline
DS5513 - Rev 2 page 6/13
EMIF03-SIM02M8
Micro QFN 1.7x1.5-8L package information
Ref.
A
A1 b
D
D2
E
E2 e k
L
Table 3. Micro QFN 1.7x1.5-8L package mechanical data
1.45
0.25
0.35
0.20
0.25
Min.
0.50
0.00
0.15
1.65
0.85
Dimensions
Millimeters
Typ.
0.55
0.02
0.20
1.70
1.00
1.50
0.40
0.40
0.30
Figure 12. Micro QFN 1.7x1.5-8L footprint (dimensions in mm)
Figure 13. Marking
Max.
0.60
0.05
0.25
1.75
1.10
1.55
0.50
0.45
0.35
XX
Dot : Pin 1 identification
XX : Marking code (cf Table 4: Ordering information)
The marking can be rotated by multiples of 90° to differentiate assembly locations
DS5513 - Rev 2 page 7/13
DS5513 - Rev 2
Figure 14. Tape and reel outline
EMIF03-SIM02M8
Micro QFN 1.7x1.5-8L package information
2.00 ± 0.05
4.00 ± 0.1
Ø 1.5 ± 0.1
0.75
1.70
4.00
All dimensions in mm User direction of unreeling
Product marking may be rotated by 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose.
page 8/13
EMIF03-SIM02M8
Recommendation on PCB assembly
4
Recommendation on PCB assembly
4.1
Stencil opening design
1.
General recommendation on stencil opening design a.
Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 15. Stencil opening dimensions
L
T
W
4.2
4.3
2.
General design rule a.
Stencil thickness (T) = 75 ~ 125 μm b.
Aspect ratio =
W
T
≥ 1.5
c.
Aspect area =
L × W
2T L + W
3.
Reference design
≥ 0.66
a.
Stencil opening thickness: 100 μm b.
Stencil opening for central exposed pad: Opening to footprint ratio is 50%.
c.
Stencil opening for leads: Opening to footprint ratio is 90%
Solder paste
1.
Halide-free flux qualification ROL0 according to ANSI/J-STD-004.
2.
“No clean” solder paste is recommended.
3.
Offers a high tack force to resist component movement during high speed.
4.
Solder paste with fine particles: powder particle size is 20-45 μm.
Placement
1.
Manual positioning is not recommended.
2.
It is recommended to use the lead recognition capabilities of the placement system, not the outline centering
3.
Standard tolerance of ±0.05 mm is recommended.
4.
3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages.
5.
To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool.
6.
For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
DS5513 - Rev 2 page 9/13
4.4
4.5
EMIF03-SIM02M8
PCB design preference
PCB design preference
1.
To control the solder paste amount, the closed via is recommended instead of open vias.
2.
The position of tracks and open vias in the solder area should be well balanced. A symmetrical layout is recommended, to avoid any tilt phenomena caused by asymmetrical solder paste due to solder flow away.
Reflow profile
Figure 16. ST ECOPACK ® recommended soldering reflow profile for PCB mounting
250
Temperature (°C)
200
150
100
50
0 30
0.9 °C/s
60
2 - 3 °C/s
240-245 °C
60 sec
(90 max)
-2 °C/s
-3 °C/s
-6 °C/s
90 120 150
Time (s)
180 210 240 270 300
Note: Minimize air convection currents in the reflow oven to avoid component movement. Maximum soldering profile corresponds to the latest IPC/JEDEC J-STD-020.
DS5513 - Rev 2 page 10/13
5
Table 4. Ordering information
Part number
EMIF03-SIM02M8
Marking
HA
(1)
Package
Micro QFN
Weight
4 mg
1. The marking can be rotated by multiples of 90° to differentiate assembly locations.
Base qty.
3000
EMIF03-SIM02M8
Ordering information
Ordering information
Figure 17. Ordering information scheme
EMIF yy - xxx zz Mx
EMI Filter
Number of lines
Information xxx = application zz = version
Package
Mx = Micro QFN x leads
Delivery mode
Tape and reel (7”)
DS5513 - Rev 2 page 11/13
EMIF03-SIM02M8
Revision history
Date
07-Oct-2007
31-Jan-2022 2
Table 5. Document revision history
Version
1
Changes
Initial release.
Updated Table 3. Micro QFN 1.7x1.5-8L package mechanical data
and
Figure 13. Marking . Minor text changes.
DS5513 - Rev 2 page 12/13
EMIF03-SIM02M8
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DS5513 - Rev 2 page 13/13
