STD80N3LL
Nchannel 30 V, 4 mΩ typ., 80 A
Power MOSFET in a DPAK package
Datasheet - production data
Figure 1: Internal schematic diagram
D(2, TAB)
Features
Order code V
DS
R
DS(on)
max.
STD80N3LL 30 V 5.2 mΩ
Very low on-resistance
Very low gate charge
High avalanche ruggedness
Low gate drive power loss
I
D
P
TOT
80 A 75 W
Applications
Switching applications
Description
This device is an N-channel Power MOSFET with very low R
DS(on)
in all packages.
G(1)
S(3)
Order code
STD80N3LL
AM01475v1_Tab
Table 1: Device summary
Marking Package
80N3LL DPAK
Packaging
Tape and reel
December 2016 DocID029591 Rev 2
This is information on a product in full production.
1/15 www.st.com
Contents
Contents
STD80N3LL
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 5
3 Test circuits ..................................................................................... 7
4 Package information ....................................................................... 8
4.1
4.2
DPAK package information ............................................................... 9
DPAK (TO-252) packing information ............................................... 12
5 Revision history ............................................................................ 14
2/15 DocID029591 Rev 2
STD80N3LL
1 Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
DS
V
GS
I
D
(1)
I
D
(1)
I
DM
(1)(2)
P
TOT
(1)
T j
T stg
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Operating junction temperature range
Storage temperature range
Notes:
(1)
This value is limited by package
(2)
Pulse width limited by safe operating area
Table 3: Thermal data
Parameter Symbol
R
thj-pcb
(1)
R thj-case
Thermal resistance junction-pcb max.
Thermal resistance junction-case max.
Notes:
(1)
When mounted on FR-4 board of 1 inch², 2oz Cu
Electrical ratings
Value
30
±20
80
60
320
75
-55 to 175
Unit
A
A
W
V
V
A
°C
Value
50
2
Unit
°C/W
°C/W
DocID029591 Rev 2 3/15
Electrical characteristics
2
4/15
STD80N3LL
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Symbol Parameter
Table 4: On/off states
Test conditions
V
(BR)DSS
Drain-source breakdown voltage I
D
= 1 mA, V
GS
= 0 V
I
DSS
Zero gate voltage drain current
V
V
GS
DS
= 0 V
= 30 V
I
GSS
Gate-body leakage current
V
GS(th)
Gate threshold voltage
V
GS
= 20 V, V
DS
= 0 V
R
DS(on)
Static drain-source on-resistance
V
DS
= V
GS
, I
D
= 250 μA
V
GS
= 10 V, I
D
= 40 A
V
GS
= 4.5 V, I
D
= 40 A
Symbol Parameter
Table 5: Dynamic
Test conditions
C iss
C oss
C rss
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 25 V, f = 1 MHz,
V
GS
= 0 V
V
DD
= 15 V, I
D
= 80 A,
V
GS
= 4.5 V (see Figure
14: "Test circuit for gate charge behavior" )
Symbol Parameter
Table 6: Switching times
Test conditions
Min. Typ. Max. Unit
30
1
V
µA
1
100 nA
2.5 V
4 5.2 mΩ
5.5 6.5 mΩ
Min. Typ. Max. Unit
-
-
-
-
-
1640
207
160
18
5.3
-
-
-
-
- pF nC
- 8.8 -
Min. Typ. Max. Unit t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time t f
Fall time
V
DD
= 15 V, I
D
= 40 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see Figure 13: "Test circuit for resistive load switching times" )
Symbol Parameter
V
SD
(1)
Forward on voltage t rr
Reverse recovery time
Q rr
Reverse recovery charge
I
RRM
Table 7: Source-drain diode
Test conditions
Reverse recovery current
I
SD
= 80 A, V
GS
= 0 V
I
D
= 80 A, di/dt = 100 A/µs
V
DD
= 24 V (see Figure 15:
"Test circuit for inductive load switching and diode recovery times" )
-
-
-
-
6.4
8
36
12
-
-
-
-
Min. Typ. Max. Unit
-
- 21
- 14
1.2 V ns nC
- 1.3 ns ns ns ns
A
Notes:
(1)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
DocID029591 Rev 2
STD80N3LL
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
Electrical characteristics
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
DocID029591 Rev 2 5/15
Electrical characteristics
Figure 8: Capacitance variations
STD80N3LL
Figure 9: Normalized gate threshold voltage vs temperature
Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature
Figure 12: Source-drain diode forward characteristics
6/15 DocID029591 Rev 2
STD80N3LL
3 Test circuits
Figure 13: Test circuit for resistive load switching times
Test circuits
Figure 14: Test circuit for gate charge behavior
Figure 15: Test circuit for inductive load switching and diode recovery times
Figure 16: Unclamped inductive load test circuit
Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform
DocID029591 Rev 2 7/15
Package information
4 Package information
STD80N3LL
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
8/15 DocID029591 Rev 2
STD80N3LL
4.1 DPAK package information
Package information
Figure 19: DPAK (TO-252) type A2 package outline
DocID029591 Rev 2
0068772_type-A2_rev21
9/15
Package information
Dim.
D1
E
E1 e e1
H
L
L1
L2
L4
R
V2 b4 c c2
D
A
A1
A2 b
STD80N3LL
Table 8: DPAK (TO-252) type A2 mechanical data mm
Min. Typ.
4.95
6.40
5.10
2.16
4.40
9.35
1.00
2.20
0.90
0.03
0.64
5.20
0.45
0.48
6.00
2.60
0.65
0.60
5.20
2.28
0.20
0°
2.80
0.80
5.10
Max.
5.25
6.60
5.30
2.40
4.60
10.10
1.50
2.40
1.10
0.23
0.90
5.40
0.60
0.60
6.20
3.00
0.95
1.00
8°
10/15 DocID029591 Rev 2
STD80N3LL Package information
Figure 20: DPAK (TO-252) type A2 recommended footprint (dimensions are in mm)
DocID029591 Rev 2 11/15
Package information
4.2 DPAK (TO-252) packing information
Figure 21: DPAK (TO-252) tape outline
STD80N3LL
12/15 DocID029591 Rev 2
STD80N3LL
Figure 22: DPAK (TO-252) reel outline
Package information
Dim.
F
K0
P0
P1
P2
R
T
W
A0
B0
B1
D
D1
E
7.9
1.9
40
0.25
15.7
1.5
1.5
1.65
7.4
2.55
3.9
Table 9: DPAK (TO-252) tape and reel mechanical data
Tape Reel mm
Dim.
Min.
6.8
10.4
Max.
7
10.6
12.1
1.6
1.85
7.6
2.75
4.1
8.1
2.1
A
B
C
D
G
N
T
Base qty.
Bulk qty.
Min.
1.5
12.8
20.2
16.4
50
0.35
16.3 mm
Max.
330
13.2
18.4
22.4
2500
2500
DocID029591 Rev 2 13/15
Revision history
5
STD80N3LL
Revision history
Date Revision
Table 10: Document revision history
Changes
26-Jul-2016
06-Dec-2016
1
2
First release.
Document status promoted from preliminary to production data.
Updated Section 2: "Electrical characteristics"
and added Section
2.1: "Electrical characteristics (curves)" .
Minor text changes.
14/15 DocID029591 Rev 2
STD80N3LL
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