STH180N10F3-2
N-channel 100 V, 3.9 mΩ typ.,180 A, STripFET™ F3
Power MOSFET in H²PAK-2 package
Datasheet - production data
Features
Order code
VDS
RDS(on)
max.
ID
STH180N10F3-2
100 V
4.5 mΩ
180 A
Ultra low on-resistence
100% avalanche tested
Applications
Figure 1: Internal schematic diagram
Switching applications
Description
This device is an N-channel Power MOSFET
developed using STripFET™ F3 technology. It is
designed to minimize on-resistance and gate
charge to provide superior switching
performance.
Table 1: Device summary
Order code
Marking
Package
Packing
STH180N10F3-2
180N10F3
H2PAK-2
Tape
and reel
S(2,3)
November 2014
DocID019060 Rev 2
This is information on a product in full production.
1/16
www.st.com
Contents
STH180N10F3-2
Contents
1
Electrical ratings ............................................................................. 3
2
Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3
Test circuits ..................................................................................... 8
4
Package information ....................................................................... 9
5
2/16
4.1
H2PAK-2 package information ......................................................... 10
4.2
Packing information......................................................................... 13
Revision history ............................................................................ 15
DocID019060 Rev 2
STH180N10F3-2
1
Electrical ratings
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage
100
V
VGS
Gate-source voltage
± 20
V
(1)
ID
Drain current (continuous) at TC = 25 °C
180
A
(1)
ID
Drain current (continuous) at TC = 100 °C
120
A
Drain current (pulsed)
720
A
Total dissipation at TC = 25 °C
315
W
(2)
IDM
PTOT
Derating factor
2.1
W/ºC
dv/dt
Peak diode recovery voltage slope
20
V/ns
(3)
EAS
Single pulse avalanche energy
350
mJ
TJ
Operating junction temperature
Tstg
Storage temperature
-55 to 175
°C
°C
Notes:
(1)
(2)
(3)
Current limited by package
Pulse width limited by safe operating area
Starting TJ = 25 °C, ID = 80, VDD = 50 V
Table 3: Thermal data
Symbol
Rthj-case
Rthj-pcb
(1)
Parameter
Value
Unit
Thermal resistance junction-case
0.48
°C/W
Thermal resistance junction-pcb
35
°C/W
Notes:
(1)
When mounted on FR-4 board of 1 inch², 2 oz Cu
DocID019060 Rev 2
3/16
Electrical characteristics
2
STH180N10F3-2
Electrical characteristics
(TCASE = 25 °C unless otherwise specified)
Table 4: On/off-state
Symbol
V(BR)DSS
Parameter
Test conditions
Drain-source breakdown
voltage (VGS= 0)
ID = 250 µA
Min.
Typ.
Max.
100
Unit
V
VDS = 100 V
10
µA
VDS = 100 V;
TC = 125 °C
100
µA
±200
nA
4
V
4.5
mΩ
Max.
Unit
IDSS
Zero gate voltage drain
current (VGS = 0)
IGSS
Gate body leakage current
(VDS = 0)
VGS = ±20 V
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250 µA
RDS(on)
Static drain-source onresistance
VGS = 10 V, ID = 60 A
2
3.9
Table 5: Dynamic
Symbol
Parameter
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer
capacitance
Test conditions
Min.
VDS = 25 V, f = 1 MHz,
VGS = 0
Typ.
6665
pF
786
pF
49
-
Qg
Total gate charge
Qgs
Gate-source charge
Qgd
Gate-drain charge
pF
-
VDD = 50 V, ID = 120 A
VGS = 10 V
See Figure 14: "Gate
charge test circuit"
114.6
nC
38.8
nC
31.9
nC
Table 6: Switching times
Symbol
td(on)
tr
td(off)
tf
4/16
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
VDD = 50 V, ID = 60 A,
RG = 4.7 Ω, VGS= 10 V
See Figure 13:
"Switching times test
circuit for resistive load"
DocID019060 Rev 2
Min.
Typ.
Max.
25.6
ns
97.1
-
99.9
6.9
Unit
ns
-
ns
ns
STH180N10F3-2
Electrical characteristics
Table 7: Source-drain diode
Symbol
ISD
(1)
ISDM
(2)
VSD
Parameter
Test conditions
Min.
Typ.
Source-drain current
Source-drain current (pulsed)
Forward on voltage
trr
Reverse recovery time
Qrr
Reverse recovery charge
IRRM
Reverse recovery current
ISD = 120 A,
VGS = 0
ISD = 120 A,
di/dt = 100 A/µs,
VDD = 80 V,
Tj = 150 °C
Max.
Unit
180
A
720
A
1.5
V
83.4
ns
295.7
nC
7.1
A
Notes:
(1)
(2)
Pulse width limited by safe operating area
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
DocID019060 Rev 2
5/16
Electrical characteristics
2.1
STH180N10F3-2
Electrical characteristics (curves)
Figure 3: Thermal impedance
Figure 2: Safe operating area
ID
(A)
280tok
K
GIPG110620141143SA
ᵟ =0.5
100
0.2
is
)
ea
ar S(on
D
hi s
nt xR
i
on ma
i
t
y
a
er d b
Op ite
Li m
10
0.1
10ms
10
0.05
-1
0.02
Zth=k Rthj-c
ᵟ =tp/ t
0.01
1
1ms
Tj=175°C
Tc=25°C
Single pulse
0.1
0.1
1
Single pulse
10
-2
10 -5
10
10
-4
10
10
-2
10
-1
tp (s)
AM08617v1
ID (A)
AM08616v1
V GS=10V
350
350
7V
300
300
250
250
200
200
150
-3
Figure 5: Transfer characteristics
Figure 4: Output characteristics
ID(A)
tp
t
100µs
V DS(V)
V DS=2V
150
6V
100
100
50
50
5V
0
0
1
2
4
3
5
6
7
8
0
V DS(V)
0
Figure 6: Normalized V(BR)DSS vs
temperature
2
3
4
5
6
7
8
9
V GS(V)
Figure 7: Static drain-source on-resistance
AM08618v1
V (BR)DSS
(norm)
1
AM08626v1
R DS(on)
(mΩ)
V GS=10V
4.2
ID=1m A
1.10
4.1
4.0
1.05
3.9
1.00
3.8
0.95
0.90
-75
6/16
3.7
-25
25
75
125
175 T J(°C)
DocID019060 Rev 2
3.6
0
20 40 60
80 100 120 140 160 180
ID(A)
STH180N10F3-2
Electrical characteristics
Figure 9: Capacitance variations
Figure 8: Gate charge vs gate-source
voltage
V GS
(V)
V DD=50V
ID=120 A
12
AM08621v1
C
(pF)
AM08620v1
20000
10
15000
8
6
10000
Ciss
4
5000
2
Crss
0
0
20
40
60
80
100 120 140
0
0
Q g(nC)
40
60
80
100
V DS(V)
Figure 11: Normalized on-resistance vs
temperature
Figure 10: Normalized gate threshold
voltage vs temperature
AM08623v1
R DS(on)
AM08622v1
V GS(th)
(norm)
Coss
20
(norm)
ID=60 A
V GS=10V
2.1
ID=250µ A
1.3
1.9
1.7
1.1
1.5
0.9
1.3
0.7
1.1
0.9
0.5
0.7
0.3
-75
-25
25
75
125
0.5
-75
175 T J(°C)
-25
25
75
125
175
T J(°C)
Figure 12: Source-drain diode forward characteristics
AM08624v1
V SD
(V)
1.0
T J=-55°C
0.9
0.8
T J=25°C
0.7
0.6
0.5
T J=175°C
0.4
0
20
40
60
DocID019060 Rev 2
80
100
120
ISD(A)
7/16
Test circuits
3
STH180N10F3-2
Test circuits
Figure 13: Switching times test circuit for resistive
load
Figure 14: Gate charge test circuit
VDD
47 k Ω
12 V
1 kΩ
100 nF
I G = CONST
Vi ≤ V GS
100 Ω
D.U.T.
VG
2.7 k Ω
2200 μ F
47 k Ω
PW
1 kΩ
AM01469v 1
Figure 15: Test circuit for inductive load
switching and diode recovery times
Figure 16: Unclamped inductive load test circuit
Figure 17: Unclamped inductive waveform
Figure 18: Switching time waveform
t on
V(BR)DSS
t d(on)
VD
t off
tr
t d(off)
tf
90%
90%
I DM
10%
ID
VDD
10%
0
VDD
VGS
AM01472v 1
8/16
DocID019060 Rev 2
0
10%
VDS
90%
AM01473v 1
STH180N10F3-2
4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
DocID019060 Rev 2
9/16
Package information
4.1
STH180N10F3-2
2
H PAK-2 package information
Figure 19: H²PAK-2 outline
8159712_D
10/16
DocID019060 Rev 2
STH180N10F3-2
Package information
Table 8: H²PAK-2 mechanical data
mm
Dim.
Min.
Typ.
Max.
A
4.30
4.80
A1
0.03
0.20
C
1.17
1.37
e
4.98
5.18
E
0.50
0.90
F
0.78
0.85
H
10.00
10.40
H1
7.40
L
15.30
L1
1.27
1.40
L2
4.93
5.23
L3
6.85
7.25
L4
1.5
1.7
M
2.6
2.9
R
0.20
0.60
V
0°
8°
DocID019060 Rev 2
-
7.80
15.80
11/16
Package information
STH180N10F3-2
Figure 20: H²PAK-2 recommended footprint
8159712_D
12/16
DocID019060 Rev 2
STH180N10F3-2
4.2
Package information
Packing information
Figure 21: Tape outline
Figure 22: Reel outline
T
REE L DIMENS IONS
40 mm min.
Acc ess hole
At slot location
B
D
C
N
A
Tape slot
In core for
Full radius
G measured
At hub
Tape start
DocID019060 Rev 2
13/16
Package information
STH180N10F3-2
Table 9: Tape and reel mechanical data
Tape
Reel
mm
mm
Dim.
14/16
Dim.
Min.
Max.
A0
10.5
10.7
A
B0
15.7
15.9
B
1.5
D
1.5
1.6
C
12.8
D1
1.59
1.61
D
20.2
E
1.65
1.85
G
24.4
F
11.4
11.6
N
100
K0
4.8
5.0
T
P0
3.9
4.1
P1
11.9
12.1
Base quantity
1000
P2
1.9
2.1
Bulk quantity
1000
R
50
T
0.25
0.35
W
23.7
24.3
DocID019060 Rev 2
Min.
Max.
330
13.2
26.4
30.4
STH180N10F3-2
5
Revision history
Revision history
Table 10: Document revision history
Date
Revision
18-Jul-2011
1
First version
2
26-Nov-2014
Changes
Modified fig 2.
Updated package mechanical data.
Updated the title, features and description.
DocID019060 Rev 2
15/16
STH180N10F3-2
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST
products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2014 STMicroelectronics – All rights reserved
16/16
DocID019060 Rev 2
">
