ESDALC20-1BF4
Low clamping, low capacitance bidirectional single line ESD protection
Datasheet
-
production data
Description
The ESDALC20-1BF4 is a bidirectional single line
TVS diode designed to protect the data line or other I/O ports against ESD transients.
The device is ideal for applications where both reduced line capacitance and board space saving are required.
Figure 1. Functional diagram
SDFNDJH
Features
Low V
BR
/V
CL
ratio
Bidirectional device
Low leakage current < 1 nA typ.
0201 package
Ultra low PCB area: 0.18 mm
2
ECOPACK
®
2 compliant component
Complies with the following standards
IEC 61000-4-2 level 4:
– ±30 kV (air discharge)
– ±20 kV (contact discharge)
Applications
Where transient over voltage protection in ESD sensitive equipment is required, such as:
Smartphones, mobile phones and accessories
Tablet, PC, netbooks and notebooks
Portable multimedia devices and accessories
Digital cameras and camcorders
Communication and highly integrated systems
August 2016
This is information on a product in full production.
DocID028009 Rev 2 1/10 www.st.com
Characteristics
1 Characteristics
ESDALC20-1BF4
Symbol
Table 1. Absolute maximum ratings
Parameter
V
PP
(1)
Peak pulse voltage
IEC 61000-4-2 contact discharge
IEC 61000-4-2 air discharge
P
PP
(1)
I
PP
(1)
T j
T stg
T
L
Peak pulse power (8/20 µs)
Peak pulse current (8/20 µs)
Operating junction temperature range
Storage temperature range
Maximum lead temperature for soldering during 10 s
1.
For a surge greater than the maximum values, the diode will fail in short-circuit.
Figure 2. Electrical characteristics (definitions)
Value
20
30
90
2.4
-40 to 150
-65 to +150
260
Unit kV
W
A
°C
°C
°C
6\PERO
9
%5
9
&/
,
50
9
50
,
33
5
G
Ⱥ 7
&
/,1(
3DUDPHWHU
%UHDNGRZQYROWDJH
&ODPSLQJYROWDJH
/HDNDJHFXUUHQW# 9
50
6WDQGRIIYROWDJH
3HDNSXOVHFXUUHQW
'\QDPLFUHVLVWDQFH
9ROWDJHWHPSHUDWXUH
/LQHFDSDFLWDQFH
9
&/
6ORSH 5
G ,
33
9
&/
Symbol
V
BR
I
RM
V
RM
V
CL
C
LINE
Table 2. Electrical characteristics (values, T amb
= 25 °C)
Value
Test conditions
I
R
= 1 mA
V
RM
= 20 V
Stand-off voltage
8 kV contact discharge after 30 ns (I
PP
= 16 A), IEC 61000-4-2
V
LINE
= 0 V, F = 1 MHz, V
OSC
= 30 mV
Min.
Typ.
Max.
22
-20
23
< 1 10
20
37
10.5
11.5
Unit
V nA
V
V pF
2/10 DocID028009 Rev 2
ESDALC20-1BF4 Characteristics
Figure 3. Leakage current versus junction temperature (typical values)
,
5
Q$
9
5
9
50
9
,2,2
Figure 4. Junction capacitance versus applied voltage (typical values)
$ Q'
7M&
Figure 5. ESD response to IEC 61000-4-2
(+8 kV contact discharge)
9GLY
9
9
9
9 33 (6'SHDNYROWDJH
9
9
&/ &ODPSLQJYROWDJH#QV
&/ &ODPSLQJYROWDJH#QV
9 &ODPSLQJYROWDJH#QV
9
9
5
9
Figure 6. ESD response to IEC 61000-4-2
(-8 kV contact discharge)
9GLY
9 33 (6'SHDNYROWDJH
9
9
&/ &ODPSLQJYROWDJH#QV
&/ &ODPSLQJYROWDJH#QV
9 &/ &ODPSLQJYROWDJH#QV
, 33 $
Figure 7. Dynamic resistance
/LQHDU3RVLWLYH3RODULW\
/LQHDU1HJDWLYH3RODULW\
QVGLY
9
9
9
9
QVGLY
Figure 8. S21 attenuation measurement result
6G%
9
&/
9
N
)+]
0
6
0 0 *
DocID028009 Rev 2 3/10
10
Package information ESDALC20-1BF4
2.1
Epoxy meets UL94, V0
Lead-free package
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
0201 package information
Figure 9. 0201 package outline
'
Ref.
D1
E
E1
A b
D fD fE
(
7RS
$
I'
6LGH
'
I(
(
%RWWRP
E
Min.
0.28
0.125
0.57
0.27
0.175
0.11
0.04
Table 3. 0201 package mechanical data
Dimensions
Millimeters
Typ.
0.3
0.14
0.6
0.35
0.3
0.19
0.125
0.055
Max.
0.32
0.155
0.63
0.33
0.205
0.14
0.07
Min.
0.0110
0.0049
0.0224
0.0106
0.0069
0.0043
0.0016
Inches
Typ.
0.0118
0.0055
0.0236
0.0138
0.0118
0.0075
0.0049
0.0022
Max.
0.0126
0.0061
0.0248
0.0130
0.0081
0.0055
0.0028
4/10 DocID028009 Rev 2
ESDALC20-1BF4
Figure 10. Footprint in mm (inches)
Package information
Figure 11. Marking
3LQ 3LQ
Note: The marking codes can be rotated by 90° or 180° to differentiate assembly location.In no case should this product marking be used to orient the component for its placement on a
PCB. Only pin 1 mark is to be used for this purpose.
Figure 12. Tape and reel outline
DocID028009 Rev 2 5/10
10
Recommendation on PCB assembly
3 Recommendation on PCB assembly
ESDALC20-1BF4
1.
General recommendations on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 13. Stencil opening dimensions
/
7
: b) General design rule
Stencil thickness (T) = 75 ~ 125 µm
Aspect Ratio =
Aspect Area =
W
1.5
T
L
2T L
W
+ W
0.66
2. Recommended stencil window a) Stencil opening thickness: 80 µm b) Other dimensions: see
Figure 14
Figure 14. Recommended stencil window position, stencil opening thickness: 80 µm
6/10
)RRWSULQW
DocID028009 Rev 2
PP
LQFKHV
6WHQFLOZLQGRZ
ESDALC20-1BF4 Recommendation on PCB assembly
1.
Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004.
2. “No clean” solder paste recommended.
3. Offers a high tack force to resist component displacement during PCB movement.
4. Use solder paste with fine particles: Type 4 (powder particle size 20-48 µm per
IPC J STD-005).
3.3 Placement
1.
Manual positioning is not recommended.
2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering.
3. Standard tolerance of ± 0.05 mm is recommended.
4. 1.0 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages.
5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool.
6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
1.
To control the solder paste amount, the closed via is recommended instead of open vias.
2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, to avoid any tilt phenomena caused by asymmetrical solder paste due to the solder flow away.
DocID028009 Rev 2 7/10
10
Recommendation on PCB assembly ESDALC20-1BF4
Note:
Figure 15. ST ECOPACK
®
recommended soldering reflow profile for PCB mounting
7HPSHUDWXUH&
&
&V
&V
VHF
PD[ &V
&V
&V
7LPHV
Minimize air convection currents in the reflow oven to avoid component movement.
8/10 DocID028009 Rev 2
ESDALC20-1BF4 Ordering information
Figure 16. Ordering information scheme
(6'$ /& % )
(6' DUUD\
/RZFDSDFLWDQFH
:RUNLQJYROWDJH
9PLQ
1XPEHURIOLQHV
'LUHFWLRQDO
% %LGLUHFWLRQDO
3DFNDJH
)
Order code
ESDALC20-1BF4
Marking
2
(1)
Table 4. Ordering information
Package Weight
0201 0.116 mg
Base qty Delivery mode
15000
1.
The marking codes can be rotated by 90° or 180° to differentiate assembly location
Tape and reel
Date
23-Jul-2015
01-Aug-2016
Table 5. Document revision history
Revision
1
2
First issue
Updated
Table 3 .
Changes
DocID028009 Rev 2 9/10
10
ESDALC20-1BF4
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2016 STMicroelectronics – All rights reserved
10/10 DocID028009 Rev 2
