Chapter 5 Software Considerations. NI NAT7210 Reference

Chapter 5

Software Considerations

The chapter explains important NAT7210 programming considerations, including chip initialization, Talkers and Listeners, message reception, and holdoffs. You should also refer to Chapter 6, Controller Software Considerations , for applications that use the

NAT7210 GPIB Controller functions.

This chapter, except where explicitly noted, assumes that the NAT7210 uses 7210-mode architecture and that the reader is familiar with the GPIB. For more information about

GPIB, refer to Appendix B, Introduction to the GPIB, and the IEEE 488.1 and

IEEE 488.2 standard.

Chip Initialization Sequence

1. Place the NAT7210 in 7210 Mode

Place the NAT7210 in 7210 mode by performing one of the following actions:

• Assert the RESET* pin.

• Write the sw7210 command to the AUXCR if the NAT7210 is in 9914 mode.

• Write 99 (hex) to offset 3 if you do not know whether the NAT7210 is in 7210 mode or 9914 mode. If the chip is in 9914 mode, this write places it in 7120 mode. If the chip is already in 7210 mode, this write access writes to the 7210-mode SPMR.

2. Make Sure the Local pon Message Is Asserted

Write the Chip Reset auxiliary command (2 hex) to the AUXMR to assert the local pon message. When pon is asserted, the chip is logically disconnected from the GPIB and the

GPIB interface functions of the NAT7210 are idle (and ignore GPIB signals).

3. Set the Clock Frequency

Set the clock frequency of the NAT7210 by writing to the ICR and the ICR2.

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4. Configure the Chip for GPIB Operation

A. Set the GPIB Address(es)

Write to the ADMR to configure the GPIB addressing mode of the NAT7210. In most applications, you write 31 (hex) to the ADMR to set the dual primary addressing mode.

Load the primary GPIB address of the NAT7210 into internal Address Register 0

(ADR0) by writing to the Address register. If the device has only one GPIB address, disable ADR1 by writing E0 (hex) to the Address Register.

Note: If the device has only one GPIB address, disable ADR1 by writing E0 (hex) to the Address Register.

B. Write the Initial Serial Poll Response

If another device in your system has Controller capabilities, write the initial serial poll response of the NAT7210 to the SPMR. See the Serial Polling section in Appendix B,

Introduction to the GPIB.

C. Configure Initial Parallel Response

If another device in your system has Controller capabilities, configure the initial parallel poll response of the NAT7210 by writing to AUXRI and PPR. (See the Parallel Polling section in Appendix B, Introduction to the GPIB.)

D. Set GPIB Handshake Parameters

1.

Set the Source Handshake T1 delay by setting or clearing the TRI and USTD bits.

(See the T1 Delay Generation section, which is located later in this chapter.)

2.

Set CHES to enable the clearing of the END detection circuitry on the reception of a data byte without END.

3.

Set NTNL to prevent the NAT7210 from sourcing data or commands when no

Listeners are on the GPIB.

4.

Issue the hldi auxiliary command to make the NAT7210 perform an RFD holdoff if it is addressed to listen.

5. Enable Interrupts

Set or clear the appropriate Interrupt Enable bits in IMR0, IMR1, and IMR2. Set the

SISB bit, if desired.

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6. Clear the Local pon Message

Issue the pon auxiliary command to clear the local pon message and to begin GPIB operation.

GPIB Talker or Listener Considerations

GPIB Addressing

Logical and Physical Devices

When you connect the NAT7210 to the GPIB by using standard GPIB transceivers, the

NAT7210 is one physical GPIB device. The IEEE 488.1 transceiver places a single physical device load on the GPIB. The IEEE 488.1 standard specifies that a GPIB system contain no more than 15 physical devices.

In most applications, the NAT7210 is also one logical device. However, a single physical

GPIB device can implement more than one logical GPIB device. Each logical device must have a unique GPIB address. The NAT7210 can implement up to 961 logical GPIB devices.

Normal and Extended Addressing

Logical GPIB devices use either normal or extended addressing. With normal addressing, a GPIB device has a single address; valid addresses are 0 through 30

(decimal), inclusive. To address a device to become a Talker or Listener, a Controller sends the talk or listen address of the device. If a device’s address is 6, for example, a

Controller sends the My Talk Address 6 (MTA6) message to address that device to become a Talker.

With extended addressing, a GPIB device has two addresses: a primary address and a secondary address. Valid primary addresses are 0 through 30 (decimal), inclusive; valid secondary addresses are also 0 through 30 (decimal), inclusive. With extended addressing, 961 (decimal) unique GPIB addresses exist. To address a device to become a

Talker or Listener, a Controller sends the primary talk or listen address of the device, then sends the secondary address of the device.

Implementing One Logical Device: Normal Addressing

The NAT7210 can implement one logical device that uses normal addressing. The

NAT7210 can become an Addressed Listener or Talker without the intervention of the host interface. The TA bit in ADSR sets when the NAT7210 is an Addressed Talker, and the Listener Active (LA) bit in ADSR sets when the NAT7210 is an Addressed Listener.

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Complete the following steps to implement one logical device that uses normal addressing:

1.

Choose the normal dual addressing mode by writing a 31 (hex) to the ADMR.

2.

Write the logical address to ADR0.

3.

Disable ADR1 by setting the Disable Talker (DT) and Disable Listener (DL) bits in

ADR1—that is, write a hex E0 to offset hex 6. Notice that ADR1 and ADR0 both appear at offset 6.

Implementing One Logical Device: Extended Addressing

The NAT7210 can implement one logical device that uses extended addressing. The

NAT7210 can become an Addressed Listener or Talker without the intervention of the host interface. When the Controller sends the primary talk or listen address of the

NAT7210, the Talker Primary Addressed State (TPAS) bit or the Listener Primary

Addressed State (LPAS) bit in the ADSR sets. When the Controller sends the secondary address of the NAT7210, the TA bit and the LA bit in the ADSR set.

Complete the following steps to implement one logical device that uses extended addressing:

1.

Choose the extended single addressing mode by writing a 32 (hex) to the ADMR.

2. Write the primary and secondary addresses to ADR0 and ADR1, respectively.

Notice that ADR1 and ADR0 both appear at offset 6.

Implementing Two Logical Devices: Normal Addressing

The NAT7210 can implement two logical devices that use normal addressing. The

NAT7210 can become an Addressed Listener or Talker for either of these devices without the intervention of the host interface. The TA bit in ADSR sets when the

NAT7210 is an Addressed Talker, and the LA bit in ADSR sets when the NAT7210 is an

Addressed Listener. The Major-Minor (MJMN) bit in ADSR indicates which of the two devices is addressed.

This mode requires one logical address for each device: the major device address and the minor device address. Major and minor distinguish between the two devices and do not denote the priority of one device over the other.

Complete the following steps to implement two logical devices that use normal addressing:

1.

Choose the normal dual addressing mode by writing a 31 (hex) to the ADMR.

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2.

Write the major address to ADR0 and write the minor address to ADR1. Notice that

ADR1 and ADR0 both appear at offset 6.

Implementing Two Logical Devices: Extended Addressing

The NAT7210 can implement two logical devices that use extended addressing. The

NAT7210 can become an Addressed Talker or Listener only after the Controller sends the primary and secondary addresses of one of the two logical devices. The two logical devices are the major logical device and the minor logical device.

This mode requires intervention from the host interface. Complete the following steps to implement two logical devices that use extended addressing:

1.

Choose the extended dual addressing mode by writing a 33 (hex) to the ADMR.

2.

Write the primary address of the major device to the ADR0 and write the primary address of the minor device to the ADR1. The host interface stores the secondary addresses of the NAT7210 external to the NAT7210, then the following sequence of events occurs:

• The Controller sends the primary talk or listen address of the NAT7210 to the

GPIB.

• The NAT7210 enters the TPAS or LPAS state. The MJMN bit sets or clears to indicate the reception of the minor or major primary address.

• The Controller sends a secondary address to the GPIB.

• The Address Pass Through (APT) bit sets (see ISR1).

• The NAT7210 performs a Data Accepted (DAC) holdoff.

• The host interface reads the Command Pass Through Register (CPTR) to determine whether the Controller sent the secondary address of the NAT7210.

• If the host interface determines that the Controller sent the secondary address of the NAT7210, it issues the valid auxiliary command, and the NAT7210 becomes addressed.

• If the host interface determines that the Controller sent the secondary address of another device, it issues the nonvalid auxiliary command.

Implementing Three or More Logical Devices: Normal Addressing

The NAT7210 can implement three or more logical devices that use normal addressing.

This mode requires intervention from the host interface. Refer to the Talker function in the IEEE 488.1 standard.

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Complete the following steps to implement three logical devices that use normal addressing:

1.

Choose the no-addressing mode by writing a 30 (hex) to the ADMR. The host interface stores the addresses of the NAT7210 external to the NAT7210.

2.

Set the following bits in Auxiliary Register F (AUXRF): DAC Holdoff On All

Talker Addresses (DHATA) bit and DAC Holdoff On All Listener Addresses

(DHALA) bit. The following sequence of events then occurs:

• The Controller sends a talk or listen address to the GPIB.

• The Command Pass Through (CPT) bit sets (see ISR1).

• The NAT7210 performs a DAC holdoff.

3.

Wait for the CPT bit to set. CPT sets when the Controller sends any talk or listen address over the GPIB.

4.

Read the CPTR to determine whether the Controller sent one of the talk or listen addresses of the NAT7210.

5.

If the CPTR matches one of the talk addresses of the NAT7210, the following sequence programs the NAT7210 to be the Addressed Talker:

• Write B0 to the ADMR.

• Write 30 to the ADMR.

If the CPTR matches one of the listen addresses of the NAT7210, the following sequence programs the NAT7210 to be the Addressed Listener:

• Write 70 to the ADMR.

• Write 30 to the ADMR.

6.

Write the valid auxiliary command to the AUXMR. The NAT7210 performs a DAC holdoff on the command byte the Controller sends. The valid auxiliary command releases the DAC holdoff.

Implementing Three or More Logical Devices: Extended Addressing

The NAT7210 can implement three or more logical devices that use extended addressing.

The required steps are similar to the steps for implementing three or more logical devices that use normal addressing. By using CPT and CPTR, the host interface monitors all commands. The host interface addresses and unaddresses the NAT7210 as needed. See the Extended Talker function in the IEEE 488.1 standard.

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Complete the following steps to implement three logical devices that use extended addressing:

1.

Choose the no-addressing mode by writing a 30 (hex) to the ADMR. The host interface stores the addresses of the NAT7210 external to the NAT7210.

2.

Set the DAC Holdoff On All UCG, ACG, and SCG Commands (DHALL) bit in

AUXRF.

Programmed Implementation of a Talker and Listener

When no Controller is in the GPIB system, you can use the ton and lon address modes to activate the NAT7210 GPIB Talker and Listener functions (refer to the Address Mode

Register section in Chapter 3, 7210-Mode Interface Registers). Set the ton or lon mode during NAT7210 initialization.

Detecting a GPIB Listener

When the NAT7210 is the Active Talker (and not an Active Listener), it can determine whether a Listener is in the GPIB system. Simply read the BCR. If either NDAC or

NRFD is asserted in the BCR, an Active Listener is in the system.

Sending GPIB Data Messages

Basic Flow

Complete the following steps to send GPIB (device-dependent) data to another device in your system:

1. Be certain that NTNL = 1 (AUXRG[3]). NTNL prevents the NAT7210 from sourcing commands if there are no listening devices in the system.

2. Be certain that the you have enabled the desired T1 delay. (See the T1 Delay

Generation section, which is located later in this chapter.)

3. Wait until the NAT7210 has been programmed or addressed to be the Active Talker.

Poll or interrupt on the ADSC (ISR2[0]) condition, then read the ADSR to determine whether the NAT7210 is a Talker.

4. Wait for the DO bit to set.

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5. Perform the following steps for each data byte that is sent:

• Write the data byte to the CDOR.

• Wait for either the DO bit or the ERR (ISR1[2]) bit to set. DO indicates that all devices in the system have accepted the command. ERR indicates that no properly operating GPIB devices are in the system.

The host interface can either poll the DO and ERR bits or configure the NAT7210 to interrupt on DO and ERR by setting the DO IE and ERR IE bits.

If the ERR bit sets, issue the nbaf auxiliary command to clear any byte that may be in the CDOR, then issue the ClearERR auxiliary command to clear the ERR bit.

Sending EOI or EOS

To send the GPIB END message and a data byte, issue the SendEOI auxiliary command just before you write the byte to the CDOR. To send the EOS message, simply make the last byte that you write to the CDOR the End-of-String (EOS) code. You can also use the

XEOS bit (AUXRA[3]) to send the END message whenever the byte in the CDOR matches the End-of-String Register (EOSR).

Using DMA

To use DMA to send data bytes, set the DMAO bit after the NAT7210 has been addressed to talk. The DRQ pin of the NAT7210 asserts whenever the CDOR is empty.

The DMA Controller should respond to DRQ by asserting the DACK* and WR* pins to place a data byte into the CDOR.

T1 Delay Generation

The T1 Delay

When the NAT7210, as a GPIB Talker, transfers data bytes to GPIB Listeners, it drives the data byte on the GPIB DIO[8–1] signals. After waiting for a certain delay (known as the T1 delay), the NAT7210 asserts DAV to indicate to the Listeners that the data byte has settled on the DIO[8–1] signals.

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HSTS Definition

The length of the T1 delay depends on several factors. One factor is the internal HSTS signal of the NAT7210. HSTS clears when the GPIB Controller asserts the GPIB ATN signal. HSTS sets after the NAT7210, as a GPIB Talker, transfers a byte. Usually, the

T1 delay is longer for the first data byte of a transfer (HSTS = 0). The T1 delay is shorter for the second byte of a transfer (and for subsequent bytes).

IEEE 488.1 Standard Requirements

The IEEE 488.1 standard describes minimum T1 delay requirements for three cases:

• Case 1: The Talking device uses three-state drivers on the DIO, DAV, and EOI signals. Usually, the NAT7210 is connected to the GPIB with 75160 and 75162 transceivers. In the typical configuration, the 75160 and 75162 transceivers use three-state drivers on the DIO, DAV, and EOI signals.

• Case 2: The Talking device satisfies the requirements of case 1 and uses 48-mA three-state drivers (again, the 75160 and 75162 satisfy this requirement). In addition, the following requirements are placed on the GPIB system (and not just on the

Talking device):

– All devices in the system must be powered on.

– The maximum cable length for the system is either 15 m or 1 m times the number of equivalent device loads in the system—whichever is less.

– The device capacitance on each signal should be less that 50 pF per device

(again, the 75160 and 75162 satisfy this requirement).

• Case 3: All other configurations.

Table 5-1 shows the IEEE 488.1 minimum T1 delay requirements for the three cases.

Table 5-1. IEEE 488.1 Minimum T1 Delay Requirements

Case

Number

Case 1

Case 2

Case 3

First Byte (HSTS = 0, or ATN asserted)

1100 ns

1100 ns

2000 ns

Other Bytes

(HSTS = 1)

500 ns

350 ns

2000 ns

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T1 Delay: 7210 Mode

In 7210 mode, the USTD bit (AUXRI[3]), the B2 bit (AUXRB[2]), and the HSTS signal determine the NAT7210 T1 delay. Table 5-2 shows the T1 delay for various settings.

Table 5-2. T1 Delay Settings in 7210 Mode

HSTS USTD

0 0

0

1

1

0

1

1

1

1

0

1

TRI

X

X

0

0

1

1

T1 Delay (ns)

2000

1100

2000

1100

500

350

T1 Delay: 9914 Mode

In 9914 mode, the USTD bit (ACCRI[3]), the vstdl bit (AUXCR), the stdl bit (AUXCR), and the HSTS signal determine the NAT7210 T1 delay (see the HSTS Definition section in this chapter). Table 5-3 shows the T1 delay for various settings.

Table 5-3. T1 Delay Settings in 9914 Mode

HSTS USTD

X 0

0

0

X

X

1

1

1

0

0

1 vstdl

0

X

X

0

1

X stdl

0

0

1

1

X

X

T1 Delay (ns)

2000

2000

1100

1100

500

350

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Using nbaf

You can use the nbaf auxiliary command in the following situation: Suppose the

NAT7210 is a Talker and a byte is written to the CDOR. Also suppose that the

Controller asserts ATN before the NAT7210 transfers the byte in the CDOR. The

Controller unasserts ATN and the NAT7210 is still a Talker. If NTNL is set, the Talker transmits the byte stored in the CDOR. The nbaf command suppresses the transmission of this byte.

Receiving GPIB Data Messages

Basic Flow

Complete the following steps to receive GPIB (device-dependent) data from another device in your system:

1. Wait until the NAT7210 has been programmed or addressed to be an Active

Listener.

2. Issue the rhdf auxiliary command to release holdoffs caused by the hldi auxiliary command.

3. Perform the following steps for each data byte that is received:

• Wait for the DI bit to set.

• Read the DIR to obtain the received byte.

The host interface can either poll the DI bit or configure the NAT7210 to interrupt on the DI condition by setting DI IE.

Receiving END or EOS

The END RX bit (ISR1[4]) informs the control program that the NAT7210 has received an END or EOS message. The EOS message can be the new line character, 0A hex (if the NLEN bit is set in IMR0), the value written to the EOSR (if the REOS bit in AUXRA is set), or both.

When the END bit is set, read the EOI bit in ADR1 and the NL and EOS bits in ISR0 to determine which terminating event caused END to set.

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Performing an RFD Holdoff on the Last Data Byte

You usually want to perform an RFD holdoff on the last byte of a string of data that was read in from the GPIB during a GPIB read operation. If the last byte of the data read in was sent with EOI asserted or was the EOS character, an RFD holdoff is performed automatically if the NAT7210 has been programmed for the RFD Holdoff On END Mode

(AUXRA(1–0) = 10 (bin)).

If you do not know whether the last byte that the Talker sent will be transmitted with EOI or whether it will match the EOS character, program the NAT7210 to RFD Holdoff On

All Data Mode (AUXRA(1–0) = 01 (bin)). By programming the NAT7210 to RFD

Holdoff On All Data Mode, you force the NAT7210 to perform an RFD holdoff on the next byte of data that is received in the DIR until a Release Handshake Holdoff auxiliary command is issued.

Also see the Acceptor Handshake Holdoffs section, which is located later in this chapter.

Using DMA

To use DMA to receive data bytes, set the DMAI bit after the NAT7210 has been addressed to listen. The DRQ pin of the NAT7210 asserts whenever the DIR contains a byte to read. The DMA Controller should respond to DRQ by asserting the DACK* and

RD* pins in order to read a data byte from the DIR.

Acceptor Handshake Holdoffs

The GPIB rdy Message and RFD Holdoffs

When it is a Listener, the NAT7210 must let the Talker know whether the NAT7210 is ready to receive another data byte. The NAT7210 unasserts the GPIB Not Ready For

Data (NRFD) signal to indicate that it is ready to receive another byte. The NAT7210 generates the Ready For Next (rdy) message internally. When rdy = 1, the NAT7210 is ready to receive a data byte. When rdy = 0, the NAT7210 is not ready to receive a data byte and it asserts the GPIB NRFD signal. When the NAT7210 asserts the GPIB NRFD signal to prevent the transmission of a data byte, the NAT7210 is performing a Ready For

Data (RFD) holdoff. (For more information, refer to Figure B-5, Three-Wire Handshake

Process , in Appendix B, Introduction to the GPIB.)

The NAT7210 performs RFD holdoffs only on data bytes—that is, bytes sent with ATN unasserted. The NAT7210 can holdoff command bytes by using DAC holdoffs.

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Generating the rdy Message

The local rdy message becomes true if ATN is asserted or if the following conditions are both true:

• The NAT7210 is not performing an immediate RFD holdoff.

• The NAT7210 is not performing a data byte RFD holdoff.

Immediate RFD Holdoff

Write the Holdoff Handshake Immediately (hldi) auxiliary command to the AUXMR in order to start an immediate RFD holdoff. You can clear the immediate RFD holdoff by writing the Release RFD Holdoff (rhdf) or Chip Reset auxiliary command to the

AUXMR. The pon message does not clear an immediate RFD holdoff condition, so the host interface can issue hldi while pon is set and the NAT7210 is being configured.

Read the Acceptor Not Ready Holdoff Immediately (ANHS2) bit (SASR[4]) to determine the state of the Immediate Holdoff function.

Data-Receiving Modes

The data byte RFD holdoff condition is set and cleared depending on the data-receiving mode. When the NAT7210 is a Listener, it receives data in one of four modes. One (and only one) data-receiving mode is active at any time.

1. Normal

In normal mode, the NAT7210 performs a data byte RFD holdoff after every byte it accepts. After receiving a data byte, the NAT7210 is not ready to receive another byte until the data byte RFD holdoff condition is cleared. The NAT7210 releases the holdoff when the DIR is read.

2. RFD Holdoff On All Data (hlda)

In hlda mode, the NAT7210 performs a data byte RFD holdoff after every data byte it receives. Writing the rhdf auxiliary command to the AUXMR clears the RFD holdoff condition in hlda mode.

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3. RFD Holdoff On END (hlde)

In hlde mode, the NAT7210 performs a data byte RFD holdoff after every data byte it receives. If the last data byte the NAT7210 received satisfies the END condition, writing the rhdf auxiliary command to the AUXMR clears the RFD holdoff. The END condition is defined by

END = EOI + (REOS & EOS) + (NLEE & newline)

If the last data byte the NAT7210 received does not satisfy the END condition, the

NAT7210 releases the holdoff when the DIR is read.

4. Continuous (cont)

You generally use continuous mode when the NAT7210, as a Controller, wants to monitor a data transfer between two devices but does not need to store the data.

The NAT7210 performs an RFD holdoff in continuous mode if it receives a byte that satisfies the END condition. If the NAT7210 receives a byte that does not satisfy the

END condition, it does not perform an RFD holdoff. Writing the rhdf auxiliary command to the AUXMR clears the RFD holdoff in continuous mode. Bytes are not stored in the

DIR and the DI bit does not set in continuous mode.

Choosing a Data-Receiving Mode

The value of the AUXRA[1–0] bits usually determines the data-receiving mode.

However, if the host interface writes the (ltn&cont) command to the AUXMR, the

NAT7210 uses continuous mode until the host interface either writes the ltn command to the AUXMR or the NAT7210 becomes unaddressed as a Listener.

DAC Holdoffs

When a DAC holdoff condition is true, the NAT7210 is interpreting but has not yet accepted a command byte sent by the Controller. A DAC holdoff forces the Controller to keep the command byte on the GPIB valid and the GPIB Data Valid (DAV) signal asserted. (For more information, refer to Figure B-5, Three-Wire Handshake Process , in

Appendix B, Introduction to the GPIB.) By using DAC holdoffs, a control program prevents another command from being sent until the current command has been completely processed. Once the host interface responds to the command byte, it releases the DAC holdoff by writing the valid or nonvalid auxiliary command to the AUXMR.

In most applications, you do not need to use DAC holdoffs: the NAT7210 automatically interprets command bytes and sets various interrupt bits when it receives certain command bytes.

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DAC holdoffs can occur only on GPIB command bytes (ATN asserted). Data bytes

(ATN unasserted) can be held off with RFD holdoffs, which are described earlier in this chapter.

Determining When DAC Holdoffs Occur

The NAT7210 can be configured to perform DAC holdoffs on many different types of command bytes. The SDHS signal determines which command bytes will cause a DAC holdoff. SDHS is defined by the following:

SDHS = [UCG + ACG & (TADS + LADS)] & undefined & CPT ENAB

+ UDPCF & SCG & CPT ENAB

+ DHADT & GET

+ DHADC & (SDC + DCL)

+ DHATA & TAG & ~UNT

+ DHALA & LAG & ~UNL

+ DHUNTL & (UNT + UNL)

+ DHALL & (UCG + ACG + SCG)

+ DHDC & (DCL + SDC & LADS)

+ DHDT & GET

+ SCG & (TPAS + LPAS) & (dual extended address mode)

By issuing the valid or nonvalid auxiliary command, you clear the Acceptor Data Holdoff

State (ADHS). By clearing ADHS, you clear the DAC holdoff.

Read the ADHS bit (SASR[3]) to determine the state of the DAC holdoff condition.

Device Status Reporting (Polling)

Requesting Service

Asserting the SRQ Signal

The NAT7210 requests service from the GPIB CIC by asserting the GPIB SRQ signal.

However, the host interface cannot directly control the SRQ signal: the rsv signal determines when the NAT7210 asserts SRQ.

After rsv asserts, the NAT7210 asserts the SRQ signal. When the CIC serial polls the

NAT7210, the NAT7210 unasserts SRQ. The NAT7210 does not assert SRQ again until rsv unasserts, then reasserts. Refer to the SR1 function in the IEEE 488.1 standard for more information.

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IEEE 488.2 Service Requesting

To request service, issue the reqt auxiliary command, then write the status byte (STB) to the SPMR.

Note: If STBO IE = 1 after issuing reqt, do not write to the SPMR until the STBO interrupt condition becomes true.

When you write to the SPMR, write 0 to bit 6 (the rsv bit). The NAT7210 asserts and unasserts the rsv signal according to the Set rsv State Machine that is described in the

IEEE 488.2 standard.

After the CIC serial polls the NAT7210, you must issue the reqt auxiliary command and write to the SPMR again to request service. If you want to stop requesting service before a serial poll occurs, issue the reqf auxiliary command.

7210-Style Service Requesting

Most applications should use the IEEE 488.2 service-requesting method that is described in the section above. However, the NAT7210 also supports the 7210 style of requesting service. To request service, check the PEND bit of the SPSR to make sure that the

NAT7210 is not currently responding to a serial poll. If PEND = 0, write the desired

STB to the SPMR. When you write to the SPMR, set bit 6, which is the rsv bit. This write causes the PEND bit to set and the NAT7210 to assert the GPIB SRQ line. The

PEND bit remains set until the serial poll completes.

Responding to Serial Polls

If STBO IE = 0 when the CIC serial polls the NAT7210, the NAT7210 sends the STB to the CIC without the host interface intervening.

If the contents of the STB are likely to change between the time you issue reqt and the time the CIC serial polls the NAT7210, you can use the STBO IE bit. When

STBO IE = 1, the NAT7210 does not respond to a serial poll immediately. Instead, when the CIC serial polls the NAT7210, the NAT7210 generates an interrupt. In response to this interrupt, the host interface writes the STB to the SPMR (write 0 to bit 6). The

NAT7210 responds to the serial poll by sending the STB to the CIC.

When the NAT7210 sends the STB to the CIC, it also sends the RQS message to the CIC by asserting the GPIB DIO7 signal if the NAT7210 is requesting service. The CIC normally reads the STB once, but if the CIC asserts ATN between each 1-byte read, the

CIC can read the STB any number of times. The NAT7210 asserts the GPIB DIO7 signal, however, only during the first read. After the first read, rsv clears. PEND clears when the CIC asserts ATN in order to terminate the serial poll.

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The NAT7210 asserts the GPIB EOI line during a serial poll if the SPEOI bit of AUXRB is set.

Responding to Parallel Polls

For more information, see the Parallel Polling section in Appendix B, Introduction to

the GPIB.

The ist Message

When it responds to a Parallel Poll, the NAT7210 can transmit only one bit of information to the CIC. This one bit contains the status of the ist message. If ISS = 1

(AUXRB[4]), ist is true if the NAT7210 is asserting the SRQ signal—that is, the

IEEE 488.1 Service Request function of the NAT7210 is in the SRQS state.

If ISS = 0, you set and clear the ist message by using the ist and ~ist auxiliary commands.

If ISS = 0, the meaning of the ist message is device dependent.

Remote Configuration

Before the CIC can parallel poll the NAT7210, the NAT7210 must first be configured to respond to parallel polls. The control program can locally configure the NAT7210

(IEEE 488.1 capability code PP1) or the NAT7210 can let the CIC remotely configure the

NAT7210 (IEEE 488.1 capability code PP2).

To let the CIC remotely configure the NAT7210, clear the PP2 bit in AUXRI. Do not write to the PPR. The CIC configures the NAT7210 without software intervention, and it enables or disables the NAT7210 to respond to parallel polls. The CIC configures the polarity of the NAT7210’s response, and it also selects the PPR message that the

NAT7210 uses to respond to parallel polls.

Local Configuration

To implement local configuration, disable remote configuration by setting the PP2 in

AUXRI, then write to the PPR to configure the parallel poll response. The bits in the

PPR determine which GPIB data line the NAT7210 uses to respond to parallel polls.

The PPR also determines the polarity of the parallel poll response. See Table 5-4.

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Software Considerations

Table 5-4. Parallel Poll Register Example

Binary Value Written to the AUXMR

0 1 1 1 0 0 0 0

0 1 1 0 0 0 0 0

0 1 1 0 1 0 0 1

Result

Unconfigures PPR. U = 1.

0 0 0 0 0 is written to the PPR. The NAT7210 participates in parallel polls, asserting the

DIO1 line if ist is 0.

0 1 0 0 1 is written to the PPR. The NAT7210 participates in parallel polls, asserting the

DIO2 line if ist is 1.

Chapter 5

Disabling the Parallel Poll Response

To completely disable the NAT7210 from responding to parallel polls (IEEE 488.1

capability code PP0), set the PP2 bit in AUXRI and set the U bit in the PPR.

Generating Hardware Interrupts

The Interrupt pin asserts when the INT bit (ISR2[7]) is true. If INV = 1 (AUXRB[3]), the

INTR pin is active low. If INV = 0, the INTR pin is active high.

Remote/Local State Considerations

The NAT7210 implements the GPIB Remote/Local (RL1) function as described by the

IEEE 488.1 standard. The host interface determines the state of the RL1 function by reading the Lockout (LOK) bit and the Remote (REM) bit in ISR2. The Lockout Change

(LOKC) bit and the Remote Change (REMC) bit can be used to interrupt the host interface when the state of the RL1 function changes.

If the NAT7210 is not in a Lockout state (that is, LOK = 0), the host interface can force the NAT7210 to enter a Local state (REM = 0) by writing one of the Return To Local

(rtl) auxiliary commands to the AUXMR.

See the IEEE 488.1 standard and the IEEE 488.2 standard for device requirements that depend on the RL1 function.

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Chapter 5 Software Considerations

Device Triggering

The NAT7210 enters the Device Trigger Active State (DTAS) when the GPIB Controller sends the Group Execute Trigger (GET) command to the NAT7210. As the IEEE 488.1

standard requires, the NAT7210 enters DTAS only if the NAT7210 is an Addressed

Listener. The DET bit in ISR1 sets when the NAT7210 enters DTAS. If the Data

Accepted Holdoff On Device Trigger Active State (DHDT) bit (AUXRE[1]) is set, the

NAT7210 performs a DAC holdoff when the DET bit sets.

If the DAC Holdoff On Get (DHADT) bit (AUXRE[3]) is set, the NAT7210 performs a

DAC holdoff when the NAT7210 receives the GET command (whether or not the

NAT7210 is a GPIB Listener).

The DET bit can cause an interrupt if the Enable Interrupt On Device Execute Trigger

(DET IE) bit in IMR1 is set. DHADT and DHDT can cause an interrupt if the Enable

Interrupt On Command Pass Through (CPT IE) bit (IMR1) is set.

Device Clearing

As the IEEE 488.1 standard requires, the NAT7210 enters the Device Clear Active State

(DCAS) when the GPIB Controller sends the Device Clear (DCL) command or when the

NAT7210 is a GPIB Listener and the Controller sent the Selected Device Clear (SDC) command. The Device Clear (DEC) bit in ISR1 detects when the NAT7210 enters

DCAS. If the Data Accepted Holdoff On Device Clear Active State (DHDC) bit

(AUXRE[0]) is set, the NAT7210 performs a DAC holdoff when the DEC bit sets.

If the DAC Holdoff On DCL Or SDC (DHADC) bit (AUXRE[2]) is set, the NAT7210 performs a DAC holdoff when the NAT7210 receives the DCL or SDC command

(whether or not the NAT7210 is a GPIB Listener).

DEC can cause an interrupt if the Device Clear Interrupt Enable (DEC IE) bit in IMR1 is set. DHADC and DHDC can cause an interrupt if the CPT IE bit (IMR1) is set.

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