Infineon CY8C4045PVA-S412 Microcontroller Data Sheet

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Automotive PSoC

®

4: PSoC 4000S

Family Datasheet

Programmable System-on-Chip (PSoC)

General Description

PSoC

®

ARM

®

4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an

Cortex

®

-M0+ CPU while being AEC-Q100 compliant. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4000S product family is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC 4000S products will be upward compatible with members of the PSoC 4 platform for new applications and design needs.

Features

■ Automotive Electronics Council (AEC) AEC-Q100 Qualified

32-bit MCU Subsystem

■ 48-MHz ARM Cortex-M0+ CPU

■ Up to 32 KB of flash with Read Accelerator

■ Up to 4 KB of SRAM

Programmable Analog

■ Single-slope 10-bit ADC function provided by Capacitance sensing block

■ Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin

■ Two low-power comparators that operate in Deep Sleep low-power mode

Programmable Digital

Programmable logic blocks allowing Boolean operations to be performed on port inputs and outputs

Low-Power 1.71-V to 5.5-V Operation

■ Deep Sleep mode with operational analog and 2.5 system current



A digital

Capacitive Sensing

■ Cypress CapSense Sigma-Delta (CSD) provides best-in-class signal-to-noise ratio (SNR) (>5:1) and water tolerance

■ Cypress-supplied software component makes capacitive sensing design easy

■ Automatic hardware tuning (SmartSense™)

Serial Communication

■ Two independent run-time reconfigurable Serial

Communication Blocks (SCBs) with re-configurable I2C, SPI, or UART functionality

LCD Drive Capability

■ LCD segment drive capability on GPIOs

Timing and Pulse-Width Modulation

■ Five 16-bit timer/counter/pulse-width modulator (TCPWM) blocks

■ Center-aligned, Edge, and Pseudo-random modes

■ Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications

Up to 24 Programmable GPIO Pins

■ 24-pin QFN and 28-pin SSOP packages

■ Any GPIO pin can be CapSense, analog, or digital

■ Drive modes, strengths, and slew rates are programmable

PSoC Creator Design Environment

■ Integrated Development Environment (IDE) provides schematic design entry and build (with analog and digital automatic routing)

■ Applications Programming Interface (API) component for all fixed-function and programmable peripherals

Industry-Standard Tool Compatibility

■ After schematic entry, development can be done with

ARM-based industry-standard development tools

Temperature Range

■

■

A-Grade:



40 °C to +85 °C

S-Grade:



40 °C to +105 °C

Cypress Semiconductor Corporation • 198 Champion Court

Document Number: 002-18381 Rev. *E

• San Jose

,

CA 95134-1709 • 408-943-2600

Revised November 13, 2020

Automotive PSoC

®

4: PSoC 4000S


Contents

Functional Definition ........................................................ 4

CPU and Memory Subsystem ..................................... 4

System Resources ...................................................... 4

Analog Blocks .............................................................. 5

Programmable Digital Blocks ....................................... 5

Fixed Function Digital .................................................. 5

GPIO ........................................................................... 6

Special Function Peripherals ....................................... 6

Pinouts .............................................................................. 7

Alternate Pin Functions ............................................... 8

Power ................................................................................. 9

Mode 1: 1.8 V to 5.5 V External Supply ...................... 9

Mode 2: 1.8 V ±5% External Supply ............................ 9

Development Support .................................................... 10

Documentation .......................................................... 10

Online ........................................................................ 10

Tools.......................................................................... 10

Electrical Specifications ................................................ 11

Absolute Maximum Ratings ...................................... 11

Device Level Specifications ....................................... 11

Analog Peripherals .................................................... 15

Digital Peripherals ..................................................... 18

Memory ..................................................................... 20

System Resources .................................................... 21

Ordering Information ...................................................... 23

Packaging ........................................................................ 25

Package Diagrams .................................................... 26

Acronyms ........................................................................ 28

Document Conventions ................................................. 30

Units of Measure ....................................................... 30

Revision History ............................................................. 31

Sales, Solutions, and Legal Information ...................... 32

Worldwide Sales and Design Support ....................... 32

Products .................................................................... 32

PSoC® Solutions ...................................................... 32

Cypress Developer Community ................................. 32

Technical Support ..................................................... 32

Document Number: 002-18381 Rev. *E Page 2 of 32

Automotive PSoC

®

4: PSoC 4000S


PSoC 4000S

Architecture

32-bit

AHB- Lite

System Resources

Lite

Power

Sleep Control

WIC

POR REF

PWRSYS

Clock

Clock Control

WDT

ILO IMO

Reset

Reset Control

XRES

Test

TestMode Entry

Digital DFT

Analog DFT

Figure 1. Block Diagram

CPU Subsystem

SWD/TC

Cortex

M0+

48 MHz

FAST MUL

NVIC, IRQMUX

SPCIF

FLASH

32 KB

Read Accelerator

SRAM

4 KB

SRAM Controller

Peripherals

PCLK

System Interconnect (Single Layer AHB)

Peripheral Interconnect (MMIO)

ROM

8 KB

ROM Controller

High Speed I/ O Matrix & 2x Programmable I/O

Power Modes

Active/ Sleep

DeepSleep

I/O Subsystem

PSoC 4000S devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware.

The ARM Serial-Wire Debug (SWD) interface supports all programming and debug features of the device.

Complete debug-on-chip functionality enables full-device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug.

The PSoC Creator IDE provides fully integrated programming and debug support for the PSoC 4000S devices. The SWD interface is fully compatible with industry-standard third-party tools. The PSoC 4000S family provides a level of security not possible with multi-chip application solutions or with microcontrollers. It has the following advantages:

■

Allows disabling of debug features

■ Robust flash protection

■

Allows customer-proprietary functionality to be implemented in on-chip programmable blocks

24x GPIOs, LCD

The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables debugging.

Thus firmware control of debugging cannot be over-ridden without erasing the firmware thus providing security.

Additionally, all device interfaces can be permanently disabled

(device security) for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when maximum device security is enabled. Therefore,

PSoC 4000S, with device security enabled, may not be returned for failure analysis. This is a trade-off the PSoC 4000S allows the customer to make.


Automotive PSoC

®

4: PSoC 4000S


Functional Definition

CPU and Memory Subsystem

CPU

The Cortex-M0+ CPU in the PSoC 4000S is part of the 32-bit

MCU subsystem, which is optimized for low-power operation with extensive clock gating. Most instructions are 16 bits in length and the CPU executes a subset of the Thumb-2 instruction set.

It includes a nested vectored interrupt controller (NVIC) block with eight interrupt inputs and also includes a Wakeup Interrupt

Controller (WIC). The WIC can wake the processor from Deep

Sleep mode, allowing power to be switched off to the main processor when the chip is in Deep Sleep mode.

The CPU also includes a debug interface, the serial wire debug

(SWD) interface, which is a two-wire form of JTAG. The debug configuration used for PSoC 4000S has four breakpoint

(address) comparators and two watchpoint (data) comparators.

Flash

The PSoC 4000S device has a flash module with a flash accelerator, tightly coupled to the CPU to improve average access times from the flash block. The low-power flash block is designed to deliver two wait-state (WS) access time at 48 MHz.

The flash accelerator delivers 85% of single-cycle SRAM access performance on average.

SRAM

Four KB of SRAM are provided with zero wait-state access at

48 MHz.

SROM

A supervisory ROM that contains boot and configuration routines is provided.

System Resources

Power System

The power system is described in detail in the section Power on page 9 . It provides assurance that voltage levels are as required

for each respective mode and either delays mode entry (for example, on power-on reset (POR)) until voltage levels are as required for proper functionality, or generates resets (for example, on brown-out detection). The PSoC 4000S operates with a single external supply over the range of either 1.8 V ±5%

(externally regulated) or 1.8 to 5.5 V (internally regulated) and has three different power modes, transitions between which are managed by the power system. The PSoC 4000S provides

Active, Sleep, and Deep Sleep low-power modes.

All subsystems are operational in Active mode. The CPU subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep mode, while all peripherals and interrupts are active with instantaneous wake-up on a wake-up event. In Deep Sleep mode, the high-speed clock and associated circuitry is switched off; wake-up from this mode takes 35 µs. The opamps can remain operational in Deep Sleep mode.

Clock System

The PSoC 4000S clock system is responsible for providing clocks to all subsystems that require clocks and for switching between different clock sources without glitching. In addition, the clock system ensures that there are no metastable conditions.

The clock system for the PSoC 4000S consists of the internal main oscillator (IMO), internal low-frequency oscillator (ILO), a

32 kHz Watch Crystal Oscillator (WCO) and provision for an external clock. Clock dividers are provided to generate clocks for peripherals on a fine-grained basis. Fractional dividers are also provided to enable clocking of higher data rates for UARTs.

The HFCLK signal can be divided down to generate synchronous clocks for the analog and digital peripherals. There are eight clock dividers for the PSoC 4000S, two of those are fractional dividers. The 16-bit capability allows flexible generation of fine-grained frequency values, and is fully supported in

PSoC Creator.

Figure 2. PSoC 4000S MCU Clocking Architecture

IMO HFCLK

Divide By

2,4,8

External Clock

ILO LFCLK

HFCLK Prescaler

Integer

Dividers

Fractional

Dividers

6X 16-bit

2X 16.5-bit

SYSCLK

IMO Clock Source

The IMO is the primary source of internal clocking in the

PSoC 4000S. It is trimmed during testing to achieve the specified accuracy.The IMO default frequency is 24 MHz and it can be adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO tolerance with Cypress-provided calibration settings is ±2%.

ILO Clock Source

The ILO is a very low power, nominally 40-kHz oscillator, which is primarily used to generate clocks for the watchdog timer

(WDT) and peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy.

Cypress provides a software component, which does the calibration.

Watch Crystal Oscillator (WCO)

The PSoC 4000S clock subsystem also implements a low-frequency (32-kHz watch crystal) oscillator that can be used for precision timing applications.


Automotive PSoC

®

4: PSoC 4000S


Watchdog Timer

A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during Deep Sleep and generates a watchdog reset if not serviced before the set timeout occurs. The watchdog reset is recorded in a Reset Cause register, which is firmware readable.

Reset

The PSoC 4000S can be reset from a variety of sources including a software reset. Reset events are asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset and allows software to determine the cause of the reset. An XRES pin is reserved for external reset by asserting it active low. The XRES pin has an internal pull-up resistor that is always enabled.

Voltage Reference

The PSoC 4000S reference system generates all internally required references. A 1.2-V voltage reference is provided for the comparator. The IDACs are based on a ±5% reference.

Analog Blocks

Low-power Comparators (LPC)

The PSoC 4000S has a pair of low-power comparators, which can also operate in Deep Sleep modes. This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode where the system wake-up circuit is activated by a comparator switch event. The LPC outputs can be routed to pins.

Current DACs

The PSoC 4000S has two IDACs, which can drive any of the pins on the chip. These IDACs have programmable current ranges.

Analog Multiplexed Buses

The PSoC 4000S has two concentric independent buses that go around the periphery of the chip. These buses (called amux buses) are connected to firmware-programmable analog switches that allow the chip's internal resources (IDACs, comparator) to connect to any pin on the I/O Ports.

Programmable Digital Blocks

The programmable I/O (Smart I/O) block is a fabric of switches and LUTs that allows Boolean functions to be performed in signals being routed to the pins of a GPIO port. The Smart I/O can perform logical operations on input pins to the chip and on signals going out as outputs.

Fixed Function Digital

Timer/Counter/PWM (TCPWM) Block

The TCPWM block consists of a 16-bit counter with user-programmable period length. There is a capture register to record the count value at the time of an event (which may be an

I/O event), a period register that is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals that are used as PWM duty cycle outputs. The block also provides true and complementary outputs with programmable offset between them to allow use as dead-band programmable complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this is used in motor drive systems when an over-current state is indicated and the PWM driving the FETs needs to be shut off immediately with no time for software intervention. There are five TCPWM blocks in the PSoC 4000S.

Serial Communication Block (SCB)

The PSoC 4000S has two serial communication blocks, which can be programmed to have SPI, I2C, or UART functionality.

I

2

C Mode : The hardware I

2

C block implements a full multi-master and slave interface (it is capable of multi-master arbitration). This block is capable of operating at speeds of up to

1 Mbps (Fast Mode Plus) and has flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EZI2C that creates a mailbox address range in the memory of the PSoC 4000S and effectively reduces I

2

C communication to reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock stretching caused by the

CPU not having read data on time.

The I

2

C peripheral is compatible with the I

2

C Standard-mode and

Fast Mode Plus devices as defined in the NXP I specification and user manual (UM10204). The I implemented with GPIO in open-drain modes.

2

2

C-bus

C bus I/O is

The PSoC 4000S is not completely compliant with the I

2 in the following respect:

C spec

■

I

GPIO cells are not overvoltage tolerant and, therefore, cannot be hot-swapped or powered up independently of the rest of the

2

C system.

UART Mode : This is a full-feature UART operating at up to

1 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated.

SPI Mode : The SPI mode supports full Motorola SPI, TI SSP

(adds a start pulse used to synchronize SPI Codecs), and

National Microwire (half-duplex form of SPI). The SPI block can use the FIFO.

LIN Slave Mode: The LIN Slave mode uses the SCB hardware block and implements a full LIN slave interface. This LIN Slave is compliant with LIN v1.3, v2.1/2.2, ISO 17987-6, and SAE

J2602-2 specification standards. It is certified by C&S GmbH based on the standard protocol and data link layer conformance tests. LIN slave can be operated at baud rates of up to ~20 Kbps with a maximum of 40-meter cable length. PSoC Creator software supports up to two LIN slave interfaces in the PSoC 4 device, providing built-in application programming interfaces

(APIs) based on the LIN specification standard.


Automotive PSoC

®

4: PSoC 4000S


GPIO

The PSoC 4000S has up to 24 GPIOs. The GPIO block implements the following:

■

■

❐

❐

❐

❐

❐

❐

❐

❐

Eight drive modes:

Analog input mode (input and output buffers disabled)

Input only

Weak pull-up with strong pull-down

Strong pull-up with weak pull-down

Open drain with strong pull-down

Open drain with strong pull-up

Strong pull-up with strong pull-down

Weak pull-up with weak pull-down

Input threshold select (CMOS or LVTTL).

■

Individual control of input and output buffer enabling/disabling in addition to the drive strength modes

■

Selectable slew rates for dV/dt related noise control to improve

EMI

The pins are organized in logical entities called ports, which are

8-bit in width (less for Ports 2 and 3). During power-on and reset, the blocks are forced to the disabled state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may connect to an I/O pin.

Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the pins themselves.

Every I/O pin can generate an interrupt if so enabled and each

I/O port has an interrupt request (IRQ) and interrupt service routine (ISR) vector associated with it (5 for PSoC 4000S).

Special Function Peripherals

CapSense

CapSense is supported in the PSoC 4000S through a CapSense

Sigma-Delta (CSD) block that can be connected to any pins through an analog multiplex bus via analog switches. CapSense function can thus be provided on any available pin or group of pins in a system under software control. A PSoC Creator component is provided for the CapSense block to make it easy for the user.

Shield voltage can be driven on another analog multiplex bus to provide water-tolerance capability. Water tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input. Proximity sensing can also be implemented.

The CapSense block has two IDACs, which can be used for general purposes if CapSense is not being used (both IDACs are available in that case) or if CapSense is used without water tolerance (one IDAC is available).

The CapSense block also provides a 10-bit Slope ADC function, which can be used in conjunction with the CapSense function.

The CapSense block is an advanced, low-noise, programmable block with programmable voltage references and current source ranges for improved sensitivity and flexibility. It can also use an external reference voltage. It has a full-wave CSD mode that alternates sensing to VDDA and Ground to null out power-supply related noise.

LCD Segment Drive

The PSoC 4000S has an LCD controller, which can drive up to

4 commons and 20 segments. It uses full digital methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods used are referred to as Digital

Correlation and PWM. Digital Correlation pertains to modulating the frequency and drive levels of the common and segment signals to generate the highest RMS voltage across a segment to light it up or to keep the RMS signal to zero. This method is good for STN displays but may result in reduced contrast with TN

(cheaper) displays. PWM pertains to driving the panel with PWM signals to effectively use the capacitance of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This method results in higher power consumption but can result in better results when driving TN displays. LCD operation is supported during Deep Sleep refreshing a small display buffer (4 bits; 1 32-bit register per port).


Automotive PSoC

®

4: PSoC 4000S


Pinouts

Table 1 provides the pin list for PSoC 4000S for the 24-pin QFN and 28-pin SSOP packages. All port pins support GPIO.

Table 1. Automotive PSoC 4000S Pin List

24-QFN 28-SSOP

Pin

13

14

Name

P0.0

P0.1

Pin

19

20

21

22

Name

P0.0

P0.1

P0.2

P0.3

15

16

17

P0.4

P0.5

P0.6

18

19

20

21

22

XRES

VCCD

VSSD

VDD

VSSA

23

24

25

26

27

28

P0.6

P0.7

XRES

VCCD

VSS

VDD

23

24

P1.2

P1.3

4

5

6

1

2

3

P1.0

P1.1

P1.2

P1.3

P1.4

P1.7

1

2

3

P1.7

P2.0

P2.1

4

5

P2.6

P2.7

7

8

9

10

P2.4

P2.5

P2.6

P2.7

6

7

8

9

10

11

12

P3.0

P3.2

P3.3

P4.0

P4.1

P4.2

P4.3

15

16

17

18

11

12

13

14

Descriptions of the pin functions are as follows:

VDDD : Power supply for the digital section.

VDDA : Power supply for the analog section.

VSSD, VSSA : Ground pins for the digital and analog sections respectively.

VCCD : Regulated digital supply (1.8 V ±5%)

VDD: On some packages, VDDA and VDDD are shorted inside and brought out as a single power supply

VSS: On some packages, VSSA and VSSD are shorted inside and brought out as a single ground

P3.0

P3.1

P3.2

P3.3

P4.0

P4.1

P4.2

P4.3


Automotive PSoC

®

4: PSoC 4000S


Alternate Pin Functions

Each port pin can be assigned to one of multiple functions; it can, for instance, be an analog I/O, a digital peripheral function, an LCD pin, or a CapSense pin. The pin assignments are shown in the following table.

Port/

Pin

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

Analog lpcomp.in_p[0] lpcomp.in_n[0] lpcomp.in_p[1] lpcomp.in_n[1] wco.wco_in

wco.wco_out

Smart I/O Alternate Function 1 Alternate Function 2 Alternate Function 3 tcpwm.tr_in[0] tcpwm.tr_in[1] srss.ext_clk

scb[1].uart_rx:0 scb[1].uart_tx:0 scb[1].uart_cts:0 scb[1].uart_rts:0

Deep Sleep 1 scb[1].i2c_scl:0 scb[1].i2c_sda:0

Deep Sleep 2 scb[0].spi_select1:0 scb[0].spi_select2:0 scb[0].spi_select3:0 scb[1].spi_mosi:1 scb[1].spi_miso:1 scb[1].spi_clk:1 scb[1].spi_select0:1

P1.0

tcpwm.line[2]:1 scb[0].uart_rx:1 scb[0].i2c_scl:0 scb[0].spi_mosi:1

P1.1

P1.2

P1.3

P1.4

tcpwm.line_compl[2]:1 tcpwm.line[3]:1 tcpwm.line_compl[3]:1 scb[0].uart_tx:1 scb[0].uart_cts:1 scb[0].uart_rts:1 tcpwm.tr_in[2] tcpwm.tr_in[3] scb[0].i2c_sda:0 scb[0].spi_miso:1 scb[0].spi_clk:1 scb[0].spi_select0:1 scb[0].spi_select1:1

P1.7

P2.0

P3.1

P3.2

P3.3

P3.4

P4.0

P4.1

P4.2

P2.1

P2.4

P2.5

P2.6

P2.7

P3.0

P4.3

csd.vref_ext

csd.cshieldpads

csd.cmodpad

csd.csh_tank

prgio[0].io[0] tcpwm.line[4]:0 csd.comp

prgio[0].io[1] prgio[0].io[4] prgio[0].io[5] prgio[0].io[6] prgio[0].io[7] prgio[1].io[0] prgio[1].io[1] prgio[1].io[2] prgio[1].io[3] prgio[1].io[4] tcpwm.line_compl[4]:0 tcpwm.line[0]:1 tcpwm.line_compl[0]:1 tcpwm.line[1]:1 tcpwm.line_compl[1]:1 tcpwm.line[0]:0 scb[1].uart_rx:1 tcpwm.line_compl[0]:0 tcpwm.line[1]:0 tcpwm.line_compl[1]:0 tcpwm.line[2]:0 scb[1].uart_tx:1 scb[1].uart_cts:1 scb[1].uart_rts:1 scb[0].uart_rx:0 scb[0].uart_tx:0 scb[0].uart_cts:0 scb[0].uart_rts:0 tcpwm.tr_in[4] scb[1].i2c_scl:1 scb[1].spi_mosi:2 tcpwm.tr_in[5] tcpwm.tr_in[6] tcpwm.tr_in[10] tcpwm.tr_in[11] scb[1].i2c_sda:1 scb[1].spi_miso:2 scb[1].spi_select1:1 scb[1].spi_select2:1 scb[1].spi_select3:1 lpcomp.comp[0]:1 scb[1].i2c_scl:2 scb[1].spi_mosi:0 scb[1].i2c_sda:2 scb[1].spi_miso:0 cpuss.swd_data

cpuss.swd_clk

scb[0].i2c_scl:1 scb[0].i2c_sda:1 lpcomp.comp[0]:0 scb[1].spi_clk:0 scb[1].spi_select0:0 scb[1].spi_select1:0 scb[0].spi_mosi:0 scb[0].spi_miso:0 scb[0].spi_clk:0 lpcomp.comp[1]:0 scb[0].spi_select0:0


Automotive PSoC

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4: PSoC 4000S


Power

The following power system diagram shows the set of power supply pins as implemented for the PSoC 4000S. The system has one regulator in Active mode for the digital circuitry. There is no analog regulator; the analog circuits run directly from the

V

DDA

input.

Figure 3. Power Supply Connections

VDDA

VSSA

Analog

Domain

Digital

Domain

1.8 Volt

Regulator

VDDD

VSSD

VCCD

VDD

Mode 1: 1.8 V to 5.5 V External Supply

In this mode, the PSoC 4000S is powered by an external power supply that can be anywhere in the range of 1.8 to 5.5 V. This range is also designed for battery-powered operation. For example, the chip can be powered from a battery system that starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of the PSoC 4000S supplies the internal logic and its output is connected to the V

CCD

pin. The VCCD pin must be bypassed to ground via an external capacitor (0.1 µF; X5R ceramic or better) and must not be connected to anything else.

Mode 2: 1.8 V ±5% External Supply

In this mode, the PSoC 4000S is powered by an external power supply that must be within the range of 1.71 to 1.89 V; note that this range needs to include the power supply ripple too. In this mode, the VDD and VCCD pins are shorted together and bypassed.

Bypass capacitors must be used from VDD to ground. The typical practice for systems in this frequency range is to use a capacitor in the 1-µF range, in parallel with a smaller capacitor

(0.1 µF, for example). Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing.

An example of a bypass scheme is shown in Figure 4 .

There are two distinct modes of operation. In Mode 1, the supply voltage range is 1.8 V to 5.5 V (unregulated externally; internal regulator operational). In Mode 2, the supply range is1.8 V ±5%

(externally regulated; 1.71 to 1.89, internal regulator bypassed).

Figure 4. External Supply Range from 1.8 V to 5.5 V with Internal Regulator Active

Power supply bypass connections example

 F

1.8V to 5.5V

0.1

 F

PSoC 4000S

V

DD

V

CCD

0.1

 F

V

SS


Automotive PSoC

®

4: PSoC 4000S


Development Support

The PSoC 4000S family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit www.cypress.com/go/psoc4 to find out more.

Documentation

A suite of documentation supports the PSoC 4000S family to ensure that you can find answers to your questions quickly. This section contains a list of some of the key documents.

Software User Guide : A step-by-step guide for using

PSoC Creator. The software user guide shows you how the

PSoC Creator build process works in detail, how to use source control with PSoC Creator, and much more.

Component Datasheets : The flexibility of PSoC allows the creation of new peripherals (components) long after the device has gone into production. Component data sheets provide all of the information needed to select and use a particular component, including a functional description, API documentation, example code, and AC/DC specifications.

Application Notes : PSoC application notes discuss a particular application of PSoC in depth; examples include brushless DC motor control and on-chip filtering. Application notes often include example projects in addition to the application note document.

Technical Reference Manual : The Technical Reference Manual

(TRM) contains all the technical detail you need to use a PSoC device, including a complete description of all PSoC registers.

The TRM is available in the Documentation section at www.cypress.com/psoc4.

Online

In addition to print documentation, the Cypress PSoC forums connect you with fellow PSoC users and experts in PSoC from around the world, 24 hours a day, 7 days a week.

Tools

With industry standard cores, programming, and debugging interfaces, the PSoC 4000S family is part of a development tool ecosystem. Visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy to use PSoC Creator

IDE, supported third party compilers, programmers, debuggers, and development kits.


Automotive PSoC

®

4: PSoC 4000S


Electrical Specifications

Absolute Maximum Ratings

Table 2. Absolute Maximum Ratings

[1]

Spec ID#

SID1

SID2

SID3

SID4

SID5

BID44

BID45

BID46

Parameter

V

DDD_ABS

V

CCD_ABS

V

GPIO_ABS

I

GPIO_ABS

I

GPIO_injection

ESD_HBM

ESD_CDM

LU

Description

Digital supply relative to V

SS

Direct digital core voltage input relative to V

SS

GPIO voltage

Maximum current per GPIO

GPIO injection current, Max for V

IH

V

DDD

, and Min for V

IL

< V

SS

>

Electrostatic discharge human body model

Electrostatic discharge charged device model

Pin current for latch-up

Min

–0.5

–0.5

–0.5

–25

–0.5

2200

500

–140

Typ

–

–

–

–

–

–

–

–

Max

6

1.95

V

DD

+0.5

25

0.5

–

–

140

Units

V mA

V mA

Details/

Conditions

–

–

–

–

Current injected per pin

–

–

–

Device Level Specifications

All specifications are valid for –40 °C  T

A

 85 °C for A grade devices and –40 °C  T

A

 105 °C for S grade devices, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.

Table 3. DC Specifications

Typical values measured at V

DD

= 3.3 V and 25 °C.

Spec ID#

SID53

Parameter

V

DD

Description

Power supply input voltage

Min

1.8

Typ

–

Max

5.5

Units

Details/

Conditions

Internally regulated supply

SID255

SID54

SID55

SID56

V

DD

V

CCD

C

EFC

C

EXC

Power supply input voltage (V

CCD

V

DD

= V

DDA

)

=

Output voltage (for core logic)

External regulator voltage bypass

Power supply bypass capacitor

1.71

–

–

–

–

1.8

0.1

1

1.89

–

–

–

V

µ F

Internally unregulated supply

–

X5R ceramic or better

X5R ceramic or better

Active Mode, V

DD

= 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 °C.

SID10

SID16

SID19

I

DD5

I

DD8

I

DD11

Execute from flash; CPU at 6 MHz



–

–

–

1.2

2.4

4.6

2.0

4.0

5.9

mA

Max is at 105 °C and 5.5 V



Note

1. Usage above the absolute maximum conditions listed in Table 2 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended

periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature

Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.


Automotive PSoC

®

4: PSoC 4000S


Table 3. DC Specifications

(continued)

Typical values measured at V

DD

= 3.3 V and 25 °C.

Spec ID# Parameter Description

Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)

SID22 I

DD17

I

2

C wakeup WDT, and Comparators on

SID25 I

DD20

I

2

C wakeup, WDT, and Comparators on

Sleep Mode, V

DDD

= 1.71 V to 1.89 V (Regulator bypassed)

SID28 I

DD23

I

2


SID28A I

DD23A

I

2


Min

–

–

–

–

Deep Sleep Mode, V

DD

= 1.8 V to 3.6 V (Regulator on)

SID31 I

DD26

I

2

C wakeup and WDT on –


DD

= 3.6 V to 5.5 V (Regulator on)

SID34 I

DD29

I

2

C wakeup and WDT on


DD

= V

CCD

= 1.71 V to 1.89 V (Regulator bypassed)

SID37 I

DD32

I

2

C wakeup and WDT on

XRES Current

SID307 I

DD_XR

Supply current while XRES asserted

–

–

–

Table 4. AC Specifications

Spec ID#

SID48

SID49

[3]

SID50

[3]

Parameter

F

CPU

T

SLEEP

T

DEEPSLEEP

Description

CPU frequency

Wakeup from Sleep mode

Wakeup from Deep Sleep mode

Min

DC

–

–

Typ

1.1

1.4

0.7

0.9

2.5

2.5

2.5

2

Typ

–

0

35

0.9

1.1

60

60

60

5

Max

48

–

–

Max

1.6

1.9

Units

Details/

Conditions mA 6 MHz, Max is at

105 °C and 5.5 V

12 MHz, Max is at

105 °C and 5.5 V mA mA

µ

µ

µ

A

A

A mA

Units

6 MHz, Max is at

105 °C

12 MHz, Max is at

105 °C and 5.5 V


Max is at 105 °C

Max is at 105 °C

Details/

Conditions

MHz 1.71  V

DD

 5.5

µs

Max is at 105 °C

Note

2. Guaranteed by characterization.


Automotive PSoC

®

4: PSoC 4000S


GPIO

Table 5. GPIO DC Specifications

Spec ID#

SID57

Parameter

V

IH

[3]

Description

Input voltage high threshold

SID58

SID241

V

IL

V

IH

[3]

Input voltage low threshold

LVTTL input, V

DDD

< 2.7 V

SID242

SID243

SID244

SID59

SID60

SID61

SID62

SID62A

SID63

SID64

SID65

SID66

SID67

[4]

SID68

[4]

SID68A

SID69

[4]

SID69A

[4]

[4]

Min

0.7 



V

DDD

–

0.7 



V

DDD

I

I

I

V

IL

V

IH

[3]

V

IL

V

OH

V

OH

V

OL

V

OL

V

OL

R

PULLUP

R

PULLDOWN

IL

C

IN

V

HYSTTL

V

HYSCMOS

V

HYSCMOS5V5

DIODE

TOT_GPIO

LVTTL input, V

DDD

< 2.7 V –

LVTTL input, V

DDD

 2.7 V

LVTTL input, V

DDD

 2.7 V

Output voltage high level

Output voltage high level

Output voltage low level



Pull-up resistor

Pull-down resistor

2.0

–

V

DDD

–0.6

V

DDD

–0.5

–

–

–

3.5

3.5

Input leakage current (absolute value)

Input capacitance

–

–

Input hysteresis LVTTL

Input hysteresis CMOS

Input hysteresis CMOS

Current through protection diode to

V

DD

/V

SS

Maximum total source or sink chip current

25

0.05 × V

DDD

200

–

–

–

–

–

–

–

–

–

–

5.6

5.6

–

–

40

–

–

–

Typ

–

–

–

–

2

7

–

–

–

100

0.6

0.4

8.5

8.5

0.8

–

–

0.6

Max

–

0.3 

V

DDD



–

0.3 

V

DDD



–

Units Details/Conditions

CMOS Input

CMOS Input

–

V kΩ

–

–

–

I

OH

= 4 mA at 3 V V

DDD

I

OH

= 1 mA at 3 V V

DDD

I

OL

= 4 mA at 1.8 V V

DDD

I

OL

= 10 mA at 3 V V

DDD

I

OL

= 3 mA at 3 V V

DDD

–

– nA 25 °C, V

DDD

= 3.0 V pF mV

–

V

DDD

 2.7 V

V

DD

< 4.5 V

V

DD

> 4.5 V

µ A –

200 mA –

Table 6. GPIO AC Specifications

(Guaranteed by Characterization)

Spec ID#

SID70 T

Parameter

RISEF

Description

Rise time in fast strong mode

SID71 T

FALLF

Fall time in fast strong mode

SID72

SID73

T

RISES

T

FALLS

Rise time in slow strong mode

Fall time in slow strong mode

Min

2

2

10

10

–

–

Typ

–

–

Max

12

12

60

60

Units ns

–

–

Details/Conditions

3.3 V V

DDD

,

Cload = 25 pF

3.3 V V

DDD

,

Cload = 25 pF

3.3 V V

DDD

,

Cload = 25 pF

3.3 V V

DDD

,

Cload = 25 pF

Notes

3. V

IH

must not exceed V

DDD

+ 0.2 V.



Automotive PSoC

®

4: PSoC 4000S


Table 6. GPIO AC Specifications

(Guaranteed by Characterization) (continued)

Spec ID# Parameter

SID74

SID75

SID76

SID245

SID246

F

F

F

F

F

GPIOUT1

GPIOUT2

GPIOUT3

GPIOUT4

GPIOIN

Description

GPIO F

OUT

; 3.3 V  V

DDD

 5.5 V

Fast strong mode

GPIO F

OUT

; 1.71 V  V

DDD

Fast strong mode

 3.3 V

GPIO F

OUT

; 3.3 V  V

DDD

 5.5 V

Slow strong mode

GPIO F

OUT

; 1.71 V  V

DDD

 3.3 V

Slow strong mode.

GPIO input operating frequency;

1.71 V  V

DDD

 5.5 V

Min

–

–

–

–

–

XRES

Table 7. XRES DC Specifications

Spec ID#

SID77

SID78

SID79

SID80

Parameter

V

IH

V

IL

R

PULLUP

C

IN

Description Min

Input voltage high threshold 0.7 × V

DDD

Input voltage low threshold –

Pull-up resistor

Input capacitance

–

–

SID81

[5]

V

HYSXRES

Input voltage hysteresis –

SID82 I

DIODE

Current through protection diode to V

DD

/V

SS

–

Typ

–

–

–

–

–

100

–

Typ

–

–

60

–

Max

33

16.7

7

3.5

48

Units

MHz


90/10%, 25 pF load,

60/40 duty cycle

90/10%, 25 pF load,

60/40 duty cycle

90/10%, 25 pF load,

60/40 duty cycle

90/10%, 25 pF load,

60/40 duty cycle

90/10% V

IO

Max

–

0.3  V

DDD

–

7

–

Units

V kΩ pF mV


CMOS Input

–

–

Typical hysteresis is

200 mV for V

DD

> 4.5 V

100 µA

Table 8. XRES AC Specifications

Spec ID#

SID83

[5]

T

Parameter

RESETWIDTH

BID194

[5]

T

RESETWAKE

Description

Reset pulse width

Wake-up time from reset release

Min

1

–

Typ

–

–

Max

–

2.7

Units

µs ms


–

–

Note



Automotive PSoC

®

4: PSoC 4000S


Analog Peripherals

Table 9. Comparator DC Specifications


SID84 V

OFFSET1

SID85

SID86

V

OFFSET2

V

HYST

SID87 V

ICM1

SID247 V

ICM2

Description

Input offset voltage, Factory trim

Input offset voltage, Custom trim

Hysteresis when enabled

Input common mode voltage in normal mode

Min

–

–

–

0

Input common mode voltage in low power mode 0

Typ

–

–

10

–

–

SID247A V

ICM3

Input common mode voltage in ultra low power mode

0 –

SID88 C

MRR

SID88A C

MRR

SID89 I

CMP1

SID248 I

CMP2

Common mode rejection ratio

Common mode rejection ratio

Block current, normal mode

Block current, low power mode

50

42

–

–

–

–

–

–

SID259

SID90

I

CMP3

Z

CMP

Block current in ultra low-power mode

DC Input impedance of comparator

–

35

6

–

Max

±10

±4

35

V

DDD

-0.1

V

DDD

V

DDD

-1.15

–

–

400

100

28

–


– mV –

–

V dB

µA

MΩ

Modes 1 and 2

–

V

DDD

≥ 2.2 V at –40

°C

V

DDD

≥ 2.7V

V

DDD

≤ 2.7V

–

–

V

DDD

≥ 2.2 V at –40

°C

–

Table 10. Comparator AC Specifications


SID91 TRESP1

Description

Response time, normal mode, 50 mV overdrive

Min Typ

– 38

70 SID258 TRESP2 Response time, low power mode, 50 mV overdrive –

SID92 TRESP3

Response time, ultra-low power mode, 200 mV overdrive

– 2.3

Max

110

200

15


– ns

–

µs

V

DDD

≥ 2.2 V at

–40 °C


Automotive PSoC

®

4: PSoC 4000S


CSD

Table 11. CSD and IDAC Specifications

SPEC ID#

SYS.PER#3

Parameter

VDD_RIPPLE

Description

Max allowed ripple on power supply,

DC to 10 MHz

SYS.PER#16 VDD_RIPPLE_1.8

Max allowed ripple on power supply,

DC to 10 MHz

SID.CSD.BLK

ICSD Maximum block current

Min

–

–

–

SID.CSD#15

SID.CSD#15A

SID.CSD#16

SID.CSD#17

SID308

SID308A

SID309

SID310

SID311

SID312

SID313

SID314

SID314A

SID314B

SID314C

SID314D

SID314E

SID315

SID315A

SID315B

SID315C

SID315D

SID315E

V

REF

VREF_EXT

IDAC1IDD

IDAC2IDD

VCSD

Voltage reference for CSD and

Comparator

External Voltage reference for CSD and Comparator

IDAC1 (7-bits) block current

IDAC2 (7-bits) block current

Voltage range of operation

VCOMPIDAC Voltage compliance range of IDAC

IDAC1DNL

IDAC1INL

IDAC2DNL

IDAC2INL

SNR

IDAC1CRT1

IDAC1CRT2

IDAC1CRT3

IDAC1CRT12

IDAC1CRT22

IDAC1CRT32

IDAC2CRT1

IDAC2CRT2

IDAC2CRT3

IDAC2CRT12

IDAC2CRT22

IDAC2CRT32

DNL

INL

DNL

INL

Ratio of counts of finger to noise.

Guaranteed by characterization

Output current of IDAC1 (7 bits) in low range

Output current of IDAC1(7 bits) in medium range

Output current of IDAC1(7 bits) in high range

Output current of IDAC1 (7 bits) in low range, 2X mode

Output current of IDAC1(7 bits) in medium range, 2X mode

Output current of IDAC1(7 bits) in high range, 2X mode

Output current of IDAC2 (7 bits) in low range

Output current of IDAC2 (7 bits) in medium range

Output current of IDAC2 (7 bits) in high range

Output current of IDAC2 (7 bits) in low range, 2X mode

Output current of IDAC2(7 bits) in medium range, 2X mode

Output current of IDAC2(7 bits) in high range, 2X mode

0.6

0.6

–

–

1.71

0.6

–1

–2

–1

–2

5

4.2

34

275

8

69

540

4.2

34

275

8

69

540

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

Typ

–

–

–

1.2

Max

±50

±25

4000

V

DDA

- 0.6

V

DDA

- 0.6

1750

1750

5.5

V

DDA

–0.6

1

2

1

2

–

5.4

Units mV mV

µA

Details / Conditions

V

DD

> 2 V (with ripple), 25 °C T

A

,

Sensitivity = 0.1 pF

V

DD

T

A

> 1.75V (with ripple), 25 °C

, Parasitic Capacitance (C

20 pF, Sensitivity ≥ 0.4 pF

P

) <

Maximum block current for both

IDACs in dynamic (switching) mode including comparators, buffer, and reference generator.

V

V

V

DDA lower

- 0.06 or 4.4, whichever is

V

DDA lower


µA

µA

V 1.8 V ±5% or 1.8 V to 5.5 V

V

V

DDA lower


LSB

LSB INL is ±5.5 LSB for V

DDA

< 2 V

LSB

LSB INL is ±5.5 LSB for V

DDA

< 2 V

Ratio

Capacitance range of 5 to 35 pF,

0.1-pF sensitivity. All use cases.

V

DDA

> 2 V.

µA LSB = 37.5-nA typ.

41

330

µA LSB = 300-nA typ.

µA LSB = 2.4-µA typ.

10.5

82

660

5.4





41

330

10.5

82

660







Automotive PSoC

®

4: PSoC 4000S


SIDA99

SIDA100

SIDA101

SIDA103

SIDA104

SIDA106

SIDA107

Table 11. CSD and IDAC Specifications (continued)

SPEC ID#

SID315F

SID315G

SID315H

Parameter

IDAC3CRT13

IDAC3CRT23

IDAC3CRT33

Description

Output current of IDAC in 8-bit mode in low range

Output current of IDAC in 8-bit mode in medium range

Output current of IDAC in 8-bit mode in high range

Min

8

69

540

SID320 IDACOFFSET All zeroes input –

SID321

SID322

SID322A

SID322B

SID323

SID324

SID325

IDACGAIN

IDACMISMATCH1

IDACMISMATCH2

IDACMISMATCH3

Full-scale error less offset

Mismatch between IDAC1 and

IDAC2 in Low mode


IDAC2 in Medium mode


IDAC2 in High mode

IDACSET8 Settling time to 0.5 LSB for 8-bit IDAC

IDACSET7

CMOD

Settling time to 0.5 LSB for 7-bit IDAC

External modulator capacitor.

–

–

–

–

–

–

–

Table 12. 10-bit CapSense ADC Specifications

Spec ID#

SIDA94

SIDA95

SIDA97

Parameter

A_RES

A_CHNLS_S

A-MONO

Description

Resolution

Number of channels - single ended

Monotonicity

SIDA98 A_GAINERR Gain error

Min

–

–

–

–

Typ

–

–

–

Typ

–

–

–

–

–

–

2.2

–

–

–

–

–

Max

10.5

82

660

Max

10

16

–

±2

10

10

–

5.6

6.8

1

±10

9.2

SIDA108

A_OFFSET

A_ISAR

A_VINS

A_INRES

A_INCAP

A_PSRR

A_TACQ

A_CONV8

Input offset voltage

Current consumption

Input voltage range - single ended

Input resistance

Input capacitance

Power supply rejection ratio

Sample acquisition time

Conversion time for 8-bit resolution at conversion rate =

Fhclk/(2^(N+2)). Clock frequency

= 48 MHz.

–

–

V

SSA

–

–

–

–

–

–

–

–

2.2

20

60

1

–

3

0.25

V

DDA

–

–

–

–

21.3

Units Details / Conditions




LSB

Polarity set by Source or Sink.

Offset is 2 LSBs for 37.5 nA/LSB mode

%

LSB LSB = 37.5-nA typ.

LSB LSB = 300-nA typ.

LSB LSB = 2.4-µA typ.

µs

Full-scale transition. No external load.

µs

Full-scale transition. No external load.

nF 5-V rating, X7R or NP0 cap.

Units Details/Conditions bits

Auto-zeroing is required every millisecond

Defined by AMUX Bus.

Yes

% mV mA

V

KΩ pF dB

µs

µs

In V

REF with V

(2.4 V) mode

DDA

bypass capacitance of 10 µF

In V

REF with V

(2.4 V) mode

DDA


In V

REF with V

(2.4 V) mode

DDA


Does not include acquisition time. Equivalent to

44.8 ksps including acquisition time.


Automotive PSoC

®

4: PSoC 4000S


Table 12. 10-bit CapSense ADC Specifications (continued)

Spec ID#

SIDA108A

SIDA109

SIDA110

SIDA111

SIDA112

Parameter

A_CONV10

A_SND

A_BW

A_INL

A_DNL

Description

Conversion time for 10-bit resolution at conversion rate =

Fhclk/(2^(N+2)). Clock frequency

= 48 MHz.

Signal-to-noise and Distortion ratio (SINAD)

Input bandwidth without aliasing

Integral Non Linearity. 1 ksps

Differential Non Linearity. 1 ksps

I

2

C

Table 14. Fixed I

2

C DC Specifications

[7]

Spec ID

SID149

SID150

SID151

SID152

Parameter

I

I2C1

I

I2C2

I

I2C3

I

I2C4

Description

Block current consumption at 100 kHz

Block current consumption at 400 kHz

Block current consumption at 1 Mbps

I

2

C enabled in Deep Sleep mode

Min

–

–

–

–

–

Min

–

–

–

–

Typ

–

61

–

–

–

Typ

–

–

–

–

Max

85.3

–

22.4

2

1

Max Units

50

135

310

1.4

µA


µs dB

Does not include acquisition time. Equivalent to

11.6 ksps including acquisition time.

With 10-Hz input sine wave, external 2.4-V reference, V mode

REF

(2.4 V) kHz 8-bit resolution

LSB V

REF

= 2.4 V or greater

LSB

Digital Peripherals

Timer Counter Pulse-Width Modulator (TCPWM)

Table 13. TCPWM Specifications

Spec ID Parameter

SID.TCPWM.1

ITCPWM1

SID.TCPWM.2

ITCPWM2

SID.TCPWM.2A ITCPWM3

Description

Block current consumption at 3 MHz

Min

–

Block current consumption at 12 MHz –

Typ

–

–

Max

45

155

Units

μ A

Block current consumption at 48 MHz – – 650


All modes (TCPWM)

All modes (TCPWM)

All modes (TCPWM)

SID.TCPWM.3

TCPWM

FREQ

SID.TCPWM.4

TPWM

ENEXT

Operating frequency

Input trigger pulse width

–

2/Fc

–

–

SID.TCPWM.5

TPWM

EXT

SID.TCPWM.5A TC

RES

SID.TCPWM.5B PWM

RES

SID.TCPWM.5C Q

RES

Output trigger pulse widths

Resolution of counter

PWM resolution

Quadrature inputs resolution

2/Fc

1/Fc

1/Fc

1/Fc

–

–

–

–

Fc MHz Fc max = CLK_SYS

– For all trigger events

[6]

–

– ns

Minimum possible width of

Overflow, Underflow, and

CC (Counter equals

Compare value) outputs

Minimum time between successive counts

–

–

Minimum pulse width of

PWM Output

Minimum pulse width between Quadrature phase inputs


–

–

–

Note

6. Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected.



Automotive PSoC

®

4: PSoC 4000S


Table 15. Fixed I

2

C AC Specifications

[8]

Spec ID

SID153 F

Parameter

I2C1

Bit rate

Description

Table 16. SPI DC Specifications

[8]

Spec ID

SID163

SID164

SID165

Parameter

ISPI1

ISPI2

ISPI3

Description




Min

–

Typ

–

Max Units

1 Msps


–

Min

–

–

–

Typ

–

–

–

Max Units

360

560

600

µA


–

–

–

Table 17. SPI AC Specifications

[8]

Spec ID Parameter Description

SID166 FSPI

SPI operating frequency (Master; 6X

Oversampling)

Fixed SPI Master Mode AC Specifications

SID167 TDMO

SID168 TDSI

MOSI Valid after SClock driving edge

MISO Valid before SClock capturing edge

SID169 THMO Previous MOSI data hold time

Fixed SPI Slave Mode AC Specifications

SID170 TDMI

MOSI Valid before Sclock Capturing edge

SID171 TDSO MISO Valid after Sclock driving edge

SID171A

SID172

TDSO_EXT

THSO

MISO Valid after Sclock driving edge in

Ext. Clk mode

Previous MISO data hold time

SID172A TSSELSSCK SSEL Valid to first SCK Valid edge

Min

–

–

20

0

40

–

–

0

–

Table 18. UART DC Specifications

[8]

Spec ID

SID160

SID161

Parameter

I

UART1

I

UART2

Description

Block current consumption at 100 Kbps

Block current consumption at 1000 Kbps

Min

–

–

Typ

–

–

–

–

–

–

–

–

–

Typ

–

–

Max

8

15

–

–

Units

MHz ns


–

Full clock, late MISO sampling

Referred to Slave capturing edge

–

42 +

3*Tcpu

48

–

100

– ns

T

CPU

= 1/F

CPU ns

–

–

–

Max

55

312

Units

µA

µA


–

–

Table 19. UART AC Specifications

[8]

Spec ID

SID162 F

Parameter

UART

Bit rate

Description Min

–

Typ

–

Max

1

Units

Mbps


–

Note



Automotive PSoC

®

4: PSoC 4000S


Table 20. LCD Direct Drive DC Specifications

[9]


SID154 I

LCDLOW

Operating current in low power mode

SID155 C

LCDCAP

SID156 LCD

OFFSET

LCD capacitance per segment/common driver

Long-term segment offset

SID157 I

LCDOP1

LCD system operating current Vbias = 5 V

SID158 I

LCDOP2

LCD system operating current Vbias = 3.3 V

Min

–

–

–

–

–

Table 21. LCD Direct Drive AC Specifications

[9]

Spec ID

SID159 F

Parameter

LCD

Description

LCD frame rate

Min

10

Memory

Table 22. Flash DC Specifications

Spec ID

SID173 V

PE

Parameter Description

Erase and program voltage

Min

1.71

Typ

50

Typ

–

Typ

5

500

20

2

2

Max Units

– µA


16  4 small segment disp. at 50 Hz

5000

–

–

– pF mV mA

–

–

32  4 segments. 50 Hz.

25 °C

32  4 segments. 50 Hz.

25 °C

Max Units Details/Conditions

150 Hz –

Max

5.5

Units

V


–

Table 23. Flash AC Specifications

Spec ID

SID174

SID175

SID176 T

ROWPROGRAM

[9]

SID178 T

BULKERASE

[9]

SID180

[11]

T

ROWERASE

[9]

T

DEVPROG

[9]

SID181

[11]

F

END

SID182

[11]

T

ROWWRITE

[9]

F

RET

SID182A

[11]

SID182B

Parameter

F

RETQ

Description

Row (block) write time (erase and program)

Row erase time

Row program time after erase

Bulk erase time (32 KB)

Total device program time

Flash endurance

Flash retention. T

A

P/E cycles

 55 °C, 100 K

Flash retention. T

A

P/E cycles

 85 °C, 10 K

Flash retention. T years at T

A

A

 105 °C, 10 K

P/E cycles with no more than 3

 85 °C

Min

–

–

–

–

–

100 K

20

10

10

SID256 TWS48 Number of Wait states at 48 MHz 2

Typ

–

–

–

–

–

–

–

–

–

–

Max

20

16

4

35

7

–

–

Units ms

Seconds

Cycles


Row (block) = 128 bytes

–

–

–

–

–

–

–

Years

–

–

–

Guaranteed by design

CPU execution from

Flash

Notes


10. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.

Make certain that these are not inadvertently activated.



Automotive PSoC

®

4: PSoC 4000S


Table 23. Flash AC Specifications

SID257 TWS24 Number of Wait states at 24 MHz 1 – –

CPU execution from

Flash

System Resources

Power-on Reset (POR)

Table 24. Power On Reset (PRES)


SID.CLK#6 SR_POWER Power supply slew rate

SID185

SID186

[12]

[12]

V

RISEIPOR

V

FALLIPOR

Rising trip voltage

Falling trip voltage

Table 25. Brown-out Detect (BOD) for V

CCD

Spec ID

SID190

[12]

V

Parameter

FALLPPOR

Description

BOD trip voltage in active and sleep modes

SID192

[12]

V

FALLDPSLP

BOD trip voltage in Deep Sleep

SWD Interface

Table 26. SWD Interface Specifications


SID213 F_SWDCLK1 3.3 V  V

DD

 5.5 V

SID214 F_SWDCLK2 1.71 V  V

DD

 3.3 V

SID215

[12]

SID216

[12]

SID217

[12]

SID217A

[12]

T_SWDI_SETUP T = 1/f SWDCLK

T_SWDI_HOLD T = 1/f SWDCLK

T_SWDO_VALID T = 1/f SWDCLK

T_SWDO_HOLD T = 1/f SWDCLK

Internal Main Oscillator

Table 27. IMO DC Specifications

(Guaranteed by Design)

Spec ID

SID218

SID219

Parameter

I

IMO1

I

IMO2

Description

IMO operating current at 48 MHz

IMO operating current at 24 MHz

Table 28. IMO AC Specifications

Spec ID Parameter

SID223

SID226

SID228

F

T

T

IMOTOL1

STARTIMO

JITRMSIMO2

Description

Frequency variation at 24, 32, and

48 MHz (trimmed)

IMO startup time

RMS jitter at 24 MHz

Min

1.48

1.11

Min

1

0.80

0.70

Min

–

–

0.25*T

0.25*T

–

1

Min

–

–

Min

–

–

–

Typ

–

–

–

Typ

–

–

Typ

–

–

Typ

–

Typ

–

–

145

–

–

–

–

–

Max

1.62

1.5

Max

67

1.5

1.4

Max

14

7

–

–

0.5*T

–

Max

250

180

Max

±2

7

–

Units

V/ms

V


On power-up and power-down

–

–

Units

V


–

–


MHz

SWDCLK ≤ 1/3 CPU clock frequency

SWDCLK ≤ 1/3 CPU clock frequency ns

–

–

–

–

Units

µ A

µ A


–

–


%

µs ps

–

–

Note



Automotive PSoC

®

4: PSoC 4000S


Internal Low-Speed Oscillator

Table 29. ILO DC Specifications

(Guaranteed by Design)

Spec ID

SID231

[13]

I

Parameter

ILO1

Description

ILO operating current

Table 30. ILO AC Specifications

Spec ID

SID234

[13]

SID236

[13]

SID237

Parameter

T

STARTILO1

T

ILODUTY

F

ILOTRIM1

Description

ILO startup time

ILO duty cycle

ILO frequency range

Min

–

Min

–

40

20

Typ

0.3

Table 31. Watch Crystal Oscillator (WCO) Specifications

Spec ID#

SID398

SID399

SID400

SID401

SID402

SID403

SID404

SID405

SID406

FWCO

FTOL

ESR

PD

TSTART

CL

C0

Parameter

IWCO1

IWCO2

Description

Crystal Frequency

Frequency tolerance

Equivalent series resistance

Drive Level

Startup time

Crystal Load Capacitance

Crystal Shunt Capacitance

Min

–

–

–

6

–

–

–

Operating Current (high power mode) –

Operating Current (low power mode) –

Table 32. External Clock Specifications

Spec ID

SID305

SID306

[13]

[13]

Parameter

ExtClkFreq

ExtClkDuty

Description

External clock input frequency

Duty cycle; measured at V

DD/2

Min

0

45

Typ

32.768

50

50

–

–

–

1.35

–

–

Typ

–

–

Typ

–

50

40

Table 33. Block Specs

Spec ID

SID262

[13]

T

Parameter

CLKSWITCH

Description

System clock source switching time

Min

3

Typ

–

Max

1.05

Max

2

60

80

Max

48

55 %

Units

MHz

µA

Units ms

% kHz

Units


–



–

–

–

–

–

Max Units

– kHz

250

– ppm kΩ


With 20-ppm crystal

1

500

12.5

–

8

1

µW ms pF pF uA uA

Max

4

Units

Periods


–

Table 34. Smart I/O Pass-through Time (Delay in Bypass Mode)

Spec ID# Parameter Description Min

SID252 –

Typ

–

Max

1.6

Units ns


Note



Automotive PSoC

®

4: PSoC 4000S


Ordering Information

The Automotive PSoC 4000S part numbers and features are listed in

Table 35 .

Table 35. Automotive PSoC 4000S Ordering Information

Features Packages

Operating

Temperature

Category MPN

4024

4025

4045

4024

4025

4045

CY8C4024LQA-S411 24

CY8C4024PVA-S412 24

CY8C4025LQA-S411 24

CY8C4025PVA-S412 24

CY8C4045LQA-S411 48

CY8C4045PVA-S412 48

CY8C4024LQS-S411 24

CY8C4024PVS-S412 24

CY8C4025LQS-S411 24

CY8C4025PVS-S412 24

CY8C4045LQS-S411 48

CY8C4045PVS-S412 48

4

2

4

4

2

2

4

4

4

2

4

4

32

32

32

16

16

16

32

16

32

32

32

32

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

5

5

5

5

5

5

5

5

5

5

5

5

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

24

19

24

19

19

24

19

24

19

24

19

24

✔

–

✔

–

✔

–

✔

–

✔

–

✔

–

✔

–

✔

–

–

✔

–

✔

–

✔

–

✔

–

✔

✔

✔

✔

✔

✔

–

–

–

–

–

–

–

–

–

–

✔

✔

–

✔

✔

✔

✔


Automotive PSoC

®

4: PSoC 4000S


The nomenclature used in the preceding table is based on the following part numbering convention:

Field

CY8C

4

A

B

C

DE

F

S

XYZ

Description

Cypress Prefix

Architecture

Family

CPU Speed

Flash Capacity

Package Code

Temperature Range

Silicon Family

Attributes Code

Values

4

0

2

S

S

M

PV

I

A

6

7

LQ

4

4

5

L

BL

000-999

Meaning

PSoC 4

4000 Family

24 MHz

48 MHz

16 KB

32 KB

64 KB

128 KB

QFN

SSOP

Industrial

Automotive (AEC-Q100: –40 °C to +85 °C)

Automotive (AEC-Q100: –40 °C to +105 °C)

PSoC 4A-S1, PSoC 4A-S2

PSoC 4A-M

PSoC 4A-L

PSoC 4A-BLE

Code of feature set in the specific family

The following is an example of a part number:

Example

4 : PSoC 4

0 : 4000 Family

4 : 48 MHz

5 : 32 KB

PV : SSOP

A , S : Automotive

Cypress Prefix

Architecture

Family within Architecture

CPU Speed

Flash Capacity

Package Code

Temperature Range

Silicon Family

Attributes Code

T = Tape and Reel

CY8C 4 A B C DE F – S XYZ T


Automotive PSoC

®

4: PSoC 4000S


Packaging

The Automotive PSoC 4000S will be offered in 24-QFN and 28-SSOP packages.

Table 36

provides the package dimensions and Cypress drawing numbers.

Table 36. Package List

Spec ID#

BID34

BID28

Package

24-pin QFN

28-pin SSOP

Description

4 × 4 × 0.6 mm height, 2.75 × 2.75 mm EPAD (Sawn) 002-18982

Package Dwg

210 Mils O28.21

51-85079

Table 37. Package Thermal Characteristics

Parameter

T

T

A

J

T

JA

T

JC

T

JA

T

JC

Description

Operating Ambient temperature

Package

Operating Junction temperature

Package θ

JA

Package θ

JC

Package θ

JA

Package θ

JC

24-pin QFN

24-pin QFN

28-pin SSOP

28-pin SSOP

Conditions

For A-grade devices

For S-grade devices

For A-grade devices

For S-grade devices

Min

–

–

–

–

–40

–40

–40

–40

Table 38. Solder Reflow Peak Temperature

Package

All

Maximum Peak Temperature

260 °C

Typ

25

25

–

–

21.7

5.6

66.58

46.28

Max

–

–

–

–

85

105

100

120

Units

°C

°C

°C/Watt

°C/Watt

°C/Watt

°C/Watt

Maximum Time at Peak Temperature

30 seconds

Table 39. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-020

Package

All

MSL

MSL 3


Package Diagrams

Automotive PSoC

®

4: PSoC 4000S


Figure 5. 24-pin QFN Package Outline

002-18982 *A

The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance.

If not connected to ground, it should be electrically floating and not connected to any other signal.


Automotive PSoC

®

4: PSoC 4000S


Figure 6. 28-Pin SSOP Package Outline

51-85079 *G


Automotive PSoC

®

4: PSoC 4000S


Acronyms

Table 40. Acronyms Used in this Document

EMI

EMIF

EOC

EOF

EPSR

ESD

DMIPS

DMA

DNL

DNU

DR

DSI

DWT

ECC

ECO

Acronym abus

ADC

AG

CAN

CMRR

CPU

Description analog local bus analog-to-digital converter analog global

AHB

AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus arithmetic logic unit ALU

AMUXBUS analog multiplexer bus

API application programming interface

APSR

ARM

® application program status register advanced RISC machine, a CPU architecture

ATM

BW automatic thump mode bandwidth

Controller Area Network, a communications protocol common-mode rejection ratio

CRC

DAC

DFB central processing unit cyclic redundancy check, an error-checking protocol digital-to-analog converter, see also IDAC, VDAC digital filter block

DIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO.

Dhrystone million instructions per second direct memory access, see also TD differential nonlinearity, see also INL do not use port write data registers

EEPROM digital system interconnect data watchpoint and trace error correcting code external crystal oscillator electrically erasable programmable read-only memory electromagnetic interference external memory interface end of conversion end of frame execution program status register electrostatic discharge

IIR

ILO

IMO

INL

I/O

IPOR

IPSR

IRQ

ITM

LCD

NC

NMI

NRZ

NVIC

NVL opamp

PAL

LR

LUT

LVD

LVI

LVTTL

MAC

MCU

MISO

Table 40. Acronyms Used in this Document

(continued)

I

Acronym

ETM

FIR

FPB

FS

GPIO

HVI

IC

IDAC

IDE

2

C, or IIC

LIN

Description embedded trace macrocell finite impulse response, see also IIR flash patch and breakpoint full-speed general-purpose input/output, applies to a PSoC pin high-voltage interrupt, see also LVI, LVD integrated circuit current DAC, see also DAC, VDAC integrated development environment

Inter-Integrated Circuit, a communications protocol infinite impulse response, see also FIR internal low-speed oscillator, see also IMO internal main oscillator, see also ILO integral nonlinearity, see also DNL input/output, see also GPIO, DIO, SIO, USBIO initial power-on reset interrupt program status register interrupt request instrumentation trace macrocell liquid crystal display

Local Interconnect Network, a communications protocol.

link register lookup table low-voltage detect, see also LVI low-voltage interrupt, see also HVI low-voltage transistor-transistor logic multiply-accumulate microcontroller unit master-in slave-out no connect nonmaskable interrupt non-return-to-zero nested vectored interrupt controller nonvolatile latch, see also WOL operational amplifier programmable array logic, see also PLD


Automotive PSoC

®

4: PSoC 4000S


Table 40. Acronyms Used in this Document (continued)

PLA

PLD

PLL

PMDD

POR

PRES

PRS

PS

PSoC

®

PSRR

Acronym

PC

PCB

PGA

PHUB

PHY

PICU

PWM

RAM

RISC

RMS

RTC

RTL

RTR

RX

SAR

SC/CT

SCL

SDA

S/H

SINAD

SIO

SOC

SOF

SPI

SR

SRAM

SRES

SWD program counter

Description printed circuit board programmable gain amplifier peripheral hub physical layer port interrupt control unit programmable logic array programmable logic device, see also PAL phase-locked loop package material declaration data sheet power-on reset precise power-on reset pseudo random sequence port read data register

Programmable System-on-Chip™ power supply rejection ratio pulse-width modulator random-access memory reduced-instruction-set computing root-mean-square real-time clock register transfer language remote transmission request receive successive approximation register switched capacitor/continuous time

I

2

C serial clock

I

2

C serial data sample and hold signal to noise and distortion ratio special input/output, GPIO with advanced features. See GPIO.

start of conversion start of frame

Serial Peripheral Interface, a communications protocol slew rate static random access memory software reset serial wire debug, a test protocol

Table 40. Acronyms Used in this Document (continued)

Acronym

SWV

TD

THD

TIA

TRM

TTL

TX

UART

UDB

USB

USBIO

VDAC

WDT

WOL

WRES

XRES

XTAL single-wire viewer

Description transaction descriptor, see also DMA total harmonic distortion transimpedance amplifier technical reference manual transistor-transistor logic transmit

Universal Asynchronous Transmitter Receiver, a communications protocol universal digital block

Universal Serial Bus

USB input/output, PSoC pins used to connect to a USB port voltage DAC, see also DAC, IDAC watchdog timer write once latch, see also NVL watchdog timer reset external reset I/O pin crystal


Document Conventions

Units of Measure

Table 41. Units of Measure

µV

µW mA ms

µA

µF

µH

µs mV nA ns nV

 pF kHz k  ksps

LSB

Mbps

MHz

M 

Msps

°C

Symbol dB fF

Hz

KB kbps

Khr ppm ps s sps sqrtHz

V degrees Celsius

Unit of Measure decibel femto farad hertz

1024 bytes kilobits per second kilohour kilohertz kilo ohm kilosamples per second least significant bit megabits per second megahertz mega-ohm megasamples per second microampere microfarad microhenry microsecond microvolt microwatt milliampere millisecond millivolt nanoampere nanosecond nanovolt ohm picofarad parts per million picosecond second samples per second square root of hertz volt

Document Number: 002-18381 Rev. *E

Automotive PSoC

®

4: PSoC 4000S


Page 30 of 32

Automotive PSoC

®

4: PSoC 4000S


Revision History

Description Title: Automotive PSoC

®

Document Number: 002-18381

4: PSoC 4000S Family Datasheet Programmable System-on-Chip (PSoC)

Revision ECN

Submission

Date

Description of Change

**

*A

*B

*C

5585298

5651125

01/13/2017 New datasheet

03/06/2017 Corrected 28-pin SSOP pin details in

Table 1

.

5909901 10/05/2017

Updated

General Description , Features ,

Timer/Counter/PWM (TCPWM)

Block

,

Ordering Information

, and

Packaging .

Updated

Table 1

.

Updated

Sales, Solutions, and Legal Information

.

6078471 02/22/2018 Replaced Spec 002-18982 in

Figure 5

.

24-pin QFN Package Outline .

*D

*E

6212923

7023012

06/21/2018

11/13/2020

Updated Details/Conditions in DC Specifications .

Removed SID182B.

Updated 24-pin QFN package diagram.

Updated I2C mode speed to 1 Mbps (Fast Mode Plus).

Updated VDD and VSS pin notes in

Pinouts .

Updated

Power

.

Updated SID.CLK#6 parameter.

Added SID182B

Added tape and reel to ordering code definition.

Refer to Product Information Notice #6965423.


Automotive PSoC ® 4: PSoC 4000S


Sales, Solutions, and Legal Information

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© Cypress Semiconductor Corporation, 2017-2020. . This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by

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Document Number: 002-18381 Rev. *E Revised November 13, 2020 Page 32 of 32

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