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CY8C40xx
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
General description
PSoC™ 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm® Cortex®-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC™ 4000S product family is a member of the PSoC™ 4 platform architecture. It is a combination of a microcontroller with standard communication and timing peripherals, a capacitive touch-sensing system (CAPSENSE™) with best-in-class performance, programmable general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC™ 4000S products are upward compatible with members of the PSoC™ 4 platform for new applications and design needs.
Features
• 32-bit MCU subsystem
- 48-MHz Arm® Cortex®-M0+ CPU with single-cycle multiply
- Up to 32 KB of flash with read accelerator
- Up to 4 KB of SRAM
• Programmable analog
- Single-slope 10-bit ADC function provided by Capacitance sensing block
- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
- Two low-power comparators that operate in Deep Sleep low-power mode
• Programmable digital
- Programmable logic blocks allowing boolean operations to be performed on port inputs and outputs
• Low-power 1.71-V to 5.5-V operation
- Deep Sleep mode with operational analog and 2.5 µA digital system current
• Capacitive sensing
- Capacitive sigma-delta provides best-in-class signal-to-noise ratio (SNR) (>5:1) and water tolerance
- Infineon-supplied software component makes capacitive sensing design easy
- Automatic hardware tuning (SmartSense)
• LCD drive capability
- LCD segment drive capability on GPIOs
• Serial communication
- Two independent run-time reconfigurable serial communication blocks (SCBs) with re-configurable I or UART functionality
2 C, SPI,
• Timing and pulse-width modulation
- Five 16-bit timer/counter/pulse-width modulator (TCPWM) blocks
- Center-aligned, edge, and pseudo-random modes
- Comparator-based triggering of kill signals for motor drive and other high-reliability digital logic applications
• Up to 36 programmable GPIO pins
- 48-pin TQFP, 40-pin QFN, 32-pin QFN, 24-pin QFN, 32-pin TQFP, and 25-ball WLCSP packages
- Any GPIO pin can be CAPSENSE™, analog, or digital
- Drive modes, strengths, and slew rates are programmable
Datasheet www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1
002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Features
• Clock sources
- 32-kHz watch crystal oscillator (WCO)
- ±2% internal main oscillator (IMO)
- 32-kHz internal low-power oscillator (ILO)
• ModusToolbox™ software
- Comprehensive collection of multi-platform tools and software libraries
- Includes board support packages (BSPs), peripheral driver library (PDL), and middleware such as CAPSENSE™
• PSoC™ Creator design environment
- Integrated development environment (IDE) provides schematic design entry and build, with analog and digital automatic routing
- Application programming interface (API) components for all fixed-function and programmable peripherals
• Industry-standard tool compatibility
- After schematic entry, development can be done with Arm®-based industry-standard development tools
Datasheet 2 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Table of contents
Table of contents
Datasheet 3 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Development ecosystem
1 Development ecosystem
1.1
PSoC™ 4 MCU resources
Infineon provides a wealth of data at www.cypress.com
to help you select the right PSoC™ device and quickly and effectively integrate it into your design. The following is an abbreviated, hyperlinked list of resources for
PSoC™ 4 MCU:
• Overview: PSoC™ Portfolio , PSoC™ Roadmap
• Product selectors: PSoC™ 4 MCU
• Application notes cover a broad range of topics, from basic to advanced level, and include the following:
AN79953 : Getting Started With PSoC™ 4. This application note has a convenient flow chart to help decide
which IDE to use: ModusToolbox™ software
AN91184 : PSoC™ 4 BLE - Designing BLE Applications
AN88619: PSoC™ 4 hardware design considerations
AN73854 : Introduction To bootloaders
AN89610: Arm® Cortex® code optimization
AN86233 : PSoC™ 4 MCU power reduction techniques
AN57821: Mixed signal circuit board layout
AN85951 : PSoC™ 4, PSoC™ 6 CAPSENSE™ design guide
• Code examples demonstrate product features and usage, and are also available on Infineon GitHub repositories .
• Technical Reference Manuals (TRMs) provide detailed descriptions of PSoC™ 4 MCU architecture and registers.
• PSoC™ 4 MCU programming specification provides the information necessary to program PSoC™ 4 MCU non-volatile memory.
• Development tools
-
libraries.
-
3, PSoC™ 4, PSoC™ 5LP, and PSoC™ 6 MCU based systems. Applications are created using schematic capture and over 150 pre-verified, production-ready peripheral components.
CY8CKIT-145-40XX PSoC™ 4000S CAPSENSE™ prototyping kit, is a low-cost and easy-to-use evaluation platform. This kit provides easy access to all the device I/Os in a breadboard-compatible format.
MiniProg4 and MiniProg3 all-in-one development programmers and debuggers.
PSoC™ 4 MCU CAD libraries provide footprint and schematic support for common tools. IBIS models are also available.
• Training Videos are available on a wide range of topics including the PSoC™ 4 MCU 101 series .
• Infineon developer community enables connection with fellow PSoC™ developers around the world, 24 hours a day, 7 days a week, and hosts a dedicated PSoC™ 4 MCU community .
Datasheet 4 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Development ecosystem
1.2
ModusToolbox™ software
ModusToolbox™ software is Infineon’ comprehensive collection of multi-platform tools and software libraries that enable an immersive development experience for creating converged MCU and wireless systems. It is:
• Comprehensive - it has the resources you need
• Flexible - you can use the resources in your own workflow
• Atomic - you can get just the resources you want
Infineon provides a large collection of code repositories on GitHub , including:
• Board support packages (BSPs) aligned with Infineon kits
• Low-level resources, including a peripheral driver library (PDL)
• Middleware enabling industry-leading features such as CAPSENSE™
• An extensive set of thoroughly tested code example applications
ModusToolbox™ software is IDE-neutral and easily adaptable to your workflow and preferred development environment. It includes a project creator, peripheral and library configurators, a library manager, as well as the optional Eclipse IDE for ModusToolbox™, as
shows. For information on using Infineon tools, refer to the documentation delivered with ModusToolbox™ software, and AN79953: Getting Started with PSoC™ 4 .
Figure 1 ModusToolbox™ software tools
Datasheet 5 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Development ecosystem
1.3
PSoC™ Creator
PSoC™ Creator is a free Windows-based IDE. It enables you to design hardware and firmware systems
concurrently, based on PSoC™ 4 MCU. As Figure 2 shows, with PSoC™ Creator you can:
1. Drag and drop component icons to build your hardware system design in the main design workspace
2. Co-design your application firmware with the PSoC™ hardware, using the PSoC™ Creator IDE C compiler
3. Configure components using the configuration tools
4. Explore the library of 100+ components
5. Review component datasheets
6. Prototype your solution with the PSoC™ 4 Pioneer kits. If a design change is needed, PSoC™ Creator and components enable you to make changes on-the-fly without the need for hardware revisions.
1
2
3
4
5
Figure 2 Multiple-sensor example project in PSoC™ Creator
Datasheet 6 002-00123 Rev. *O
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Block diagram
Block diagram
PSoC™ 4000S
Architecture
32-bit
AHB-Lite
System Resources
Lite
Power
Sleep Control
WIC
POR
PWRSYS
REF
Clock
Clock Control
WDT
ILO IMO
Reset
Reset Control
XRES
Test
TestMode Entry
Digital DFT
Analog DFT
CPU Subsystem
SWD/TC
Cortex® M0+
48 MHz
FAST MUL
NVIC, IRQMUX
SPCIF
FLASH
32 KB
Read Accelerator
SRAM
4 KB
SRAM Controller
Peripherals
PCLK
System Interconnect (Single Layer AHB)
Peripheral Interconnect (MMIO)
ROM
8 KB
ROM Controller
Power Modes
Active/Sleep
DeepSleep
High Speed I/O Matrix & 2 x Programmable I/O
36x GPIOs, LCD
I/O Subsystem
PSoC™ 4000S devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware.
The Arm® serial-wire debug (SWD) interface supports all programming and debug features of the device.
Complete debug-on-chip functionality enables full-device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug.
The PSoC™ Creator IDE provides fully integrated programming and debug support for the PSoC™ 4000S devices.
The SWD interface is fully compatible with industry-standard third-party tools. The PSoC™ 4000S provides a level of security not possible with multi-chip application solutions or with microcontrollers.
It has the following advantages:
• Allows disabling of debug features
• Robust flash protection
• Allows customer-proprietary functionality to be implemented in on-chip programmable blocks
Datasheet 7 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Block diagram
The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables debugging. Thus firmware control of debugging cannot be over-ridden without erasing the firmware thus providing security.
Additionally, all device interfaces can be permanently disabled (device security) for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when maximum device security is enabled. Therefore, PSoC™ 4000S, with device security enabled, may not be returned for failure analysis. This is a trade-off the PSoC™ 4000S allows the customer to make.
Datasheet 8 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Functional description
2 Functional description
PSoC™ 4000S devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware.
The Arm® serial-wire debug (SWD) interface supports all programming and debug features of the device.
Complete debug-on-chip functionality enables full-device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug.
The PSoC™ Creator IDE provides fully integrated programming and debug support for the PSoC™ 4000S devices.
The SWD interface is fully compatible with industry-standard third-party tools. The PSoC™ 4000S family provides a level of security not possible with multi-chip application solutions or with microcontrollers. It has the following advantages:
• Allows disabling of debug features
• Robust flash protection
• Allows customer-proprietary functionality to be implemented in on-chip programmable blocks
The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables debugging. Thus firmware control of debugging cannot be over-ridden without erasing the firmware thus providing security.
Additionally, all device interfaces can be permanently disabled (device security) for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when maximum device security is enabled. Therefore, PSoC™ 4000S, with device security enabled, may not be returned for failure analysis. This is a trade-off the PSoC™ 4000S allows the customer to make.
Datasheet 9 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Functional definition
3
3.1
Functional definition
CPU and memory subsystem
3.1.1
CPU
The Cortex®-M0+ CPU in the PSoC™ 4000S is part of the 32-bit MCU subsystem, which is optimized for low-power operation with extensive clock gating. Most instructions are 16 bits in length and the CPU executes a subset of the thumb-2 instruction set. It includes a nested vectored interrupt controller (NVIC) block with eight interrupt inputs and also includes a wakeup interrupt controller (WIC). The WIC can wake the processor from Deep Sleep mode, allowing power to be switched off to the main processor when the chip is in Deep Sleep mode.
The CPU also includes a debug interface, the serial wire debug (SWD) interface, which is a two-wire form of JTAG.
The debug configuration used for PSoC™ 4000S has four breakpoint (address) comparators and two watchpoint
(data) comparators.
3.1.2
Flash
The PSoC™ 4000S device has a flash module with a flash accelerator, tightly coupled to the CPU to improve average access times from the flash block. The low-power flash block is designed to deliver two wait-state (WS) access time at 48 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average.
3.1.3
SRAM
Four KB of SRAM are provided with zero wait-state access at 48 MHz.
3.1.4
SROM
A supervisory ROM that contains boot and configuration routines is provided.
3.2
System resources
3.2.1
Power system
The power system is described in detail in the section
“Power” on page 19. It provides assurance that voltage
levels are as required for each respective mode and either delays mode entry (for example, on power-on reset
(POR)) until voltage levels are as required for proper functionality, or generates resets (for example, on brown-out detection). The PSoC™ 4000S operates with a single external supply over the range of either 1.8 V ±5% (externally regulated) or 1.8 to 5.5 V (internally regulated) and has three different power modes, transitions between which are managed by the power system. The PSoC™ 4000S provides Active, Sleep, and Deep Sleep low-power modes.
All subsystems are operational in Active mode. The CPU subsystem (CPU, flash, and SRAM) is clock-gated off in
Sleep mode, while all peripherals and interrupts are active with instantaneous wake-up on a wake-up event. In
Deep Sleep mode, the high-speed clock and associated circuitry is switched off; wake-up from this mode takes
35 µs.
Datasheet 10 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Functional definition
3.2.2
Clock system
The PSoC™ 4000S clock system is responsible for providing clocks to all subsystems that require clocks and for switching between different clock sources without glitching. In addition, the clock system ensures that there are no metastable conditions.
The clock system for the PSoC™ 4000S consists of the internal main oscillator (IMO), internal low-frequency oscillator (ILO), a 32 kHz watch crystal oscillator (WCO) and provision for an external clock. Clock dividers are provided to generate clocks for peripherals on a fine-grained basis. Fractional dividers are also provided to enable clocking of higher data rates for UARTs.
The HFCLK signal can be divided down to generate synchronous clocks for the analog and digital peripherals.
There are eight clock dividers for the PSoC™ 4000S, two of those are fractional dividers. The 16-bit capability allows flexible generation of fine-grained frequency values, and is fully supported in PSoC™ Creator.
HFCLK
IMO
External Clock
Divide By
2,4,8
ILO LFCLK
Prescaler
SYSCLK
HFCLK
Integer
Dividers
Fractional
Dividers
6X 16-bit
2X 16.5-bit
PSoC™ 4000S MCU clocking architecture Figure 3
3.2.3
IMO clock source
The IMO is the primary source of internal clocking in the PSoC™ 4000S. It is trimmed during testing to achieve the specified accuracy. The IMO default frequency is 24 MHz and it can be adjusted from 24 to 48 MHz in steps of
4 MHz. The IMO tolerance with Infineon-provided calibration settings is ±2%.
3.2.4
ILO clock source
The ILO is a very low power, nominally 40-kHz oscillator, which is primarily used to generate clocks for the watchdog timer (WDT) and peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy. Infineon provides a software component, which does the calibration.
3.2.5
Watch crystal oscillator (WCO)
The PSoC™ 4000S clock subsystem also implements a low-frequency (32-kHz watch crystal) oscillator that can be used for precision timing applications. The WCO block allows locking the IMO to the 32-kHz oscillator. The
WCO on PSoC™ 4000S series devices does not connect to the LFCLK or WDT. Due to this, RTC functionality is not supported.
Datasheet 11 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Functional definition
3.2.6
Watchdog timer
A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during
Deep Sleep and generates a watchdog reset if not serviced before the set timeout occurs. The watchdog reset is recorded in a Reset Cause Register, which is firmware readable.
3.2.7
Reset
The PSoC™ 4000S can be reset from a variety of sources including a software reset. Reset events are asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset and allows software to determine the cause of the reset. An XRES pin is reserved for external reset by asserting it active low. The XRES pin has an internal pull-up resistor that is always enabled.
3.2.8
Voltage reference
The PSoC™ 4000S reference system generates all internally required references. A 1.2-V voltage reference is provided for the comparator. The IDACs are based on a ±5% reference.
3.3
Analog blocks
3.3.1
Low-power comparators (LPC)
The PSoC™ 4000S has a pair of low-power comparators, which can also operate in Deep Sleep modes. This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode where the system wake-up circuit is activated by a comparator switch event.
The LPC outputs can be routed to pins.
3.3.2
Current DACs
The PSoC™ 4000S has two IDACs, which can drive any of the pins on the chip. These IDACs have programmable current ranges.
3.3.3
Analog multiplexed buses
The PSoC™ 4000S has two concentric independent buses that go around the periphery of the chip. These buses
(called amux buses) are connected to firmware-programmable analog switches that allow the chip’s internal resources (IDACs, comparator) to connect to any pin on the I/O Ports.
3.4
Programmable digital blocks
The programmable I/O (Smart I/O) block is a fabric of switches and LUTs that allows boolean functions to be performed in signals being routed to the pins of a GPIO port. The Smart I/O can perform logical operations on input pins to the chip and on signals going out as outputs.
Datasheet 12 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Functional definition
3.5
Fixed function digital
3.5.1
Timer/Counter/PWM (TCPWM) block
The TCPWM block consists of a 16-bit counter with user-programmable period length. There is a capture register to record the count value at the time of an event (which may be an I/O event), a period register that is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals that are used as PWM duty cycle outputs. The block also provides true and complementary outputs with programmable offset between them to allow use as dead-band programmable complementary PWM outputs. It also has a kill input to force outputs to a predetermined state; for example, this is used in motor drive systems when an over-current state is indicated and the PWM driving the FETs needs to be shut off immediately with no time for software intervention. There are five TCPWM blocks in the PSoC™ 4000S.
3.5.2
Serial communication block (SCB)
I
The PSoC™ 4000S has two serial communication blocks, which can be programmed to have SPI, I2C, or UART functionality.
2 C Mode : The hardware I 2 C block implements a full multi-master and slave interface (it is capable of multi-master arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EZI2C that creates a mailbox address range in the memory of the PSoC™ 4000S and effectively reduces I 2 C communication to reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock stretching caused by the CPU not having read data on time.
The I
I 2
2 C peripheral is compatible with the I C Standard-mode and Fast-mode devices as defined in the NXP
C-bus specification and user manual (UM10204). The I modes.
2
2 C bus I/O is implemented with GPIO in open-drain
The PSoC™ 4000S is not completely compliant with the I 2 C spec in the following respect:
• GPIO cells are not over-voltage tolerant and, therefore, cannot be hot-swapped or powered up independently of the rest of the I 2 C system.
UART Mode : This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface
(LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic
UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated.
SPI Mode : The SPI mode supports full Motorola SPI, TI SSP (adds a start pulse used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO.
Datasheet 13 002-00123 Rev. *O
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Functional definition
3.6
GPIO
The PSoC™ 4000S has up to 36 GPIOs. The GPIO block implements the following:
• Eight drive modes:
- Analog input mode (input and output buffers disabled)
- Input only
- Weak pull-up with strong pull-down
- Strong pull-up with weak pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up with strong pull-down
- Weak pull-up with weak pull-down
• Input threshold select (CMOS or LVTTL).
• Individual control of input and output buffer enabling/disabling in addition to the drive strength modes
• Selectable slew rates for dV/dt related noise control to improve EMI
The pins are organized in logical entities called ports, which are 8-bit in width (less for ports 2 and 3). During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may connect to an I/O pin.
Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt service routine (ISR) vector associated with it (5 for PSoC™ 4000S).
3.7
Special function peripherals
3.7.1
CAPSENSE™
CAPSENSE™ is supported in the PSoC™ 4000S through a CAPSENSE™ Sigma-Delta (CSD) block that can be connected to any pins through an analog multiplex bus via analog switches. CAPSENSE™ function can thus be provided on any available pin or group of pins in a system under software control. A PSoC™ Creator component is provided for the CAPSENSE™ block to make it easy for the user.
Shield voltage can be driven on another analog multiplex bus to provide water-tolerance capability. Water tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input. Proximity sensing can also be implemented.
The CAPSENSE™ block has two IDACs, which can be used for general purposes if CAPSENSE™ is not being used
(both IDACs are available in that case) or if CAPSENSE™ is used without water tolerance (one IDAC is available).
The CAPSENSE™ block also provides a 10-bit slope ADC function, which can be used in conjunction with the
CAPSENSE™ function.
The CAPSENSE™ block is an advanced, low-noise, programmable block with programmable voltage references and current source ranges for improved sensitivity and flexibility. It can also use an external reference voltage. It has a full-wave CSD mode that alternates sensing to VDDA and Ground to null out power-supply related noise.
3.7.2
LCD segment drive
The PSoC™ 4000S has an LCD controller, which can drive up to 8 commons and up to 28 segments. It uses full digital methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods used are referred to as digital correlation and PWM. Digital correlation pertains to modulating the frequency and drive levels of the common and segment signals to generate the highest RMS voltage across a segment to light it up or to keep the RMS signal to zero. This method is good for STN displays but may result in reduced contrast with TN (cheaper) displays. PWM pertains to driving the panel with PWM signals to effectively use the capacitance of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This method results in higher power consumption but can result in better results when driving TN displays.
Datasheet 14 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Pinouts
4 Pinouts
The following table provides the pin list for PSoC™ 4000S for the 48-pin TQFP, 40-pin QFN, 32-pin QFN,
24-pin QFN, 32-pin TQFP, and 25-ball CSP packages. All port pins support GPIO. Pin 11 is a No-Connect in the
48-TQFP.
9
10
12
13
7
8
3
4
5
6
47
48
1
2
43
44
45
46
39
40
41
42
35
36
37
38
Table 1
48-pin TQFP
PSoC™ 4000S pin list
32-pin QFN 24-pin QFN 25-ball CSP 40-pin QFN 32-pin TQFP
Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name
28
29
30
P0.0
P0.1
P0.2
17
18
19
P0.0
P0.1
P0.2
13
14
P0.0
P0.1
D1
C3
P0.0
P0.1
22
23
24
P0.0
P0.1
P0.2
17
18
19
P0.0
P0.1
P0.2
31
32
33
34
P0.3
P0.4
P0.5
P0.6
20
21
22
23
P0.3
P0.4
P0.5
P0.6
15
16
17
P0.4
P0.5
P0.6
C2
C1
B1
P0.4
P0.5
P0.6
25
26
27
28
P0.3
P0.4
P0.5
P0.6
20
21
22
23
P0.3
P0.4
P0.5
P0.6
P0.7
XRES
VCCD
VSSD
VDDD
VDDA
VSSA
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
VSSD
P3.0
P3.1
24
25
26
27
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
XRES
VCCD
VSSD
VDD
VDD
VSSA
P1.0
P1.1
P1.2
P1.3
P1.7
P2.0
P2.1
P2.2
P2.3
P2.5
P2.6
P2.7
P3.0
P3.1
18
19
20
21
21
22
23
24
1
2
3
4
5
6
XRES
VCCD
VSSD
VDD
VDD
VSSA
P1.2
P1.3
P1.7
P2.0
P2.1
P2.6
P2.7
P3.0
B2
B3
A1
A2
A3
A3
A2
A4
B4
A5
B5
C5
D5
C4
A2
E5
D4
P0.7
XRES
VCCD
VSS
VDD
VDD
VSS
P1.2
P1.3
P1.7
P2.0
P2.1
P2.6
P2.7
VSS
P3.0
P3.1
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
8
9
10
11
6
7
P0.7
XRES
VCCD
VDDD
VDDA
VSSA
P1.0
P1.1
P1.2
P1.3
P1.4
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
VSSD
P3.0
P3.1
24
25
26
27
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
XRES
VCCD
VSSD
VDD
VDD
VSSA
P1.0
P1.1
P1.2
P1.3
P1.7
P2.0
P2.1
P2.2
P2.3
P2.5
P2.6
P2.7
P3.0
P3.1
Datasheet 15 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Pinouts
Table 1
48-pin TQFP
14
16
17
P3.2
P3.3
P3.4
PSoC™ 4000S pin list
(continued)
32-pin QFN
11
12
P3.2
P3.3
24-pin QFN
7
8
P3.2
P3.3
25-ball CSP
E4
D3
P3.2
P3.3
40-pin QFN
12
13
14
P3.2
P3.3
P3.4
32-pin TQFP
Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name
11
12
P3.2
P3.3
18
19
20
21
P3.5
P3.6
P3.7
VDDD
15
16
17
P3.5
P3.6
P3.7
22
23
24
25
P4.0
P4.1
P4.2
P4.3
13
14
15
16
P4.0
P4.1
P4.2
P4.3
9
10
11
12
P4.0
P4.1
P4.2
P4.3
E3
D2
E2
E1
P4.0
P4.1
P4.2
P4.3
18
19
20
21
P4.0
P4.1
P4.2
P4.3
13
14
15
16
P4.0
P4.1
P4.2
P4.3
Note: Pins 11, 15, 26, and 27 are No connects (NC) on the 48-pin TQFP.
Descriptions of the pin functions are as follows:
VDDD : Power supply for the digital section.
VDDA : Power supply for the analog section.
VSSD, VSSA : Ground pins for the digital and analog sections respectively.
VCCD : Regulated digital supply (1.8 V ± 5%)
VDD: Power supply to all sections of the chip
VSS: Ground for all sections of the chip
Datasheet 16 002-00123 Rev. *O
2022-07-28
4.1
Alternate pin functions
Each port pin can be assigned to one of multiple functions; it can, for instance, be an analog I/O, a digital peripheral function, an LCD pin, or a CAPSENSE™ pin. The pin assignments are shown in the following table.
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
Table 2
Port/Pin
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
Pin assignments
Analog lpcomp.in_p[0] lpcomp.in_n[0] lpcomp.in_p[1] lpcomp.in_n[1] wco.wco_in
wco.wco_out
Smart I/O Alternate Function 1 Alternate Function 2 Alternate Function 3 Deep Sleep 1 tcpwm.tr_in[0] tcpwm.tr_in[1] srss.ext_clk
tcpwm.line[2]:1 tcpwm.line_compl[2]:1 tcpwm.line[3]:1 tcpwm.line_compl[3]:1 scb[1].uart_rx:0 scb[1].uart_tx:0 scb[1].uart_cts:0 scb[1].uart_rts:0 scb[0].uart_rx:1 scb[0].uart_tx:1 scb[0].uart_cts:1 scb[0].uart_rts:1 tcpwm.tr_in[2] tcpwm.tr_in[3] scb[1].i2c_scl:0 scb[1].i2c_sda:0 scb[0].i2c_scl:0 scb[0].i2c_sda:0
Deep Sleep 2 scb[0].spi_select1:0 scb[0].spi_select2:0 scb[0].spi_select3:0 scb[1].spi_mosi:1 scb[1].spi_miso:1 scb[1].spi_clk:1 scb[1].spi_select0:1 scb[0].spi_mosi:1 scb[0].spi_miso:1 scb[0].spi_clk:1 scb[0].spi_select0:1 scb[0].spi_select1:1 scb[0].spi_select2:1 scb[0].spi_select3:1
P1.7
P2.0
P2.1
P2.2
P2.3
prgio[0].io[0] prgio[0].io[1] prgio[0].io[2] prgio[0].io[3] tcpwm.line[4]:0 tcpwm.line_compl[4]:0 csd.comp
tcpwm.tr_in[4] tcpwm.tr_in[5] scb[1].i2c_scl:1 scb[1].i2c_sda:1 scb[1].spi_mosi:2 scb[1].spi_miso:2 scb[1].spi_clk:2 scb[1].spi_select0:2
Table 2
Port/Pin
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
Pin assignments
(continued)
Analog Smart I/O prgio[0].io[4] prgio[0].io[5] prgio[0].io[6] prgio[0].io[7] prgio[1].io[0]
Alternate Function 1 Alternate Function 2 Alternate Function 3 Deep Sleep 1 tcpwm.line[0]:1 tcpwm.line_compl[0]:1 tcpwm.line[1]:1 tcpwm.line_compl[1]:1 tcpwm.line[0]:0 scb[1].uart_rx:1 lpcomp.comp[0]:1 scb[1].i2c_scl:2 prgio[1].io[1] tcpwm.line_compl[0]:0 scb[1].uart_tx:1 scb[1].i2c_sda:2
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
csd.vref_ext
P4.1
csd.cshieldpads
P4.2
csd.cmodpad
prgio[1].io[2] tcpwm.line[1]:0 prgio[1].io[3] tcpwm.line_compl[1]:0 prgio[1].io[4] tcpwm.line[2]:0 prgio[1].io[5] tcpwm.line_compl[2]:0 prgio[1].io[6] tcpwm.line[3]:0 prgio[1].io[7] tcpwm.line_compl[3]:0 scb[1].uart_cts:1 scb[1].uart_rts:1 scb[0].uart_rx:0 scb[0].uart_tx:0 scb[0].uart_cts:0 tcpwm.tr_in[6] tcpwm.tr_in[7] tcpwm.tr_in[8] tcpwm.tr_in[9] tcpwm.tr_in[10] tcpwm.tr_in[11] cpuss.swd_data
cpuss.swd_clk
lpcomp.comp[1]:1 scb[0].i2c_scl:1 scb[0].i2c_sda:1 lpcomp.comp[0]:0
P4.3
csd.csh_tank
scb[0].uart_rts:0 lpcomp.comp[1]:0
Deep Sleep 2 scb[1].spi_select1:1 scb[1].spi_select2:1 scb[1].spi_select3:1 scb[1].spi_mosi:0 scb[1].spi_miso:0 scb[1].spi_clk:0 scb[1].spi_select0:0 scb[1].spi_select1:0 scb[1].spi_select2:0 scb[1].spi_select3:0 scb[0].spi_mosi:0 scb[0].spi_miso:0 scb[0].spi_clk:0 scb[0].spi_select0:0
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Power
5 Power
The following power system diagram shows the set of power supply pins as implemented for the PSoC™ 4000S.
The system has one regulator in Active mode for the digital circuitry. There is no analog regulator; the analog circuits run directly from the V
DD
input.
VDDA
VDDA
VSSA
Analog
Domain
VDDD
Digital
Domain
VSSD
VDDD
VCCD
1.8 Volt
Regulator
Figure 4 Power supply connections
There are two distinct modes of operation. In Mode 1, the supply voltage range is 1.8 V to 5.5 V (unregulated externally; internal regulator operational). In Mode 2, the supply range is1.8 V ± 5% (externally regulated; 1.71 V to 1.89 V, internal regulator bypassed).
5.1
Mode 1: 1.8 V to 5.5 V external supply
In this mode, the PSoC™ 4000S is powered by an external power supply that can be anywhere in the range of
1.8 V to 5.5 V. This range is also designed for battery-powered operation. For example, the chip can be powered from a battery system that starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of the
PSoC™ 4000S supplies the internal logic and its output is connected to the V
CCD
pin. The VCCD pin must be bypassed to ground via an external capacitor (0.1 µF; X5R ceramic or better) and must not be connected to anything else.
Datasheet 19 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Power
5.2
Mode 2: 1.8 V ± 5% external supply
In this mode, the PSoC™ 4000S is powered by an external power supply that must be within the range of 1.71 V to
1.89 V; note that this range needs to include the power supply ripple too. In this mode, the VDD and VCCD pins are shorted together and bypassed. The internal regulator can be disabled in the firmware.
Bypass capacitors must be used from VDDD to ground. The typical practice for systems in this frequency range is to use a capacitor in the 1-µF range, in parallel with a smaller capacitor (0.1 µF, for example). Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing.
An example of a bypass scheme is shown in the following diagram.
Power supply bypass connections example
1.8V to 5.5V
0.1mF
V
DD
PSoC TM 4000S
V
DDA
1 mF
1.8V to 5.5V
0.1mF
V
CCD
0.1mF
V
SS
Figure 5 External supply range from 1.8 V to 5.5 V with internal regulator active
Datasheet 20 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6
6.1
Electrical specifications
Absolute maximum ratings
Table 3 Absolute maximum ratings
Spec ID# Parameter
Description
SID1
SID2
SID3
SID4
V
DDD_ABS
V
V
CCD_ABS
GPIO_ABS
I
GPIO_ABS
Digital supply relative to V
SS
Direct digital core voltage input relative to V
SS
GPIO voltage
Maximum current per GPIO
SID5
BID44
BID45
BID46
I
GPIO_injection
ESD_HBM
ESD_CDM
LU
GPIO injection current,
Max for V
Min for V
IH
IL
> V
DDD
, and
< V
SS
Electrostatic discharge human body model
Electrostatic discharge charged device model
Pin current for latch-up
2200
500
–140
Min
–0.5
–0.5
–0.5
–25
–0.5
–
–
–
Typ Max Units Details/conditions
– 6 –
V – 1.95
– V
–
DD
+ 0.5
25
– 0.5
mA
–
–
–
Current injected per pin
–
–
140
–
V
– mA –
Note
maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150°C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Datasheet 21 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.2
Device level specifications
All specifications are valid for –40°C T
1.71 V to 5.5 V, except where noted.
A
105°C and T
J
125°C, except where noted. Specifications are valid for
Table 4 DC specifications
Typical values measured at V
DD
= 3.3 V and 25°C.
Spec ID Parameter Description
SID53
SID54
V
SID255 V
V
DD
DD
CCD
Power supply input voltage
Power supply input voltage
(V
CCD
= V
DD
= V
DDA
)
Output voltage
(for core logic)
External regulator voltage bypass
Min Typ Max Units Details/conditions
1.8
– 5.5
Internally regulated supply
1.71
–
–
1.8
1.89
–
V
SID55 C
EFC
SID56 C
EXC
Power supply bypass capacitor
–
–
0.1
1
–
–
µF
Active Mode, V
DD
= 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25°C.
SID10 I
DD5
Execute from flash;
CPU at 6 MHz
– 1.2
2.0
SID16 I
DD8
Execute from flash;
CPU at 24 MHz
– 2.4
4.0
mA
Internally unregulated supply
–
X5R ceramic or better
X5R ceramic or better
–
–
SID19 I
DD11
Execute from flash;
CPU at 48 MHz
Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)
SID22
SID25 I
I
DD17
DD20
I
2 comparators on
I 2
C wakeup WDT, and
C wakeup, WDT, and comparators on
–
–
–
4.6
1.1
1.4
Sleep Mode, V
DDD
= 1.71 V to 1.89 V (Regulator bypassed)
SID28 I
DD23
I 2 C wakeup, WDT, and
Comparators on
–
SID28A I
DD23A
I
2
C wakeup, WDT, and
Comparators on
–
0.7
0.9
Deep Sleep Mode, V
DD
= 1.8 V to 3.6 V (Regulator on)
SID31 I
DD26
Deep Sleep Mode, V
DD
I 2 C wakeup and WDT on
= 3.6 V to 5.5 V (Regulator on)
I
2
C wakeup and WDT on
– 2.5
SID34 I
DD29
Deep Sleep Mode, V
DD
= V
SID37 I
DD32
XRES Current
I 2
– 2.5
CCD
= 1.71 V to 1.89 V (Regulator bypassed)
C wakeup and WDT on – 2.5
SID307 I
DD_XR
Supply current while XRES asserted
– 2
5.9
1.6
1.9
1.1
60
60
60
5 mA
–
6 MHz
12 MHz mA 12 MHz
µA –
µA –
µA – mA –
Datasheet 22 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 5 AC specifications
Spec ID Parameter
SID48 F
CPU
SID49
T
SLEEP
SID50
T
DEEPSLEEP
Description
CPU frequency
Wakeup from Sleep mode
Wakeup from Deep Sleep mode
Min
DC
–
–
Typ
–
0
35
Max Units Details/conditions
48
–
–
MHz 1.71 V V
DD
–
µs
–
5.5 V
Note
2. Guaranteed by characterization.
Datasheet 23 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.2.1
GPIO
Table 6 GPIO DC specifications
Spec ID Parameter Description
SID57
SID58
SID241
SID242
SID243
SID244
SID59
SID60
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
OH
OH
Input voltage high threshold
Input voltage low threshold
LVTTL input,
V
DDD
< 2.7 V
LVTTL input,
V
DDD
< 2.7 V
LVTTL input,
V
DDD
2.7 V
LVTTL input,
V
DDD
2.7 V
Output voltage high level
Output voltage high level
SID61
SID62
SID62A
SID63
SID64
SID65
SID66
SID67
SID68
SID68A
SID69
SID69A
I
I
I
V
V
V
R
R
IL
OL
OL
OL
PULLUP
PULLDOWN
C
IN
V
HYSTTL
V
V
HYSCMOS
HYSCMOS5V5
DIODE
TOT_GPIO
Min
0.7
0.7
V
V
–
–
2.0
–
DDD
DDD
V
DDD
V
DDD
Typ
–
–
–
– 0.3
–
–
– 0.6
–
– 0.5
–
Output voltage low level
Output voltage low level
Output voltage low level
Pull-up resistor
–
–
–
Pull-down resistor
Input leakage current
(absolute value)
Input capacitance
Input hysteresis LVTTL
3.5
3.5
–
–
25
Input hysteresis CMOS 0.05 × V
DDD
Input hysteresis CMOS 200
Current through protection diode to
V
DD
/V
SS
Maximum total source or sink chip current
–
–
–
–
–
5.6
5.6
–
–
–
–
40
–
–
0.3
Max
–
–
–
–
–
8.5
8.5
2
–
–
7
–
V
V
0.8
0.6
0.6
0.4
100
200
DDD
DDD
Units Details/conditions
CMOS input
CMOS input
–
–
– k
V
Ω
–
I
OH
= 4 mA at 3 V V
I
OH
DDD
= 1 mA at 3 V V
DDD
I
OL
= 4 mA at 1.8 V V
I
OL
DDD
= 10 mA at 3 V V
DDD
I = 3 mA at 3 V V
DDD
–
OL
– nA 25°C, V
DDD
= 3.0 V pF – mV
V
V
V
DDD
2.7 V
DD
< 4.5 V
DD
> 4.5 V
µA – mA –
Notes
3. V
IH
must not exceed V
DDD
+ 0.2 V.
4. Guaranteed by characterization.
Datasheet 24 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 7 GPIO AC Specifications
(Guaranteed by characterization)
Spec ID Parameter
SID70 T
RISEF
Description
Rise time in fast strong mode
SID71 T
FALLF
Fall time in fast strong mode
SID72
SID73
SID74
SID75
SID76
T
T
F
F
F
SID245 F
SID246 F
RISES
FALLS
GPIOUT1
GPIOUT2
GPIOUT3
GPIOUT4
GPIOIN
Rise time in slow strong mode
Fall time in slow strong mode
GPIO F
OUT
;
3.3 V V
DDD
5.5 V; fast strong mode
GPIO F
OUT
;
1.71 V V
DDD
3.3 V; fast strong mode
GPIO F
OUT
;
3.3 V V
DDD
5.5 V; slow strong mode
GPIO F
OUT
;
1.71 V V
DDD
3.3 V; slow strong mode
GPIO input operating frequency;
1.71 V V
DDD
5.5 V
Min
2
2
10
10
–
–
–
–
–
–
–
Typ
–
–
–
–
–
–
–
Max Units Details/conditions
12
12 ns
3.3 V V
DDD
,
Cload = 25 pF
3.3 V V
DDD
,
Cload = 25 pF
60
60
–
–
3.3 V V
DDD
,
Cload = 25 pF
3.3 V V
DDD
,
Cload = 25 pF
33
90/10%, 25 pF load,
60/40 duty cycle
16.7
90/10%, 25 pF load,
60/40 duty cycle
7
3.5
MHz
90/10%, 25 pF load,
60/40 duty cycle
90/10%, 25 pF load,
60/40 duty cycle
48 90/10% V
IO
Datasheet 25 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.2.2
XRES
Table 8
SID77 V
SID78 V
IH
IL
XRES DC specifications
Spec ID Parameter
SID79 R
PULLUP
SID80 C
IN
Description
Input voltage high threshold 0.7 × V
DDD
Input voltage low threshold –
Pull-up resistor
Input capacitance
Min
–
–
SID81
V
HYSXRES
Input voltage hysteresis –
SID82 I
DIODE
Current through protection diode to V
DD
/V
SS
–
Typ
–
Max Units Details/conditions
–
V CMOS Input
– 0.3 × V
DDD
60 –
– 7 k Ω – pF –
100 – mV
Typical hysteresis is 200 mV for
V
DD
> 4.5 V
– 100 µA –
Table 9
Spec ID
SID83
BID194
T
T
XRES AC specifications
Parameter
RESETWIDTH
RESETWAKE
Wake-up time from reset release
Description
Reset pulse width
Min
1
–
Typ Max Units Details/conditions
– – µs –
– 2.7
ms –
Note
5. Guaranteed by characterization.
Datasheet 26 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.3
6.3.1
Analog peripherals
Comparator
Table 10
SID84
SID85
SID86
SID87
SID247 V
SID247A V
SID88
SID88A C
SID89
SID248 I
SID259 I
SID90
I
V
V
V
V
C
Z
OFFSET1
OFFSET2
HYST
ICM1
ICM2
ICM3
MRR
MRR
CMP1
CMP2
CMP3
CMP
Comparator DC specifications
Spec ID Parameter Description
Input offset voltage, factory trim
Input offset voltage, custom trim
Hysteresis when enabled
Input common mode voltage in normal mode
Input common mode voltage in low power mode
Input common mode voltage in ultra low power mode
Common mode rejection ratio
Common mode rejection ratio
Block current, normal mode
Block current, low power mode
Block current in ultra low-power mode
DC Input impedance of comparator
50
42
–
–
–
–
0
Min
–
Typ
–
Max
±10
– ±4
10 35
– V
DDD
– 0.1
Units Details/conditions
– mV
–
–
Modes 1 and 2
0 – V
DDD V
–
0 – V
DDD
– 1.15
V
–40°C
≥ 2.2 V at
–
35
–
–
–
–
6
–
–
–
400
100
28
–
V
DDD
≥ 2.7V
dB
V
DDD
≤ 2.7V
–
µA
–
V
–40°C
≥ 2.2 V at
M Ω –
Table 11
Spec ID Parameter
SID91
SID258 TRESP2
SID92
Comparator AC specifications
TRESP1
TRESP3
Description
Response time, normal mode, 50 mV overdrive
Response time, low power mode, 50 mV overdrive
Response time, ultra-low power mode, 200 mV overdrive
Min
–
–
–
Typ
38
70
2.3
Max Units Details/conditions
110 ns
–
200 –
15 µs
V
–40°C
≥ 2.2 V at
Datasheet 27 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.3.2
CSD and IDAC
Table 12
Spec ID
SYS.PER#3
SID308
SID308A
SID309
CSD and IDAC specifications
VDD_RIPPLE
SYS.PER#16 VDD_RIPPLE_1.8
SID.CSD.BLK ICSD
SID.CSD#15 V
SID.CSD#15A V
SID.CSD#16 IDAC1IDD
SID.CSD#17 IDAC2IDD
VCSD
V
Parameter
REF
REF_EXT
COMPIDAC
IDAC1DNL
Description
Max allowed ripple on power supply,
DC to 10 MHz
Max allowed ripple on power supply,
DC to 10 MHz
Maximum block current
Min Typ
–
–
–
–
–
–
Max Units Details/conditions
±50 mV
V
DD
> 2 V (with ripple),
A
,
Sensitivity = 0.1 pF
±25
4000 mV
µA
V
DD
> 1.75 V (with ripple), 25°C T
Parasitic Capacitance
(C
P
) < 20 pF,
A
,
Sensitivity ≥ 0.4 pF
Maximum block current for both IDACs in dynamic (switching) mode including comparators, buffer, and reference generator.
Voltage reference for CSD and comparator
External Voltage reference for CSD and comparator
IDAC1 (7-bits) block current
0.6
0.6
–
1.2 V
–
–
V
DDA
DDA
– 0.6
– 0.6
V
1750
V
V whichever is lower
V
DDA
DDA
– 0.6 or 4.4 V,
– 0.6 or 4.4 V, whichever is lower
µA –
IDAC2 (7-bits) block current
Voltage range of operation
–
1.71
–
–
1750
5.5
µA –
V
1.8 V ± 5% or 1.8
V to
5.5 V
Voltage compliance range of IDAC
0.6
DNL –1
–
–
V
DDA
– 0.6
V
1 LSB –
V
DDA
– 0.6 or 4.4 V, whichever is lower
SID310
SID311
SID312
IDAC1INL
IDAC2DNL
IDAC2INL
INL –2
DNL –1
–2
–
–
–
2
1
2
V
LSB –
DDA
< 2 V
SID313
SID314
SID314A
SNR
IDAC1CRT1
IDAC1CRT2
INL
Ratio of counts of finger to noise.
Guaranteed by characterization
Output current of
IDAC1 (7 bits) in low range
Output current of
IDAC1 (7 bits) in medium range
5
4.2
34
–
–
–
–
5.4
41
Ratio
V
DDA
< 2 V
Capacitance range of
5 pF to 35 pF, 0.1-pF sensitivity. All use cases.
V
DDA
> 2 V.
µA LSB = 37.5-nA typ.
µA LSB = 300-nA typ.
Datasheet 28 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 12
Spec ID
SID314B
SID314C
SID314D
SID314E
SID315
SID315A
SID315B
SID315C
SID315D
SID315E
SID315F
SID315G
SID315H
SID320
SID321
SID322
CSD and IDAC specifications
(continued)
Parameter Description Min Typ
IDAC1CRT3
IDAC1CRT12
Output current of
IDAC1 (7 bits) in high range
Output current of
IDAC1 (7 bits) in low range, 2X mode
275
8
–
–
IDAC1CRT22
IDAC1CRT32
IDAC2CRT1
IDAC2CRT2
Output current of
IDAC1 (7 bits) in medium range, 2X mode
Output current of
IDAC1 (7 bits) in high range, 2X mode
Output current of
IDAC2 (7 bits) in low range
Output current of
IDAC2 (7 bits) in medium range
69
540
4.2
34
–
–
–
–
IDAC2CRT3
IDAC2CRT12
IDAC2CRT22
IDAC2CRT32
IDAC3CRT13
IDAC3CRT23
IDAC3CRT33
Output current of
IDAC2 (7 bits) in high range
Output current of
IDAC2 (7 bits) in low range, 2X mode
Output current of
IDAC2 (7 bits) in medium range, 2X mode
Output current of
IDAC2 (7 bits) in high range, 2X mode
Output current of
IDAC in 8-bit mode in low range
Output current of
IDAC in 8-bit mode in medium range
Output current of
IDAC in 8-bit mode in high range
275
8
69
540
8
69
540
–
–
–
–
–
–
–
IDACOFFSET All zeroes input – –
IDACGAIN
IDACMISMATCH1
Full-scale error less offset
Mismatch between
IDAC1 and IDAC2 in
Low mode
–
–
–
–
Max Units Details/conditions
330 µA LSB = 2.4-µA typ.
10.5
82
660
5.4
41
330
10.5
82
660
10.5
82
660
1
±10
9.2
µA LSB = 75-nA typ.
µA LSB = 600-nA typ.
µA LSB = 4.8-µA typ.
µA LSB = 37.5-nA typ.
µA LSB = 300-nA typ.
µA LSB = 2.4-µA typ.
µA LSB = 75-nA typ.
µA LSB = 600-nA typ.
µA LSB = 4.8-µA typ.
µA LSB = 37.5-nA typ.
µA LSB = 300-nA typ.
µA LSB = 2.4-µA typ.
LSB
Polarity set by Source or
Sink. Offset is 2 LSBs for
37.5 nA/LSB mode
% –
LSB LSB = 37.5-nA typ.
Datasheet 29 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 12
Spec ID
SID322A
SID322B
SID323
SID324
SID325
CSD and IDAC specifications
(continued)
Parameter Description Min Typ
IDACMISMATCH2
IDACMISMATCH3
Mismatch between
IDAC1 and IDAC2 in
Medium mode
Mismatch between
IDAC1 and IDAC2 in
High mode
–
–
–
–
IDACSET8
IDACSET7
CMOD
Settling time to
0.5 LSB for
8-bit IDAC
Settling time to
0.5 LSB for
7-bit IDAC
External modulator capacitor.
–
–
–
–
–
2.2
Max Units Details/conditions
5.6
LSB LSB = 300-nA typ.
6.8
10
10
–
LSB LSB = 2.4-µA typ.
µs
µs
Full-scale transition. No external load.
Full-scale transition. No external load.
Datasheet 30 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.3.3
Table 13 10-bit CAPSENSE™ ADC specifications
Spec ID Parameter Description
SIDA94 A_RES Resolution
Min
–
SIDA95
SIDA97
SIDA98
10-bit CAPSENSE™ ADC
A-MONO Monotonicity
A_GAINERR Gain error
–
–
–
SIDA99 A_OFFSET Input offset voltage
SIDA100 A_ISAR
SIDA101 A_VINS
SIDA103 A_INRES
SIDA104 A_INCAP
SIDA106 A_PSRR
Current consumption
Input voltage range - single ended
Input resistance
Input capacitance
Power supply rejection ratio
–
–
V
SSA
–
–
–
– SIDA107
SIDA108
A_TACQ
A_CONV8
SIDA108A A_CONV10
Sample acquisition time
Conversion time for 8-bit resolution at conversion rate = Fhclk/(2^(N+2)). Clock frequency = 48 MHz.
Conversion time for 10-bit resolution at conversion rate = Fhclk/(2^(N+2)). Clock frequency = 48 MHz.
SIDA109
SIDA110
SIDA111
SIDA112
A_SND
A_BW
A_INL
A_DNL
Signal-to-noise and
Distortion ratio (SINAD)
Input bandwidth without aliasing
Integral Non Linearity.
1 ksps
Differential Non Linearity.
1 ksps
–
–
–
–
–
–
–
2.2
20
Typ Max Units Details/conditions
–
–
10
16 bits
Auto-zeroing is required every millisecond
Defined by AMUX
Bus.
– –
–
–
–
±2
3
0.25
Yes –
%
In V with V
(2.4 V) mode
DDA
bypass capacitance of
10 µF mV
In V with V
(2.4 V) mode
DDA
bypass capacitance of
10 µF mA –
60
1
–
–
61
–
V
DDA
–
–
–
–
21.3
85.3
–
V –
K Ω – pF – dB
In V with V
(2.4 V) mode
DDA
bypass capacitance of
10 µF
µs –
µs
Does not include acquisition time.
Equivalent to
44.8 ksps including acquisition time.
µs dB
Does not include acquisition time.
Equivalent to
11.6 ksps including acquisition time.
With 10-Hz input sine wave, external
2.4-V reference,
V
REF
(2.4 V) mode
22.4
kHz 8-bit resolution
–
–
2
1
LSB V REF
= 2.4 V or greater
LSB –
Datasheet 31 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.4
6.4.1
Digital peripherals
Timer counter pulse-width modulator (TCPWM)
Table 14
Spec ID
TCPWM specifications
Parameter
SID.TCPWM.1 ITCPWM1
SID.TCPWM.2 ITCPWM2
SID.TCPWM.2A ITCPWM3
Description
Block current consumption at 3 MHz
Block current consumption at 12 MHz
Block current consumption at 48 MHz
SID.TCPWM.3 TCPWM
FREQ
Operating frequency
SID.TCPWM.4 TPWM
ENEXT
Input trigger pulse width
Min
–
–
–
–
2/Fc
SID.TCPWM.5 TPWM
EXT
SID.TCPWM.5A TC
RES
SID.TCPWM.5B PWM
RES
SID.TCPWM.5C Q
RES
Output trigger pulse widths
Resolution of counter
PWM resolution
Quadrature inputs resolution
2/Fc
1/Fc
1/Fc
1/Fc
Typ Max Units Details/conditions
– 45 All modes (TCPWM)
– 155 µA All modes (TCPWM)
– 650 All modes (TCPWM)
– Fc
–
–
–
–
–
–
–
–
–
– ns
For all trigger events
Minimum possible width of Overflow,
Underflow, and CC
(Counter equals
Compare value) outputs
Minimum time between successive counts
Minimum pulse width of PWM
Output
Minimum pulse width between
Quadrature phase inputs
Note
6. Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected.
Datasheet 32 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.4.2
I
2
C
Table 15 Fixed I
Spec ID Parameter
2 C DC specifications
Description
SID149 I
SID150 I
SID151 I
SID152 I
I2C1
I2C2
I2C3
I2C4
Block current consumption at 100 kHz
Block current consumption at 400 kHz
Block current consumption at 1 Mbps
I 2 C enabled in Deep Sleep mode
Min
–
–
–
–
Table 16 Fixed I 2 C AC specifications
Spec ID Parameter
SID153 F
I2C1
Bit rate
Description
Typ
–
–
–
–
Max Units Details/conditions
50 –
135
310
1.4
µA
–
–
–
Min
–
Typ
–
Max Units Details/conditions
1 Msps –
Note
7. Guaranteed by characterization.
Datasheet 33 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.4.3
SPI
Table 17 SPI DC specifications
Spec ID Parameter
Description
SID163 ISPI1
SID164 ISPI2
SID165 ISPI3
Block current consumption at 1 Mbps
Block current consumption at 4 Mbps
Block current consumption at 8 Mbps
Min
–
–
–
Typ
–
–
–
Max Units Details/conditions
360 –
560
600
µA –
–
Table 18 SPI AC specifications
Spec ID Parameter Description
SID166 FSPI
SPI operating frequency
(Master; 6X Oversampling)
Fixed SPI Master Mode AC specifications
SID167
SID168
TDMO
TDSI
MOSI valid after SClock driving edge
MISO valid before SClock capturing edge
SID169 THMO
Previous MOSI data hold time
Fixed SPI Slave Mode AC specifications
SID170
SID171
SID171A
SID172
TDMI
TDSO
TDSO_EXT
THSO
MOSI valid before Sclock capturing edge
MISO valid after Sclock driving edge
MISO valid after Sclock driving edge in External
Clock mode
Previous MISO data hold time
SID172A TSSELSSCK SSEL valid to first SCK valid
Min Typ
– –
–
20
0
40
–
–
0
100
–
–
–
–
–
–
–
–
Max
8
15
–
–
–
42 + (3 × Tcpu)
48
–
–
Units Details/conditions
MHz – ns ns ns
–
Full clock, late
MISO sampling
Referred to Slave capturing edge
–
T
–
–
–
CPU
= 1/F
CPU
Datasheet 34 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.4.4
UART
Table 19 UART DC specifications
Spec ID Parameter
Description
SID160 I
SID161 I
UART1
UART2
Block current consumption at 100 Kbps
Block current consumption at 1000 Kbps
Min
–
–
Table 20 UART AC specifications
Spec ID Parameter
Description
SID162 F
UART
Bit rate
6.4.5
LCD direct drive
Table 21 LCD direct drive DC specifications
Spec ID Parameter
SID154 I
LCDLOW
Description
Operating current in low power mode
SID155 C
LCDCAP
SID156 LCD
OFFSET
SID157 I
LCDOP1
SID158 I
LCDOP2
LCD capacitance per segment/common driver
Long-term segment offset
LCD system operating current Vbias = 5 V
LCD system operating current Vbias = 3.3 V
Min
–
Min
–
–
–
–
–
Typ
–
–
Max Units Details/conditions
55 µA –
312 µA –
Typ
–
Max Units Details/conditions
1 Mbps –
500
20
2
2
Typ
5
–
–
–
Max Units Details/conditions
– µA 16 × 4 small segment disp. at 50 Hz
5000 pF – mV – mA 32 × 4 segments.
50 Hz. 25°C
32 × 4 segments.
50 Hz. 25°C
Table 22
Spec ID Parameter
SID159 F
LCD
LCD direct drive AC specifications
Description
LCD frame rate
Min
10
Typ
50
Max Units Details/conditions
150 Hz –
Note
8. Guaranteed by characterization.
Datasheet 35 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.5
6.5.1
Memory
Flash
Table 23
Spec ID Parameter
SID173 V
PE
Flash DC specifications
Description
Erase and program voltage
Min
1.71
Typ
–
Max Units Details/conditions
5.5
V –
Table 24
Spec ID
SID174
SID175
SID176
SID178
SID180
SID181
SID182
SID182A
T
T
T
T
T
F
F
Flash AC specifications
Parameter
ROWWRITE
ROWERASE
ROWPROGRAM
BULKERASE
DEVPROG
END
RET
Description
Row (block) write time (erase and program)
Row erase time
Row program time after erase
Bulk erase time
(32 KB)
Total device program time
Flash endurance
Flash retention.
T 55°C,
–
Flash retention.
T 85°C,
SID182B
SID256
SID257
F
RETQ
TWS48
TWS24
Flash retention.
T ≤ 105°C,
10 K P/E cycles,
≤ three years at T
A
≥ 85 °C.
Number of Wait states at 48 MHz
Number of Wait states at 24 MHz
–
–
100 K
20
10
10
2
1
Min Typ Max
–
–
–
–
–
–
20
16
4
–
–
–
–
–
–
–
–
–
20
–
–
35
7
–
–
Units Details/conditions ms
Row (block) =
128 bytes
–
–
–
Seconds –
Cycles –
–
Years
–
Guaranteed by
Characterization
CPU execution from Flash
CPU execution from Flash
Notes
9. It can take as much as 20 milliseconds to write to flash. During this time the device should not be Reset, or Flash operations may be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated.
10.Guaranteed by characterization.
Datasheet 36 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.6
6.6.1
System resources
Power-on reset (POR)
Table 25
Spec ID
Power-on reset (PRES)
Parameter Description
SID.CLK#6 SR_POWER_UP Power supply slew rate
SID185
SID186
V
V
RISEIPOR
FALLIPOR
Rising trip voltage
Falling trip voltage
Min
1
0.80
0.70
Typ Max Units Details/conditions
–
–
–
67
1.5
1.4
V
–
–
Table 26 Brown-out detect (BOD) for V
CCD
Spec ID Parameter Description
SID190
SID192
V
V
FALLPPOR
FALLDPSLP
BOD trip voltage in active and sleep modes
BOD trip voltage in Deep
Sleep
6.6.2
SWD interface
Table 27
Spec ID
SID213
SID214
SID215
SID216
SID217
SID217A
SWD interface specifications
Parameter Description
F_SWDCLK1 3.3 V V
DD
5.5 V
F_SWDCLK2 1.71 V V
DD
3.3 V
T_SWDI_SETUP T = 1/f SWDCLK
T_SWDI_HOLD T = 1/f SWDCLK
T_SWDO_VALID T = 1/f SWDCLK
T_SWDO_HOLD T = 1/f SWDCLK
Min
1.48
1.11
Typ Max Units Details/conditions
– 1.62
–
V
– 1.5 –
Min Typ Max Units Details/conditions
– – 14
MHz
SWDCLK ≤ 1/3 CPU clock frequency
– – 7
SWDCLK ≤ 1/3 CPU clock frequency
0.25 × T – –
0.25 × T –
– –
–
0.5 × T
1 – – ns
–
–
–
–
Datasheet 37 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.6.3
Internal main oscillator (IMO)
Table 28 IMO DC specifications
(Guaranteed by design)
Spec ID Parameter
SID218 I
SID219 I
IMO1
IMO2
Description
IMO operating current at 48 MHz
IMO operating current at 24 MHz
Min
–
–
Table 29
Spec ID
IMO AC specifications
Parameter Description Min
SID223
SID223A
SID223B
F
IMOTOL1
Frequency variation at
24, 32, and 48 MHz
(trimmed)
SID223C
SID223D
SID226
SID228
T
STARTIMO
T
JITRMSIMO2
IMO startup time
RMS jitter at 24 MHz
–
–
–
–
–
–
–
Typ
–
–
Max Units Details/conditions
250 µA –
180 µA –
Typ
–
–
–
–
–
–
145
Max Units Details/conditions
±2.0
%
At –40°C to 85°C, for industrial temperature range and original extended industrial range parts
±2.5
±2.0
±1.5
±1.25
7
–
%
%
%
%
µs – ps –
At –40°C to 105°C, for all extended industrial temperature range parts
At –30°C to 105°C, for enhanced IMO extended industrial temperature range parts
At –20°C to 105°C, for enhanced IMO extended industrial temperature range parts
At 0°C to 85°C, for enhanced IMO extended industrial temperature range parts
Note
11.The enhanced IMO extended temperature range parts replace the original extended industrial temperature range parts. For details on how to identify enhanced IMO extended temperature range parts, please visit the Infineon knowledge base article.
Datasheet 38 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.6.4
Internal low-speed oscillator (ILO)
Table 30 ILO DC specifications
(Guaranteed by design)
Spec ID
SID231
I
Parameter
ILO1
Description
ILO operating current
Min
–
Typ
0.3
Table 31
Spec ID
SID234
SID236
SID237
ILO AC specifications
Parameter Description
T
STARTILO1
T
ILODUTY
F
ILOTRIM1
ILO startup time
ILO duty cycle
ILO frequency range
Min
–
40
20
Max Units Details/conditions
1.05
µA –
Typ
–
50
40
Max Units Details/conditions
2 ms –
60
80
% – kHz –
6.6.5
Watch crystal oscillator (WCO)
Table 32 Watch crystal oscillator (WCO) specifications
Spec ID Parameter Description Min
SID398 FWCO Crystal frequency –
SID399 FTOL Frequency tolerance –
SID400 ESR
SID401 PD
SID402 TSTART
SID403 CL
SID404 C0
SID405 IWCO1
SID406 IWCO2
Equivalent series resistance
Drive level
Startup time
Crystal load capacitance
Crystal shunt capacitance
Operating current (high power mode)
Operating current (low power mode)
–
6
–
–
–
–
–
6.6.6
External clock
Typ
32.768
50
–
–
50
–
1.35
–
–
Table 33
SID305
SID306
External clock specifications
Spec ID Parameter
ExtClkFreq
ExtClkDuty
Description
External clock input frequency
Duty cycle; measured at
V
DD/2
Min
0
45
Max Units Details/conditions
– kHz –
250 ppm With 20-ppm
–
1 k Ω –
µW –
500
12.5
– ms – pF – pF –
8 µA –
1 µA –
Typ Max Units Details/conditions
– 48 MHz –
– 55 % –
Notes
12.Guaranteed by characterization.
13.For industrial temperature range parts, the maximum temperature is 85°C.
Datasheet 39 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.6.7
Clock
Table 34 Clock specs
Spec ID Parameter
SID262
T
CLKSWITCH
Description
System clock source switching time
6.6.8
Smart I/O Pass-through Time
Min
3
Typ
–
Max
4
Units Details/conditions
Periods –
Table 35 Smart I/O pass-through time (Delay in Bypass Mode)
Spec ID Parameter
SID252 PRG_BYPASS
Description
Max delay added by Smart
I/O in Bypass Mode
Min
–
Typ
–
Max
1.6
Units Details/conditions ns –
Note
14.Guaranteed by characterization.
Datasheet 40 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Ordering information
7 Ordering information
The PSoC™ 4000S part numbers and features are listed in the following table.
Table 36 PSoC™ 4000S ordering information
Features
Category MPN
Package
4024
4025
4045
CY8C4024FNI-S402
CY8C4024LQI-S401
CY8C4024LQI-S402
CY8C4024AXI-S402
CY8C4024LQI-S403
CY8C4024AZI-S403
CY8C4024FNI-S412
CY8C4024LQI-S411
CY8C4024LQI-S412
CY8C4024AXI-S412
CY8C4024LQI-S413
CY8C4024AZI-S413
CY8C4024AZQ-S413
CY8C4025FNI-S402
CY8C4025LQI-S401
CY8C4025LQI-S402
CY8C4025AXI-S402
CY8C4025LQI-S403
CY8C4025AZI-S403
CY8C4025AZQ-S403
CY8C4025FNI-S412
CY8C4025LQI-S411
CY8C4025LQI-S412
CY8C4025AXI-S412
CY8C4025LQI-S413
CY8C4025AZI-S413
CY8C4025AZQ-S413
CY8C4045FNI-S412
CY8C4045LQI-S411
CY8C4045LQI-S412
CY8C4045AXI-S412
CY8C4045LQI-S413
CY8C4045AZI-S413
CY8C4045AZQ-S413
24 32 4
24 32 4
24 32 4
24 32 4
48 32 4
48 32 4
48 32 4
48 32 4
48 32 4
48 32 4
48 32 4
24 16 2
24 16 2
0 0 1 0
0 0 1 0
24 16 2 0 0 1 0
24 16 2 0 0 1 0
24 16 2
24 16 2
24 16 2
24 16 2
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
24 16 2
24 16 2
24 16 2
24 16 2
24 16 2
24 32 4
24 32 4
24 32 4
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 0 1 0
0
0
0
0
1
1
0
0
24 32 4
24 32 4
24 32 4
0 0 1 0
0 0 1 0
0 0 1 0
24 32 4
24 32 4
24 32 4
24 32 4
0 0 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
2 5 2 8 21 ✔ – –
2 5 2 8 19 – ✔ –
–
–
–
–
–
–
2 5 2 16 27 – – ✔ – – –
2 5 2 16 27 – – – ✔ – –
2 5 2 16 34 – – –
2 5 2 16 36 – – –
– ✔
– – ✔
2 5 2 8 21 ✔ – –
2 5 2 8 19 – ✔ –
2 5 2 16 36 – – –
–
–
–
–
–
–
2 5 2 16 27 – – ✔ – – –
2 5 2 16 27 – – – ✔ – –
2 5 2 16 34 – – – – ✔ –
– – ✔
–40°C to 85°C
2
2 5 2 8 21 ✔ – –
2 5 2 8 19 – ✔ –
2 5 2 16 27 – – ✔ – – –
2
5
5
2
2
16 36
16 27
–
–
–
–
–
–
– – ✔ –40°C to 105°C
–
–
✔
–
–
–
–
–
–
–40°C to 85°C
2
2
2
2
5
5
5
5
2
2
2
2
16 34
16 36
16 36
8 21
–
–
–
✔
–
–
–
–
–
–
–
–
– ✔ –
– – ✔
– – ✔ –40°C to 105°C
– – –
2 5 2 8 19 – ✔ – – – –
2 5 2 16 27 – – ✔ – – –
2 5 2 16 27 – – – ✔ – –
2 5 2 16 34 – – – – ✔ –
–40°C to 85°C
2 5 2 16 36 – – – – – ✔
2
2
5
5
2
2
16 36
8 21
–
✔
–
–
– – – ✔ –40°C to 105°C
– – – –
2 5 2 8 19 – ✔ – – – –
2 5 2 16 27 – – ✔ – – –
–40°C to 85°C
2 5 2 16 27 – – – ✔ – –
2 5 2 16 34 – – – – ✔ –
2 5 2 16 36 – – – – – ✔
2 5 2 16 36 – – – – – ✔ –40°C to 105°C
Datasheet 41 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Ordering information
The nomenclature used in the preceding table is based on the following part numbering convention:
Field
CY8C Prefix
4
A
B
C
DE
F
S
Architecture
Family
CPU Speed
Description
Flash Capacity
Package Code
Temperature Range
Series Designator
XYZ Attributes Code
The following is an example of a part number:
Values Meaning
PV
FN
I
Q
7
AX
AZ
LQ
4
4
5
6
4
0
2
PSoC™ 4
4000 Family
24 MHz
48 MHz
16 KB
32 KB
64 KB
128 KB
TQFP (0.8-mm pitch)
TQFP (0.5-mm pitch)
QFN
SSOP
CSP
Industrial
Extended Industrial
S
M
PSoC™ 4 S-Series
PSoC™ 4 M-Series
L
BL
PSoC™ 4 L-Series
PSoC™ 4 BLE-Series
000-999 Code of feature set in the specific family
Example
4: PSoC 4
4: 48 MHz
5: 32 KB
I: Industrial
Cypress Prefix
Architecture
Family within Architecture
CPU Speed
Flash Capacity
Package Code
Temperature Range
Silicon Family
Attributes Code
CY8C 4 A B C DE F – S XYZ
Datasheet 42 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Packaging
8 Packaging
The PSoC™ 4000S is offered in 48-pin TQFP, 40-pin QFN, 32-pin QFN, 24-pin QFN, 32-pin TQFP, and 25-ball WLCSP packages.
Package dimensions and Infineon drawing numbers are in the following table.
Table 37
Spec ID
BID20
BID27
BID34A
BID34
BID34G
BID34F
Package list
Package
48-pin TQFP
40-pin QFN
32-pin QFN
24-pin QFN
32-pin TQFP
25-ball WLCSP
Description
7 × 7 × 1.4 mm height with 0.5-mm pitch
6 × 6 × 0.6 mm height with 0.5-mm pitch
5 × 5 × 0.6 mm height with 0.5-mm pitch
4 × 4 × 0.6 mm height with 0.5-mm pitch
7 × 7 × 1.4 mm height with 0.8-mm pitch
2.02 × 1.93 × 0.48 mm height with 0.35-mm pitch
Package drawing
51-85135
001-80659
001-42168
001-13937
51-85088
002-09957
T
JC
T
JA
T
JC
Table 38
Parameter
T
A
T
J
T
JA
T
JC
T
JA
T
JC
T
JA
T
JC
T
JA
T
JC
T
JA
Package thermal characteristics
Description
Operating ambient temperature –
Operating junction temperature –
Package θ
JA
Package θ
JC
Package θ
JA
Package θ
JC
Package θ
JA
Package θ
JC
Package θ
JA
Package
48-pin TQFP
40-pin QFN
32-pin QFN
Package θ
JC
Package θ
JA
24-pin QFN
32-pin TQFP Package θ
JC
Package θ
JA
Package θ
JC
25-ball WLCSP
Table 39 Solder reflow peak temperature
Package Maximum peak temperature
All 260 °C
Min
–40
–40
–
–
–
–
–
–
Typ
25
–
73.5
33.5
17.8
2.8
20.8
5.9
21.7
5.6
29.4
3.5
40
0.5
–
–
–
–
–
–
–
–
Max Units
105 °C
125
–
–
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
– °C/W
– °C/W
°C/W
°C/W
°C/W
°C/W
Maximum time at peak temperature
30 seconds
Datasheet 43 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Packaging
Table 40
8.1
Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-020
Package
All except WLCSP
25-ball WLCSP
MSL
MSL 3
MSL 1
Package diagrams
Figure 6
51-85135 *C
48-pin TQFP (7 × 7 × 1.4 mm) package outline, 51-85135
Datasheet 44 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Packaging
Figure 7
001-80659 *A
40-pin QFN ((6 × 6 × 0.6 mm) 4.6 × 4.6 E-Pad (Sawn)) package outline, 001-80659
Datasheet 45 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Packaging
SEE NOTE 1
TOP VIEW
BOTTOM VIEW
SIDE VIEW
Figure 8
DIMENSIONS
E
E2
L b e
A
A1
A2
D
D2
SYMBOL
MIN.
NOM.
MAX.
0.50
-
0.55
0.020
0.60
0.045
4.90
3.40
0.15 BSC
5.00
3.50
5.10
3.60
4.90
3.40
5.00
3.50
5.10
3.60
0.30
0.18
0.40
0.25
0.50 TYP
0.50
0.30
NOTES:
1. HATCH AREA IS SOLDERABLE EXPOSED PAD
2. BASED ON REF JEDEC # MO-248
3. PACKAGE WEIGHT: 0.0388g
4. DIMENSIONS ARE IN MILLIMETERS
001-42168 *F
32-pin QFN ((5.0 × 5.0 × 0.55 mm) 3.5 × 3.5 mm E-Pad (Sawn)) package outline, 001-42168
Datasheet 46 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Packaging
Figure 9
001-13937 *H
24-pin QFN ((4 × 4 × 0.60 mm) 2.65 × 2.65 E-Pad (Sawn)) package outline, 001-13937
The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floating and not connected to any other signal.
Datasheet 47 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Packaging
Figure 10 32-pin TQFP (7 × 7 × 1.4 mm) package outline, 51-85088
51-85088 *E
Figure 11
002-09957 **
25-ball WLCSP (2.02 × 1.93 × 0.48 mm) package outline, 002-09957
Datasheet 48 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Acronyms
9 Acronyms
EMI
EMIF
EOC
EOF
EPSR
ESD
ETM
FIR
DNL
DNU
DR
DSI
DWT
ECC
ECO
EEPROM
CMRR
CPU
CRC
DAC
DFB
DIO
DMIPS
DMA
Table 41
Acronym
Acronyms used in this document abus
ADC
AG
AHB analog local bus analog-to-digital converter analog global
Description
AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus
ALU
AMUXBUS
API
APSR
ARM ®
ATM
BW
CAN arithmetic logic unit analog multiplexer bus application programming interface application program status register advanced RISC machine, a CPU architecture automatic thump mode bandwidth
Controller Area Network, a communications protocol common-mode rejection ratio central processing unit cyclic redundancy check, an error-checking protocol digital-to-analog converter, see also IDAC, VDAC digital filter block digital input/output, GPIO with only digital capabilities, no analog. See GPIO.
Dhrystone million instructions per second direct memory access, see also TD differential nonlinearity, see also INL do not use port write data registers digital system interconnect data watchpoint and trace error correcting code external crystal oscillator electrically erasable programmable read-only memory electromagnetic interference external memory interface end of conversion end of frame execution program status register electrostatic discharge embedded trace macrocell finite impulse response, see also IIR
Datasheet 49 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Acronyms
NMI
NRZ
NVIC
NVL opamp
PAL
PC
PCB
PGA
PHUB
PHY
PICU
LUT
LVD
LVI
LVTTL
MAC
MCU
MISO
NC
ITM
LCD
LIN
LR
I/O
IPOR
IPSR
IRQ
Table 41
Acronym
Acronyms used in this document
(continued)
Description
FPB
FS
GPIO
HVI flash patch and breakpoint full-speed general-purpose input/output, applies to a PSoC pin high-voltage interrupt, see also LVI, LVD
IIR
ILO
IMO
INL
IC
IDAC
I
IDE
2 C, or IIC integrated circuit current DAC, see also DAC, VDAC integrated development environment
Inter-Integrated Circuit, a communications protocol infinite impulse response, see also FIR internal low-speed oscillator, see also IMO internal main oscillator, see also ILO integral nonlinearity, see also DNL input/output, see also GPIO, DIO, SIO, USBIO initial power-on reset interrupt program status register interrupt request instrumentation trace macrocell liquid crystal display
Local Interconnect Network, a communications protocol.
link register lookup table low-voltage detect, see also LVI low-voltage interrupt, see also HVI low-voltage transistor-transistor logic multiply-accumulate microcontroller unit master-in slave-out no connect nonmaskable interrupt non-return-to-zero nested vectored interrupt controller nonvolatile latch, see also WOL operational amplifier programmable array logic, see also PLD program counter printed circuit board programmable gain amplifier peripheral hub physical layer port interrupt control unit
Datasheet 50 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Acronyms
SR
SRAM
SRES
SWD
SWV
TD
THD
TIA
TRM
TTL
TX
UART
SCL
SDA
S/H
SINAD
SIO
SOC
SOF
SPI
RISC
RMS
RTC
RTL
RTR
RX
SAR
SC/CT
Table 41
Acronym
Acronyms used in this document
(continued)
Description
PLA
PLD
PLL
PMDD programmable logic array programmable logic device, see also PAL phase-locked loop package material declaration datasheet
POR
PRES
PRS
PS
PSoC™
PSRR
PWM
RAM power-on reset precise power-on reset pseudo random sequence port read data register
Programmable System-on-Chip™ power supply rejection ratio pulse-width modulator random-access memory reduced-instruction-set computing root-mean-square real-time clock register transfer language remote transmission request receive successive approximation register
I switched capacitor/continuous time
2 C serial clock
I 2 C serial data sample and hold signal to noise and distortion ratio special input/output, GPIO with advanced features. See GPIO.
start of conversion start of frame
Serial Peripheral Interface, a communications protocol slew rate static random access memory software reset serial wire debug, a test protocol single-wire viewer transaction descriptor, see also DMA total harmonic distortion transimpedance amplifier technical reference manual transistor-transistor logic transmit
Universal Asynchronous Transmitter Receiver, a communications protocol
Datasheet 51 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 41
Acronym
Acronyms used in this document
(continued)
Description
UDB
USB
USBIO
VDAC universal digital block
Universal Serial Bus
USB input/output, PSoC pins used to connect to a USB port voltage DAC, see also DAC, IDAC
WDT
WOL
WRES
XRES
XTAL watchdog timer write once latch, see also NVL watchdog timer reset external reset I/O pin crystal
Datasheet 52 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Document conventions
10
10.1
Document conventions
Units of measure
pF ppm ps s sps sqrtHz
V nA ns nV
µW mA ms mV
µF
µH
µs
µV
MHz
M
Msps
µA
KB kbps
Khr kHz k ksps
LSB
Mbps
Table 42
Symbol
Units of measure
°C dB fF
Hz degrees Celsius decibel femto farad hertz
1024 bytes kilobits per second kilohour kilohertz kilo ohm kilosamples per second least significant bit megabits per second megahertz mega-ohm megasamples per second microampere microfarad microhenry microsecond microvolt microwatt milliampere millisecond millivolt nanoampere nanosecond nanovolt ohm picofarad parts per million picosecond second samples per second square root of hertz volt
Unit of measure
Datasheet 53 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Revision history
Revision history
Document version
**
*A
*B
*C
*D
*E
Date of release Description of changes
2015-08-28 New datasheet.
2015-10-30
Removed 20-ball WLCSP package related information in all instances across the document.
Added 25-ball WLCSP package related information in all instances across the document.
Updated
Updated
.
Updated
Updated
Updated
:
Updated
(Updated details in “Details/Conditions” column corresponding to V
ICM3
, I
CMP3
parameters (Added V
DDD
≥ 2.2V at –40 °C)).
Updated
(Updated details in “Details/Conditions” column corresponding to TRESP3 parameter (Added V
DDD
Updated
:
Updated
.
Updated
:
Updated part numbers.
≥ 2.2V at –40 °C)).
2015-12-08 Changed status from Advance to Preliminary.
2016-01-27
Updated
Updated
(Replaced TBD with values for Theta J
A
and Theta J
C parameters).
Updated
:
Replaced TBD with spec 002-09957 **.
Added Errata.
2016-02-16 Updated to new template.
2016-03-15
Updated
Updated
.
Updated
Updated
Updated
Updated
(Updated all values corresponding to R
PULLUP
parameter).
RESETWAKE
Updated
(Updated all values corresponding to T parameter).
Updated
Updated
:
Updated
.
Updated
Updated
.
Updated
Updated
Updated
Table 24 (Updated all values corresponding to T
T
ROWPROGRAM
parameters).
ROWERASE
,
Datasheet 54 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Revision history
Document version
*F
*G
*H
*I
*J
Date of release Description of changes
2016-05-12
2016-07-27
2016-09-14
2017-01-09
Updated
Updated
:
Updated
.
Updated
Updated
Updated
:
Updated
(Updated all values corresponding to IDAC1INL,
IDAC2INL, SNR, IDAC1CRT1, IDAC1CRT12, IDAC1CRT22, IDAC1CRT32,
IDAC2CRT1, IDAC2CRT12, IDAC2CRT22, IDAC2CRT32, IDACMISMATCH2,
IDACMISMATCH3 parameters).
Updated
Updated
Table 13 (Updated all values corresponding to A_SND parameter).
Removed Errata.
Updated to new template.
Changed status from Preliminary to Final.
Updated
:
Updated
:
Updated
Updated description.
Updated
Updated
Updated
(Updated details corresponding to I
parameters).
, I
DD8
, I
DD11
, I
DD17
,
I
DD20
, I
Updated
, I
, I
DD26
, I
DD29
, I
DD32
, I
DD_XR
Updated
(Updated details in “Details/Conditions” column corresponding to V
OH
parameter and spec ID SID60).
Updated
Updated
Table 37 (Updated details in “Description” column corresponding
to 25-Ball WLCSP package (Updated package dimensions)).
Updated
(Added 25-ball WLCSP package and its corresponding details).
Completing Sunset Review.
Added 40-pin QFN package related information in all instances across the document.
Updated
Updated
Updated
(Updated details corresponding to I
DD5
I
DD20
, I
DD23
Updated
, I
DD23A
, I
, I
Updated
:
Added spec 001-80659 *A.
DD29
, I
DD32
, I
DD_XR
parameters).
, I
DD8
, I
DD11
, I
DD17
,
Updated
Replaced PRGIO with Smart I/O in all instances.
2017-04-26 Updated Cypress Logo and Copyright.
Datasheet 55 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Revision history
Document version
*K
*L
Date of release
2017-11-17
2019-07-31
Description of changes
Updated Document Title to read as “PSoC® 4: PSoC 4000S Datasheet
Programmable System-on-Chip (PSoC®)”.
Added 32-pin TQFP Package related information in all instance across the document.
Updated
:
Updated part numbers.
Updated
Updated
: spec 001-42168 – Changed revision from *E to *F.
Added spec 51-85088 *E.
Updated
Updated
:
Updated description.
Added
.
Added
.
Updated
:
Updated
Updated
:
Updated description.
Updated
Watch crystal oscillator (WCO)
:
Updated description.
Updated
Updated
Serial communication block (SCB) :
Updated description.
Updated
:
Updated
Updated description.
Updated
Added Note below
Updated
Updated
Updated
Updated
(Updated details in “Details/Conditions” column corresponding to V
REF
, V
REF_EXT
and V
COMPIDAC
parameters).
Updated
:
Updated
Updated
(Updated all values corresponding to TSSELSSCK parameter).
Updated
:
Updated part numbers.
Updated
Updated
: spec 001-13937 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
Datasheet 56 002-00123 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Revision history
Document version
*M
*N
*O
Date of release
2020-11-20
2020-12-23
2022-07-28
Description of changes
Updated
Added “Clock sources”.
Added “ModusToolbox™ software”.
Updated
:
Replaced “More Information” with “Development ecosystem” in heading.
Updated description.
Added
Updated
Updated
Updated temperature range in description below heading.
Updated
Updated
Updated
.
Updated
:
Updated
:
Added Q-temp MPNs for the 48-pin TQFP package.
Updated
Updated
.
Updated to new template.
Updated
:
Updated Nomenclature:
Updated details under Temperature Range to show “Extended Industrial”.
Updated
: Updated spec SID223 and SID223A. Added specs
SID223B through SID223D.
Migrated to Infineon template.
Datasheet 57 002-00123 Rev. *O
2022-07-28
Please read the Important Notice and Warnings at the end of this document
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2022-07-28
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2022 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about this document?
Go to www.infineon.com/support
Document reference
002-00123 Rev. *O
IMPORTANT NOTICE
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”).
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office
( www.infineon.com
).
With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon
Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon
Technologies office.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by authorized representatives of Infineon
Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application.
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