STMicroelectronics LSM6DSO16IS Datasheet
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LSM6DSO16IS
Datasheet iNEMO inertial module: always-on 3-axis accelerometer and 3-axis gyroscope with ISPU - intelligent sensor processing unit
LSM6DSO16IS
LGA-14L
(2.5 x 3.0 x 0.83 mm) typ.
Product status link
LSM6DSO16IS
Product summary
Order code LSM6DSO16ISTR
Temperature range [°C]
-40 to +85
Package
Packing
LGA-14L
(2.5 x 3 x 0.83 mm)
Tape and reel
Product resources
TN0018 (Design and soldering)
Product label
Features
• 3-axis accelerometer with selectable full scale: ±2/±4/±8/±16 g
• 3-axis gyroscope with selectable full scale: ±125/±250/±500/±1000/±2000 dps
• Embedded ISPU: ultra-low-power, high-performance programmable core to execute signal processing and AI algorithms in the edge for a seamless digitallife experience
• Low-power consumption: 0.59 mA in high-performance mode, 0.46 mA in lowpower mode (gyroscope + accelerometer only, ISPU not included)
• Low noise: 70 μg/√Hz in high-performance mode
• Sensor hub feature to efficiently collect data from additional external sensors (up to 4 external sensors)
• SPI / I²C serial interface
• Analog supply voltage: 1.71 V to 3.6 V with independent IO supply (1.62 V)
• Temperature range from -40 to +85 °C
• Embedded temperature sensor
• Compact footprint: 2.5 mm x 3 mm x 0.83 mm
• ECOPACK and RoHS compliant
Applications
• Complex motion detection and gesture recognition
• Activity recognition and tracking
• IoT and connected devices
• Wearables and smart watches for sports and personal health
• Smart pens, gaming and remote controllers
Description
The LSM6DSO16IS is a system-in-package featuring a 3-axis digital accelerometer and a 3-axis digital gyroscope, boosting performance at 0.59 mA in high-performance mode and enabling always-on low-power features for optimal motion results in personal electronics and IoT solutions.
The LSM6DSO16IS has a full-scale acceleration range of ±2/±4/±8/±16 g and an angular rate range of ±125/±250/±500/±1000/±2000 dps. The module features programmable interrupts and an on-chip sensor hub which includes up to 6 sensors: the internal accelerometer & gyroscope and 4 external sensors.
The LSM6DSO16IS embeds a new ST category of processing, ISPU (intelligent sensor processing unit) to support real-time applications that rely on sensor data. The
ISPU is an ultra-low-power, high-performance programmable core which can execute signal processing and AI algorithms in the edge. The main benefits of the ISPU are C programming and an enhanced ecosystem with libraries and 3 rd party tools/IDE.
Its optimized ultra-low-power hardware circuitry for real-time execution of the algorithms is a state-of-the-art feature for any personal electronics, from wearable accessories to high-end applications.
The LSM6DSO16IS is available in a plastic land grid array (LGA) package.
DS13892 - Rev 2 - June 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
1
LSM6DSO16IS
Overview
Overview
The LSM6DSO16IS is a system-in-package featuring a high-performance 3-axis digital accelerometer and 3-axis digital gyroscope which embeds an ISPU (intelligent sensor processing unit) .
ISPU is the new ST category of processing: it is an ultra-low-power, high-performance programmable core with high computational efficiency which can execute signal processing and AI algorithms on the real-time data from the sensor(s). It is compatible with the most common tools to enable flexible development and supports both machine learning and deep learning, offering broad options and freedom for programming.
ISPU is equipped with 32 KB of program RAM, 8 KB of data RAM and an FPU supporting addition, subtraction, and multiplication.
The LSM6DSO16IS features programmable interrupts and an on-chip sensor hub which includes up to six sensors: two internal (accelerometer and gyroscope) and four external sensors.
The sensor hub is accessible from the ISPU.
Like the entire portfolio of MEMS sensor modules, the LSM6DSO16IS leverages the robust and mature in-house manufacturing processes already used for the production of micromachined accelerometers and gyroscopes.
The sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the characteristics of the sensing element.
The LSM6DSO16IS is available in a small plastic land grid array (LGA) package of 2.5 x 3.0 x 0.83 mm to address ultra-compact solutions.
DS13892 - Rev 2 page 2/107
2
LSM6DSO16IS
ISPU (intelligent sensor processing unit)
ISPU (intelligent sensor processing unit)
The LSM6DSO16IS embeds a general-purpose core, a new ST category of processing, called ISPU (intelligent sensor processing unit). The ISPU is based on STRED architecture, a proprietary architecture developed by
STMicroelectronics. Its optimized ultra-low-power hardware circuitry for the real-time execution of the algorithms is a state-of-the-art feature for any personal electronics, from wearable accessories to high-end applications (for example, smartwatches, convertible laptops, smartphones, and so on).
A toolchain allows developing in C code and loading any custom program in the core, with the only limitation being the available memory size of the program.
Several algorithms running on the ISPU can generate interrupts to wake up the host processor accordingly.
The ISPU core includes an 8 KB RAM for data storage and a dedicated 32 KB RAM for program memory in order to have maximum configurability. The program of the ISPU, hosted in volatile memory, should be loaded at power-up of the device by an external host through the SPI/I²C interface.
The LSM6DSO16IS is internally organized as follows:
•
• the sensor core (with 8-bit registers) which communicates with the user over the SPI or I²C and handles the sensor features (from settings to outputs) the processing core: ISPU which is based on 32-bit registers and communicates with the user through the
8-bit interface registers of the sensor core
The registers that enable the exchange between the ISPU and the sensor core are:
•
ISPU reading accelerometer data
ISPU_ARAW_Y_L (6884h), ISPU_ARAW_Y_H (6885h)
,
ISPU_ARAW_Z_L (6888h), ISPU_ARAW_Z_H
ISPU_ARAW_X_L (6880h), ISPU_ARAW_X_H (6881h)
,
•
•
ISPU reading gyroscope data
ISPU_GRAW_X_L (688Ch), ISPU_GRAW_X_H (688Dh) ,
(6890h), ISPU_GRAW_Y_L (6891h)
,
ISPU_GRAW_Z_L (6894h), ISPU_GRAW_Z_H (6895h)
ISPU reading external sensor data
ISPU_ERAW_0_L (6898h), ISPU_ERAW_0_H (6899h)
,
ISPU_ERAW_1_L (689Ch), ISPU_ERAW_1_H (689Dh) , ISPU_ERAW_2_L (68A0h), ISPU_ERAW_2_H
• ISPU reading temperature sensor data
ISPU_TEMP_L (68A4h), ISPU_TEMP_H (68A5h)
The data in the registers above comes from physical sensors (accelerometer, gyroscope, temperature and external sensors) in 16-bit two’s complement format, without any decoding.
DS13892 - Rev 2 page 3/107
DS13892 - Rev 2
LSM6DSO16IS
ISPU (intelligent sensor processing unit)
There are 64-byte registers for general-purpose output data coming from the ISPU in registers
through ISPU_DOUT_31_L (4Eh), ISPU_DOUT_31_H (4Fh) .
The device also provides four sets of 16-bit registers which can be used for loading input data (like algorithm
configuration) for the ISPU in registers ISPU_DUMMY_CFG_1_L (73h) and ISPU_DUMMY_CFG_1_H (74h)
through ISPU_DUMMY_CFG_4_L (79h) and ISPU_DUMMY_CFG_4_H (7Ah) .
SPI / I 2 C
Sensor hub
I 2 C Sensor hub
Figure 1. ISPU block diagram
LSM6DSO16IS
Accelerometer
Gyroscope
Temperature
Sensor
Core
ISPU input data from sensors
• Accelerometer (ISPU_ARAW)
• Gyroscope (ISPU_GRAW)
• Temperature (ISPU_TEMP)
• External sensor (ISPU_ERAW)
ISPU configuration registers
(ISPU_DUMMY_CFG)
IF to ISPU flags registers
(ISPU_IF2S_FLAG)
ISPU to IF flags registers
(ISPU_S2IF_FLAG)
ISPU output data registers
(ISPU_DOUT)
ISPU
ISPU core
page 4/107
LSM6DSO16IS
Pin description
3
Pin description
Z
Figure 2. Pin connections
Y
Direction of detectable acceleration (top view)
X
Ω
Y
Ω
R
12 14
RES
RES
INT2
Vdd
11
8
BOTTOM
VIEW
7 5
1
4
SDO/SA0
MSDA
MSCL
INT1
Direction of detectable angular rate (top view)
Ω
P
DS13892 - Rev 2 page 5/107
3.1
LSM6DSO16IS
Pin connections
•
•
Pin connections
The LSM6DSO16IS offers flexibility to connect the pins in order to have two different mode connections and functionalities. In detail:
Mode 1 : I²C or SPI (3- and 4-wire) serial interface is available.
Mode 2 : I²C or SPI (3- and 4-wire) serial interface and I²C interface master for external sensor connections are available.
Figure 3. LSM6DSO16IS connection modes
Mode 1
HOST
I 2 C /
SPI (3/4-w)
LSM6DSO16IS
Mode 2
HOST
I 2 C /
SPI (3/4-w)
LSM6DSO16IS
Master I 2 C
LSM6DSM sensors
DS13892 - Rev 2 page 6/107
DS13892 - Rev 2
LSM6DSO16IS
Pin connections
In the following table each mode is described for the pin connections and function.
Table 1. Pin description
7
8
5
6
2
3
4
Pin#
1
9
10
11
12
13
14
Name
SDO/SA0
MSDA
MSCL
INT1
Vdd_IO
GND
GND
Vdd
RES
RES
CS
INT2
SCL
SDA
Mode 1 function Mode 2 function
SPI 4-wire interface serial data output (SDO)
I²C least significant bit of the device address (SA0)
Connect to Vdd_IO or GND
Connect to Vdd_IO or GND
I²C serial data master (MSDA)
I²C serial clock master (MSCL)
Programmable interrupt 1
Programmable interrupt 2
Power supply for I/O pins
0 V supply
0 V supply
Power supply
Programmable interrupt 2 (INT2)
I²C master external synchronization signal (MDRDY)
Leave unconnected
Connect to Vdd_IO or leave unconnected
I²C/SPI mode selection
(1: SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
I²C serial clock (SCL)
SPI serial port clock (SPC)
I²C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
1. Recommended 100 nF filter capacitor.
2. Leave pin electrically unconnected and soldered to PCB.
page 7/107
4
4.1
LSM6DSO16IS
Module specifications
Module specifications
Mechanical characteristics
@ Vdd = 1.8 V, T = 25 °C, unless otherwise noted.
Symbol
G_FS
LA_So Linear acceleration sensitivity
G_So
Angular rate measurement range
Parameter
Table 2. Mechanical characteristics
LA_FS Linear acceleration measurement range
G_So% Sensitivity tolerance
LA_So% Sensitivity tolerance
LA_SoDr Linear acceleration sensitivity change vs. temperature (5)
G_SoDr Angular rate sensitivity change vs. temperature
LA_TyOff Linear acceleration zerog
G_TyOff Angular rate zero-rate level
LA_OffDr Linear acceleration zerog
level change vs. temperature (5)
G_OffDr
Angular rate typical zero-rate level change vs.
temperature
Rn Rate noise density in high-performance mode
RnRMS
Gyroscope RMS noise in low-power mode (7)
Test conditions
FS = ±2 g
FS = ±4 g
FS = ±8 g
FS = ±16 g
FS = ±125 dps
FS = ±250 dps
FS = ±500 dps
FS = ±1000 dps
FS = ±2000 dps at component level, T = 25 °C at component level, T = 25 °C from -40° to +85° from -40° to +85°
T = 25 °C
T = 25 °C from -40° to +85°
Min.
Max.
0.244
0.488
4.375
8.75
17.50
35
70
±1
±1
±0.01
±500
±1000
±2000
0.061
0.122
±2
±4
±8
±16
±125
±250
±0.01
±40
±3
±0.1
m
Unit dps g g
/LSB mdps/LSB
%
%
%/°C
%/°C m g dps m g/ °C from -40° to +85° ±0.015
dps/°C mdps/√Hz mdps
An
RMS
Acceleration noise density in high-performance mode (8)
Acceleration RMS noise in low-power mode
FS = ±2 g
FS = ±4 g
FS = ±8 g
FS = ±16 g
FS = ±2 g
FS = ±4 g
FS = ±8 g
3.4
75
70
75
85
110
1.8
2.0
2.4
µ g /√Hz m g (RMS)
DS13892 - Rev 2 page 8/107
DS13892 - Rev 2
LSM6DSO16IS
Mechanical characteristics
Symbol Parameter Test conditions
Min.
Max.
Unit
RMS Acceleration RMS noise in low-power mode
LA_ODR Linear acceleration output data rate
G_ODR Angular rate output data rate
FS = ±16 g 3.0
208
416
833
1667
3333
6667
12.5
26
52
104
12.5
26
52
104
208
416
833
1667
3333
6667 m g (RMS)
Hz
Vst
Linear acceleration self-test output change (12)(13)(14)
Angular rate self-test output change
FS = ±250 dps
FS = ±2000 dps
50
20
150
-40
1700
80
700
+85 m g dps dps
°C Top Operating temperature range
1. Min/Max values are based on characterization results at 3σ on a limited number of samples, not tested in production and not guaranteed.
2. Typical specifications are not guaranteed.
3. Sensitivity values after factory calibration test and trimming.
4. Values after factory calibration test and trimming.
5. Measurements are performed in a uniform temperature setup and they are based on characterization data in a limited number of samples. Not measured during final test for production.
6. Gyroscope rate noise density in high-performance mode is independent of the ODR and FS setting.
7. Gyroscope RMS noise in low-power mode is independent of the ODR and FS setting.
8. Accelerometer noise density in high-performance mode is independent of the ODR.
9. Accelerometer RMS noise in low-power mode is independent of the ODR.
10. Noise RMS related to BW = ODR/2.
11. This ODR is available when the accelerometer is in low-power mode.
12. The sign of the linear acceleration self-test output change is defined by the STx_XL bits in a dedicated register for all axes.
13. The linear acceleration self-test output change is defined with the device in stationary condition as the absolute value of:
OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 0.061 mg at ±2 g full scale.
14. Accelerometer self-test limits are full-scale independent.
15. The sign of the angular rate self-test output change is defined by the STx_G bits in a dedicated register for all axes.
16. The angular rate self-test output change is defined with the device in stationary condition as the absolute value of:
OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 70 mdps at ±2000 dps full scale.
page 9/107
LSM6DSO16IS
Electrical characteristics
4.2
Electrical characteristics
@ Vdd = 1.8 V, T = 25 °C, unless otherwise noted.
Table 3. Electrical characteristics
Symbol Parameter
Vdd Supply voltage
Vdd_IO Power supply for I/O
IddHP
IddLP
Gyroscope and accelerometer current consumption in high-
Gyroscope and accelerometer current consumption in low-power mode
G_IddHP Gyroscope current consumption in high-performance mode (3)
Test conditions
ODR = 208 Hz
Min.
1.71
1.62
1.8
595
465
490
Max.
3.6
3.6
Unit
V
V
µA
µA
µA
G_IddLP Gyroscope current consumption in low-power mode
ODR = 52 Hz
ODR = 12.5 Hz
320
290
µA
LA_IddHP Accelerometer current consumption in high-performance mode
LA_IddLP Accelerometer current consumption in low-power mode (3)
ODR = 52 Hz
ODR = 1.6 Hz
180
37
15
µA
µA
IddPD
Ton
V
IH
V
IL
V
OH
V
OL
Top
Gyroscope and accelerometer current consumption during powerdown
Turn-on time
Digital high-level input voltage
Digital low-level input voltage
High-level output voltage
Low-level output voltage
Operating temperature range
I
I
OH
= 4 mA
OL
0.7 * Vdd_IO
Vdd_IO - 0.2
-40
6
35
0.3 * Vdd_IO
0.2
+85
µA ms
1. Min/Max values are based on characterization results at 3σ on a limited number of samples, not tested in production and not guaranteed.
2. Typical specifications are not guaranteed.
3. Current consumption is intended for accelerometer and gyroscope sensors only, ISPU consumption is not taken into account.
4. 4 mA is the maximum driving capability, that is, the maximum DC current that can be sourced/sunk by the digital pin in order to guarantee the correct digital output voltage levels V
OH
and V
OL
.
V
V
V
V
°C
DS13892 - Rev 2 page 10/107
4.3
LSM6DSO16IS
Temperature sensor characteristics
Temperature sensor characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted.
Table 4. Temperature sensor characteristics
Symbol
Parameter
Temperature refresh rate
Test condition Min.
52
Max.
Unit
Hz
Toff
TSen
Temperature offset
Temperature sensitivity
TST Temperature stabilization time
T_ADC_res Temperature ADC resolution
Top Operating temperature range
-15
256
16
+15
500
°C
LSB/°C
µs bit
°C -40 +85
1. Min/Max values are based on characterization results at 3σ on a limited number of samples, not tested in production and not guaranteed.
2. Typical specifications are not guaranteed.
3. When the accelerometer is in low-power mode and the gyroscope part is turned off, the TODR value is equal to the accelerometer ODR.
4. The output of the temperature sensor is 0 LSB (typ.) at 25 °C.
5. Time from power ON to valid data based on characterization data.
DS13892 - Rev 2 page 11/107
4.4
4.4.1
LSM6DSO16IS
Communication interface characteristics
Communication interface characteristics
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top. @ Vdd_IO = 1.8 V, T = 25 °C unless otherwise noted.
Table 5. SPI slave timing values
Symbol Parameter
Min
Typ Max
Unit f c(SPC) t c(SPC) t high(SPC) t low(SPC)
SPI clock frequency
SPI clock period
SPI clock high 45
10
100
MHz t t su(CS) h(CS) t su(SI) t h(SI) t v(SO) t dis(SO)
C load
SPI clock low
CS setup time (mode 3)
CS setup time (mode 0)
CS hold time (mode 3)
CS hold time (mode 0)
SDI input setup time
SDI input hold time
SDO valid output time
SDO output disable time
Bus capacitance
45
5
20
20
20
5
15
15 25
50
100 ns pF
1. Values are evaluated at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production
Figure 4. SPI slave timing in mode 0
CS t su(CS) t high(SPC) t c(SPC) t h(CS)
SPC
SDI
SDO t su(SI) t h(SI)
MSB IN t low(SPC) t v(SO)
MSB OUT
LSB IN
LSB OUT t dis(SO)
DS13892 - Rev 2 page 12/107
Note:
LSM6DSO16IS
Communication interface characteristics
Figure 5. SPI slave timing in mode 3
CS t su(CS) t high(SPC) t c(SPC)
SPC
SDI t su(SI) t h(SI)
MSB IN t low(SPC) t v(SO)
MSB OUT SDO
Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both input and output ports.
LSB IN
LSB OUT t dis(SO)
DS13892 - Rev 2 page 13/107
4.4.2
Note:
LSM6DSO16IS
Communication interface characteristics
I²C - inter-IC control interface
Subject to general operating conditions for Vdd and Top.
Table 6. I²C slave timing values
Symbol f
(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t h(ST) t su(SR) t su(SP) t w(SP:SR)
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
Parameter
START/REPEATED START condition hold time
REPEATED START condition setup time
STOP condition setup time
Bus free time between STOP and START condition
Min
0
1.3
0.6
100
0
0.6
0.6
0.6
1.3
Max
400
0.9
Min
0
0.5
0.26
50
0
0.26
0.26
0.26
0.5
Max
1000
Data valid time
Data valid acknowledge time
0.9
0.9
0.45
0.45
C
B
Capacitive load for each bus line 400 550
1. Data based on standard I²C protocol requirement, not tested in production.
2. Data for I²C fast mode and I²C fast mode plus have been validated by characterization, not tested in production.
Unit kHz
µs ns
µs pF
Figure 6. I²C slave timing diagram
SDA
START t su(SR) t w(SP:SR)
REPEATED
START
START t su (SDA) t h(SDA) t su(SP)
STOP
SCL t h(ST) t w(SCLL) t w(SCLH)
Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both ports.
DS13892 - Rev 2 page 14/107
4.5
Note:
LSM6DSO16IS
Absolute maximum ratings
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Symbol
Vdd
T
STG
Sg
ESD
Vin
Table 7. Absolute maximum ratings
Ratings
Supply voltage
Storage temperature range
Acceleration g for 0.2 ms
Electrostatic discharge protection (HBM)
Input voltage on any control pin
(including CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)
Maximum value
-0.3 to 4.8
-40 to +125
10,000
2
-0.3 to Vdd_IO +0.3
Unit
V
°C g kV
V
Supply voltage on any pin should never exceed 4.8 V.
This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.
DS13892 - Rev 2 page 15/107
4.6
4.6.1
4.6.2
LSM6DSO16IS
Terminology
Terminology
Sensitivity
Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device.
Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and over time. The sensitivity tolerance describes the range of sensitivities of a large
number of sensors (see Table 2 ).
An angular rate gyroscope is a device that produces a positive-going digital output for counterclockwise rotation around the axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time (see
).
Zero-g and zero-rate level
Linear acceleration zerog level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface measures 0 g on both the X-axis and Y-axis, whereas the Z-axis measures 1 g . Ideally, the output is in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as a two’s complement number). A deviation from the ideal value in this case is called zerog offset.
Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Linear acceleration zerog level change vs. temperature” in
. The zerog level tolerance (TyOff) describes the standard deviation of the range of zerog levels of a group of sensors.
Zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of precise
MEMS sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress.
This value changes very little over temperature and time (see
DS13892 - Rev 2 page 16/107
5
5.1
5.1.1
LSM6DSO16IS
Digital interfaces
Digital interfaces
I²C/SPI interface
The registers embedded inside the LSM6DSO16IS may be accessed through both the I²C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The device is compatible with SPI modes 0 and 3.
The serial interfaces are mapped onto the same pins. To select/exploit the I²C interface, the CS line must be tied high (that is, connected to Vdd_IO).
Pin name
CS
SCL/SPC
SDA/SDI/SDO
SDO/SA0
Table 8. Serial interface pin description
Pin description
Enables SPI
I²C/SPI mode selection (1: SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
I²C serial clock (SCL)
SPI serial port clock (SPC)
I²C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
SPI serial data output (SDO)
I²C less significant bit of the device address
I²C serial interface
The LSM6DSO16IS I²C is a bus slave. The I²C is employed to write the data to the registers, whose content can also be read back.
The relevant I²C terminology is provided in the table below.
Table 9. I²C terminology
Term Description
Transmitter The device which sends data to the bus
Receiver The device which receives data from the bus
Master
Slave
The device which initiates a transfer, generates clock signals and terminates a transfer
The device addressed by the master
There are two signals associated with the I²C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines must be connected to Vdd_IO through external pull-up resistors. When the bus is free, both the lines are high.
The I²C interface is implemented with fast mode (400 kHz) I²C standards as well as with fast mode plus
(1000 kHz).
In order to disable the I²C block, (I2C_disable) = 1 must be written in CTRL4_C (13h) .
DS13892 - Rev 2 page 17/107
LSM6DSO16IS
I²C/SPI interface
5.1.1.1
Master
Slave
I²C operation
The transaction on the bus is started through a start (ST) signal. A start condition is defined as a high to low transition on the data line while the SCL line is held high. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master.
The slave address (SAD) associated to the LSM6DSO16IS is 110101xb. The SDO/SA0 pin can be used to modify the less significant bit of the device address. If the SDO/SA0 pin is connected to the supply voltage, LSb is 1
(address 1101011b); else if the SDO/SA0 pin is connected to ground, the LSb value is 0 (address 1101010b). This solution permits to connect and address two different inertial modules to the same I²C bus.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.
The I²C embedded inside the LSM6DSO16IS behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been
(IF_INC).
The slave address is completed with a read/write bit. If the bit is 1 (read), a repeated start (SR) condition must be issued after the two subaddress bytes. If the bit is 0 (write) the master transmits to the slave with direction unchanged.
Table 10 explains how the SAD + read/write bit pattern is composed, listing all the possible
configurations.
Command
Read
Write
Read
Write
SAD[6:1]
110101
110101
110101
110101
Table 10. SAD + read/write patterns
SAD[0] = SA0
0
0
1
1
R/W
1
0
1
0
SAD+R/W
11010101 (D5h)
11010100 (D4h)
11010111 (D7h)
11010110 (D6h)
ST
Table 11. Transfer when master is writing one byte to slave
SAD + W SUB DATA
SAK SAK SAK
SP
Master
Slave
ST
Table 12. Transfer when master is writing multiple bytes to slave
SAD + W SUB DATA DATA
SAK SAK SAK SAK
ST
Table 13. Transfer when master is receiving (reading) one byte of data from slave
SAD + W SUB SR SAD + R NMAK
SAK SAK SAK DATA
SP
Master
Slave
SP
Master
Slave
ST
Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave
SAD+W SUB SR SAD+R MAK MAK
SAK SAK SAK DATA DATA DATA
NMAK SP
DS13892 - Rev 2 page 18/107
5.1.2
LSM6DSO16IS
I²C/SPI interface
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit (MSb) first. If a slave receiver doesn’t acknowledge the slave address (that is, it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. The master can then abort the transfer. A low to high transition on the
SDA line while the SCL line is high is defined as a stop condition. Each data transfer must be terminated by the generation of a stop (SP) condition.
In the presented communication format MAK is master acknowledge and NMAK is no master acknowledge.
SPI bus interface
The LSM6DSO16IS SPI is a bus slave. The SPI allows writing and reading the registers of the device.
The serial interface communicates to the application using 4 wires: CS , SPC , SDI and SDO .
Figure 7. Read and write protocol (in mode 3)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS enables the serial port and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are, respectively, the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC .
Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC . The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS .
bit 0 : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip drives SDO at the start of bit 8.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
bit is 0, the address used to read/write data remains the same for every block. When the
(IF_INC) bit is 1, the address used to read/write data is increased at every block.
The function and the behavior of SDI and SDO remain unchanged.
DS13892 - Rev 2 page 19/107
5.1.2.1
LSM6DSO16IS
I²C/SPI interface
SPI read
Figure 8. SPI read protocol (in mode 3)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
bit 16-...
: data DO(...-8). Further data in multiple byte reads.
Figure 9. Multiple byte SPI read protocol (2-byte example) (in mode 3)
CS
SPC
SDI
SDO
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11DO10 DO9 DO8
DS13892 - Rev 2 page 20/107
LSM6DSO16IS
I²C/SPI interface
5.1.2.2
SPI write
Figure 10. SPI write protocol (in mode 3)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
The SPI write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : WRITE bit. The value is 0.
bit 1 -7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written inside the device (MSb first).
bit 16-... : data DI(...-8). Further data in multiple byte writes.
Figure 11. Multiple byte SPI write protocol (2-byte example) (in mode 3)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
DS13892 - Rev 2 page 21/107
5.1.2.3
5.2
LSM6DSO16IS
Master I²C interface
SPI read in 3-wire mode
A 3-wire mode is entered by setting the
CTRL3_C (12h) (SIM) bit equal to 1 (SPI serial interface mode selection).
Figure 12. SPI read protocol in 3-wire mode (in mode 3)
CS
SPC
SDI/O
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI read command is performed with 16 clock pulses: bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
A multiple read command is also available in 3-wire mode.
Master I²C interface
If the LSM6DSO16IS is configured in mode 2, a master I²C line is available. The master serial interface is mapped in the following dedicated pins.
Pin name
MSCL
MSDA
MDRDY
Table 15. Master I²C pin details
I²C serial clock master
I²C serial data master
I²C master external synchronization signal
Pin description
DS13892 - Rev 2 page 22/107
6
6.1
6.2
6.3
LSM6DSO16IS
Functionality
Functionality
•
•
•
Operating modes
In the LSM6DSO16IS, the accelerometer and the gyroscope can be turned on/off independently of each other and are allowed to have different ODRs and power modes.
The LSM6DSO16IS has three operating modes available: only accelerometer active and gyroscope in power-down only gyroscope active and accelerometer in power-down both accelerometer and gyroscope sensors active with independent ODR
The accelerometer is activated from power-down by writing ODR_XL[3:0] in
CTRL1_XL (10h) while the gyroscope
is activated from power-down by writing ODR_G[3:0] in CTRL2_G (11h)
. For combo-mode the ODRs are totally independent.
Accelerometer power modes
In the LSM6DSO16IS, the accelerometer can be configured in three different operating modes: power-down, lowpower, and high-performance mode. The operating mode selected depends on the value of the XL_HM_MODE
. If XL_HM_MODE is set to 0, high-performance mode is valid for all ODRs (from 12.5 Hz up to 6667 Hz).
To enable low-power mode, the XL_HM_MODE bit has to be set to 1. Low-power mode is available for ODRs of
1.6, 12.5, 26, 52, 104, 208 Hz.
Gyroscope power modes
In the LSM6DSO16IS, the gyroscope can be configured in three different operating modes: power-down, lowpower, and high-performance mode. The operating mode selected depends on the value of the G_HM_MODE bit
. If G_HM_MODE is set to 0, high-performance mode is valid for all ODRs (from 12.5 Hz up to
6667 Hz).
To enable low-power mode, the G_HM_MODE bit has to be set to 1. Low-power mode is available for ODRs of
12.5, 26, 52, 104, 208 Hz.
DS13892 - Rev 2 page 23/107
6.4
6.4.1
6.4.2
6.5
LSM6DSO16IS
Block diagram of filters
Block diagram of filters
•
•
Block diagram of the accelerometer filters
In the LSM6DSO16IS, the filtering chain for the accelerometer part is composed of the following:
Analog filter (anti-aliasing)
Digital low-pass filter (LPF1)
Figure 13. Accelerometer filters
Analog
Anti-aliasing
LP Filter
Digital
LP Filter
LPF1
ADC
ODR_XL[3:0]
Block diagram of the gyroscope filter
In the LSM6DSO16IS, the filtering chain for the gyroscope part is composed of a digital low-pass filter (LPF1).
Figure 14. Gyroscope filter
Digital
LP Filter
LPF1
ADC
ODR_G[3:0]
Temperature sensor
The temperature is available in OUT_TEMP_L (20h), OUT_TEMP_H (21h)
stored as two's complement data.
Refer to
Table 4. Temperature sensor characteristics for the conversion factor.
DS13892 - Rev 2 page 24/107
7
7.1
LSM6DSO16IS
Application hints
Application hints
LSM6DSO16IS electrical connections in mode 1
Figure 15. LSM6DSO16IS electrical connections in mode 1
GND or Vdd_IO
SDO/SA0
MSDA
MSCL
INT1
1
4
14 12
5
TOP
VIEW
7
11 RES
(1)
RES
(1)
8
INT2
Vdd
C1
Vdd
GND
100 nF
C2
GND
100 nF
Vdd_IO
Mode 1
HOST
I 2 C
SPI (3/4-w)
/
LSM6DSO16IS
I 2 C configuration
Vdd_IO
R pu
SCL
SDA
Pull-up to be added
R pu
=10kOhm
R pu
1.
Leave pin electrically unconnected and soldered to PCB.
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic) should be placed as near as possible to the supply pin of the device (common design practice).
The functionality of the device and the measured acceleration/angular rate data is selectable and accessible through the SPI/I²C interface.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user through the SPI/I²C interface.
DS13892 - Rev 2 page 25/107
7.2
LSM6DSO16IS
LSM6DSO16IS electrical connections in mode 2
LSM6DSO16IS electrical connections in mode 2
Figure 16. LSM6DSO16IS electrical connections in mode 2
SDO/SA0
MSDA
MSCL
INT1
1
4
14 12
5
TOP
VIEW
7
11
8
RES
(1)
RES
(1)
Vdd
MDRDY/INT2
Vdd
C1
GND
100 nF
C2
GND
100 nF
Vdd_IO
Mode 2
HOST
I 2 C /
SPI (3/4-w)
LSM6DSO16IS
Master I 2 C
LSM6DSM sensors
I 2 C configuration
Vdd_IO
R pu
SCL
SDA
Pull-up to be added
R pu
=10kOhm
R pu
1.
Leave pin electrically unconnected and soldered to PCB.
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic) should be placed as near as possible to the supply pin of the device (common design practice).
The functionality of the device and the measured acceleration/angular rate data is selectable and accessible through the SPI/I²C primary interface.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user through the SPI/I²C primary interface.
DS13892 - Rev 2 page 26/107
Pin # Name
1
SDO
SA0
Mode 1 function
SPI 4-wire interface serial data output (SDO)
I²C least significant bit of the device address (SA0)
2
3
MSDA Connect to Vdd_IO or GND
MSCL Connect to Vdd_IO or GND
Table 16. Internal pin status
Mode 2 function
SPI 4-wire interface serial data output (SDO)
I²C least significant bit of the device address (SA0)
Pin status - mode 1 Pin status - mode 2
Default: input without pull-up
Pull-up is enabled if bit SDO_PU_EN = 1 in
.
Default: input without pull-up
Pull-up is enabled if bit SDO_PU_EN = 1 in
I²C serial data master (MSDA)
I²C serial clock master (MSCL)
Default: input without pull-up
Pull-up is enabled if bit SHUB_PU_EN = 1
in the sensor hub registers (see Note to enable pull-up).
Default: input without pull-up
Pull-up is enabled if bit SHUB_PU_EN = 1
in the sensor hub registers (see Note to enable pull-up).
Default: input with pull-down
Default: input without pull-up
Pull-up is enabled if bit SHUB_PU_EN = 1
in MASTER_CONFIG (14h) in the sensor
hub registers (see Note to enable pull-up).
Default: input without pull-up
Pull-up is enabled if bit SHUB_PU_EN = 1
in MASTER_CONFIG (14h) in the sensor
hub registers (see Note to enable pull-up).
Default: input with pull-down (1)
4
9
INT1
INT2
Programmable interrupt 1
5 Vdd_IO Power supply for I/O pins
6
7
8
GND
GND
Vdd
0 V supply
0 V supply
Power supply
Programmable interrupt 2 (INT2)
10
11
12
13
14
RES Leave unconnected
RES
Connect to Vdd_IO or leave unconnected
CS
I²C/SPI mode selection
(1:SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
SCL
SDA
I²C serial clock (SCL) / SPI serial port clock (SPC)
I²C serial data (SDA) / SPI serial data input (SDI) / 3-wire interface serial data output (SDO)
1. INT1 must be set to 0 or left unconnected during power-on.
Programmable interrupt 1
Power supply for I/O pins
0 V supply
0 V supply
Power supply
Programmable interrupt 2 (INT2) /
I²C master external synchronization signal (MDRDY)
Leave unconnected
Connect to Vdd_IO or leave unconnected
I²C/SPI mode selection
(1:SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
I²C serial clock (SCL) / SPI serial port clock (SPC)
I²C serial data (SDA) / SPI serial data input (SDI) / 3-wire interface serial data output (SDO)
Default: output forced to ground
Default: input with pull-up
Default: input without pull-up
Default: input without pull-up
Default: output forced to ground
Default: input with pull-up
Default: input without pull-up
Default: input without pull-up
Note:
Internal pull-up value is from 30 kΩ to 50 kΩ, depending on Vdd_IO.
The procedure to enable the pull-up on pins 2 and 3 is as follows:
1. From the primary I²C/SPI interface: write 40h in register at address 01h (enable access to the sensor hub registers)
2. From the primary I²C/SPI interface: write 08h in register at address 14h (enable the pull-up on pins 2 and 3)
3. From the primary I²C/SPI interface: write 00h in register at address 01h (disable access to the sensor hub registers)
8
LSM6DSO16IS
Register mapping
Register mapping
Name
FUNC_CFG_ACCESS
PIN_CTRL
RESERVED
DRDY_PULSED_REG
RESERVED
INT1_CTRL
INT2_CTRL
WHO_AM_I
CTRL1_XL
CTRL2_G
CTRL3_C
CTRL4_C
CTRL5_C
CTRL6_C
CTRL7_G
RESERVED
CTRL9_C
CTRL10_C
ISPU_INT_STATUS0_MAINPAGE
ISPU_INT_STATUS1_MAINPAGE
ISPU_INT_STATUS2_MAINPAGE
ISPU_INT_STATUS3_MAINPAGE
STATUS_REG
RESERVED
OUT_TEMP_L
OUT_TEMP_H
OUTX_L_G
OUTX_H_G
OUTY_L_G
OUTY_H_G
OUTZ_L_G
OUTZ_H_G
OUTX_L_A
OUTX_H_A
The table given below provides a list of the 8/16-bit registers embedded in the device and the corresponding addresses.
All these registers are accessible from the primary SPI/I²C interface only.
Table 17. Registers address map
Type
1F
20
21
22
23
18
19
1A
1B
1C
1D
1E
27
28
29
24
25
26
0D
0E
0F
10
11
Hex
01
02
03-0A
0B
0C
12
13
14
15
16
17
Register address
Binary
00000001
00000010
00001011
00011000
00011001
00011010
00011011
00011100
00011101
00011110
00001101
00001110
00001111
00010000
00010001
00010010
00010011
00010100
00010101
00010110
00100000
00100001
00100010
00100011
00100100
00100101
00100110
00100111
00101000
00101001
-
R
R
R
R
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
-
R/W
-
R/W
R/W
Default
00000000
00111111
00000000
00000000
00000000
00100010
00000000
00000000
00000100
00000000
00000000
00000000
00000000 output output output output output output output output output output
11100000
00000000 output output output output output
DS13892 - Rev 2 page 29/107
DS13892 - Rev 2
LSM6DSO16IS
Register mapping
Name
OUTY_L_A
OUTY_H_A
OUTZ_L_A
OUTZ_H_A
RESERVED
STATUS_MASTER_ MAINPAGE
RESERVED
TIMESTAMP0
TIMESTAMP1
TIMESTAMP2
TIMESTAMP3
RESERVED
MD1_CFG
MD2_CFG
INTERNAL_FREQ_FINE
ISPU_DUMMY_CFG_1_L
ISPU_DUMMY_CFG_1_H
ISPU_DUMMY_CFG_2_L
ISPU_DUMMY_CFG_2_H
ISPU_DUMMY_CFG_3_L
ISPU_DUMMY_CFG_3_H
ISPU_DUMMY_CFG_4_L
ISPU_DUMMY_CFG_4_H
Type
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R
R
-
R
-
R/W
R
R
-
R
R
R
5F
63
73
74
75
3A-3F
40
41
42
43
44-5D
5E
76
77
78
79
7A
Register address
Hex Binary
2A
2B
00101010
00101011
2C
2D
2E-38
39
00101100
00101101
00111001
01000000
01000001
01000010
01000011
01011110
01011111
01100011
01110011
01110100
01110101
01110110
01110111
01111000
01111001
01111010
Default output output output output output output output output output
00000000
00000000 output
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
Reserved registers must not be changed. Writing to those registers may cause permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
page 30/107
9
9.1
9.2
LSM6DSO16IS
Register description
Register description
The device contains a set of registers which are used to control its behavior and to retrieve linear acceleration, angular rate and temperature data. The register addresses, made up of 7 bits, are used to identify them and to write the data through the serial interface.
FUNC_CFG_ACCESS (01h)
Enable ISPU / sensor hub functions register (R/W)
Table 18. FUNC_CFG_ACCESS register
ISPU_REG
_ACCESS
SHUB_REG
_ACCESS
0
0
1. This bit must be set to 0 for the correct operation of the device.
0
0
SW_RESET
_ISPU
0
Table 19. FUNC_CFG_ACCESS register description
ISPU_REG_ACCESS Enables access to the ISPU interaction registers
. Default value: 0
SHUB_REG_ACCESS Enables access to the sensor hub (I²C master) registers
. Default value: 0
SW_RESET_ISPU
Software reset of ISPU core. Set the bit to 1 to activate the reset sequence and immediately write back to 0 (this bit is not automatically cleared). Default value: 0
1. Details regarding the ISPU interaction registers are available in
Section 10 ISPU interaction register mapping
and
Section 11 ISPU interaction register description .
Section 15 Sensor hub register description .
PIN_CTRL (02h)
SDO pin pull-up register (R/W)
Table 20. PIN_CTRL register
0
SDO_PU_EN 1
1
1. This bit must be set to 0 for the correct operation of the device.
2. This bit must be set to 1 for the correct operation of the device.
1
1
1
1
SDO_PU_EN
Table 21. PIN_CTRL register description
Enables pull-up on SDO pin.
(0: SDO pin pull-up disconnected (default); 1: SDO pin with pull-up)
DS13892 - Rev 2 page 31/107
9.3
9.4
LSM6DSO16IS
DRDY_PULSED_REG (0Bh)
DRDY_PULSED_REG (0Bh)
Pulsed data-ready mode register (R/W)
Table 22. DRDY_PULSED_REG register
DRDY_
PULSED
0
0
0
1. This bit must be set to 0 for the correct operation of the device.
0
0
0
0
DRDY_PULSED
Table 23. DRDY_PULSED_REG register description
Enables pulsed data-ready mode.
(0: Data-ready latched mode (returns to 0 only after an interface reading) (default);
1: Data-ready pulsed mode (the data-ready pulses are 75 µs long))
INT1_CTRL (0Dh)
INT1 pin control register (R/W)
Table 24. INT1_CTRL register
0
0
0
0
1. This bit must be set to 0 for the correct operation of the device.
0
INT1_ BOOT
INT1_
DRDY_G
INT1_
DRDY_XL
INT1_ BOOT
INT1_DRDY_G
INT1_DRDY_XL
Table 25. INT1_CTRL register description
Boot status available on the INT1 pin. Default value: 0
(0: disabled; 1: enabled)
Enables gyroscope data-ready interrupt on the INT1 pin. Default value: 0
(0: disabled; 1: enabled)
Enables accelerometer data-ready interrupt on the INT1 pin. Default value: 0
(0: disabled; 1: enabled)
DS13892 - Rev 2 page 32/107
9.5
9.6
LSM6DSO16IS
INT2_CTRL (0Eh)
INT2_CTRL (0Eh)
INT2 pin control register (R/W)
Table 26. INT2_CTRL register
INT2_SLEEP
_ISPU
0
0
0
1. This bit must be set to 0 for the correct operation of the device.
0
INT2_
DRDY_TEMP
INT2_
DRDY_G
INT2_
DRDY_XL
INT2_SLEEP_ISPU
INT2_DRDY_TEMP
INT2_DRDY_G
INT2_DRDY_XL
Table 27. INT2_CTRL register description
Enables ISPU sleep state signal on the INT2 pin. Default value: 0
(0: disabled; 1: enabled)
•
•
When enabled:
INT2 low: ISPU is running;
INT2 high: ISPU is in sleep state.
Enables temperature sensor data-ready interrupt on the INT2 pin. Default value: 0
(0: disabled; 1: enabled)
Enables gyroscope data-ready interrupt on the INT2 pin. Default value: 0
(0: disabled; 1: enabled)
Enables accelerometer data-ready interrupt on the INT2 pin. Default value: 0
(0: disabled; 1: enabled)
WHO_AM_I (0Fh)
WHO_AM_I register (R). This is a read-only register. Its value is fixed at 22h.
0 0 1
Table 28. WHO_AM_I register
0 0 0 1 0
DS13892 - Rev 2 page 33/107
9.7
LSM6DSO16IS
CTRL1_XL (10h)
CTRL1_XL (10h)
Control register 1 (R/W)
Table 29. CTRL1_XL register
ODR_XL3 ODR_XL2 ODR_XL1 ODR_XL0
1. This bit must be set to 0 for the correct operation of the device.
FS1_XL FS0_XL
ODR_XL[3:0]
FS[1:0]_XL
Table 30. CTRL1_XL register description
Accelerometer ODR selection (see
).
Accelerometer full-scale selection (see
0
0
1
1
1
1
0
0
1
0
0
0
0
1
0
0
0
1
0
0
1
1
0
0
0
0
0
0
1
1
1 x
1
0
0
1
0
1
0
1
0
1
0
1
1 x
0
1
1
1
0
0
1
1
0
1
0
0
Table 31. Accelerometer ODR configuration setting
ODR_XL3 ODR_XL2 ODR_XL1 ODR_XL0
ODR selection [Hz] when
XL_HM_MODE = 1 in
Power-down
1.6 Hz (low power)
12.5 Hz (low power)
26 Hz (low power)
52 Hz (low power)
104 Hz (low power)
208 Hz (low power)
416 Hz (high performance)
833 Hz (high performance)
1667 Hz (high performance)
3333 Hz (high performance)
6667 Hz (high performance)
Reserved
Reserved
ODR selection [Hz] when
Power-down
12.5 Hz (high performance)
12.5 Hz (high performance)
26 Hz (high performance)
52 Hz (high performance)
104 Hz (high performance)
208 Hz (high performance)
416 Hz (high performance)
833 Hz (high performance)
1667 Hz (high performance)
3333 Hz (high performance)
6667 Hz (high performance)
Reserved
Reserved
Table 32. Accelerometer full-scale selection
FS[1:0]_XL
00 (default)
01
10
11
Full scale
±2 g
±16 g
±4 g
±8 g
DS13892 - Rev 2 page 34/107
9.8
LSM6DSO16IS
CTRL2_G (11h)
CTRL2_G (11h)
Control register 2 (R/W)
Table 33. CTRL2_G register
ODR_G3 ODR_G2 ODR_G1 ODR_G0
1. This bit must be set to 0 for the correct operation of the device.
FS1_G
ODR_G[3:0]
FS[1:0]_G
FS_125
Table 34. CTRL2_G register description
Gyroscope output data rate selection. Default value: 0000
Gyroscope chain full-scale selection. Default value: 00
(00: ±250 dps;
01: ±500 dps;
10: ±1000 dps;
11: ±2000 dps)
Gyroscope chain full-scale selection for ±125 dps. Default value: 0
(0: FS selected through bits FS[1:0]_G;
1: FS set to ±125 dps)
FS0_G FS_125
Table 35. Gyroscope ODR configuration setting
ODR_G3 ODR_G2 ODR_G1 ODR_G0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1 x
0
1
0
1
0
1
0
1
0
1
0
1 x
ODR selection [Hz] when
G_HM_MODE = 1 in
Power-down
12.5 Hz (low power)
26 Hz (low power)
52 Hz (low power)
104 Hz (low power)
208 Hz (low power)
416 Hz (high performance)
833 Hz (high performance)
1667 Hz (high performance)
3333 Hz (high performance)
6667 Hz (high performance)
Reserved
Reserved
ODR selection [Hz] when
G_HM_MODE = 0 in CTRL7_G (16h)
Power-down
12.5 Hz (high performance)
26 Hz (high performance)
52 Hz (high performance)
104 Hz (high performance)
208 Hz (high performance)
416 Hz (high performance)
833 Hz (high performance)
1667 Hz (high performance)
3333 Hz (high performance)
6667 Hz (high performance)
Reserved
Reserved
DS13892 - Rev 2 page 35/107
9.9
9.10
LSM6DSO16IS
CTRL3_C (12h)
CTRL3_C (12h)
Control register 3 (R/W)
Table 36. CTRL3_C register
BOOT BDU H_LACTIVE PP_OD
1. This bit must be set to 0 for the correct operation of the device.
SIM IF_INC 0
SW_RESET
Table 37. CTRL3_C register description
BOOT
BDU
Reboot memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
Block data update. Default value: 0
(0: continuous update;
1: output registers are not updated until MSB and LSB have been read)
H_LACTIVE
Interrupt activation level. Default value: 0
(0: interrupt output pins active-high; 1: interrupt output pins active-low)
PP_OD
SIM
Push-pull/open-drain selection on INT1 and INT2 pins. This bit must be set to 0 when H_LACTIVE is set to 1.
Default value: 0
(0: push-pull mode; 1: open-drain mode)
SPI serial interface mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface)
IF_INC
Register address automatically incremented during a multiple byte access with a serial interface (I²C or SPI).
Default value: 1
(0: disabled; 1: enabled)
SW_RESET
Software reset. Default value: 0
(0: normal mode; 1: reset device)
This bit is automatically cleared.
CTRL4_C (13h)
Control register 4 (R/W)
Table 38. CTRL4_C register
0
SLEEP_G
INT2_on
_INT1
0
1. This bit must be set to 0 for the correct operation of the device.
0
I2C_disable
SLEEP_G
INT2_on_INT1
I2C_disable
Table 39. CTRL4_C register description
Enables gyroscope sleep mode. Default value: 0
(0: disabled; 1: enabled)
Enables all interrupt signals available on INT1 pin. Default value: 0
(0: interrupt signals divided between INT1 and INT2 pins;
1: all interrupt signals in logic or on INT1 pin)
Disables I²C interface. Default value: 0
(0: SPI and I²C interfaces enabled (default); 1: I²C interface disabled)
0
0
DS13892 - Rev 2 page 36/107
9.11
9.12
LSM6DSO16IS
CTRL5_C (14h)
CTRL5_C (14h)
Control register 5 (R/W)
Table 40. CTRL5_C register
0
0
0
0
1. This bit must be set to 0 for the correct operation of the device.
ST1_G ST0_G
ST[1:0]_G
ST[1:0]_XL
Table 41. CTRL5_C register description
Enables angular rate sensor self-test. Default value: 00
(00: Self-test disabled; Other: refer to Table 42
)
Enables linear acceleration sensor self-test. Default value: 00
(00: Self-test disabled; Other: refer to Table 43
)
ST1_G
1
1
0
0
Table 42. Angular rate sensor self-test mode selection
ST0_G
0
1
0
1
Normal mode
Positive sign self-test
Not allowed
Negative sign self-test
Self-test mode
ST1_XL
ST1_XL
0
0
1
1
CTRL6_C (15h)
Control register 6 (R/W)
Table 43. Linear acceleration sensor self-test mode selection
ST0_XL
0
1
0
1
Normal mode
Positive sign self-test
Negative sign self-test
Not allowed
Self-test mode
Table 44. CTRL6_C register
0
0
0
XL_
HM_MODE
1. This bit must be set to 0 for the correct operation of the device.
0
0
0
XL_HM_MODE
Table 45. CTRL6_C register description
Disables high-performance operating mode for the accelerometer. Default value: 0
(0: high-performance operating mode enabled;
1: high-performance operating mode disabled)
ST0_XL
0
DS13892 - Rev 2 page 37/107
9.13
9.14
LSM6DSO16IS
CTRL7_G (16h)
CTRL7_G (16h)
Control register 7 (R/W)
Table 46. CTRL7_G register
G_
HM_MODE
0
0
0
1. This bit must be set to 0 for the correct operation of the device.
0
0
0
0
G_HM_MODE
CTRL9_C (18h)
Control register 9 (R/W)
Table 47. CTRL7_G register description
Disables high-performance operating mode for gyroscope. Default: 0
(0: high-performance operating mode enabled;
1: high-performance operating mode disabled)
Table 48. CTRL9_C register
ISPU_
RATE_3
ISPU_
RATE_2
ISPU_
RATE_1
ISPU_
RATE_0
1. This bit must be set to 0 for the correct operation of the device.
0
0
ISPU_
BDU_1
ISPU_
BDU_0
Table 49. CTRL9_C register description
ISPU IRQ rate selection.
(0000: power-down (default);
0001: 12.5 Hz;
ISPU_RATE_[3:0]
0010: 26 Hz;
0011: 52 Hz;
0100: 104 Hz;
0101: 208 Hz;
0110: 416 Hz;
0111: 833 Hz;
1000: 1667 Hz;
1001: 3333 Hz;
1010: 6667 Hz;
1011-1111: reserved)
ISPU_BDU_[1:0]
Block data update (BDU) for ISPU output registers. Based on output data format, different configurations must be used, see
ISPU_BDU_[1:0]
00
01
10
11
Table 50. Configurations for block data update
ISPU_DOUT_00_L to ISPU_DOUT_15_H
BDU disabled
BDU on 2 bytes (16 outputs)
BDU on 2 bytes (16 outputs)
BDU on 4 bytes (8 outputs)
ISPU_DOUT_16_L to ISPU_DOUT_31_H
BDU disabled
BDU on 4 bytes (8 outputs)
BDU on 2 bytes (16 outputs)
BDU on 4 bytes (8 outputs)
DS13892 - Rev 2 page 38/107
9.15
9.16
LSM6DSO16IS
CTRL10_C (19h)
CTRL10_C (19h)
Control register 10 (R/W)
Table 51. CTRL10_C register
0
0
TIMESTAMP
_EN
0
1. This bit must be set to 0 for the correct operation of the device.
0
ISPU_
CLK_SEL
0
0
Table 52. CTRL10_C register description
TIMESTAMP_EN
Enables timestamp counter. Default value: 0
(0: disabled; 1: enabled)
The counter is readable in TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and
ISPU_CLK_SEL
Selects the ISPU core clock frequency:
0: core clock frequency set to 5 MHz (default)
1: core clock frequency set to 10 MHz
ISPU_INT_STATUS0_MAINPAGE (1Ah), ISPU_INT_STATUS1_MAINPAGE (1Bh),
ISPU_INT_STATUS2_MAINPAGE (1Ch), ISPU_INT_STATUS3_MAINPAGE (1Dh)
ISPU interrupt status registers (R)
IA_
ISPU_7
IA_
ISPU_6
Table 53. ISPU_INT_STATUS0_MAINPAGE output register
IA_
ISPU_5
IA_
ISPU_4
IA_
ISPU_3
IA_
ISPU_2
IA_
ISPU_1
IA_
ISPU_0
IA_
ISPU_15
IA_
ISPU_23
0
IA_ISPU_[29:0]
IA_
ISPU_14
Table 54. ISPU_INT_STATUS1_MAINPAGE output register
IA_
ISPU_13
IA_
ISPU_12
IA_
ISPU_11
IA_
ISPU_10
IA_
ISPU_9
IA_
ISPU_22
Table 55. ISPU_INT_STATUS2_MAINPAGE output register
IA_
ISPU_21
IA_
ISPU_20
IA_
ISPU_19
IA_
ISPU_18
IA_
ISPU_17
0
Table 56. ISPU_INT_STATUS3_MAINPAGE output register
IA_
ISPU_29
IA_
ISPU_28
IA_
ISPU_27
IA_
ISPU_26
IA_
ISPU_25
Table 57. ISPU_INT_STATUS_MAINPAGE output register description
Generic interrupt flags from ISPU.
IA_
ISPU_8
IA_
ISPU_16
IA_
ISPU_24
DS13892 - Rev 2 page 39/107
9.17
9.18
LSM6DSO16IS
STATUS_REG (1Eh)
STATUS_REG (1Eh)
Status register (R)
TIMESTAMP_
ENDCOUNT
Temp[15:0]
0 0
Table 58. STATUS_REG register
0 0 TDA GDA XLDA
TIMESTAMP_ENDCOUNT
TDA
GDA
XLDA
Table 59. STATUS_REG register description
Alerts timestamp overflow within 6.4 ms.
Temperature new data available. Default: 0
(0: no set of data is available at temperature sensor output;
1: a new set of data is available at temperature sensor output)
Gyroscope new data available. Default value: 0
(0: no set of data available at gyroscope output;
1: a new set of data is available at gyroscope output)
Accelerometer new data available. Default value: 0
(0: no set of data available at accelerometer output;
1: a new set of data is available at accelerometer output)
OUT_TEMP_L (20h), OUT_TEMP_H (21h)
Temperature data output register (R). The value is expressed as a 16-bit word in two’s complement.
Temp7 Temp6 Temp5
Table 60. OUT_TEMP_L register
Temp4 Temp3 Temp2 Temp1 Temp0
Temp15 Temp14 Temp13
Table 61. OUT_TEMP_H register
Temp12 Temp11 Temp10 Temp9 Temp8
Table 62. OUT_TEMP register description
Temperature sensor output data.
The value is expressed as two’s complement sign extended on the MSB.
DS13892 - Rev 2 page 40/107
9.19
9.20
LSM6DSO16IS
OUTX_L_G (22h) and OUTX_H_G (23h)
OUTX_L_G (22h) and OUTX_H_G (23h)
Angular rate sensor pitch axis (X) angular rate output register (R). The value is expressed as a 16-bit word in two’s complement.
Data are according to the full-scale and ODR settings (
) of the gyroscope.
D7 D6 D5
Table 63. OUTX_L_G register
D4 D3 D2 D1 D0
D15 D14 D13
Table 64. OUTX_H_G register
D12 D11 D10 D9 D8
D[15:0]
Table 65. OUTX_H_G register description
Gyroscope chain pitch axis (X) angular rate output value.
OUTY_L_G (24h) and OUTY_H_G (25h)
Angular rate sensor roll axis (Y) angular rate output register (R). The value is expressed as a 16-bit word in two’s complement.
Data are according to the full-scale and ODR settings (
) of the gyroscope.
D7 D6 D5
Table 66. OUTY_L_G register
D4 D3 D2 D1 D0
D15
D[15:0]
D14 D13
Table 67. OUTY_H_G register
D12 D11 D10
Table 68. OUTY_H_G register description
Gyroscope chain roll axis (Y) angular rate output value.
D9 D8
DS13892 - Rev 2 page 41/107
9.21
LSM6DSO16IS
OUTZ_L_G (26h) and OUTZ_H_G (27h)
OUTZ_L_G (26h) and OUTZ_H_G (27h)
Angular rate sensor yaw axis (Z) angular rate output register (R). The value is expressed as a 16-bit word in two’s complement.
Data are according to the full-scale and ODR settings (
) of the gyroscope.
D7 D6 D5
Table 69. OUTZ_L_G register
D4 D3 D2 D1 D0
D15
D[15:0]
D14 D13
Table 70. OUTZ_H_G register
D12 D11 D10
Table 71. OUTZ_H_G register description
Gyroscope chain yaw axis (Z) angular rate output value.
D9 D8
DS13892 - Rev 2 page 42/107
9.22
9.23
LSM6DSO16IS
OUTX_L_A (28h) and OUTX_H_A (29h)
OUTX_L_A (28h) and OUTX_H_A (29h)
Linear acceleration sensor X-axis output register (R). The value is expressed as a 16-bit word in two’s complement.
Data are according to the full-scale and ODR settings (
) of the accelerometer.
D7 D6 D5
Table 72. OUTX_L_A register
D4 D3 D2 D1 D0
D15 D14 D13
Table 73. OUTX_H_A register
D12 D11 D10 D9 D8
D[15:0]
Table 74. OUTX_H_A register description
Accelerometer chain X-axis linear acceleration output value.
OUTY_L_A (2Ah) and OUTY_H_A (2Bh)
Linear acceleration sensor Y-axis output register (R). The value is expressed as a 16-bit word in two’s complement.
Data are according to the full-scale and ODR settings (
) of the accelerometer.
D7 D6 D5
Table 75. OUTY_L_A register
D4 D3 D2 D1 D0
D15
D[15:0]
D14 D13
Table 76. OUTY_H_A register
D12 D11 D10
Table 77. OUTY_H_A register description
Accelerometer chain Y-axis linear acceleration output value.
D9 D8
DS13892 - Rev 2 page 43/107
9.24
LSM6DSO16IS
OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh)
OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh)
Linear acceleration sensor Z-axis output register (R). The value is expressed as a 16-bit word in two’s complement.
Data are according to the full-scale and ODR settings (
) of the accelerometer.
D7 D6 D5
Table 78. OUTZ_L_A register
D4 D3 D2 D1 D0
D15
D[15:0]
D14 D13
Table 79. OUTZ_H_A register
D12 D11 D10
Table 80. OUTZ_H_A register description
Accelerometer chain Z-axis linear acceleration output value.
D9 D8
DS13892 - Rev 2 page 44/107
9.25
9.26
LSM6DSO16IS
STATUS_MASTER_MAINPAGE (39h)
STATUS_MASTER_MAINPAGE (39h)
Sensor hub status register (R)
WR_ONCE_
DONE
SLAVE3_
NACK
Table 81. STATUS_MASTER_MAINPAGE register
SLAVE2_
NACK
SLAVE1_
NACK
SLAVE0_
NACK
0
D[31:0]
0
SENS_HUB_
ENDOP
Table 82. STATUS_MASTER_MAINPAGE register description
WR_ONCE_DONE
When the bit WRITE_ONCE in
is configured as 1, this bit is set to 1 when the write operation on slave 0 has been performed and completed. Default value: 0
This bit is set to 1 if Not acknowledge occurs on slave 3 communication. Default value: 0 SLAVE3_NACK
SLAVE2_NACK
SLAVE1_NACK
SLAVE0_NACK
This bit is set to 1 if Not acknowledge occurs on slave 2 communication. Default value: 0
This bit is set to 1 if Not acknowledge occurs on slave 1 communication. Default value: 0
This bit is set to 1 if Not acknowledge occurs on slave 0 communication. Default value: 0
SENS_HUB_ENDOP
Sensor hub communication status. Default value: 0
(0: sensor hub communication not concluded;
1: sensor hub communication concluded)
TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3
(43h)
Timestamp first data output register (R). The value is expressed as a 32-bit word and the bit resolution is 25 µs.
These registers are also accessible from ISPU at address 6940h, 6941h, 6942h, 6943h (R).
D7 D6 D5
Table 83. TIMESTAMP0 output register
D4 D3 D2 D1 D0
D15
D23
D31
D14
D22
D30
Table 84. TIMESTAMP1 output register
D13 D12 D11 D10
Table 85. TIMESTAMP2 output register
D21 D20 D19 D18
Table 86. TIMESTAMP3 output register
D29 D28 D27 D26
D9
D17
D25
D8
D16
D24
Table 87. TIMESTAMP output register description
Timestamp output registers: 1LSB = 25 µs.
DS13892 - Rev 2 page 45/107
9.27
9.28
9.29
LSM6DSO16IS
MD1_CFG (5Eh)
MD1_CFG (5Eh)
Functions routing to INT1 pin register (R/W)
Table 88. MD1_CFG register
0
0
0
0
0
1. This bit must be set to 0 for the correct operation of the device.
INT1_ISPU
INT1_SHUB
0
Table 89. MD1_CFG register description
Routing ISPU event to INT1. Default value: 0
(0: routing ISPU event to INT1 disabled;
1: routing ISPU event to INT1 enabled)
Routing sensor hub communication concluded event to INT1. Default value: 0
(0: routing sensor hub communication concluded event to INT1 disabled;
1: routing sensor hub communication concluded event to INT1 enabled)
INT1_
ISPU
MD2_CFG (5Fh)
Functions routing to INT2 pin register (R/W)
Table 90. MD2_CFG register
0
0
0
0
0
1. This bit must be set to 0 for the correct operation of the device.
0
INT2_
ISPU
INT2_ISPU
Table 91. MD2_CFG register description
Routing ISPU event to INT2. Default value: 0
(0: routing ISPU event to INT2 disabled;
1: routing ISPU event to INT2 enabled)
Enables routing the alert for timestamp overflow within 6.4 ms to the INT2 pin.
INT2_TIMESTAMP
INTERNAL_FREQ_FINE (63h)
Internal frequency register (R)
FREQ_
FINE7
FREQ_
FINE6
Table 92. INTERNAL_FREQ_FINE register
FREQ_
FINE5
FREQ_
FINE4
FREQ_
FINE3
FREQ_
FINE2
FREQ_
FINE1
INT1_SHUB
INT2_
TIMESTAMP
FREQ_
FINE0
Table 93. INTERNAL_FREQ_FINE register description
FREQ_FINE[7:0]
Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.15%.
8-bit format, two's complement.
DS13892 - Rev 2 page 46/107
9.30
9.31
LSM6DSO16IS
ISPU_DUMMY_CFG_1_L (73h) and ISPU_DUMMY_CFG_1_H (74h)
ISPU_DUMMY_CFG_1_L (73h) and ISPU_DUMMY_CFG_1_H (74h)
General-purpose input configuration register for ISPU (R/W). This register is also accessible from ISPU at address 6974h, 6975h (R).
ISPU_DUMMY
_CFG_1_7
ISPU_DUMMY
_CFG_1_6
Table 94. ISPU_DUMMY_CFG_1_L register
ISPU_DUMMY
_CFG_1_5
ISPU_DUMMY
_CFG_1_4
ISPU_DUMMY
_CFG_1_3
ISPU_DUMMY
_CFG_1_2
ISPU_DUMMY
_CFG_1_1
ISPU_DUMMY
_CFG_1_0
ISPU_DUMMY
_CFG_1_15
ISPU_DUMMY
_CFG_1_14
Table 95. ISPU_DUMMY_CFG_1_H register
ISPU_DUMMY
_CFG_1_13
ISPU_DUMMY
_CFG_1_12
ISPU_DUMMY
_CFG_1_11
ISPU_DUMMY
_CFG_1_10
ISPU_DUMMY
_CFG_1_9
ISPU_DUMMY
_CFG_1_8
ISPU_DUMMY_CFG_1_[15:0]
Table 96. ISPU_DUMMY_CFG_1 register description
Input configuration register 1 for ISPU.
ISPU_DUMMY_CFG_2_L (75h) and ISPU_DUMMY_CFG_2_H (76h)
General-purpose input configuration register for ISPU (R/W). This register is also accessible from ISPU at address 6976h, 6977h (R).
ISPU_DUMMY
_CFG_2_7
ISPU_DUMMY
_CFG_2_6
Table 97. ISPU_DUMMY_CFG_2_L register
ISPU_DUMMY
_CFG_2_5
ISPU_DUMMY
_CFG_2_4
ISPU_DUMMY
_CFG_2_3
ISPU_DUMMY
_CFG_2_2
ISPU_DUMMY
_CFG_2_1
ISPU_DUMMY
_CFG_2_0
ISPU_DUMMY
_CFG_2_15
ISPU_DUMMY
_CFG_2_14
Table 98. ISPU_DUMMY_CFG_2_H register
ISPU_DUMMY
_CFG_2_13
ISPU_DUMMY
_CFG_2_12
ISPU_DUMMY
_CFG_2_11
ISPU_DUMMY
_CFG_2_10
ISPU_DUMMY
_CFG_2_9
ISPU_DUMMY
_CFG_2_8
ISPU_DUMMY_CFG_2_[15:0]
Table 99. ISPU_DUMMY_CFG_2 register description
Input configuration register 2 for ISPU.
DS13892 - Rev 2 page 47/107
9.32
LSM6DSO16IS
ISPU_DUMMY_CFG_3_L (77h) and ISPU_DUMMY_CFG_3_H (78h)
ISPU_DUMMY_CFG_3_L (77h) and ISPU_DUMMY_CFG_3_H (78h)
General-purpose input configuration register for ISPU (R/W). This register is also accessible from ISPU at address 6978h, 6979h (R).
ISPU_DUMMY
_CFG_3_7
ISPU_DUMMY
_CFG_3_6
Table 100. ISPU_DUMMY_CFG_3_L register
ISPU_DUMMY
_CFG_3_5
ISPU_DUMMY
_CFG_3_4
ISPU_DUMMY
_CFG_3_3
ISPU_DUMMY
_CFG_3_2
ISPU_DUMMY
_CFG_3_1
ISPU_DUMMY
_CFG_3_0
ISPU_DUMMY
_CFG_3_15
ISPU_DUMMY
_CFG_3_14
Table 101. ISPU_DUMMY_CFG_3_H register
ISPU_DUMMY
_CFG_3_13
ISPU_DUMMY
_CFG_3_12
ISPU_DUMMY
_CFG_3_11
ISPU_DUMMY
_CFG_3_10
ISPU_DUMMY
_CFG_3_9
ISPU_DUMMY
_CFG_3_8
ISPU_DUMMY_CFG_3_[15:0]
Table 102. ISPU_DUMMY_CFG_3 register description
Input configuration register 3 for ISPU.
DS13892 - Rev 2 page 48/107
9.33
LSM6DSO16IS
ISPU_DUMMY_CFG_4_L (79h) and ISPU_DUMMY_CFG_4_H (7Ah)
ISPU_DUMMY_CFG_4_L (79h) and ISPU_DUMMY_CFG_4_H (7Ah)
General-purpose input configuration register for ISPU (R/W). This register is also accessible from ISPU at address 697Ah, 697Bh (R).
ISPU_DUMMY
_CFG_4_7
ISPU_DUMMY
_CFG_4_6
Table 103. ISPU_DUMMY_CFG_4_L register
ISPU_DUMMY
_CFG_4_5
ISPU_DUMMY
_CFG_4_4
ISPU_DUMMY
_CFG_4_3
ISPU_DUMMY
_CFG_4_2
ISPU_DUMMY
_CFG_4_1
ISPU_DUMMY
_CFG_4_0
ISPU_DUMMY
_CFG_4_15
ISPU_DUMMY
_CFG_4_14
Table 104. ISPU_DUMMY_CFG_4_H register
ISPU_DUMMY
_CFG_4_13
ISPU_DUMMY
_CFG_4_12
ISPU_DUMMY
_CFG_4_11
ISPU_DUMMY
_CFG_4_10
ISPU_DUMMY
_CFG_4_9
ISPU_DUMMY
_CFG_4_8
ISPU_DUMMY_CFG_4_[15:0]
Table 105. ISPU_DUMMY_CFG_4 register description
Input configuration register 4 for ISPU.
DS13892 - Rev 2 page 49/107
10
LSM6DSO16IS
ISPU interaction register mapping
ISPU interaction register mapping
IF address (hex)
14-15
16-17
18-19
1A-1B
1C-1D
1E-1F
20-21
22-23
24-25
26-27
28-29
2A-2B
2C-2D
2E-2F
02
04
08
09-0A
0B
0C-0D
0E-0F
10-11
12-13
30-31
32-33
34-35
36-37
38-39
3A-3B
3C-3D
3E-3F
40-41
The table given below provides a list of the registers for the ISPU functions available in the device and the corresponding addresses.
accessible over the I²C/SPI interface with the address indicated in the first column (IF address) of the table below.
These registers are also accessible from ISPU through the address indicated in the second column (ISPU address), regardless of the ISPU_REG_ACCESS bit configuration.
Table 106. Register map - ISPU interaction registers
ISPU address (hex)
6802
6804
-
-
-
680C-680D
680E-680F
6810-6811
6812-6813
6814-6815
6816-6817
6818-6819
681A-681B
681C-681C
681E-681F
6820-6821
6822-6823
6824-6825
6826-6827
6828-6829
682A-682B
682C-682D
682E-682F
6830-6831
6832-6833
6834-6835
6836-6837
6838-6839
683A-683B
683C-683D
683E-683F
6840-6841
Bytes
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
2
2
2
1
2
1
1
2
2
2
2
2
2
2
2
2
Name
ISPU_CONFIG
ISPU_STATUS
ISPU_MEM_SEL
ISPU_MEM_ADDR
ISPU_MEM_DATA
ISPU_IF2S_FLAG
ISPU_S2IF_FLAG
ISPU_DOUT_00
ISPU_DOUT_01
ISPU_DOUT_02
ISPU_DOUT_03
ISPU_DOUT_04
ISPU_DOUT_05
ISPU_DOUT_06
ISPU_DOUT_07
ISPU_DOUT_08
ISPU_DOUT_09
ISPU_DOUT_10
ISPU_DOUT_11
ISPU_DOUT_12
ISPU_DOUT_13
ISPU_DOUT_14
ISPU_DOUT_15
ISPU_DOUT_16
ISPU_DOUT_17
ISPU_DOUT_18
ISPU_DOUT_19
ISPU_DOUT_20
ISPU_DOUT_21
ISPU_DOUT_22
ISPU_DOUT_23
ISPU_DOUT_24
IF access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R
R/W
R/W
R/W
R/W, set only
R/W, clear only
R
R
R
R
R
R
R
R
R
R
R
ISPU access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
No
No
No
R/W, clear only
R/W, set only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DS13892 - Rev 2 page 50/107
DS13892 - Rev 2
LSM6DSO16IS
ISPU interaction register mapping
IF address (hex)
42-43
44-45
46-47
48-49
4A-4B
4C-4D
4E-4F
50-53
54-57
58-5B
70-73
ISPU address (hex)
6842-6843
6844-6845
6846-6847
6848-6849
684A-684B
684C-684D
684E-684F
6850-6853
6854-6857
6858-685B
6870-6873
2
4
4
4
4
Bytes
2
2
2
2
2
2
Name
ISPU_DOUT_25
ISPU_DOUT_26
ISPU_DOUT_27
ISPU_DOUT_28
ISPU_DOUT_29
ISPU_DOUT_30
ISPU_DOUT_31
ISPU_INT1_CTRL
ISPU_INT2_CTRL
ISPU_INT_STATUS
ISPU_ALGO
IF access
R
R
R
R
R
R
R
R/W
R/W
R
R/W
ISPU address (hex) Bytes
6940-6941 2
6942-6943
6974-6975
2
2
6976-6977
6978-6979
697A-697B
2
2
2
Table 107. Register map - ISPU to external resources
Name
TIMESTAMP0 (40h), TIMESTAMP1 (41h)
TIMESTAMP2 (42h), TIMESTAMP3 (43h)
ISPU_DUMMY_CFG_1_L (73h) and ISPU_DUMMY_CFG_1_H (74h)
ISPU_DUMMY_CFG_2_L (75h) and ISPU_DUMMY_CFG_2_H (76h)
ISPU_DUMMY_CFG_3_L (77h) and ISPU_DUMMY_CFG_3_H (78h)
ISPU_DUMMY_CFG_4_L (79h) and ISPU_DUMMY_CFG_4_H (7Ah)
ISPU access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R, clear only
ISPU access
R
R
R
R
R
R
Reserved registers must not be changed. Writing to those registers may cause permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
page 51/107
11
11.1
11.2
LSM6DSO16IS
ISPU interaction register description
ISPU interaction register description
ISPU_CONFIG (02h)
ISPU configuration register (R/W). This register is also accessible from ISPU at address 6802h (R).
Table 108. ISPU_CONFIG register
0
0
0
LATCHED
1. This bit must be set to 0 for the correct operation of the device.
0
0
LATCHED
CLK_DIS
ISPU_RST_N
Table 109. ISPU_CONFIG register description
Configures the interrupt generation.
(0: interrupt pulsed;
1: interrupt latched)
When active, stops the clock of ISPU.
ISPU active-low reset.
CLK_DIS
ISPU_
RST_N
ISPU_STATUS (04h)
ISPU status register (R). This register is also accessible from ISPU at address 6804h (R/W).
Table 110. ISPU_STATUS register
0
0
0
0
1. This bit must be set to 0 for the correct operation of the device.
0
BOOT_END
BOOT_END
Table 111. ISPU_STATUS register description
End of ISPU boot procedure.
0
0
DS13892 - Rev 2 page 52/107
11.3
11.4
11.5
LSM6DSO16IS
ISPU_MEM_SEL (08h)
ISPU_MEM_SEL (08h)
ISPU memory selection register (R/W)
Table 112. ISPU_MEM_SEL register
0
READ_
MEM_EN
0
0
1. This bit must be set to 0 for the correct operation of the device.
0
0
0
MEM_SEL
READ_MEM_EN
MEM_SEL
Table 113. ISPU_MEM_SEL register description
Enables reading from program or data memories. Default value: 0
(0: disabled; 1: enabled)
Selects the memory to be accessed. Default value: 0
(0: data RAM memory is selected; 1: program RAM memory is selected)
ISPU_MEM_ADDR1 (09h), ISPU_MEM_ADDR0 (0Ah)
ISPU memory address register (R/W)
Table 114. ISPU_MEM_ADDR1 register
MEM_ADDR_15 MEM_ADDR_14 MEM_ADDR_13 MEM_ADDR_12 MEM_ADDR_11 MEM_ADDR_10 MEM_ADDR_9 MEM_ADDR_8
MEM_ADDR_7 MEM_ADDR_6
Table 115. ISPU_MEM_ADDR0 register
MEM_ADDR_5 MEM_ADDR_4 MEM_ADDR_3 MEM_ADDR_2 MEM_ADDR_1 MEM_ADDR_0
MEM_ADDR_[15:0]
Table 116. ISPU_MEM_ADDR register description
Memory address to be read/written.
ISPU_MEM_DATA (0Bh)
ISPU memory data register (R/W)
Table 117. ISPU_MEM_DATA register
MEM_DATA_7 MEM_DATA_6 MEM_DATA_5 MEM_DATA_4 MEM_DATA_3 MEM_DATA_2 MEM_DATA_1 MEM_DATA_0
MEM_DATA_[7:0]
Table 118. ISPU_MEM_DATA register description
Byte to write to memory in write transaction or data read from memory in read transaction.
DS13892 - Rev 2 page 53/107
11.6
11.7
LSM6DSO16IS
ISPU_IF2S_FLAG_L (0Ch), ISPU_IF2S_FLAG_H (0Dh)
ISPU_IF2S_FLAG_L (0Ch), ISPU_IF2S_FLAG_H (0Dh)
Interface to ISPU register (R/W, set only). This register is also accessible from ISPU at address 680Ch, 680Dh
(R/W, clear only).
IF2S_7 IF2S_6
Table 119. ISPU_IF2S_FLAG_L register
IF2S_5 IF2S_4 IF2S_3 IF2S_2 IF2S_1 IF2S_0
IF2S_15 IF2S_14
Table 120. ISPU_IF2S_FLAG_H register
IF2S_13 IF2S_12 IF2S_11 IF2S_10 IF2S_9 IF2S_8
IF2S_[15:0]
Table 121. ISPU_IF2S_FLAG register description
16-bit general purpose bits which can be set from the interface and cleared by ISPU.
ISPU_S2IF_FLAG_L (0Eh), ISPU_S2IF_FLAG_H (0Fh)
ISPU to interface register (R/W, clear only). This register is also accessible from ISPU at address 680Eh, 680Fh
(R/W, set only).
S2IF_7 S2IF_6
Table 122. ISPU_S2IF_FLAG_L register
S2IF_5 S2IF_4 S2IF_3 S2IF_2 S2IF_1 S2IF_0
S2IF_15
S2IF_[15:0]
S2IF_14
Table 123. ISPU_S2IF_FLAG_H register
S2IF_13 S2IF_12 S2IF_11 S2IF_10 S2IF_9
Table 124. ISPU_S2IF_FLAG register description
16-bit general purpose bits which can be set from ISPU and cleared by the interface.
S2IF_8
DS13892 - Rev 2 page 54/107
11.8
11.9
11.10
LSM6DSO16IS
ISPU_DOUT_00_L (10h), ISPU_DOUT_00_H (11h)
ISPU_DOUT_00_L (10h), ISPU_DOUT_00_H (11h)
ISPU output register 0 (R). This register is also accessible from ISPU at address 6810h, 6811h (R/W).
DOUT0_7 DOUT0_6
Table 125. ISPU_DOUT_00_L register
DOUT0_5 DOUT0_4 DOUT0_3 DOUT0_2 DOUT0_1 DOUT0_0
DOUT0_15 DOUT0_14
Table 126. ISPU_DOUT_00_H register
DOUT0_13 DOUT0_12 DOUT0_11 DOUT0_10 DOUT0_9 DOUT0_8
DOUT0_[15:0]
Table 127. ISPU_DOUT_00 register description
General-purpose output.
ISPU_DOUT_01_L (12h), ISPU_DOUT_01_H (13h)
ISPU output register 1 (R). This register is also accessible from ISPU at address 6812h, 6813h (R/W).
DOUT1_7 DOUT1_6
Table 128. ISPU_DOUT_01_L registers
DOUT1_5 DOUT1_4 DOUT1_3 DOUT1_2 DOUT1_1 DOUT1_0
DOUT1_15 DOUT1_14
Table 129. ISPU_DOUT_01_H registers
DOUT1_13 DOUT1_12 DOUT1_11 DOUT1_10 DOUT1_9
DOUT2_[15:0]
DOUT1_8
DOUT1_[15:0]
Table 130. ISPU_DOUT_01 register description
General-purpose output.
ISPU_DOUT_02_L (14h), ISPU_DOUT_02_H (15h)
ISPU output register 2 (R). This register is also accessible from ISPU at address 6814h, 6815h (R/W).
DOUT2_7 DOUT2_6
Table 131. ISPU_DOUT_02_L register
DOUT2_5 DOUT2_4 DOUT2_3 DOUT2_2 DOUT2_1 DOUT2_0
DOUT2_15 DOUT2_14
Table 132. ISPU_DOUT_02_H register
DOUT2_13 DOUT2_12 DOUT2_11 DOUT2_10 DOUT2_9 DOUT2_8
Table 133. ISPU_DOUT_02 register description
General-purpose output.
DS13892 - Rev 2 page 55/107
11.11
11.12
11.13
LSM6DSO16IS
ISPU_DOUT_03_L (16h), ISPU_DOUT_03_H (17h)
ISPU_DOUT_03_L (16h), ISPU_DOUT_03_H (17h)
ISPU output register 3 (R). This register is also accessible from ISPU at address 6816h, 6817h (R/W).
DOUT3_7 DOUT3_6
Table 134. ISPU_DOUT_03_L register
DOUT3_5 DOUT3_4 DOUT3_3 DOUT3_2 DOUT3_1 DOUT3_0
DOUT3_15 DOUT3_14
Table 135. ISPU_DOUT_03_H register
DOUT3_13 DOUT3_12 DOUT3_11 DOUT3_10 DOUT3_9 DOUT3_8
DOUT3_[15:0]
Table 136. ISPU_DOUT_03 register description
General-purpose output.
ISPU_DOUT_04_L (18h), ISPU_DOUT_04_H (19h)
ISPU output register 4 (R). This register is also accessible from ISPU at address 6818h, 6819h (R/W).
DOUT4_7 DOUT4_6
Table 137. ISPU_DOUT_04_L register
DOUT4_5 DOUT4_4 DOUT4_3 DOUT4_2 DOUT4_1 DOUT4_0
DOUT4_15 DOUT4_14
Table 138. ISPU_DOUT_04_H register
DOUT4_13 DOUT4_12 DOUT4_11 DOUT4_10 DOUT4_9
DOUT5_[15:0]
DOUT4_8
DOUT4_[15:0]
Table 139. ISPU_DOUT_04 register description
General-purpose output.
ISPU_DOUT_05_L (1Ah), ISPU_DOUT_05_H (1Bh)
ISPU output register 5 (R). This register is also accessible from ISPU at address 681Ah, 681Bh (R/W).
DOUT5_7 DOUT5_6
Table 140. ISPU_DOUT_05_L register
DOUT5_5 DOUT5_4 DOUT5_3 DOUT5_2 DOUT5_1 DOUT5_0
DOUT5_15 DOUT5_14
Table 141. ISPU_DOUT_05_H register
DOUT5_13 DOUT5_12 DOUT5_11 DOUT5_10 DOUT5_9 DOUT5_8
Table 142. ISPU_DOUT_05 register description
General-purpose output.
DS13892 - Rev 2 page 56/107
11.14
11.15
11.16
LSM6DSO16IS
ISPU_DOUT_06_L (1Ch), ISPU_DOUT_06_H (1Dh)
ISPU_DOUT_06_L (1Ch), ISPU_DOUT_06_H (1Dh)
ISPU output register 6 (R). This register is also accessible from ISPU at address 681Ch, 681Dh (R/W).
DOUT6_7 DOUT6_6
Table 143. ISPU_DOUT_06_L register
DOUT6_5 DOUT6_4 DOUT6_3 DOUT6_2 DOUT6_1 DOUT6_0
DOUT6_15 DOUT6_14
Table 144. ISPU_DOUT_06_H register
DOUT6_13 DOUT6_12 DOUT6_11 DOUT6_10 DOUT6_9 DOUT6_8
DOUT6_[15:0]
Table 145. ISPU_DOUT_06 register description
General-purpose output.
ISPU_DOUT_07_L (1Eh), ISPU_DOUT_07_H (1Fh)
ISPU output register 7 (R). This register is also accessible from ISPU at address 681Eh, 681Fh (R/W).
DOUT7_7 DOUT7_6
Table 146. ISPU_DOUT_07_L register
DOUT7_5 DOUT7_4 DOUT7_3 DOUT7_2 DOUT7_1 DOUT7_0
DOUT7_15 DOUT7_14
Table 147. ISPU_DOUT_07_H register
DOUT7_13 DOUT7_12 DOUT7_11 DOUT7_10 DOUT7_9
DOUT8_[15:0]
DOUT7_8
DOUT7_[15:0]
Table 148. ISPU_DOUT_07 register description
General-purpose output.
ISPU_DOUT_08_L (20h), ISPU_DOUT_08_H (21h)
ISPU output register 8 (R). This register is also accessible from ISPU at address 6820h, 6821h (R/W).
DOUT8_7 DOUT8_6
Table 149. ISPU_DOUT_08_L register
DOUT8_5 DOUT8_4 DOUT8_3 DOUT8_2 DOUT8_1 DOUT8_0
DOUT8_15 DOUT8_14
Table 150. ISPU_DOUT_08_H register
DOUT8_13 DOUT8_12 DOUT8_11 DOUT8_10 DOUT8_9 DOUT8_8
Table 151. ISPU_DOUT_08 register description
General-purpose output.
DS13892 - Rev 2 page 57/107
11.17
11.18
11.19
LSM6DSO16IS
ISPU_DOUT_09_L (22h), ISPU_DOUT_09_H (23h)
ISPU_DOUT_09_L (22h), ISPU_DOUT_09_H (23h)
ISPU output register 9 (R). This register is also accessible from ISPU at address 6822h, 6823h (R/W).
DOUT9_7 DOUT9_6
Table 152. ISPU_DOUT_09_L register
DOUT9_5 DOUT9_4 DOUT9_3 DOUT9_2 DOUT9_1 DOUT9_0
DOUT9_15 DOUT9_14
Table 153. ISPU_DOUT_09_H register
DOUT9_13 DOUT9_12 DOUT9_11 DOUT9_10 DOUT9_9 DOUT9_8
DOUT9_[15:0]
Table 154. ISPU_DOUT_09 register description
General-purpose output.
ISPU_DOUT_10_L (24h), ISPU_DOUT_10_H (25h)
ISPU output register 10 (R). This register is also accessible from ISPU at address 6824h, 6825h (R/W).
DOUT10_7 DOUT10_6
Table 155. ISPU_DOUT_10_L register
DOUT10_5 DOUT10_4 DOUT10_3 DOUT10_2 DOUT10_1 DOUT10_0
Table 156. ISPU_DOUT_10_H register
DOUT10_15 DOUT10_14 DOUT10_13 DOUT10_12 DOUT10_11 DOUT10_10 DOUT10_9 DOUT10_8
DOUT10_[15:0]
Table 157. ISPU_DOUT_10 register description
General-purpose output.
ISPU_DOUT_11_L (26h), ISPU_DOUT_11_H (27h)
ISPU output register 11 (R). This register is also accessible from ISPU at address 6826h, 6827h (R/W).
DOUT11_7 DOUT11_6
Table 158. ISPU_DOUT_11_L register
DOUT11_5 DOUT11_4 DOUT11_3 DOUT11_2 DOUT11_1 DOUT11_0
Table 159. ISPU_DOUT_11_H register
DOUT11_15 DOUT11_14 DOUT11_13 DOUT11_12 DOUT11_11 DOUT11_10 DOUT11_9 DOUT11_8
DOUT11_[15:0]
Table 160. ISPU_DOUT_11 register description
General-purpose output.
DS13892 - Rev 2 page 58/107
11.20
11.21
11.22
LSM6DSO16IS
ISPU_DOUT_12_L (28h), ISPU_DOUT_12_H (29h)
ISPU_DOUT_12_L (28h), ISPU_DOUT_12_H (29h)
ISPU output register 12 (R). This register is also accessible from ISPU at address 6828h, 6829h (R/W).
DOUT12_7 DOUT12_6
Table 161. ISPU_DOUT_12_L register
DOUT12_5 DOUT12_4 DOUT12_3 DOUT12_2 DOUT12_1 DOUT12_0
Table 162. ISPU_DOUT_12_H register
DOUT12_15 DOUT12_14 DOUT12_13 DOUT12_12 DOUT12_11 DOUT12_10 DOUT12_9 DOUT12_8
DOUT12_[15:0]
Table 163. ISPU_DOUT_12 register description
General-purpose output.
ISPU_DOUT_13_L (2Ah), ISPU_DOUT_13_H (2Bh)
ISPU output register 13 (R). This register is also accessible from ISPU at address 682Ah, 682Bh (R/W).
DOUT13_7 DOUT13_6
Table 164. ISPU_DOUT_13_L register
DOUT13_5 DOUT13_4 DOUT13_3 DOUT13_2 DOUT13_1 DOUT13_0
Table 165. ISPU_DOUT_13_H register
DOUT13_15 DOUT13_14 DOUT13_13 DOUT13_12 DOUT13_11 DOUT13_10 DOUT13_9 DOUT13_8
DOUT13_[15:0]
Table 166. ISPU_DOUT_13 register description
General-purpose output.
ISPU_DOUT_14_L (2Ch), ISPU_DOUT_14_H (2Dh)
ISPU output register 14 (R). This register is also accessible from ISPU at address 682Ch, 682Dh (R/W).
DOUT14_7 DOUT14_6
Table 167. ISPU_DOUT_14_L register
DOUT14_5 DOUT14_4 DOUT14_3 DOUT14_2 DOUT14_1 DOUT14_0
Table 168. ISPU_DOUT_14_H register
DOUT14_15 DOUT14_14 DOUT14_13 DOUT14_12 DOUT14_11 DOUT14_10 DOUT14_9 DOUT14_8
DOUT14_[15:0]
Table 169. ISPU_DOUT_14 register description
General-purpose output.
DS13892 - Rev 2 page 59/107
11.23
11.24
11.25
LSM6DSO16IS
ISPU_DOUT_15_L (2Eh), ISPU_DOUT_15_H (2Fh)
ISPU_DOUT_15_L (2Eh), ISPU_DOUT_15_H (2Fh)
ISPU output register 15 (R). This register is also accessible from ISPU at address 682Eh, 682Fh (R/W).
DOUT15_7 DOUT15_6
Table 170. ISPU_DOUT_15_L register
DOUT15_5 DOUT15_4 DOUT15_3 DOUT15_2 DOUT15_1 DOUT15_0
Table 171. ISPU_DOUT_15_H register
DOUT15_15 DOUT15_14 DOUT15_13 DOUT15_12 DOUT15_11 DOUT15_10 DOUT15_9 DOUT15_8
DOUT15_[15:0]
Table 172. ISPU_DOUT_15 register description
General-purpose output.
ISPU_DOUT_16_L (30h), ISPU_DOUT_16_H (31h)
ISPU output register 16 (R). This register is also accessible from ISPU at address 6830h, 6831h (R/W).
DOUT16_7 DOUT16_6
Table 173. ISPU_DOUT_16_L register
DOUT16_5 DOUT16_4 DOUT16_3 DOUT16_2 DOUT16_1 DOUT16_0
Table 174. ISPU_DOUT_16_H register
DOUT16_15 DOUT16_14 DOUT16_13 DOUT16_12 DOUT16_11 DOUT16_10 DOUT16_9 DOUT16_8
DOUT16_[15:0]
Table 175. ISPU_DOUT_16 register description
General-purpose output.
ISPU_DOUT_17_L (32h), ISPU_DOUT_17_H (33h)
ISPU output register 17 (R). This register is also accessible from ISPU at address 6832h, 6833h (R/W).
DOUT17_7 DOUT17_6
Table 176. ISPU_DOUT_17_L register
DOUT17_5 DOUT17_4 DOUT17_3 DOUT17_2 DOUT17_1 DOUT17_0
Table 177. ISPU_DOUT_17_H register
DOUT17_15 DOUT17_14 DOUT17_13 DOUT17_12 DOUT17_11 DOUT17_10 DOUT17_9 DOUT17_8
DOUT17_[15:0]
Table 178. ISPU_DOUT_17 register description
General-purpose output.
DS13892 - Rev 2 page 60/107
11.26
11.27
11.28
LSM6DSO16IS
ISPU_DOUT_18_L (34h), ISPU_DOUT_18_H (35h)
ISPU_DOUT_18_L (34h), ISPU_DOUT_18_H (35h)
ISPU output register 18 (R). This register is also accessible from ISPU at address 6834h, 6835h (R/W).
DOUT18_7 DOUT18_6
Table 179. ISPU_DOUT_18_L register
DOUT18_5 DOUT18_4 DOUT18_3 DOUT18_2 DOUT18_1 DOUT18_0
Table 180. ISPU_DOUT_18_H register
DOUT18_15 DOUT18_14 DOUT18_13 DOUT18_12 DOUT18_11 DOUT18_10 DOUT18_9 DOUT18_8
DOUT18_[15:0]
Table 181. ISPU_DOUT_18 register description
General-purpose output.
ISPU_DOUT_19_L (36h), ISPU_DOUT_19_H (37h)
ISPU output register 19 (R). This register is also accessible from ISPU at address 6836h, 6837h (R/W).
DOUT19_7 DOUT19_6
Table 182. ISPU_DOUT_19_L register
DOUT19_5 DOUT19_4 DOUT19_3 DOUT19_2 DOUT19_1 DOUT19_0
Table 183. ISPU_DOUT_19_H register
DOUT19_15 DOUT19_14 DOUT19_13 DOUT19_12 DOUT19_11 DOUT19_10 DOUT19_9 DOUT19_8
DOUT19_[15:0]
Table 184. ISPU_DOUT_19 register description
General-purpose output.
ISPU_DOUT_20_L (38h), ISPU_DOUT_20_H (39h)
ISPU output register 20 (R). This register is also accessible from ISPU at address 6838h, 6839h (R/W).
DOUT20_7 DOUT20_6
Table 185. ISPU_DOUT_20_L register
DOUT20_5 DOUT20_4 DOUT20_3 DOUT20_2 DOUT20_1 DOUT20_0
Table 186. ISPU_DOUT_20_H register
DOUT20_15 DOUT20_14 DOUT20_13 DOUT20_12 DOUT20_11 DOUT20_10 DOUT20_9 DOUT20_8
DOUT20_[15:0]
Table 187. ISPU_DOUT_20 register description
General-purpose output.
DS13892 - Rev 2 page 61/107
11.29
11.30
11.31
LSM6DSO16IS
ISPU_DOUT_21_L (3Ah), ISPU_DOUT_21_H (3Bh)
ISPU_DOUT_21_L (3Ah), ISPU_DOUT_21_H (3Bh)
ISPU output register 21 (R). This register is also accessible from ISPU at address 683Ah, 683Bh (R/W).
DOUT21_7 DOUT21_6
Table 188. ISPU_DOUT_21_L register
DOUT21_5 DOUT21_4 DOUT21_3 DOUT21_2 DOUT21_1 DOUT21_0
Table 189. ISPU_DOUT_21_H register
DOUT21_15 DOUT21_14 DOUT21_13 DOUT21_12 DOUT21_11 DOUT21_10 DOUT21_9 DOUT21_8
DOUT21_[15:0]
Table 190. ISPU_DOUT_21 register description
General-purpose output.
ISPU_DOUT_22_L (3Ch), ISPU_DOUT_22_H (3Dh)
ISPU output register 22 (R). This register is also accessible from ISPU at address 683Ch, 683Dh (R/W).
DOUT22_7 DOUT22_6
Table 191. ISPU_DOUT_22_L register
DOUT22_5 DOUT22_4 DOUT22_3 DOUT22_2 DOUT22_1 DOUT22_0
Table 192. ISPU_DOUT_22_H register
DOUT22_15 DOUT22_14 DOUT22_13 DOUT22_12 DOUT22_11 DOUT22_10 DOUT22_9 DOUT22_8
DOUT22_[15:0]
Table 193. ISPU_DOUT_22 register description
General-purpose output.
ISPU_DOUT_23_L (3Eh), ISPU_DOUT_23_H (3Fh)
ISPU output register 23 (R). This register is also accessible from ISPU at address 683Eh, 683Fh (R/W).
DOUT23_7 DOUT23_6
Table 194. ISPU_DOUT_23_L register
DOUT23_5 DOUT23_4 DOUT23_3 DOUT23_2 DOUT23_1 DOUT23_0
Table 195. ISPU_DOUT_23_L register
DOUT23_15 DOUT23_14 DOUT23_13 DOUT23_12 DOUT23_11 DOUT23_10 DOUT23_9 DOUT23_8
DOUT23_[15:0]
Table 196. ISPU_DOUT_23 register description
General-purpose output.
DS13892 - Rev 2 page 62/107
11.32
11.33
11.34
LSM6DSO16IS
ISPU_DOUT_24_L (40h), ISPU_DOUT_24_H (41h)
ISPU_DOUT_24_L (40h), ISPU_DOUT_24_H (41h)
ISPU output register 24 (R). This register is also accessible from ISPU at address 6840h, 6841h (R/W).
DOUT24_7 DOUT24_6
Table 197. ISPU_DOUT_24_L register
DOUT24_5 DOUT24_4 DOUT24_3 DOUT24_2 DOUT24_1 DOUT24_0
Table 198. ISPU_DOUT_24_H register
DOUT24_15 DOUT24_14 DOUT24_13 DOUT24_12 DOUT24_11 DOUT24_10 DOUT24_9 DOUT24_8
DOUT24_[15:0]
Table 199. ISPU_DOUT_24 register description
General-purpose output.
ISPU_DOUT_25_L (42h), ISPU_DOUT_25_H (43h)
ISPU output register 25 (R). This register is also accessible from ISPU at address 6842h, 6843h (R/W).
DOUT25_7 DOUT25_6
Table 200. ISPU_DOUT_25_L register
DOUT25_5 DOUT25_4 DOUT25_3 DOUT25_2 DOUT25_1 DOUT25_0
Table 201. ISPU_DOUT_25_H register
DOUT25_15 DOUT25_14 DOUT25_13 DOUT25_12 DOUT25_11 DOUT25_10 DOUT25_9 DOUT25_8
DOUT25_[15:0]
Table 202. ISPU_DOUT_25 register description
General-purpose output.
ISPU_DOUT_26_L (44h), ISPU_DOUT_26_H (45h)
ISPU output register 26 (R). This register is also accessible from ISPU at address 6844h, 6845h (R/W).
DOUT26_7 DOUT26_6
Table 203. ISPU_DOUT_26_L register
DOUT26_5 DOUT26_4 DOUT26_3 DOUT26_2 DOUT26_1 DOUT26_0
Table 204. ISPU_DOUT_26_H register
DOUT26_15 DOUT26_14 DOUT26_13 DOUT26_12 DOUT26_11 DOUT26_10 DOUT26_9 DOUT26_8
DOUT26_[15:0]
Table 205. ISPU_DOUT_26 register description
General-purpose output.
DS13892 - Rev 2 page 63/107
11.35
11.36
11.37
LSM6DSO16IS
ISPU_DOUT_27_L (46h), ISPU_DOUT_27_H (47h)
ISPU_DOUT_27_L (46h), ISPU_DOUT_27_H (47h)
ISPU output register 27 (R). This register is also accessible from ISPU at address 6846h, 6847h (R/W).
DOUT27_7 DOUT27_6
Table 206. ISPU_DOUT_27_L register
DOUT27_5 DOUT27_4 DOUT27_3 DOUT27_2 DOUT27_1 DOUT27_0
Table 207. ISPU_DOUT_27_H register
DOUT27_15 DOUT27_14 DOUT27_13 DOUT27_12 DOUT27_11 DOUT27_10 DOUT27_9 DOUT27_8
DOUT27_[15:0]
Table 208. ISPU_DOUT_27 register description
General-purpose output.
ISPU_DOUT_28_L (48h), ISPU_DOUT_28_H (49h)
ISPU output register 28 (R). This register is also accessible from ISPU at address 6848h, 6849h (R/W).
DOUT28_7 DOUT28_6
Table 209. ISPU_DOUT_28_L register
DOUT28_5 DOUT28_4 DOUT28_3 DOUT28_2 DOUT28_1 DOUT28_0
Table 210. ISPU_DOUT_28_H register
DOUT28_15 DOUT28_14 DOUT28_13 DOUT28_12 DOUT28_11 DOUT28_10 DOUT28_9 DOUT28_8
DOUT28_[15:0]
Table 211. ISPU_DOUT_28 register description
General-purpose output.
ISPU_DOUT_29_L (4Ah), ISPU_DOUT_29_H (4Bh)
ISPU output register 29 (R). This register is also accessible from ISPU at address 684Ah, 684Bh (R/W).
DOUT29_7 DOUT29_6
Table 212. ISPU_DOUT_29_L register
DOUT29_5 DOUT29_4 DOUT29_3 DOUT29_2 DOUT29_1 DOUT29_0
Table 213. ISPU_DOUT_29_H register
DOUT29_15 DOUT29_14 DOUT29_13 DOUT29_12 DOUT29_11 DOUT29_10 DOUT29_9 DOUT29_8
DOUT29_[15:0]
Table 214. ISPU_DOUT_29 register description
General-purpose output.
DS13892 - Rev 2 page 64/107
11.38
11.39
LSM6DSO16IS
ISPU_DOUT_30_L (4Ch), ISPU_DOUT_30_H (4Dh)
ISPU_DOUT_30_L (4Ch), ISPU_DOUT_30_H (4Dh)
ISPU output register 30 (R). This register is also accessible from ISPU at address 684Ch, 684Dh (R/W).
DOUT30_7 DOUT30_6
Table 215. ISPU_DOUT_30_L register
DOUT30_5 DOUT30_4 DOUT30_3 DOUT30_2 DOUT30_1 DOUT30_0
Table 216. ISPU_DOUT_30_H register
DOUT30_15 DOUT30_14 DOUT30_13 DOUT30_12 DOUT30_11 DOUT30_10 DOUT30_9 DOUT30_8
DOUT30_[15:0]
Table 217. ISPU_DOUT_30 register description
General-purpose output.
ISPU_DOUT_31_L (4Eh), ISPU_DOUT_31_H (4Fh)
ISPU output register 31 (R). This register is also accessible from ISPU at address 684Eh, 684Fh (R/W).
DOUT31_7 DOUT31_6
Table 218. ISPU_DOUT_31_L register
DOUT31_5 DOUT31_4 DOUT31_3 DOUT31_2 DOUT31_1 DOUT31_0
Table 219. ISPU_DOUT_31_H register
DOUT31_15 DOUT31_14 DOUT31_13 DOUT31_12 DOUT31_11 DOUT31_10 DOUT31_9 DOUT31_8
DOUT31_[15:0]
Table 220. ISPU_DOUT_31 register description
General-purpose output.
DS13892 - Rev 2 page 65/107
11.40
LSM6DSO16IS
ISPU_INT1_CTRL0 (50h), ISPU_INT1_CTRL1 (51h), ISPU_INT1_CTRL2 (52h), ISPU_INT1_CTRL3 (53h)
ISPU_INT1_CTRL0 (50h), ISPU_INT1_CTRL1 (51h), ISPU_INT1_CTRL2 (52h),
ISPU_INT1_CTRL3 (53h)
ISPU INT1 configuration register (R/W). This register is also accessible from ISPU at address 6850h, 6851h,
6852h, 6853h (R).
ISPU_INT1
_CTRL7
ISPU_INT1
_CTRL6
Table 221. ISPU_INT1_CTRL0 register
ISPU_INT1
_CTRL5
ISPU_INT1
_CTRL4
ISPU_INT1
_CTRL3
ISPU_INT1
_CTRL2
ISPU_INT1
_CTRL1
ISPU_INT1
_CTRL0
ISPU_INT1
_CTRL15
ISPU_INT1
_CTRL14
Table 222. ISPU_INT1_CTRL1 register
ISPU_INT1
_CTRL13
ISPU_INT1
_CTRL12
ISPU_INT1
_CTRL11
ISPU_INT1
_CTRL10
ISPU_INT1
_CTRL9
ISPU_INT1
_CTRL8
ISPU_INT1
_CTRL23
ISPU_INT1
_CTRL22
Table 223. ISPU_INT1_CTRL2 register
ISPU_INT1
_CTRL21
ISPU_INT1
_CTRL20
ISPU_INT1
_CTRL19
ISPU_INT1
_CTRL18
ISPU_INT1
_CTRL17
ISPU_INT1
_CTRL16
0 0
Table 224. ISPU_INT1_CTRL3 register
ISPU_INT1
_CTRL29
ISPU_INT1
_CTRL28
ISPU_INT1
_CTRL27
ISPU_INT1
_CTRL26
ISPU_INT1
_CTRL25
ISPU_INT1
_CTRL24
Table 225. ISPU_INT1_CTRL register description
ISPU_INT1_CTRL[29:0]
Routing 30-bit interrupt flags (in ISPU_INT_STATUS registers) to the INT1 pin. INT1_ISPU must be set to 1 also.
DS13892 - Rev 2 page 66/107
11.41
LSM6DSO16IS
ISPU_INT2_CTRL0 (54h), ISPU_INT2_CTRL1 (55h), ISPU_INT2_CTRL2 (56h), ISPU_INT2_CTRL3 (57h)
ISPU_INT2_CTRL0 (54h), ISPU_INT2_CTRL1 (55h), ISPU_INT2_CTRL2 (56h),
ISPU_INT2_CTRL3 (57h)
ISPU INT2 configuration register (R/W). This register is also accessible from ISPU at address 6854h, 6855h,
6856h, 6857h (R).
ISPU_INT2
_CTRL7
ISPU_INT2
_CTRL6
Table 226. ISPU_INT2_CTRL0 register
ISPU_INT2
_CTRL5
ISPU_INT2
_CTRL4
ISPU_INT2
_CTRL3
ISPU_INT2
_CTRL2
ISPU_INT2
_CTRL1
ISPU_INT2
_CTRL0
ISPU_INT2
_CTRL15
ISPU_INT2
_CTRL14
Table 227. ISPU_INT2_CTRL1 register
ISPU_INT2
_CTRL13
ISPU_INT2
_CTRL12
ISPU_INT2
_CTRL11
ISPU_INT2
_CTRL10
ISPU_INT2
_CTRL9
ISPU_INT2
_CTRL8
ISPU_INT2
_CTRL23
ISPU_INT2
_CTRL22
Table 228. ISPU_INT2_CTRL2 register
ISPU_INT2
_CTRL21
ISPU_INT2
_CTRL20
ISPU_INT2
_CTRL19
ISPU_INT2
_CTRL18
ISPU_INT2
_CTRL17
ISPU_INT2
_CTRL16
0 0
Table 229. ISPU_INT2_CTRL3 register
ISPU_INT2
_CTRL29
ISPU_INT2
_CTRL28
ISPU_INT2
_CTRL27
ISPU_INT2
_CTRL26
ISPU_INT2
_CTRL25
ISPU_INT2
_CTRL24
Table 230. ISPU_INT2_CTRL register description
ISPU_INT2_CTRL[29:0]
Routing 30-bit interrupt flags (in ISPU_INT_STATUS registers) to the INT2 pin. INT2_ISPU must be set to 1 also.
DS13892 - Rev 2 page 67/107
11.42
LSM6DSO16IS
ISPU_INT_STATUS0 (58h), ISPU_INT_STATUS1 (59h), ISPU_INT_STATUS2 (5Ah), ISPU_INT_STATUS3 (5Bh)
ISPU_INT_STATUS0 (58h), ISPU_INT_STATUS1 (59h), ISPU_INT_STATUS2
(5Ah), ISPU_INT_STATUS3 (5Bh)
ISPU interrupt status register (R). This register is also accessible from ISPU at address 6858h, 6859h, 685Ah,
685Bh (R/W).
ISPU_INT_
STATUS7
ISPU_INT_
STATUS6
Table 231. ISPU_INT_STATUS0 register
ISPU_INT_
STATUS5
ISPU_INT_
STATUS4
ISPU_INT_
STATUS3
ISPU_INT_
STATUS2
ISPU_INT_
STATUS1
ISPU_INT_
STATUS0
ISPU_INT_
STATUS15
ISPU_INT_
STATUS14
Table 232. ISPU_INT_STATUS1 register
ISPU_INT_
STATUS13
ISPU_INT_
STATUS12
ISPU_INT_
STATUS11
ISPU_INT_
STATUS10
ISPU_INT_
STATUS9
ISPU_INT_
STATUS8
ISPU_INT_
STATUS23
ISPU_INT_
STATUS22
Table 233. ISPU_INT_STATUS2 register
ISPU_INT_
STATUS21
ISPU_INT_
STATUS20
ISPU_INT_
STATUS19
ISPU_INT_
STATUS18
ISPU_INT_
STATUS17
ISPU_INT_
STATUS16
0 0
Table 234. ISPU_INT_STATUS3 register
ISPU_INT_
STATUS29
ISPU_INT_
STATUS28
ISPU_INT_
STATUS27
ISPU_INT_
STATUS26
ISPU_INT_
STATUS25
ISPU_INT_
STATUS24
ISPU_INT_STATUS[29:0]
Table 235. ISPU_INT_STATUS register description
30-bit interrupt flags.
DS13892 - Rev 2 page 68/107
11.43
LSM6DSO16IS
ISPU_ALGO0 (70h), ISPU_ALGO1 (71h), ISPU_ALGO2 (72h), ISPU_ALGO3 (73h)
ISPU_ALGO0 (70h), ISPU_ALGO1 (71h), ISPU_ALGO2 (72h), ISPU_ALGO3 (73h)
ISPU algorithm register (R/W). This register is also accessible from ISPU at address 6870h, 6871h, 6872h, 6873h
(R).
ISPU_
ALGO7
ISPU_
ALGO6
ISPU_
ALGO5
Table 236. ISPU_ALGO0 register
ISPU_
ALGO4
ISPU_
ALGO3
ISPU_
ALGO2
ISPU_
ALGO1
ISPU_
ALGO0
ISPU_
ALGO15
ISPU_
ALGO23
ISPU_
ALGO14
ISPU_
ALGO22
ISPU_
ALGO13
Table 237. ISPU_ALGO1 register
ISPU_
ALGO12
ISPU_
ALGO11
ISPU_
ALGO10
ISPU_
ALGO21
Table 238. ISPU_ALGO2 register
ISPU_
ALGO20
ISPU_
ALGO19
ISPU_
ALGO18
ISPU_
ALGO9
ISPU_
ALGO17
ISPU_
ALGO8
ISPU_
ALGO16
0
ISPU_ALGO[29:0]
0
ISPU_
ALGO29
Table 239. ISPU_ALGO3 register
ISPU_
ALGO28
ISPU_
ALGO27
ISPU_
ALGO26
Table 240. ISPU_ALGO register description
Enable configurations in order to run up to 30 independent algorithms.
ISPU_
ALGO25
ISPU_
ALGO24
DS13892 - Rev 2 page 69/107
12
LSM6DSO16IS
ISPU functions register mapping
ISPU functions register mapping
The table given below provides a list of the registers internally available in the ISPU core.
ISPU address (hex)
6800
685C
6880-6881
6884-6885
6888-6889
688C-688D
6890-6891
6894-6895
6898-6899
689C-689D
68A0-68A1
68A4-68A5
68B8-68BB
6948-6949
694A-694B
Table 241. Register map - ISPU functions internally available
4
2
2
2
2
2
2
2
2
Bytes
1
1
2
2
2
2
Name
ISPU_GLB_CALL_EN
ISPU_INT_PIN
ISPU_ARAW_X
ISPU_ARAW_Y
ISPU_ARAW_Z
ISPU_GRAW_X
ISPU_GRAW_Y
ISPU_GRAW_Z
ISPU_ERAW_0
ISPU_ERAW_1
ISPU_ERAW_2
ISPU_TEMP
ISPU_CALL_EN
ISPU_DTIME_0
ISPU_DTIME_1
No
No
No
No
No
No
No
No
No
IF access
No
No
No
No
No
No
ISPU access
R/W
R/W
R
R
R
R
R/W
R
R
R
R
R
R
R
R
Reserved registers must not be changed. Writing to those registers may cause permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
DS13892 - Rev 2 page 70/107
13
13.1
13.2
13.3
LSM6DSO16IS
ISPU functions register description
ISPU functions register description
ISPU_GLB_CALL_EN (6800h)
ISPU read/write access (6800h)
-
Table 242. ISPU_GLB_CALL_EN registers
-
ISPU_GLB_C
ALL_EN
ISPU_GLB_CALL_EN
Table 243. ISPU_GLB_CALL_EN register description
Enables internal interrupt generation to run algorithm routines.
ISPU_INT_PIN (685Ch)
ISPU read/write access (685Ch)
0 0 0
Table 244. ISPU_INT_PIN registers
0 0 0 INT2 INT1
INT2
INT1
Table 245. ISPU_INT_PIN register description
Flag for interrupt generation on INT2 pin.
Flag for interrupt generation on INT1 pin.
ISPU_ARAW_X_L (6880h), ISPU_ARAW_X_H (6881h)
ISPU read access (6880h, 6881h)
ISPU_
ARAW_X_7
ISPU_
ARAW_X_6
Table 246. ISPU_ARAW_X_L register
ISPU_
ARAW_X_5
ISPU_
ARAW_X_4
ISPU_
ARAW_X_3
ISPU_
ARAW_X_2
ISPU_
ARAW_X_1
ISPU_
ARAW_X_0
ISPU_
ARAW_X_15
ISPU_
ARAW_X_14
Table 247. ISPU_ARAW_X_H register
ISPU_
ARAW_X_13
ISPU_
ARAW_X_12
ISPU_
ARAW_X_11
ISPU_
ARAW_X_10
ISPU_
ARAW_X_9
ISPU_
ARAW_X_8
ISPU_ARAW_X_[15:0]
Table 248. ISPU_ARAW_X register description
Accelerometer X-axis output expressed in two’s complement.
DS13892 - Rev 2 page 71/107
13.4
13.5
13.6
LSM6DSO16IS
ISPU_ARAW_Y_L (6884h), ISPU_ARAW_Y_H (6885h)
ISPU_ARAW_Y_L (6884h), ISPU_ARAW_Y_H (6885h)
ISPU read access (6884h, 6885h)
ISPU_
ARAW_Y_7
ISPU_
ARAW_Y_6
Table 249. ISPU_ARAW_Y_L register
ISPU_
ARAW_Y_5
ISPU_
ARAW_Y_4
ISPU_
ARAW_Y_3
ISPU_
ARAW_Y_2
ISPU_
ARAW_Y_1
ISPU_
ARAW_Y_0
ISPU_
ARAW_Y_15
ISPU_
ARAW_Y_14
Table 250. ISPU_ARAW_Y_H register
ISPU_
ARAW_Y_13
ISPU_
ARAW_Y_12
ISPU_
ARAW_Y_11
ISPU_
ARAW_Y_10
ISPU_
ARAW_Y_9
ISPU_
ARAW_Y_8
ISPU_ARAW_Y_[15:0]
Table 251. ISPU_ARAW_Y register description
Accelerometer Y-axis output expressed in two’s complement.
ISPU_ARAW_Z_L (6888h), ISPU_ARAW_Z_H (6889h)
ISPU read access (6888h, 6889h)
ISPU_
ARAW_Z_7
ISPU_
ARAW_Z_6
Table 252. ISPU_ARAW_Z_L register
ISPU_
ARAW_Z_5
ISPU_
ARAW_Z_4
ISPU_
ARAW_Z_3
ISPU_
ARAW_Z_2
ISPU_
ARAW_Z_1
ISPU_
ARAW_Z_0
ISPU_
ARAW_Z_15
ISPU_
ARAW_Z_14
Table 253. ISPU_ARAW_Z_H register
ISPU_
ARAW_Z_13
ISPU_
ARAW_Z_12
ISPU_
ARAW_Z_11
ISPU_
ARAW_Z_10
ISPU_
ARAW_Z_9
ISPU_
ARAW_Z_8
ISPU_ARAW_Z_[15:0]
Table 254. ISPU_ARAW_Z register description
Accelerometer Z-axis output expressed in two’s complement.
ISPU_GRAW_X_L (688Ch), ISPU_GRAW_X_H (688Dh)
ISPU read access (688Ch, 688Dh)
ISPU_
GRAW_X_7
ISPU_
GRAW_X_6
Table 255. ISPU_GRAW_X_L register
ISPU_
GRAW_X_5
ISPU_
GRAW_X_4
ISPU_
GRAW_X_3
ISPU_
GRAW_X_2
ISPU_
GRAW_X_1
ISPU_
GRAW_X_0
Table 256. ISPU_GRAW_X_H register
ISPU_
GRAW_X_15
ISPU_
GRAW_X_14
ISPU_
GRAW_X_13
ISPU_
GRAW_X_12
ISPU_
GRAW_X_11
ISPU_
GRAW_X_10
ISPU_
GRAW_X_9
ISPU_
GRAW_X_8
ISPU_GRAW_X_[15:0]
Table 257. ISPU_GRAW_X register description
Gyroscope pitch axis output expressed in two’s complement.
DS13892 - Rev 2 page 72/107
13.7
13.8
13.9
LSM6DSO16IS
ISPU_GRAW_Y_L (6890h), ISPU_GRAW_Y_L (6891h)
ISPU_GRAW_Y_L (6890h), ISPU_GRAW_Y_L (6891h)
ISPU read access (6890h, 6891h)
ISPU_
GRAW_Y_7
ISPU_
GRAW_Y_6
Table 258. ISPU_GRAW_Y_L registers
ISPU_
GRAW_Y_5
ISPU_
GRAW_Y_4
ISPU_
GRAW_Y_3
ISPU_
GRAW_Y_2
ISPU_
GRAW_Y_1
ISPU_
GRAW_Y_0
Table 259. ISPU_GRAW_Y_H registers
ISPU_
GRAW_Y_15
ISPU_
GRAW_Y_14
ISPU_
GRAW_Y_13
ISPU_
GRAW_Y_12
ISPU_
GRAW_Y_11
ISPU_
GRAW_Y_10
ISPU_
GRAW_Y_9
ISPU_
GRAW_Y_8
ISPU_GRAW_Y_[15:0]
Table 260. ISPU_GRAW_Y register description
Gyroscope roll axis output expressed in two’s complement.
ISPU_GRAW_Z_L (6894h), ISPU_GRAW_Z_H (6895h)
ISPU read access (6894h, 6895h)
ISPU_
GRAW_Z_7
ISPU_
GRAW_Z_6
Table 261. ISPU_GRAW_Z_L registers
ISPU_
GRAW_Z_5
ISPU_
GRAW_Z_4
ISPU_
GRAW_Z_3
ISPU_
GRAW_Z_2
ISPU_
GRAW_Z_1
ISPU_
GRAW_Z_0
Table 262. ISPU_GRAW_Z_H registers
ISPU_
GRAW_Z_15
ISPU_
GRAW_Z_14
ISPU_
GRAW_Z_13
ISPU_
GRAW_Z_12
ISPU_
GRAW_Z_11
ISPU_
GRAW_Z_10
ISPU_
GRAW_Z_9
ISPU_
GRAW_Z_8
ISPU_GRAW_Z_[15:0]
Table 263. ISPU_GRAW_Z register description
Gyroscope yaw axis output expressed in two’s complement.
ISPU_ERAW_0_L (6898h), ISPU_ERAW_0_H (6899h)
ISPU read access (6898h, 6899h)
ISPU_
ERAW_0_7
ISPU_
MERAW_0_6
Table 264. ISPU_ERAW_0_L registers
ISPU_
ERAW_0_5
ISPU_
ERAW_0_4
ISPU_
ERAW_0_3
ISPU_
ERAW_0_2
ISPU_
ERAW_0_1
ISPU_
ERAW_0_0
ISPU_
ERAW_0_15
ISPU_
ERAW_0_14
Table 265. ISPU_ERAW_0_H registers
ISPU_
ERAW_0_13
ISPU_
ERAW_0_12
ISPU_
ERAW_0_11
ISPU_
ERAW_0_10
ISPU_
ERAW_0_9
ISPU_
ERAW_0_8
ISPU_ERAW_0_[15:0]
Table 266. ISPU_ERAW_0 register description
External sensor data from SENSOR_HUB_1 and SENSOR_HUB_2.
DS13892 - Rev 2 page 73/107
13.10
13.11
13.12
LSM6DSO16IS
ISPU_ERAW_1_L (689Ch), ISPU_ERAW_1_H (689Dh)
ISPU_ERAW_1_L (689Ch), ISPU_ERAW_1_H (689Dh)
ISPU read access (689Ch, 689Dh)
ISPU_
ERAW_1_7
ISPU_
ERAW_1_6
Table 267. ISPU_ERAW_1_L register
ISPU_
MRAW_Y_5
ISPU_
ERAW_1_4
ISPU_
ERAW_1_3
ISPU_
ERAW_1_2
ISPU_
ERAW_1_1
ISPU_
ERAW_1_0
ISPU_
ERAW_1_15
ISPU_
ERAW_1_14
Table 268. ISPU_ERAW_1_H register
ISPU_
ERAW_1_13
ISPU_
ERAW_1_12
ISPU_
ERAW_1_11
ISPU_
ERAW_1_10
ISPU_
ERAW_1_9
ISPU_
ERAW_1_8
ISPU_ERAW_1_[15:0]
Table 269. ISPU_ERAW_1 register description
External sensor data from SENSOR_HUB_3 and SENSOR_HUB_4.
ISPU_ERAW_2_L (68A0h), ISPU_ERAW_2_H (68A1h)
ISPU read access (68A0h, 68A1h)
ISPU_
ERAW_2_7
ISPU_
ERAW_2_6
Table 270. ISPU_ERAW_2_L register
ISPU_
ERAW_2_5
ISPU_
ERAW_2_4
ISPU_
ERAW_2_3
ISPU_
ERAW_2_2
ISPU_
ERAW_2_1
ISPU_
ERAW_2_0
ISPU_
ERAW_2_15
ISPU_
ERAW_2_14
Table 271. ISPU_ERAW_2_H register
ISPU_
ERAW_2_13
ISPU_
ERAW_2_12
ISPU_
ERAW_2_11
ISPU_
ERAW_2_10
ISPU_
ERAW_2_9
ISPU_
ERAW_2_8
ISPU_ERAW_2_[15:0]
Table 272. ISPU_ERAW_2 register description
External sensor data from SENSOR_HUB_5 and SENSOR_HUB_6.
ISPU_TEMP_L (68A4h), ISPU_TEMP_H (68A5h)
ISPU read access (68A4h, 68A5h)
ISPU_
TEMP_7
ISPU_
TEMP_6
ISPU_
TEMP_5
Table 273. ISPU_TEMP_L register
ISPU_
TEMP_4
ISPU_
TEMP_3
ISPU_
TEMP_2
ISPU_
TEMP_1
ISPU_
TEMP_0
ISPU_
TEMP_15
ISPU_
TEMP_14
ISPU_TEMP_[15:0]
Table 274. ISPU_TEMP_H register
ISPU_
TEMP_13
ISPU_
TEMP_12
ISPU_
TEMP_11
ISPU_
TEMP_10
Table 275. ISPU_TEMP register description
Temperature sensor output expressed in two’s complement.
ISPU_
TEMP_9
ISPU_
TEMP_8
DS13892 - Rev 2 page 74/107
13.13
LSM6DSO16IS
ISPU_CALL_EN_0 (68B8h), ISPU_CALL_EN_1 (68B9h), ISPU_CALL_EN_2 (68BAh), ISPU_CALL_EN_3 (68BBh)
ISPU_CALL_EN_0 (68B8h), ISPU_CALL_EN_1 (68B9h), ISPU_CALL_EN_2
(68BAh), ISPU_CALL_EN_3 (68BBh)
ISPU read/write access (68B8h, 68B9h, 68BAh, 68BBh)
Table 276. ISPU_CALL_EN_0 register
ISPU_CALL_
ALGO_6
ISPU_CALL_
ALGO_5
ISPU_CALL_
ALGO_4
ISPU_CALL_
ALGO_3
1. This bit must be set to 0 for the correct operation of the device.
ISPU_CALL_
ALGO_2
ISPU_CALL_
ALGO1
ISPU_CALL_
ALGO_0
0
ISPU_CALL_
ALGO_14
ISPU_CALL_
ALGO_13
Table 277. ISPU_CALL_EN_1 register
ISPU_CALL_
ALGO_12
ISPU_CALL_
ALGO_11
ISPU_CALL_
ALGO_10
ISPU_CALL_
ALGO_9
ISPU_CALL_
ALGO_8
ISPU_CALL_
ALGO_7
ISPU_CALL_
ALGO_22
ISPU_CALL_
ALGO_21
Table 278. ISPU_CALL_EN_2 register
ISPU_CALL_
ALGO_20
ISPU_CALL_
ALGO_19
ISPU_CALL_
ALGO_18
ISPU_CALL_
ALGO_17
ISPU_CALL_
ALGO_16
ISPU_CALL_
ALGO_15
Table 279. ISPU_CALL_EN_3 register
0
ISPU_CALL_
ALGO_29
ISPU_CALL_
ALGO_28
ISPU_CALL_
ALGO_27
1. This bit must be set to 0 for the correct operation of the device.
ISPU_CALL_
ALGO_26
ISPU_CALL_
ALGO_25
ISPU_CALL_
ALGO_24
ISPU_CALL_
ALGO_23
Table 280. ISPU_CALL_EN register description
ISPU_CALL_ALGO_[29:0]
If bit i=1, IRQ is generated for the execution of ISPU_ALGO_(i-1). After it is written to 1, it remains at 1 until the ISPU_ALGO_(i-1) routine is completed.
DS13892 - Rev 2 page 75/107
13.14
LSM6DSO16IS
ISPU_DTIME_0_L (6948h), ISPU_DTIME_0_H (6949h), ISPU_DTIME_1_L (694Ah), ISPU_DTIME_1_H (694Bh)
ISPU_DTIME_0_L (6948h), ISPU_DTIME_0_H (6949h), ISPU_DTIME_1_L
(694Ah), ISPU_DTIME_1_H (694Bh)
ISPU read access (6948h, 6949h, 694Ah, 694Bh)
ISPU_
DTIME_7
ISPU_
DTIME_6
Table 281. ISPU_DTIME_0_L output register
ISPU_
DTIME_5
ISPU_
DTIME_4
ISPU_
DTIME_3
ISPU_
DTIME_2
ISPU_
DTIME_1
ISPU_
DTIME_0
ISPU_
DTIME_15
ISPU_
DTIME_14
Table 282. ISPU_DTIME_0_H output register
ISPU_
DTIME_13
ISPU_
DTIME_12
ISPU_
DTIME_11
ISPU_
DTIME_10
ISPU_
DTIME_9
ISPU_
DTIME_8
ISPU_
DTIME_23
ISPU_
DTIME_22
Table 283. ISPU_DTIME_1_L output register
ISPU_
DTIME_21
ISPU_
DTIME_20
ISPU_
DTIME_19
ISPU_
DTIME_18
ISPU_
DTIME_17
ISPU_
DTIME_16
ISPU_
DTIME_31
ISPU_
DTIME_30
Table 284. ISPU_DTIME_1_H output register
ISPU_
DTIME_29
ISPU_
DTIME_28
ISPU_
DTIME_27
ISPU_
DTIME_26
ISPU_
DTIME_25
ISPU_
DTIME_24
Table 285. ISPU_DTIME output register description
ISPU_DTIME_[31:0]
Actual delta time at 104 Hz (expressed in seconds): it is represented as a single precision floating-point number.
DS13892 - Rev 2 page 76/107
14
LSM6DSO16IS
Sensor hub register mapping
Sensor hub register mapping
Name
SENSOR_HUB_1
SENSOR_HUB_2
SENSOR_HUB_3
SENSOR_HUB_4
SENSOR_HUB_5
SENSOR_HUB_6
SENSOR_HUB_7
SENSOR_HUB_8
SENSOR_HUB_9
SENSOR_HUB_10
SENSOR_HUB_11
SENSOR_HUB_12
SENSOR_HUB_13
SENSOR_HUB_14
SENSOR_HUB_15
SENSOR_HUB_16
SENSOR_HUB_17
SENSOR_HUB_18
MASTER_CONFIG
SLV0_ADD
SLV0_SUBADD
SLV0_CONFIG
SLV1_ADD
SLV1_SUBADD
SLV1_CONFIG
SLV2_ADD
SLV2_SUBADD
SLV2_CONFIG
SLV3_ADD
SLV3_SUBADD
SLV3_CONFIG
DATAWRITE_SLV0
STATUS_MASTER
The table given below provides a list of the registers for the sensor hub functions available in the device and the corresponding addresses. The sensor hub registers are accessible when bit SHUB_REG_ACCESS is set to 1 in
R
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
Table 286. Registers address map
Type
16
17
18
19
1A
13
14
15
10
11
12
1E
1F
20
1B
1C
1D
21
22
0B
0C
0D
0E
0F
08
09
0A
05
06
07
Hex
Register address
Binary
02
03
04
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
00010000
00010001
00010010
00010011
00010100
00010101
00010110
00010111
00011000
00011001
00011010
00011011
00011100
00011101
00011110
00011111
00100000
00100001
00100010
Comment Default output output output output output output output output output
00000000
00000000 output output output output output output output output output
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000 output
Reserved registers must not be changed. Writing to those registers may cause permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
DS13892 - Rev 2 page 77/107
15
15.1
15.2
15.3
LSM6DSO16IS
Sensor hub register description
Sensor hub register description
SENSOR_HUB_1 (02h)
Sensor hub output register (R)
First byte associated to external sensors. The content of the register is consistent with the SLVx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub1_7
Sensor
Hub1_6
Table 287. SENSOR_HUB_1 register
Sensor
Hub1_5
Sensor
Hub1_4
Sensor
Hub1_3
Sensor
Hub1_2
Sensor
Hub1_1
Sensor
Hub1_0
SensorHub1_[7:0]
Table 288. SENSOR_HUB_1 register description
First byte associated to external sensors.
SENSOR_HUB_2 (03h)
Sensor hub output register (R)
Second byte associated to external sensors. The content of the register is consistent with the SLVx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub2_7
Sensor
Hub2_6
Table 289. SENSOR_HUB_2 register
Sensor
Hub2_5
Sensor
Hub2_4
Sensor
Hub2_3
Sensor
Hub2_2
Sensor
Hub2_1
Sensor
Hub2_0
SensorHub2_[7:0]
Table 290. SENSOR_HUB_2 register description
Second byte associated to external sensors.
SENSOR_HUB_3 (04h)
Sensor hub output register (R)
Third byte associated to external sensors. The content of the register is consistent with the SLVx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub3_7
Sensor
Hub3_6
Table 291. SENSOR_HUB_3 register
Sensor
Hub3_5
Sensor
Hub3_4
Sensor
Hub3_3
Sensor
Hub3_2
Sensor
Hub3_1
Sensor
Hub3_0
SensorHub3_[7:0]
Table 292. SENSOR_HUB_3 register description
Third byte associated to external sensors.
DS13892 - Rev 2 page 78/107
15.4
15.5
15.6
LSM6DSO16IS
SENSOR_HUB_4 (05h)
SENSOR_HUB_4 (05h)
Sensor hub output register (R)
Fourth byte associated to external sensors. The content of the register is consistent with the SLVx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub4_7
Sensor
Hub4_6
Table 293. SENSOR_HUB_4 register
Sensor
Hub4_5
Sensor
Hub4_4
Sensor
Hub4_3
Sensor
Hub4_2
Sensor
Hub4_1
Sensor
Hub4_0
SensorHub4_[7:0]
Table 294. SENSOR_HUB_4 register description
Fourth byte associated to external sensors.
SENSOR_HUB_5 (06h)
Sensor hub output register (R)
Fifth byte associated to external sensors. The content of the register is consistent with the SLVx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub5_7
Sensor
Hub5_6
Table 295. SENSOR_HUB_5 register
Sensor
Hub5_5
Sensor
Hub5_4
Sensor
Hub5_3
Sensor
Hub5_2
Sensor
Hub5_1
Sensor
Hub5_0
SensorHub5_[7:0]
Table 296. SENSOR_HUB_5 register description
Fifth byte associated to external sensors.
SENSOR_HUB_6 (07h)
Sensor hub output register (R)
Sixth byte associated to external sensors. The content of the register is consistent with the SLVx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub6_7
Sensor
Hub6_6
Table 297. SENSOR_HUB_6 register
Sensor
Hub6_5
Sensor
Hub6_4
Sensor
Hub6_3
Sensor
Hub6_2
Sensor
Hub6_1
Sensor
Hub6_0
SensorHub6_[7:0]
Table 298. SENSOR_HUB_6 register description
Sixth byte associated to external sensors.
DS13892 - Rev 2 page 79/107
15.7
15.8
15.9
LSM6DSO16IS
SENSOR_HUB_7 (08h)
SENSOR_HUB_7 (08h)
Sensor hub output register (R)
Seventh byte associated to external sensors. The content of the register is consistent with the SLVx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub7_7
Sensor
Hub7_6
Table 299. SENSOR_HUB_7 register
Sensor
Hub7_5
Sensor
Hub7_4
Sensor
Hub7_3
Sensor
Hub7_2
Sensor
Hub7_1
Sensor
Hub7_0
SensorHub7_[7:0]
Table 300. SENSOR_HUB_7 register description
Seventh byte associated to external sensors.
SENSOR_HUB_8 (09h)
Sensor hub output register (R)
Eighth byte associated to external sensors. The content of the register is consistent with the SLVx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub8_7
Sensor
Hub8_6
Table 301. SENSOR_HUB_8 register
Sensor
Hub8_5
Sensor
Hub8_4
Sensor
Hub8_3
Sensor
Hub8_2
Sensor
Hub8_1
Sensor
Hub8_0
SensorHub8_[7:0]
Table 302. SENSOR_HUB_8 register description
Eighth byte associated to external sensors.
SENSOR_HUB_9 (0Ah)
Sensor hub output register (R)
Ninth byte associated to external sensors. The content of the register is consistent with the SLVx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub9_7
Sensor
Hub9_6
Table 303. SENSOR_HUB_9 register
Sensor
Hub9_5
Sensor
Hub9_4
Sensor
Hub9_3
Sensor
Hub9_2
Sensor
Hub9_1
Sensor
Hub9_0
SensorHub9_[7:0]
Table 304. SENSOR_HUB_9 register description
Ninth byte associated to external sensors.
DS13892 - Rev 2 page 80/107
15.10
15.11
15.12
LSM6DSO16IS
SENSOR_HUB_10 (0Bh)
SENSOR_HUB_10 (0Bh)
Sensor hub output register (R)
Tenth byte associated to external sensors. The content of the register is consistent with the SLVx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub10_7
Sensor
Hub10_6
Table 305. SENSOR_HUB_10 register
Sensor
Hub10_5
Sensor
Hub10_4
Sensor
Hub10_3
Sensor
Hub10_2
Sensor
Hub10_1
Sensor
Hub10_0
SensorHub10_[7:0]
Table 306. SENSOR_HUB_10 register description
Tenth byte associated to external sensors.
SENSOR_HUB_11 (0Ch)
Sensor hub output register (R)
Eleventh byte associated to external sensors. The content of the register is consistent with the SLVx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub11_7
Sensor
Hub11_6
Table 307. SENSOR_HUB_11 register
Sensor
Hub11_5
Sensor
Hub11_4
Sensor
Hub11_3
Sensor
Hub11_2
Sensor
Hub11_1
Sensor
Hub11_0
SensorHub11_[7:0]
Table 308. SENSOR_HUB_11 register description
Eleventh byte associated to external sensors.
SENSOR_HUB_12 (0Dh)
Sensor hub output register (R)
Twelfth byte associated to external sensors. The content of the register is consistent with the SLVx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub12_7
Sensor
Hub12_6
Table 309. SENSOR_HUB_12 register
Sensor
Hub12_5
Sensor
Hub12_4
Sensor
Hub12_3
Sensor
Hub12_2
Sensor
Hub12_1
Sensor
Hub12_0
SensorHub12_[7:0]
Table 310. SENSOR_HUB_12 register description
Twelfth byte associated to external sensors.
DS13892 - Rev 2 page 81/107
15.13
15.14
15.15
LSM6DSO16IS
SENSOR_HUB_13 (0Eh)
SENSOR_HUB_13 (0Eh)
Sensor hub output register (R)
Thirteenth byte associated to external sensors. The content of the register is consistent with the SLVx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub13_7
Sensor
Hub13_6
Table 311. SENSOR_HUB_13 register
Sensor
Hub13_5
Sensor
Hub13_4
Sensor
Hub13_3
Sensor
Hub13_2
Sensor
Hub13_1
Sensor
Hub13_0
SensorHub13_[7:0]
Table 312. SENSOR_HUB_13 register description
Thirteenth byte associated to external sensors.
SENSOR_HUB_14 (0Fh)
Sensor hub output register (R)
Fourteenth byte associated to external sensors. The content of the register is consistent with the SLVx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub14_7
Sensor
Hub14_6
Table 313. SENSOR_HUB_14 register
Sensor
Hub14_5
Sensor
Hub14_4
Sensor
Hub14_3
Sensor
Hub14_2
Sensor
Hub14_1
Sensor
Hub14_0
SensorHub14_[7:0]
Table 314. SENSOR_HUB_14 register description
Fourteenth byte associated to external sensors.
SENSOR_HUB_15 (10h)
Sensor hub output register (R)
Fifteenth byte associated to external sensors. The content of the register is consistent with the SLVx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub15_7
Sensor
Hub15_6
Table 315. SENSOR_HUB_15 register
Sensor
Hub15_5
Sensor
Hub15_4
Sensor
Hub15_3
Sensor
Hub15_2
Sensor
Hub15_1
Sensor
Hub15_0
SensorHub15_[7:0]
Table 316. SENSOR_HUB_15 register description
Fifteenth byte associated to external sensors.
DS13892 - Rev 2 page 82/107
15.16
15.17
15.18
LSM6DSO16IS
SENSOR_HUB_16 (11h)
SENSOR_HUB_16 (11h)
Sensor hub output register (R)
Sixteenth byte associated to external sensors. The content of the register is consistent with the SLVx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub16_7
Sensor
Hub16_6
Table 317. SENSOR_HUB_16 register
Sensor
Hub16_5
Sensor
Hub16_4
Sensor
Hub16_3
Sensor
Hub16_2
Sensor
Hub16_1
Sensor
Hub16_0
SensorHub16_[7:0]
Table 318. SENSOR_HUB_16 register description
Sixteenth byte associated to external sensors.
SENSOR_HUB_17 (12h)
Sensor hub output register (R)
Seventeenth byte associated to external sensors. The content of the register is consistent with the SLVx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub17_7
Sensor
Hub17_6
Table 319. SENSOR_HUB_17 register
Sensor
Hub17_5
Sensor
Hub17_4
Sensor
Hub17_3
Sensor
Hub17_2
Sensor
Hub17_1
Sensor
Hub17_0
SensorHub17_[7:0]
Table 320. SENSOR_HUB_17 register description
Seventeenth byte associated to external sensors.
SENSOR_HUB_18 (13h)
Sensor hub output register (R)
Eighteenth byte associated to external sensors. The content of the register is consistent with the SLVx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Sensor
Hub18_7
Sensor
Hub18_6
Table 321. SENSOR_HUB_18 register
Sensor
Hub18_5
Sensor
Hub18_4
Sensor
Hub18_3
Sensor
Hub18_2
Sensor
Hub18_1
Sensor
Hub18_0
SensorHub18_[7:0]
Table 322. SENSOR_HUB_18 register description
Eighteenth byte associated to external sensors.
DS13892 - Rev 2 page 83/107
15.19
LSM6DSO16IS
MASTER_CONFIG (14h)
MASTER_CONFIG (14h)
Master configuration register (R/W)
RST_MASTER
_REGS
WRITE_
ONCE
Table 323. MASTER_CONFIG register
START_
CONFIG
PASS_THROUGH
_MODE
SHUB_
PU_EN
MASTER
_ON
AUX_SENS
_ON_1
AUX_SENS
_ON_0
Table 324. MASTER_CONFIG register description
RST_MASTER_REGS
WRITE_ONCE
START_CONFIG
PASS_THROUGH_MODE
SHUB_PU_EN
MASTER_ON
AUX_SENS_ON_[1:0]
Resets master logic and output registers. Must be set to 1 and then set it to 0. Default value: 0
Slave 0 write operation is performed only at the first sensor hub cycle.
Default value: 0
(0: write operation for each sensor hub cycle;
1: write operation only for the first sensor hub cycle)
Selects sensor hub trigger signal. Default value: 0
(0: sensor hub trigger signal is the accelerometer/gyro data-ready;
1: sensor hub trigger signal is external to INT2 pin)
I²C interface pass-through. Default value: 0
(0: pass-through disabled;
1: pass-through enabled, main I²C line is short-circuited with the auxiliary line)
Enables master I²C pull-up. Default value: 0
(0: internal pull-up on auxiliary I²C line disabled;
1: internal pull-up on auxiliary I²C line enabled)
Enables sensor hub I²C master. Default: 0
(0: master I²C of sensor hub disabled; 1: master I²C of sensor hub enabled)
Number of external sensors to be read by the sensor hub.
(00: one sensor;
01: two sensors;
10: three sensors;
11: four sensors)
DS13892 - Rev 2 page 84/107
15.20
15.21
15.22
LSM6DSO16IS
SLV0_ADD (15h)
SLV0_ADD (15h)
I²C slave address of the first external sensor (sensor 1) register (R/W) slave0_ add6 slave0_ add5 slave0_ add4
Table 325. SLV0_ADD register slave0_ add3 slave0_ add2 slave0_ add1 slave0_ add0 rw_0 slave0_add[6:0] rw_0
Table 326. SLV0_ADD register description
I²C slave address of sensor 1 that can be read by the sensor hub.
Default value: 0000000
Read/write operation on sensor 1. Default value: 0
(0: write operation; 1: read operation)
SLV0_SUBADD (16h)
Address of register on the first external sensor (sensor 1) register (R/W) slave0_ reg7 slave0_ reg6 slave0_ reg5
Table 327. SLV0_SUBADD register slave0_ reg4 slave0_ reg3 slave0_ reg2 slave0_ reg1 slave0_ reg0
Table 328. SLV0_SUBADD register description slave0_reg[7:0]
Address of register on sensor1 that has to be read/written according to the rw_0 bit value in
(15h) . Default value: 00000000
SLV0_CONFIG (17h)
First external sensor (sensor 1) configuration and sensor hub settings register (R/W)
Table 329. SLV0_CONFIG register
SHUB_
ODR_1
SHUB_
ODR_0
0
0
1. This bit must be set to 0 for the correct operation of the device.
0
Slave0_ numop2
Slave0_ numop1
SHUB_ODR_[1:0]
Slave0_numop[2:0]
Table 330. SLV0_CONFIG register description
Rate at which the master communicates. Default value: 00
(00: 104 Hz (or at the maximum ODR between the accelerometer and gyro if it is less than 104 Hz);
01: 52 Hz (or at the maximum ODR between the accelerometer and gyro if it is less than 52 Hz);
10: 26 Hz (or at the maximum ODR between the accelerometer and gyro if it is less than 26 Hz);
11: 12.5 Hz (or at the maximum ODR between the accelerometer and gyro if it is less than 12.5 Hz)
Number of read operations on sensor 1. Default value: 000
Slave0_ numop0
DS13892 - Rev 2 page 85/107
15.23
15.24
15.25
LSM6DSO16IS
SLV1_ADD (18h)
SLV1_ADD (18h)
I²C slave address of the second external sensor (sensor 2) register (R/W)
Slave1_ add6
Slave1_ add5
Slave1_ add4
Table 331. SLV1_ADD register
Slave1_ add3
Slave1_ add2
Slave1_ add1
Slave1_ add0 r_1
Slave1_add[6:0] r_1
Table 332. SLV1_ADD register description
I²C slave address of sensor 2 that can be read by the sensor hub.
Default value: 0000000
Enables read operation on sensor 2. Default value: 0
(0: read operation disabled; 1: read operation enabled)
SLV1_SUBADD (19h)
Address of register on the second external sensor (sensor 2) register (R/W)
Slave1_ reg7
Slave1_ reg6
Slave1_ reg5
Table 333. SLV1_SUBADD register
Slave1_ reg4
Slave1_ reg3
Slave1_ reg2
Slave1_ reg1
Slave1_ reg0
Table 334. SLV1_SUBADD register description
.
SLV1_CONFIG (1Ah)
Second external sensor (sensor 2) configuration register (R/W)
0
0
0
Table 335. SLV1_CONFIG register
0
0
Slave1_ numop2
1. This bit must be set to 0 for the correct operation of the device.
Slave1_ numop1
Slave1_ numop0
Slave1_numop[2:0]
Table 336. SLV1_CONFIG register description
Number of read operations on sensor 2. Default value: 000
DS13892 - Rev 2 page 86/107
15.26
15.27
15.28
LSM6DSO16IS
SLV2_ADD (1Bh)
SLV2_ADD (1Bh)
I²C slave address of the third external sensor (sensor 3) register (R/W)
Slave2_ add6
Slave2_ add5
Slave2_ add4
Table 337. SLV2_ADD register
Slave2_ add3
Slave2_ add2
Slave2_ add1
Slave2_ add0 r_2
Slave2_add[6:0] r_2
Table 338. SLV2_ADD register description
I²C slave address of sensor 3 that can be read by the sensor hub.
Enables read operation on sensor 3. Default value: 0
(0: read operation disabled; 1: read operation enabled)
SLV2_SUBADD (1Ch)
Address of register on the third external sensor (sensor 3) register (R/W)
Slave2_ reg7
Slave2_ reg6
Slave2_ reg5
Table 339. SLV2_SUBADD register
Slave2_ reg4
Slave2_ reg3
Slave2_ reg2
Slave2_ reg1
Slave2_ reg0
Table 340. SLV2_SUBADD register description
Slave2_reg[7:0]
.
SLV2_CONFIG (1Dh)
Third external sensor (sensor 3) configuration register (R/W)
0
0
0
Table 341. SLV2_CONFIG register
0
0
Slave2_ numop2
1. This bit must be set to 0 for the correct operation of the device.
Slave2_numop[2:0]
Table 342. SLV2_CONFIG register description
Number of read operations on sensor 3. Default value: 000
Slave2_ numop1
Slave2_ numop0
DS13892 - Rev 2 page 87/107
15.29
15.30
15.31
LSM6DSO16IS
SLV3_ADD (1Eh)
SLV3_ADD (1Eh)
I²C slave address of the fourth external sensor (sensor 4) register (R/W)
Slave3_ add6
Slave3_ add5
Slave3_ add4
Table 343. SLV3_ADD register
Slave3_ add3
Slave3_ add2
Slave3_ add1
Slave3_ add0 r_3
Slave3_add[6:0] r_3
Table 344. SLV3_ADD register description
I²C slave address of sensor 4 that can be read by the sensor hub.
Enables read operation on sensor 4. Default value: 0
(0: read operation disabled; 1: read operation enabled)
SLV3_SUBADD (1Fh)
Address of register on the fourth external sensor (sensor 4) register (R/W)
Slave3_ reg7
Slave3_ reg6
Slave3_ reg5
Table 345. SLV3_SUBADD register
Slave3_ reg4
Slave3_ reg3
Slave3_ reg2
Slave3_ reg1
Slave3_ reg0
Table 346. SLV3_SUBADD register description
Slave3_reg[7:0] Address of register on sensor 4 that has to be read according to the r_3 bit value in
.
SLV3_CONFIG (20h)
Fourth external sensor (sensor 4) configuration register (R/W)
0
0
0
Table 347. SLV3_CONFIG register
0
0
Slave3_ numop2
1. This bit must be set to 0 for the correct operation of the device.
Slave3_ numop1
Slave3_ numop0
Slave3_numop[2:0]
Table 348. SLV3_CONFIG register description
Number of read operations on sensor 4. Default value: 000
DS13892 - Rev 2 page 88/107
15.32
15.33
LSM6DSO16IS
DATAWRITE_SLV0 (21h)
DATAWRITE_SLV0 (21h)
Data to be written into the slave device register (R/W)
Slave0_ dataw7
Slave0_ dataw6
Table 349. DATAWRITE_SLV0 register
Slave0_ dataw5
Slave0_ dataw4
Slave0_ dataw3
Slave0_ dataw2
Slave0_ dataw1
Slave0_ dataw0
Slave0_dataw[7:0]
Table 350. DATAWRITE_SLV0 register description
Data to be written into the slave 0 device according to the rw_0 bit in register SLV0_ADD (15h)
.
Default value: 00000000
STATUS_MASTER (22h)
Sensor hub source register (R)
WR_ONCE
_DONE
SLAVE3_
NACK
Table 351. STATUS_MASTER register
SLAVE2_
NACK
SLAVE1_
NACK
SLAVE0_
NACK
0 0
SENS_HUB
_ENDOP
Table 352. STATUS_MASTER register description
WR_ONCE_DONE
SLAVE3_NACK
SLAVE2_NACK
When the bit WRITE_ONCE in
is configured as 1, this bit is set to 1 when the write operation on slave 0 has been performed and completed. Default value: 0
This bit is set to 1 if Not acknowledge occurs on slave 3 communication. Default value: 0
This bit is set to 1 if Not acknowledge occurs on slave 2 communication. Default value: 0
SLAVE1_NACK This bit is set to 1 if Not acknowledge occurs on slave 1 communication. Default value: 0
SLAVE0_NACK This bit is set to 1 if Not acknowledge occurs on slave 0 communication. Default value: 0
SENS_HUB_ENDOP
Sensor hub communication status. Default value: 0
(0: sensor hub communication not concluded;
1: sensor hub communication concluded)
DS13892 - Rev 2 page 89/107
16
16.1
16.2
LSM6DSO16IS
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
Soldering information
The LGA package is compliant with the ECOPACK and RoHS standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
For land pattern and soldering recommendations, consult technical note TN0018 available on www.st.com
.
LGA-14L package information
Figure 17. LGA-14L 2.5 x 3.0 x 0.86 mm package outline and mechanical data
W C H 0.5
Pin1 indicator
4x (0.1)
Pin 1 indicator
14x
0.25±0.05
TOP VIEW
1
BOTTOM VIEW
14x 0.475±0.05
0.05 C
ITEM
L
W e i d n g t t h h
[
[ L
W ]
]
H e i g h t [ H ]
Dimensions are in millimeter unless otherwise specified
General tolerance is +/-0.1mm unless otherwise specified
OUTER DIMENSIONS
DIMENSION [mm]
2
3
0
.
.
5
0
.
8
0
0
6
TOLERANCE [mm]
± 0
± 0
.
.
1
1
M A X
DM00249496_5
DS13892 - Rev 2 page 90/107
16.3
LGA-14 packing information
Figure 18. Carrier tape information for LGA-14 package
LSM6DSO16IS
LGA-14 packing information
Figure 19. LGA-14 package orientation in carrier tape
DS13892 - Rev 2 page 91/107
DS13892 - Rev 2
A
LSM6DSO16IS
LGA-14 packing information
Figure 20. Reel information for carrier tape of LGA-14 package
T
40mm min.
Access hole at slot location
B
C
D N
Full radius
G measured at hub
Tape slot in core for tape start
2.5mm min. width
Table 353. Reel dimensions for carrier tape of LGA-14 package
Reel dimensions (mm)
A (max)
B (min)
C
D (min)
N (min)
G
T (max)
330
1.5
13 ±0.25
20.2
60
12.4 +2/-0
18.4
page 92/107
Revision history
Date
22-Dec-2021
01-Jun-2022
Table 354. Document revision history
Version
1
2
Initial release
First public release
Changes
LSM6DSO16IS
DS13892 - Rev 2 page 93/107
LSM6DSO16IS
Contents
Contents
DS13892 - Rev 2 page 94/107
LSM6DSO16IS
Contents
ISPU_INT_STATUS0_MAINPAGE (1Ah), ISPU_INT_STATUS1_MAINPAGE (1Bh),
ISPU_INT_STATUS2_MAINPAGE (1Ch), ISPU_INT_STATUS3_MAINPAGE (1Dh) . . . . . . 39
TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h) 45
ISPU_DUMMY_CFG_1_L (73h) and ISPU_DUMMY_CFG_1_H (74h) . . . . . . . . . . . . . . . . . 47
ISPU_DUMMY_CFG_2_L (75h) and ISPU_DUMMY_CFG_2_H (76h) . . . . . . . . . . . . . . . . . 47
ISPU_DUMMY_CFG_3_L (77h) and ISPU_DUMMY_CFG_3_H (78h) . . . . . . . . . . . . . . . . 48
ISPU_DUMMY_CFG_4_L (79h) and ISPU_DUMMY_CFG_4_H (7Ah) . . . . . . . . . . . . . . . . 49
DS13892 - Rev 2 page 95/107
LSM6DSO16IS
Contents
DS13892 - Rev 2 page 96/107
LSM6DSO16IS
Contents
ISPU_INT1_CTRL0 (50h), ISPU_INT1_CTRL1 (51h), ISPU_INT1_CTRL2 (52h),
ISPU_INT2_CTRL0 (54h), ISPU_INT2_CTRL1 (55h), ISPU_INT2_CTRL2 (56h),
ISPU_INT_STATUS0 (58h), ISPU_INT_STATUS1 (59h), ISPU_INT_STATUS2 (5Ah),
ISPU_ALGO0 (70h), ISPU_ALGO1 (71h), ISPU_ALGO2 (72h), ISPU_ALGO3 (73h). . . . . 69
ISPU_CALL_EN_0 (68B8h), ISPU_CALL_EN_1 (68B9h), ISPU_CALL_EN_2 (68BAh),
ISPU_DTIME_0_L (6948h), ISPU_DTIME_0_H (6949h), ISPU_DTIME_1_L (694Ah),
DS13892 - Rev 2 page 97/107
LSM6DSO16IS
Contents
DS13892 - Rev 2 page 98/107
LSM6DSO16IS
List of tables
List of tables
DS13892 - Rev 2 page 99/107
LSM6DSO16IS
List of tables
DS13892 - Rev 2 page 100/107
LSM6DSO16IS
List of tables
DS13892 - Rev 2 page 101/107
LSM6DSO16IS
List of tables
DS13892 - Rev 2 page 102/107
LSM6DSO16IS
List of tables
DS13892 - Rev 2 page 103/107
LSM6DSO16IS
List of tables
DS13892 - Rev 2 page 104/107
LSM6DSO16IS
List of tables
DS13892 - Rev 2 page 105/107
LSM6DSO16IS
List of figures
List of figures
DS13892 - Rev 2 page 106/107
LSM6DSO16IS
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DS13892 - Rev 2 page 107/107
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