STMicroelectronics L99VR02J Datasheet
Annonce
Annonce
L99VR02J
Datasheet
Automotive linear voltage regulator with configurable output voltage having 500 mA current capability
Product status link
L99VR02J
Product summary
Order code
Package
Packing
L99VR02JTR
PowerSSO-12
Tape and reel
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Features
Max. supply voltage (load dump)
Max. output voltage tolerance
Output current
Quiescent current
1. Maximum value with regulator disabled
V
S
ΔV
O
I
O
I qn
40 V
+/-2%
500 mA
AEC-Q100 qualified
Operating DC power supply voltage range from 2.15 V to 28 V
Battery and post regulation operating modes are allowed
Low dropout voltage
Low quiescent current consumption
User-selectable output voltage (0.8 V; 1.2 V; 1.5 V; 1.8 V; 2.5 V; 2.8 V; 3.3 V or
5 V)
Output voltage precision ±2%
Enable input for enabling/disabling the voltage regulator
Output voltage monitoring with reset output
Negligible ESR effect on output voltage stability for load capacitor
Programmable autonomous watchdog through external capacitor
Undervoltage lockout UVLO
Fast output discharge
Thermal shutdown and short-circuit current limitation
Advanced thermal warning and output overvoltage diagnostic
Programmable short-circuit output current
Wide operating temperature range (T
J
= -40 °C to 175 °C)
Limited documentation available for customers that need support when dealing with ASIL requirements as per ISO 26262
DS14076 - Rev 1 - December 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
L99VR02J
Description
L99VR02J is a low dropout linear voltage regulator designed for automotive applications available in
PowerSSO-12 packages. The LDO delivers up to 500 mA of load current. It consumes as low as 1 μA of quiescent current when the regulator is disabled. The input is 40 V tolerant to withstand load dump, while the operating input voltage range is between 2.15 V and 28 V.
The L99VR02J can be configured, through SELx pins, to generate a fixed selectable output voltage (0.8 V; 1.2 V;
1.5 V; 1.8 V; 2.5 V; 2.8 V; 3.3 V or 5 V). High output voltage accuracy (±2%) is kept over wide temperature range, line, and load variation.
The L99VR02J features enable, reset, autonomous watchdog, advanced thermal warning, fast output discharge, and I short
control. The regulator output current is internally limited. The device is protected against short-circuit and overload, besides it features over temperature protection. The short current value is configurable by an external resistance.
The L99VR02J can operate both in post regulation, attached to a preregulated voltage or directly connected to the battery.
DS14076 - Rev 1 page 2/38
1
Ishort
Vcw
Wi
L99VR02J
Block diagram and pins description
Block diagram and pins description
Figure 1. Functional block diagram of L99VR02J
Vs Vo
RFD=
75 W
START-UP
EN
VOLTAGE
REFERENCE
THERMAL
SHUTDOWN POWER DRIVER
CURRENT LIMITER
+
-
OUTPUT
VOLTAGE
SELECTOR
SEL1
SEL2
SEL3
WATCHDOG
LOW VOLTAGE RESET
RST
TW
ADVANCED
THERMAL WARNING
GND
DS14076 - Rev 1 page 3/38
DS14076 - Rev 1
Pin name
V
S
SEL1
SEL2
SEL3
TW
I
Short
EN
GND
V
CW
Wi
RST
V
O
TAB
L99VR02J
Block diagram and pins description
Table 1. Pins description
PowerSSO-12 pin
1
Function
Supply voltage.
Block directly to the ground with ceramic capacitor ≥ 4.7 µF and a 100 nF capacitator as close as possible to the pin
2
3
4
Output voltage selectors.
5
6
7
8
9
10
11
12
TAB
Advanced thermal warning output.
If the device detects a junction temperature above the warning threshold, the pin is pulled low. If an overvoltage condition occurs, a square wave is provided through the TW output. Leave floating if not used.
Programmable short circuit output current input pin. A resistor between Ishort pin and GND sets the short circuit output current value.
•
•
Enable input:
With the enable high: Regulator, watchdog, and reset are operating
With the enable low: Regulator, watchdog, and reset are shutdown, while the fast discharge circuit is turned on
Connect the enable to V
S
to keep the device always enabled
Ground reference.
Watchdog timer adjusts.
A capacitor between V
CW monitor.
pin and GND sets the time response of the watchdog
Watchdog refresh input.
If the square wave frequency at this input pin is too low, a low pulse at an RST pin is generated.
Reset output.
It is pulled down when the output voltage goes below Vo_th or the frequency at Wi is too low. Leave floating if not used.
Voltage regulator output.
Block to ground with a capacitor ≥ 3.3 µF (needed for regulator stability).
Connected to ground
Figure 2. Pins configuration
PowerSSO-12 page 4/38
2
2.1
L99VR02J
Electrical specifications
Electrical specifications
Absolute maximum ratings
Stressing the device above the rating listed in the
Table 2. Absolute maximum ratings may damage to the device
permanently. These are stress ratings only. Operations of the device under conditions above those stated in this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Symbol
V
S
V
S
I
S
V
O
I
O
V
WI
V
CW
V rst
I rst
V tw
I tw
V sh_ctrl
V
EN
V
SELx
VESD HBM
VESD CDM
Table 2. Absolute maximum ratings
Parameter
DC supply voltage
Single pulse / tmax < 400 ms “transient load dump”
Input current
DC output voltage
DC output current
Watchdog input voltage
Watchdog delay voltage
Reset output voltage
Reset output current
Thermal warning output voltage
Thermal warning output current
“Short current” control voltage
Enable input
Selectors input voltage
ESD HBM voltage level (HBM-MIL STD 883C)
ESD CDM voltage level (CDM AEC-Q100-011)
ESD CDM voltage level on corner pins (CDM
AEC-Q100-011)
Value
-0.3 to 28
40
±750 internally limited
-0.3 to 6 internally limited
-0.3 to V
O
+ 0.3
- 0.3 to V
O
+ 0.3
-0.3 to V
O
+ 0.3
Internally limited
-0.3 to V
O
+ 0.3
Internally limited
-0.3 to 3.6
-0.3 to V
S
+ 0.3
-0.3 to V
S
+ 0.3
±2
±500
Unit
V
V
V
V
V
V kV
V
V
V
V
V
V
DS14076 - Rev 1 page 5/38
2.2
2.2.1
Note:
2.2.2
L99VR02J
Thermal data
Thermal data
Thermal resistance
Item
A.001
A.002
A.003
Symbol
R thj-case
R thj-PCB
R thj-amb
1. Measured on the bottom.
2. Standard JEDEC 51.8.
3. Measured on four layers.
Table 3. Operation junction temperature
Parameter
Junction to case thermal resistance
Junction to PCB thermal resistance
Junction to ambient thermal resistance
Value
8
10
25.5
Unit
°C/W
°C/W
°C/W
The values quoted are for PCB 77 mm x 86 mm x 1.6 mm, FR4, four layers; Cu thickness 0.070 mm
(outer layers). Cu thickness 0.035 mm (inner layers), thermal vias separation 1.2 mm, thermal via diameter
0.3 mm +/-0.08 mm, Cu thickness on vias 0.025 mm, footprint dimension 2.2 mm x 2.9 mm.
Thermal protection
Table 4. Temperature threshold
Item
A.004
A.005
A.006
A.007
Symbol
T prot
T prot_hyst
T
J
T stg
Parameter
Thermal protection temperature
Thermal protection hysteresis
Operating junction temperature
Storage temperature
1. Thermal protection is guaranteed by design and characterization.
Test condition
T
T
J stg
Min.
175
-40
Typ.
Max.
205
11
175
150
Unit
°C
°C
°C
°C
DS14076 - Rev 1 page 6/38
2.3
L99VR02J
Electrical characteristics
Electrical characteristics
Values specified in this section are for V
S
= 2.15 V to 18 V, T
J
= - 40 °C to +150 °C, unless otherwise stated.
Item
A.008
V
O
A.009
V
O
A.010
V
O
A.011
Pin
V
O
A.012
V
S
, V
O
Symbol
V
O
I
O
I short
I short
∆V
O
/ V
O
Table 5. Electrical characteristics
Parameter
Output voltage
DC output current
Short-circuit current lower value
Short-circuit current upper value
Static line regulation
Test condition
V
S
= 2.15 to 18 V,
I
O
= 1 to 500 mA,
SEL_CONF = [0;0;0]
V
S
= 2.15 to 18 V,
I
O
= 1 to 500 mA,
SEL_CONF = [0;0;1]
V
S
= 2.15 to 18 V,
I
O
= 1 to 500 mA,
SEL_CONF = [0;1;0]
V
S
= 2.45 to 18 V,
I
O
= 1 to 500 mA,
SEL_CONF = [0;1;1]
V
S
= 3.15 to 18 V,
I
O
= 1 to 500 mA,
SEL_CONF = [1;0;0]
V
S
= 3.45 to 18 V,
I
O
= 1 to 500 mA,
SEL_CONF = [1;0;1]
V
S
= 3.95 to 18 V,
I
O
= 1 to 500 mA,
SEL_CONF = [1;1;0]
V
S
= 5.65 to 18 V,
I
O
= 1 to 500 mA,
SEL_CONF = [1;1;1]
V
O
= 0.8 V; 1.2 V, 1.5 V;
1.8 V; 2.5 V; 2.8 V; 3.3 V;
5 V
V
S
= 4 V for V
O
= 3.3 V,
V
S
= 5.8 V for V
O
= 5 V, with I short pin connected to GND
I
V
S
V
S
= 4 V for V
O
= 3.3 V,
= 5.8 V for V
O
= 5
V, with I short
pin floating; short
> I
O
V
S
is from V
S_Low
to
18 V, I
O
500 mA,
= 1 mA; 250 mA;
V
O
= 3.3 V; 5 V
Min.
0.784
0.8
0.816
1.176
1.2
1.224
1.470
1.5
1.530
1.764
1.8
1.836
2.450
2.5
2.550
2.744
2.8
2.856
3.234
3.3
3.366
4.9
120
545
Typ.
5
220
815
Max.
5.1
500
320
1085
1
Unit
V mA mA mA
%
DS14076 - Rev 1 page 7/38
DS14076 - Rev 1
L99VR02J
Electrical characteristics
Item
A.012
A.013
A.014
A.015
V
V
V
Pin
S
S
S
V
, V
O
, V
, V
O
O
O
Symbol
∆V
∆V
O
O
V
/ V
/ V dp
PSRR
O
O
Parameter
Dynamic line regulation
Static load regulation
Dynamic load regulation
Power supply rejection ratio
Test condition
V
S
is from V
S_Low
18 V, T r
to
, f = 1 ms; I
O
=
1 mA; 250 mA; 500 mA,
V
O
= 3.3 V; 5 V
I
O
= 1 mA to 250 mA,
V
O
V
O
= 3.3 V for V
S
= 5 V for V
S
= 5 V,
= 6 V
I
O
= 10 mA to 250 mA, Tr, f = 10 us, V
O
= 3.3 V for
V
S
= 5 V, V
O
= 5 V for V
= 6 V
S
I
O
= 500 mA, V
O
= 5 V
I
O
= 500 mA, V
O
= 3.3 V
I
O
= 500 mA, V
O
= 2.8 V
I
O
= 500 mA, V
O
= 2.5 V
I
O
= 500 mA, V
O
= 1.8 V
V
S
= 13.5 V, V
O
= 5 V, I
= 500 mA, f = 1 kHz
O
Min.
Typ.
75
Max.
3
1
3
500
Unit
%
%
% mV dB
A.016
A.057
A.017
A.018
A.019
A.020
A.021
V
V
V
V
V
V
V
S
S
S
S
S
S
S
, V
, V
, V
, V
, V
, V
, V
O
O
O
O
O
O
O
I
I
I
I
I
I
I qn qn_LL qn_0 qn_50 qn_150 qn_250 qn_500
Current consumption with regulator disabled
I qn
= I
Vs
– I
O
Current consumption with
I regulator enabled qn_LL
= I
Vs
– I
O
Current consumption with regulator enabled
I qn_0
= I
Vs
– I
O
Current consumption with
I regulator enabled qn_50
= I
Vs
– I
O
Current consumption with regulator enabled
I qn_150
= I
Vs
– I
O
Current consumption with
I regulator enabled qn_250
= I
Vs
– I
O
Current consumption with regulator enabled
I qn_500
= I
Vs
– I
O
I
I
I
I
I
V
EN = low
V
V
S
O
S
= 3.5 V; 13.5 V,
= 0 µA, EN = high
= 3.5 V; 13.5 V,
0 < I
O
V
V
V
V
O
O
O
O
S
S
S
S
S
= 3.5 V; 13.5 V,
≤ 60 µA, EN = high
= 3.5 V; 13.5 V,
= 50 mA, EN = high
= 3.5 V; 13.5 V,
= 150 mA, EN = high
= 3.5 V; 13.5 V,
= 250 mA, EN = high
= 3.5 V; 13.5 V,
= 500 mA, EN = high
105
140
0.55
1
1.05
1.4
1
130
180
0.9
1.5
2
2.5
µA
µA
µA mA mA mA mA
A.022
A.023
V
V
S
S
V
V
UVLO_fall
UVLO_ rise
Undervoltage lockout, falling
Undervoltage lockout, rising
V
O
= 0.8 V; 1.2 V; 1.5 V;
1.8 V
V
O
= 2.5 V; 2.8 V; 3.3 V
V
O
= 5 V
V
O
= 0.8 V; 1.2 V; 1.5 V;
1.8 V
V
O
= 2.5 V; 2.8 V; 3.3 V
V
O
= 5 V
1.5
2.3
4.6
1.7
2.6
4.9
1.6
2.4
4.8
1.8
2.7
5.1
1.7
2.55
5.0
2.1
2.8
5.3
1. I
Short
typical value of 120 mA for t = 400 µs during the power on.
2. V
S_Low
= 3.5 V at V
O
= 0.8 V; 1.2 V;1.5 V;1.8 V and 2.5 V, V
S_Low
= 5 V at V
O
= 2.8 V and 3.3 V, V
S_Low
= 6 V at V
O
= 5 V
V
V page 8/38
DS14076 - Rev 1
L99VR02J
Electrical characteristics
3. Parameters are guaranteed by design.
.
5. Considering that the minimum operating input voltage is 2.15 V, the dropout voltage (V dp below 1.8 V.
) is not defined for output voltages
Item
A.024
Pin
V
O
Symbol
R
FD
Table 6. Fast output discharge
Parameter
Fast discharge - pull down resistor
Test condition
V
S
= 3.95 V; 13.5 V,
V
O
= 3.3 V; 5 V, EN = low
Min.
50
Typ.
75
Max.
120
Unit
Ω
Table 7. Reset
Item Pin
A.025 RST
A.026 RST
A.027 RST
A.055 RST
A.028 RST
A.029 RST
V
Symbol
I
V rst_lkg
V
O_th
O_th_hyst
T
T rst_l rr rd
1. T rd
= 120 µs for V
S
< 3.5 V.
Parameter
Reset output low voltage
Test condition
V
S
= 5 V; 13.5 V,
R ext
≥ 4.7 KΩ to V
O
,
V
O
= 3.3 V; 5 V
Reset output high leakage current
V rst
= 0.8 V
V
O
out of regulation, low threshold
V
O
out of regulation– low threshold hysteresis
Reset reaction time
Reset delay time
V
S
= 5 V, 13.5 V,
V
O
decreasing,
V
O
= 3.3 V; 5 V
V
S
= 5 V; 13.5 V, V increasing, V
O
O
= 3.3
V; 5 V
V
S
V
O
= 5 V; 13.5 V,
= 3.3 V; 5 V
V
S
V
O
= 5 V; 13.5 V,
= 3.3 V; 5 V
Min.
Typ.
13.5% 10%
10
2%
16
250
Max.
0.2 x V
O
1
6.5%
37
310
Unit
V
µA
Below V
O
V
O_th
µs
µs page 9/38
DS14076 - Rev 1
L99VR02J
Electrical characteristics
Table 8. Watchdog
Item
A.030
A.031
A.032
A.033
A.034
A.035
A.036
A.040
A.041
Pin
V
V
V
V
W
W
W
V
V
CW
CW
CW
CW
O
O i i i
Symbol
I
I
I
I
V
V
I
V
V ih il
Wi wlth whth
CWc
CWd w_off w_on
Parameter
Input high voltage
Input low voltage
Pull down current
Low threshold
High threshold
Charge current
Discharge current
Watchdog deactivation current threshold
Watchdog activation current threshold
Test condition
V
S
= 5 V; 13.5 V,
V
O
= 3.3 V; 5 V
V
S
= 5 V; 13.5 V,
V
O
= 3.3 V; 5 V
V wi
= 3.3 V
V
S
= 5 V; 13.5 V,
V
O
= 3.3 V; 5 V
V
S
= 5 V; 13.5 V,
V
O
= 3.3 V; 5 V
V
S
= 5 V; 13.5 V,
V
CW
= 0.1 V,
V
O
= 3.3 V; 5 V
V
S
= 5 V; 13.5 V,
V
CW
= 2.5 V,
V
O
= 3.3 V; 5 V
V
S
= 5 V; 13.5 V,
V
O
= 3.3 V; 5 V
V
S
= 5 V; 13.5 V,
V
O
= 3.3 V; 5 V
1. Watchdog input requires a square wave signal (duty cycle of 50 %).
Item
A.042
A.043
A.045
Pin
EN
EN
EN
Table 9. Enable
Symbol
V
EN_low
V
EN_high
I
EN
Parameter
EN input low voltage
EN input high voltage
Pull down current
Test condition
V
S
= 13.5 V
Min.
0.7 x V
O
Typ.
Min.
1.5
10%
44%
5
1.25
0.4
1.8
Item
A.046
A.047
A.048
Pin
SELx
SELx
SELx
Symbol
V
SELx_low
V
SELx_high
I
SELx
Table 10. Output voltages selectors
Parameter
SELx input low voltage
SELx input high voltage
Pull down current
Test condition
V
S
= 3.5 V; 13.5 V
Min.
0.7
4
47%
Typ.
10
2.5
1.05
3.35
Max.
Unit
V
6
13%
0.25 x V
O
10
16%
V
µA
V
O
50%
20
5
1.5
4.8
Max.
0.6
12
V
O
μA
μA mA mA
Typ.
0.1
Max.
0.3
0.4
Unit
V
V
µA
Unit
V
V
µA page 10/38
Note:
Note:
L99VR02J
Electrical characteristics
Item Pin
A.049
TW
A.050
TW
A.051
TW
A.052
V
O
A.056
V
O
A.054
TW
Symbol
V
Tw_low
T warn
T warn_hyst
OV
OV
_hyst
T w_per
Table 11. Thermal warning and protection
Parameter
Thermal warning output low voltage
Test condition
R ext
≥ 4.7 kΩ to V
O
,
V
O
= 3.3 V; 5 V
Min.
Typ.
Thermal warning temperature
Thermal warning hysteresis
140
3
150
11
V
O
overvoltage
V
O
overvoltage hysteresis
Thermal warning square wave period
V
S
= 5 V; 13.5 V,
V
O
increasing,
V
O
= 3.3 V; 5 V
V
S
= 5 V; 13.5 V,
V
O
decreasing,
V
O
= 3.3 V; 5 V
V
S
= 5 V; 13.5 V,
V
O
= 3.3 V; 5 V
6.5% 10%
2%
250
1. T w_per
= 130 µs for V
S
< 3.5 V.
Max.
0.2 x V
O
165
15
13.5%
335
Unit
V
°C
°C
Above V
O
Below OV
µs
All parameters are guaranteed in the junction temperature range -40°C to 150 °C (unless otherwise specified).
L99VR02J device is still operative and functional at higher temperatures (up to 175 °C). Parameters limit at junction temperature above 150 °C may change respect to what is specified as per the standard temperature range. Device functionality at high junction temperature is guaranteed by characterization. All parameters are guaranteed by design for V
O
not reported in test condition.
Minimum input voltage values are achievable adopting an input ceramic capacitator: C5750X7R2A475M230KA– ceramic capacitor multistrate SMD, 4.7 μF, 100 V, ±20%, X7R, C series TDK.
DS14076 - Rev 1 page 11/38
L99VR02J
Electrical characteristics curves
2.4
Electrical characteristics curves
Figure 3. Output voltage vs T j
5.50
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
0
V
0
(V)
Io = 1 mA
V = 13.5 V
20
5V
40
3V3
2V8
60
2V5
80
1V8
100
1V5
1V2
120
0V8
140
T j
(⁰C)
160
Figure 5. Drop voltage vs output current
0.25
V dp
(V)
0.20
Ta = 25 °C
0.15
0.10
0.05
0.00
0
5V
50 100
3V3
150 200
2V8
250
2V5
300 350
1V8
400
I o
(mA)
450 500
Figure 7. Current consumption vs input voltage
(I o
< 1 mA)
0.3
I qn
(mA)
Io < 1 mA
Ta = 25 °C
0.2
0.1
V
S
(V)
0.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
5V 2V8 1V8 1V2
3V3 2V5 1V5 0V8
Figure 4. Output voltage vs V
S
4.0
3.5
3.0
2.5
2.0
1.5
1.0
5.5
5.0
4.5
0.5
0.0
-0.5
0
V
0
(V)
Io = 250 mA
Ta = 25 °C V
1
5V
2
2.8V
3
3.3V
2.5V
4
1.8V
5
1.5V
6
1.2V
7
0.8V
V
S
(V)
8
Figure 6. Current consumption vs output current
I qn
(mA)
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
Vs = 13.5 V
Ta = 25 °C
0.3
I out
(mA)
0.0
0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500
5V
3V3
2V8
2V5
1V8
1V5
1V2
0V8
Figure 8. Current consumption vs input voltage (I o
= 50 mA)
1.5
I qn
(mA)
Io = 50 mA
Ta = 25 °C
1.0
0.5
0.0
V
S
(V)
3V3
2V8
2V5
1V8
1V5
1V2
0V8
DS14076 - Rev 1 page 12/38
L99VR02J
Electrical characteristics curves
Figure 9. Current consumption vs input voltage (I o
= 250 mA)
2.0
I qn
(mA)
Io = 250 mA
Ta = 25 °C
1.5
1.0
0.5
V
S
(V)
0.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
5V
3V3
2V8
2V5
1V8
1V5
1V2
0V8
Figure 10. Short-circuit current vs T j
(I short
pin tied to GND)
750
I sht
(mA)
740
730
Vs = 13.5 V
720
-60 -40
5V
-20
3V3
0 20
2V8
40
2V5
60
1V8
80
1V5
100 120
1V2
T j
(⁰C)
140 160
0V8
Figure 11. Short-circuit current vs T j
(I short
pin floating)
220
I sht
(mA)
215
210
Vs = 13.5 V
205
200
-60 -40
5V
-20 0
3V3
20
2V8
40
2V5
60
1V8
80
1V5
100 120
1V2
T j
(⁰C)
140
0V8
160
Figure 12. Short-circuit current vs input voltage
I sht
(A)
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
5 6
Rsh = Floting
Ta = 25 °C
7 8
5V_Ishort_max
3.3V_Ishort_max
2.8V_Ishort_max
2.5V_Ishort_max
1.8V_Ishort_max
1.5V_Ishort_max
1.2V_Ishort_max
0.8V_Ishort_max
5V_Ishort_min
3.3V_Ishort_min
2.8V_Ishort_min
2.5V_Ishort_min
1.8V_Ishort_min
1.5V_Ishort_min
1.2V_Ishort_min
0.8V_Ishort_min
9 10 11 12 13 14 15 16 17
T j
(V)
18 19
Figure 13. Output voltage vs enable voltage (V
O
= 0.8 V)
0.9
V
0
(V)
0.8
0.7
0.6
0.5
Io = 250 mA
Ta = 25 ⁰C
Vs = 13.5 V
0.4
0.3
0.8V
0.2
0.1
0.0
V
EN
(V)
-0.1
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Figure 14. Output voltage vs enable voltage (V
O
= 1.2 V)
V
0
(V)
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
0.0
Io = 250 mA
Ta = 25 ⁰C
Vs = 13.5 V
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.2 V
V
EN
(V)
1.8
2.0
DS14076 - Rev 1 page 13/38
L99VR02J
Electrical characteristics curves
Figure 15. Output voltage vs enable voltage (V
O
= 1.5 V)
V
0
(V)
0.8
0.7
0.6
0.5
1.2
1.1
1.0
0.9
1.6
1.5
1.4
1.3
0.4
0.3
0.2
0.1
0.0
-0.1
0.0
Io = 250 mA
Ta = 25 ⁰C
Vs = 13.5 V
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.5 V
V
EN
(V)
1.8
2.0
Figure 16. Output voltage vs enable voltage (V
O
= 1.8 V)
V
0
(V)
1.4
1.2
1.0
0.8
0.6
0.4
2.0
1.8
1.6
0.2
0.0
-0.2
0.0
Io = 250 mA
Ta = 25 ⁰C
Vs = 13.5 V
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8 V
V
EN
(V)
1.8
2.0
Figure 17. Output voltage vs enable voltage (V
O
= 2.5 V)
2.8
2.6
2.4
2.2
2.0
1.8
V
0
(V)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
0.0
Io = 250 mA
Ta = 25 ⁰C
Vs = 13.5 V
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
2.5 V
V
EN
(V)
1.8
2.0
Figure 18. Output voltage vs enable voltage (V
O
= 2.8 V)
V
0
(V)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.2
2.0
1.8
1.6
0.0
-0.2
3.0
2.8
2.6
2.4
0.0
Io = 250 mA
Ta = 25 ⁰C
Vs = 13.5 V
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
2.8 V
1.8
V
EN
(V)
2.0
Figure 19. Output voltage vs enable voltage (V
O
= 3.3 V)
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
0.0
V
0
(V)
Io = 250 mA
Ta = 25 ⁰C
Vs = 13.5 V
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
3.3 V
1.8
V
EN
(V)
2.0
Figure 20. Output voltage vs enable voltage (V
O
= 5 V)
1.0
0.5
0.0
-0.5
0.0
3.5
3.0
2.5
2.0
1.5
5.5
V
0
(V)
5.0
4.5
4.0
Io = 250 mA
Ta = 25 ⁰C
Vs = 13.5 V
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
5 V
1.8
V
EN
(V)
2.0
DS14076 - Rev 1 page 14/38
DS14076 - Rev 1
Figure 21. V
EN_high
vs T j
L99VR02J
Electrical characteristics curves
Figure 22. V
EN_low
vs T j
Figure 23. V whth
vs T j
Figure 24. V wlth
vs T j
Figure 25. I
CWc
vs T j
Figure 26. I
CWd
vs T j page 15/38
Figure 27. PSRR
L99VR02J
Electrical characteristics curves
DS14076 - Rev 1 page 16/38
L99VR02J
Test circuit and waveforms plot
3 Test circuit and waveforms plot
3.1
Load regulation
Vbat
C 1 C 2
C tw
Figure 28. Load regulation test circuit
Vs
TW
E N
Wi
Vo
R
RST
Io
3.3 µF
ESR
Vcw
Ishort
SEL 1
SEL 2
SEL 3
R ST
GND
R sh
Vo
+
LOAD
-
Step Change of Load
Current
200
100
0
0 250 750 1000
Time (µs)
Resultant
Output Voltage xx x
0
0 250 750 1000
Time (µs)
Figure 29. Maximum load variation response (V o
= 5 V) Figure 30. Maximum load variation response (V o
= 3.3 V)
DS14076 - Rev 1 page 17/38
L99VR02J
Application information
4 Application information
Figure 31. Application schematic
Vbat
C1 C2
Ctw
Rsh
Vs
TW
EN
Wi
Vo
Vcw
Ishort
GND
SEL1
SEL2
SEL3
RST
R
RST
Co
Figure 32. Application schematic – Post regulation
Vbat
DC/DC
CONVERTER
OR
PRE-REGULATOR
Vin
C1
Ctw
C2
Rsh
Vs
TW
EN
Wi
Vo
Vcw
Ishort
GND
SEL1
SEL2
SEL3
RST
R
RST
Co
DS14076 - Rev 1
Input ceramic capacitor C
2
≥ 4.7 μF is necessary for the regulator to operate properly. The other input capacitor
C1 can be used as backup supply for the application. The C
O
capacitor, connected to the output pin, is for bypassing to GND the high-frequency noise and it guarantees stability even during sudden line and load variations.
Suggested value is C
O
= 3.3 µF.
page 18/38
4.1
4.2
L99VR02J
Voltage regulator
The ESR of the SMD output ceramic capacitor has a negligible effect on the stability of the L99VR02J for capacitors with low ESR. A ceramic SMD capacitor is recommended on the V
O
pin.
Voltage regulator
The voltage regulator uses a p-channel MOS transistor as a regulating element. With this structure, a very low dropout voltage at current up to I
O
= 500 mA is obtained. The high-precision of the output voltage (±2%) is obtained with a pretrimmed reference voltage. The voltage regulator automatically adapts its own quiescent current to the output current level. In light load conditions, the quiescent current goes down to I qn_LL
= 105 µA
(low consumption mode). L99VR02J operates with reduced input voltage (post regulation) minimizing the internal power dissipation and maximizing the output current.
Output current limitation
Output current limitation is present to protect the regulator and the application from the overload condition, such as short to ground.
Figure 33. Behavior of output current versus regulated voltage V
O
DS14076 - Rev 1
The I short
current can be set in the range from 220mA (typ) to 815mA (typ). This through an external resistor R sh connected between the I short
pin and the ground.
Figure 34. I short
versus R sh page 19/38
4.3
L99VR02J
Output voltage selection
Open pin (no resistance on the I short
pin), is seen as a max resistance corresponding to the maximum I short current.
Output voltage selection
The L99VR02J can provide one out of eight different output voltages. The combination of three digital input
selectors (SELx) determines the output voltage according to the following Table 12
.
V
O
5
3.3
2.8
2.5
1.8
1.5
1.2
0.8 (default)
SEL1
1
1
1
1
0
0
0
0
Table 12. Truth table
SEL2
1
1
0
0
1
1
0
0
SEL3
1
0
1
0
1
0
1
0
The SELx pins configuration is acquired at the device startup (EN transition from low to high) and once configuration is acknowledged. It cannot be changed until the next EN transition.
When all the pins are left not connected, the default configuration is selected.
Figure 35. Example of output voltage selection
Vbat
Ctw
Rsh
Vs
TW
EN
Wi
Vo
Vcw
Ishort
GND
SEL1
SEL2
SEL3
RST
Vs
Vo =2.5V
SELx pins are internally connected to GND via the pull-down current source.
DS14076 - Rev 1 page 20/38
4.4
L99VR02J
Enable
Enable
The L99VR02J is enabled/disabled by the enable input; a high voltage signal switches the regulator ON. When the enable pin is set low, the output is switched-off. The current consumption of the device becomes as low as 1
μA and the fast output discharge circuit is activated.
It may happen that the components drive the enable pin supplied at a voltage different from the regulator supply voltage. In this case, the EN input pin must be set high only once V
S
> 1.5 V. A solution to drive the enable pin is
.
Figure 36. Typical example of enable control
4.5
In any case, to avoid exceeding the absolute maximum rating, a special care must be adopted in driving the EN pin since the enable input voltage is linked to the maximum DC supply voltage (V
S
) applied to the L99VR02J
(-0.3 V to V
S
+ 0.3 V).
Reset
The reset circuit supervises the output voltage V
O
. If the output voltage falls below V
O_th
, then RST is pulled low with a reaction time T rr
. When the output voltage rises above, V
O_th
+ V
O_th_hyst
then RST is pulled high with a delay time T rd
. An internal circuit generates the delay. The reset circuit is active when EN is high. Being RST an open-drain output an external resistance (R rst
) is needed between the RST pin and the V
O
pin. The external resistance value can be in a range between 4.7 KΩ and 20 KΩ. Leave the RST pin floating if not used. Be aware that the current flowing through the RST pin drawn from V
O
when the RST pin is pulled low. It may affect the watchdog activation/deactivation based on the regulator output current consumption monitoring.
Figure 37. Reset timing diagram
DS14076 - Rev 1 page 21/38
4.6
L99VR02J
Autonomous watchdog
Autonomous watchdog
The watchdog input W i
monitor a supplied microcontroller. If pulses are missing, the RST output pin is set low.
The watchdog timeout can be set within a wide range with the external capacitor, C tw
. The watchdog circuit discharges the capacitor C tw
, with the constant current I
CWd
. If the lower threshold V wlth
is reached, a watchdog reset is generated. To avoid it, the microcontroller must generate a positive edge during the discharge of the capacitor before the voltage reaches the threshold V wlth
. To calculate the sawtooth period “T wop
”, taking care that the microcontroller triggers the positive edge during the discharge phase of C tw
(T d
). The following equations can be used:
Vwℎtℎ − Vwltℎ × Ctw = ICWd × Td
Vwℎtℎ − Vwltℎ × Ctw = ICWc × Twol
Twop = Td + Twol
Every W i
positive edge switches the current source from discharging to charging. The same happens when the lower threshold is reached. When the voltage reaches the upper threshold, V whth
, the current switches from charging to discharging. The result is a saw-tooth voltage at the watchdog timer capacitor C tw
. If a microcontroller operates in low power mode, it is not able to generate any pulse to refresh the voltage regulator watchdog, triggering so the microcontroller reset. In such a case, the watchdog functionality is automatically deactivated anytime the microcontroller current consumption falls under the I w_off
threshold. This to avoid generating the microcontroller reset. On the other hand, when the current consumption rises above the I w_on
threshold the watchdog functionality is once again activated. Once the regulator is enabled for the first time, if I
O
< I w_off
, the watchdog is not activated. While if I
O
> I w_off
, the watchdog is activated.
W i
Figure 38. Watchdog timing diagram
V
CW
T wop
I
O
T wol
V whth
V wlth
I w_on
I w_off
RST
Note:
Note:
Since the RST output pin is shared by the watchdog circuit and the output voltage monitoring circuit, for applications where the watchdog is not needed, to prevent the watchdog from generating RST pulses without anyhow losing the reset functionality of the V
O
monitoring, the V cw
pin has to be connected to V
O be always tied to ground by an external capacitor (C tw
) when watchdog function is used.
. V cw
pin must when the watchdog timer is used and the regulator recovers from a thermal shut-down event or recovers from an output under-voltage event (including the recovery from output under-voltage event at the regulator output turning on), the reset pin might be pulled back high with a delay longer than T rd
, in the range between T rd and T rd
+T wol
due to the watchdog that might affect the RST pin release. The watchdog will not affect the
RST pin release in the case where recovering from a thermal shut-down event or recovering from an output under-voltage event (including the recovery from output under-voltage event at the regulator output turning on) the I
O
drops below I w_off
before T rd
. The output current I
O
consists in the load current, the current drawn from the RST pin and the TW pin through the pull-down resistors connected to V
O
when the RST and the TW pins are asserted low and the current needed to charge/discharge the output capacitor C
O
.
When the watchdog timer is used, in the case of an output under-voltage event not making the V
O
drop to zero volt, since the watchdog will still be running during the output under-voltage condition, the first watchdog timeout after the reset pin is released coming out of the output under-voltage event might occur before expected
(0 ≤ timeout ≤ T wop
- T wol
).
DS14076 - Rev 1 page 22/38
4.7
L99VR02J
Thermal warning and thermal shutdown
Usage of watchdog timer
Watchdog timer is not used
Watchdog timer is used
Table 13. Watchdog timer
Connection of V
CW
pin
Connect to the V
O
pin
Connect to an external capacitor C tw
Thermal warning and thermal shutdown
To warn the microcontroller about a severe temperature increase, a thermal warning output has been implemented. If the device detects a junction temperature above T warn
, the advanced thermal warning (TW) output pin is pulled low while the voltage regulator, and its features remain all active. The TW pin returns to its high logic level (equal to the V
O
output value) once the temperature falls below the threshold T wam
- T wam_hyst
.
Figure 39. Thermal warning diagram
When junction temperature reaches the T prot
thermal shutdown threshold the regulator output is quickly shut-off through the internal fast output discharge circuit; to be reactivated, junction temperature has to decrease below
T prot
- T prot_hyst
. Being TW an open-drain output an external resistance (R
TW
) is needed between the TW pin and the V
O
pin. The external resistance value can be in a range between 4.7 KΩ and 20 KΩ. Be aware that the current flowing through the TW pin drawn from V
O
when the TW pin is pulled low may affect the watchdog activation/deactivation based on the regulator output current consumption monitoring. Leave floating if not used.
DS14076 - Rev 1 page 23/38
4.8
L99VR02J
Overvoltage detection by advanced thermal warning read-out
Overvoltage detection by advanced thermal warning read-out
The TW pin also provides diagnostics about output overvoltage (OV); to distinguish between a thermal warning event and an output overvoltage event, two different signals are generated at the same TW output pin. How reported in the previous paragraph a thermal warning event detection sets the TW pin LOW, instead an output overvoltage event generates a square wave at the TW pin (
Figure 40. Square wave on TW pin generated during an overvoltage
). Overvoltage detection has higher priority than thermal warning detection so that concurrence of thermal warning and over voltage events lead to a square wave like in the case of overvoltage detection (as shown in
Figure 41. Warning signal caused by overvoltage and thermal warning on TW pin
).
Figure 40. Square wave on TW pin generated during an overvoltage
TW
T
w_per
t
.
Vo
Figure 41. Warning signal caused by overvoltage and thermal warning on TW pin
Vo_hth t
T
150ºC t
TW t
DS14076 - Rev 1 page 24/38
4.9
4.10
L99VR02J
Fast output discharge
Fast output discharge
To assure a quick discharge of the external capacitor tied to the output pin down to around 1.3 V the L99VR02J uses an internal pulldown circuit. Activated each time the EN pin goes low, during thermal shutdown and during undervoltage lockout, the output current flows through the pulldown resistor of the fast output discharge circuit to the ground. The fast output discharge feature is available for the output voltages,
V
O
= 2.5 V (SELx = [1;0;0]); V
[1;1;1]).
O
= 2.8 V (SELx = [1;0;1]); V
O
= 3.3 V (SELx = [1;1;0]) and V
O
= 5 V (SELx =
Undervoltage lockout UVLO
The undervoltage lockout (UVLO) circuit allows a fast regulating element to turn off (activating the internal fast output discharge circuit). This if the input voltage drops below the threshold, V
UVLO_fall
, avoiding an undesired unknown output state during low input voltage. When the input voltage is above the V
UVLO_rise
threshold, the regulating element is again turned on.
V
S
Figure 42. Undervoltage lock out on output voltage
V
UVLO_rise
V
UVLO_fall
V
O
DS14076 - Rev 1 page 25/38
4.11
L99VR02J
Support to ISO26262
Support to ISO26262
Even if not designed as the safety HW element, the device contains some features that can be used to support the application that needs to fulfill functional safety requirements. Analysis of the IC’s capability to reach the required safety level, should be made at system level under user responsibility.
The following device safety requirements have been considered for a typical application:
ID
SR-001
SR-002
SR-003
SR-004
Table 14. Safety requirement
Description
Operation of voltage regulator is allowed until over the temperature limit.
Operation of voltage regulator is enabled until the programmed current limit is reached.
Output voltage of regulator shall remain within programmed range when the RST pin is not asserted.
Output voltage of the regulator shall remain within programmed range when the square wave at the TW pin is not generated.
Based on the above requirements list the following safety mechanism has been implemented:
ID
SM1
SM2
SM3
SM4
SM5
SM6
Table 15. Implemented safety mechanism
Description
Thermal sensor acting by the TW pin
Overtemperature protection
Limitation on maximum output current
Output voltage V
O
monitoring for undervoltage detection
Output voltage V
O
monitoring for overvoltage detection
RST reset assertion in case of V
O undervoltage detection
SR covered
SR-004
SR-001
SR-002
SR-002
SR-002
SR-003
In addition to the internal watchdog for checking the correct operation of the microcontroller, it can be considered a system-level safety mechanism.
More details about functional safety can be found in the device safety manual, provided on customer request.
DS14076 - Rev 1 page 26/38
5
L99VR02J
Application
Application
Vbat
Cin
Ctw
Vo
R
TW
µc input
µc output
Rsh
Figure 43. Typical application
Vs
TW
EN
Wi
Vcw
Ishort
GND
Vo
Vo =2.5V
Vs
SEL1
SEL2
SEL3
R
RST
Vo
RST
µc input
Co
µc supply
DS14076 - Rev 1 page 27/38
6
6.1
Package and PCB thermal data
PowerSSO-12 thermal data
Figure 44. PowerSSO-12 PC board
L99VR02J
Package and PCB thermal data
Note: The values quoted are for PCB 77 mm x 86 mm x 1.6 mm, FR4, two and four layers; Cu thickness 0.070 mm
(outer layers). Cu thickness 0.035 mm (inner layers), thermal vias separation 1.2 mm, thermal via diameter
0.3 mm +/- 0.08 mm, Cu thickness on vias 0.025 mm, footprint dimension 2.2 mm x 2.9 mm.
DS14076 - Rev 1 page 28/38
DS14076 - Rev 1
Pulse calculation:
Z
THδ
= R
TH
.δ+ Z
THtp
(1-δ)
Where δ = tp/T
L99VR02J
PowerSSO-12 thermal data
Figure 45. R thj-amb
versus PCB copper area in open box free air condition
Figure 46. PowerSSO-12 thermal impedance junction ambient single pulse page 29/38
DS14076 - Rev 1
Figure 47. Thermal fitting model of a V reg
in PowerSSO-12
L99VR02J
PowerSSO-12 thermal data
Area/island (cm 2 )
R1 (°C/W)
R2 (°C/W)
R3 (°C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
Table 16. PowerSSO-12 thermal parameter
Footprint
3.8
4.2
6
18
22
26
0.0015
0.035
0.15
0.4
0.27
3
2
15
20
6
9
0.4
0.8
6
8
0.4
1
8
10
15
6
8
4L
5
4.5
4
4
0.8
7
15 page 30/38
7
7.1
L99VR02J
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
PowerSSO-12 package information
Figure 48. PowerSSO-12 package dimensions
DS14076 - Rev 1 page 31/38
Symbol c
D
E e
H
A
A1
A2 b
X
Y ddd h
L k
L99VR02J
PowerSSO-12 package information
Table 17. PowerSSO-12 package mechanical data
Millimeters
Typ.
Min
1.250
0.000
1.100
0.230
0.190
4.800
3.800
0.800
5.800
0.250
0.400
0°
2.200
2.900
6.200
0.500
1.270
8°
2.800
3.500
0.100
Max
1.700
0.100
1.600
0.410
0.250
5.000
4.000
DS14076 - Rev 1 page 32/38
7.2
L99VR02J
PowerSSO-12 packaging information
PowerSSO-12 packaging information
Figure 49. PowerSSO-12 tape and reel shipment (suffix “TR”)
DS14076 - Rev 1 page 33/38
Revision history
Date
22-Dec-2022
Version
1
Table 18. Document revision history
Changes
Initial release
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DS14076 - Rev 1 page 34/38
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Contents
Contents
DS14076 - Rev 1 page 35/38
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List of tables
List of tables
DS14076 - Rev 1 page 36/38
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List of figures
List of figures
Figure 3. Output voltage vs T j
Figure 7. Current consumption vs input voltage (I o
< 1 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Current consumption vs input voltage (I o
= 50 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Current consumption vs input voltage (I o
= 250 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Short-circuit current vs T j
Figure 11. Short-circuit current vs T j
Figure 13. Output voltage vs enable voltage (V
Figure 14. Output voltage vs enable voltage (V
Figure 15. Output voltage vs enable voltage (V
Figure 16. Output voltage vs enable voltage (V
Figure 17. Output voltage vs enable voltage (V
Figure 18. Output voltage vs enable voltage (V
Figure 19. Output voltage vs enable voltage (V
Figure 20. Output voltage vs enable voltage (V
Figure 29. Maximum load variation response (V o
Figure 30. Maximum load variation response (V o
Figure 33. Behavior of output current versus regulated voltage V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 47. Thermal fitting model of a V reg
DS14076 - Rev 1 page 37/38
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DS14076 - Rev 1 page 38/38
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