Teensy LC Reference Manual
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KL26 Sub-Family Reference Manual
Supports: MKL26Z32VFM4, MKL26Z64VFM4, MKL26Z128VFM4,
MKL26Z32VFT4, MKL26Z64VFT4, MKL26Z128VFT4,
MKL26Z32VLH4, MKL26Z64VLH4, MKL26Z128VLH4,
MKL26Z256VLH4, MKL26Z256VMP4, MKL26Z128VLL4,
MKL26Z256VLL4, MKL26Z128VMC4, MKL26Z256VMC4
Document Number: KL26P121M48SF4RM
Rev. 3.2, October 2013
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Section number
Contents
Title Page
Chapter 1
About This Information
Chapter 2
Introduction
Chapter 3
Chip Configuration
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Section number Title Page
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Section number Title Page
Chapter 4
Memory Map
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Section number Title Page
Chapter 5
Clock Distribution
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Section number Title Page
Chapter 6
Reset and Boot
Chapter 7
Power Management
Chapter 8
Security
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Section number Title Page
Chapter 9
Debug
Chapter 10
Signal Multiplexing and Signal Descriptions
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Section number Title Page
Chapter 11
Port control and interrupt (PORT)
Chapter 12
System Integration Module (SIM)
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Section number Title Page
Chapter 13
System Mode Controller (SMC)
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Section number Title Page
Chapter 14
Power Management Controller (PMC)
Chapter 15
Low-Leakage Wakeup Unit (LLWU)
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Section number Title Page
Chapter 16
Reset Control Module (RCM)
Chapter 17
Bit Manipulation Engine (BME)
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Section number Title Page
Chapter 18
Miscellaneous Control Module (MCM)
Chapter 19
Micro Trace Buffer (MTB)
Chapter 20
Crossbar Switch Lite (AXBS-Lite)
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Section number Title Page
Chapter 21
Peripheral Bridge (AIPS-Lite)
Chapter 22
Direct Memory Access Multiplexer (DMAMUX)
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Section number Title Page
Chapter 23
DMA Controller Module
Chapter 24
Multipurpose Clock Generator (MCG)
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Section number Title Page
Chapter 25
Oscillator (OSC)
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Chapter 26
Flash Memory Controller (FMC)
Chapter 27
Flash Memory Module (FTFA)
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Section number Title Page
Chapter 28
Analog-to-digital converter (ADC)
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Section number Title Page
Chapter 29
Comparator (CMP)
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Chapter 30
12-bit digital-to-analog converter (DAC)
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Section number Title Page
Chapter 31
Timer/PWM Module (TPM)
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Section number Title Page
Chapter 32
Periodic interrupt timer (PIT)
Chapter 33
Low-power timer (LPTMR)
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Section number Title Page
Chapter 34
Real Time Clock (RTC)
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Chapter 35
Universal Serial Bus OTG Controller (USBOTG)
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Section number Title Page
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Chapter 36
USB Voltage Regulator
Chapter 37
Serial Peripheral Interface (SPI)
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Section number Title Page
Chapter 38
Inter-Integrated Circuit (I2C)
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Chapter 39
Universal Asynchronous Receiver/Transmitter (UART0)
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Section number Title Page
Chapter 40
Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
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Chapter 41
Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
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Section number Title Page
Chapter 42
General-purpose input/output (GPIO)
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Chapter 43
Touch Sensing Input (TSI)
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Section number Title Page
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Chapter 1
About This Information
This section provides some basic considerations for using this information.
1.1 Overview
1.1.1 Purpose
This document describes the features, architecture, and programming model of the
Freescale microcontroller.
1.1.2 Audience
A reference manual is primarily for system architects and software application developers who are using or considering using a Freescale product in a system.
1.2 Conventions
1.2.1 Numbering systems
The following suffixes identify different numbering systems: b
This suffix Identifies a
Binary number. For example, the binary equivalent of the number 5 is written 101b. In some cases, binary numbers are shown with the prefix 0b .
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Conventions d h
This suffix Identifies a
Decimal number. Decimal numbers are followed by this suffix only when the possibility of confusion exists. In general, decimal numbers are shown without a suffix.
Hexadecimal number. For example, the hexadecimal equivalent of the number 60 is written 3Ch. In some cases, hexadecimal numbers are shown with the prefix 0x .
1.2.2 Typographic notation
The following typographic notation is used throughout this document:
Example placeholder , x code
SR[SCM]
REVNO[6:4], XAD[7:0]
Description
Items in italics are placeholders for information that you provide. Italicized text is also used for the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers.
Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type is also used for example code. Instruction mnemonics and directives in text and tables are shown in all caps; for example, BSR.
A mnemonic in brackets represents a named field in a register. This example refers to the
Scaling Mode (SCM) field in the Status Register (SR).
Numbers in brackets and separated by a colon represent either:
• A subset of a register's named field
For example, REVNO[6:4] refers to bits 6–4 that are part of the COREREV field that occupies bits 6–0 of the REVNO register.
• A continuous range of individual signals of a bus
For example, XAD[7:0] refers to signals 7–0 of the XAD bus.
1.2.3 Special terms
The following terms have special meanings:
Term asserted deasserted
Meaning
Refers to the state of a signal as follows:
• An active-high signal is asserted when high (1).
• An active-low signal is asserted when low (0).
Refers to the state of a signal as follows:
• An active-high signal is deasserted when low (0).
• An active-low signal is deasserted when high (1).
In some cases, deasserted signals are described as negated .
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reserved
Term
Chapter 1 About This Information
Meaning
Refers to a memory space, register, or field that is either reserved for future use or for which, when written to, the module or chip behavior is unpredictable.
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Conventions
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Chapter 2
Introduction
This section provides high-level descriptions of the modules available on the devices covered by this document.
2.1 Overview
Information found here provides an overview of the Kinetis L series of ARM ® Cortex ® -
M0+ MCUs and KL26 product family. It also presents high-level descriptions of the modules available on the devices covered by this document.
2.1.1 Kinetis L series
The Kinetis L series is the most scalable portfolio of ultra low-power, mixed-signal
ARM ® Cortex ® -M0+ MCUs in the industry. The portfolio includes five MCU families that offer a broad range of memory, peripheral and package options. Kinetis L Series families share common peripherals and pin-counts allowing developers to migrate easily within an MCU family or between MCU families to take advantage of more memory or feature integration. This scalability allows developers to standardize on the Kinetis L
Series for their end product platforms, maximising hardware and software reuse and reducing time-to-market.
Features common to all Kinetis L series families include:
• 48 MHz ARM Cortex-M0+ core
• High-speed 12/16-bit analog-to-digital converters
• 12-bit digital-to-analog converters for all series except for KLx4/KLx2 family
• High-speed analog comparators
• Low-power touch sensing with wake-up on touch from reduced power states for all series except for KLx4/KLx2 family
• Powerful timers for a broad range of applications including motor control
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Overview
• Low-power focused serial communication interfaces such as low-power UART, SPI,
I2C, and others.
• Single power supply: 1.71–3.6 V with multiple low-power modes support single operation temperature:
• –40 ~ 105 °C (exclude WLCSP package)
• –40 ~ 85 °C (WLCSP package)
Kinetis L series MCU families combine the latest low-power innovations with precision mixed-signal capability and a broad range of communication, connectivity, and humanmachine interface peripherals. Each MCU family is supported by a market-leading enablement bundle from Freescale and numerous ARM third party ecosystem partners.
The KL0x family is the entry-point to the Kinetis L series and is pin-compatible with the
8-bit S08PT family. The KL1x/2x/3x/4x families are compatible with each other and their equivalent ARM Cortex-M4 Kinetis K series families—K10/20/30/40.
The following figure depicts key features, memory and package options for Kinetis L series family of MCUs.
Family
Program
Flash
KL4x Family 128-256KB
Packages
64-121pin
Key Features
KL3x Family 64-256KB
KL2x Family 32-256KB
KL1x Family 32-256KB
KL0x Family 8-32KB
64-121pin
32-121pin
32-80pin
16-48pin
Low power Mixed signal USB Segment LCD
Figure 2-1. Kinetis L series families of MCU portfolio
All Kinetis L series families include a powerful array of analog, communication and timing and control peripherals with the level of feature integration increasing with flash memory size and the pin count. Features within the Kinetis L series families include:
• Core and architecture:
• ARM Cortex-M0+ Core running up to 48 MHz with zero wait state execution from memories
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• Single-cycle access to I/O: Up to 50 percent faster than standard I/O, improves reaction time to external events allowing bit banging and software protocol emulation
• Two-stage pipeline: Reduced number of cycles per instruction (CPI), enabling faster branch instruction and ISR entry, and reducing power consumption
• Excellent code density as compared to 8-bit and 16-bit MCUs: Reduces flash size, system, cost and power consumption
• Optimized access to program memory: Accesses on alternate cycles reduces power consumption.
• 100 percent compatible with ARM Cortex-M0 and a subset ARM Cortex-
M3/M4: Reuse existing compilers and debug tools.
• Simplified architecture: 56 instructions and 17 registers enable easy programming and efficient packaging of 8/16/32-bit data in memory.
• Linear 4 GB address space removes the need for paging/banking, reducing software complexity.
• ARM third-party ecosystem support: Software and tools to help minimize development time/cost
• Micro Trace Buffer: Lightweight trace solution allows fast bug identification and correction.
• Bit Manipulation Engine (BME): BME reduces code size and cycles for bitoriented operations to peripheral registers eliminating traditional methods where the core would need to perform read-modify-write operations.
• Up to 4-channel DMA for peripheral and memory servicing with minimal CPU intervention (feature not available on KL02 family)
• Ultra low-power:
• Extreme dynamic efficiency: 32-bit ARM Cortex-M0+ core combined with
Freescale 90 nm thin-film storage flash technology delivers 50% energy savings per Coremark in comparison to the closest 8/16-bit competitive solution.
• Multiple flexible low-power modes, including new operation clocking option which reduces dynamic power by shutting off bus and system clocks for lowest power core processing. Peripherals with an alternate asynchronous clock source can continue operation.
• UART, SPI, I2C, ADC, DAC, TPM, LPTMR, I2S and DMA support low-power mode operation without waking up the core (DMA is not available on KL02).
• Memory:
• Scalable memory footprints from 8 KB flash / 1 KB SRAM to 256 KB flash / 32
KB SRAM
• Embedded 64 B cache memory for optimizing bus bandwidth and flash execution performance (32 B cache on KL02 family)
• Mixed-signal analog:
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• Fast, high-precision 16-, or 12-bit ADC with optional differential pairs, 12-bit
DAC, high-speed comparators.
• Powerful signal conditioning, conversion, and analysis capability with reduced system cost (12-bit DAC not available on KL02 family)
• Human Machine Interface (HMI):
• Optional capacitive Touch Sensing Interface with full low-power support and minimal current adder when enabled
• Segment LCD controller
• Connectivity and communications:
• Up to three UARTs:
• All UARTs support DMA transfers, and can trigger when data on bus is detected;
• UART0 supports 4x to 32x over sampling ratio;
• Asynchronous transmit and receive operation for operating in STOP/VLPS modes.
• Up to two SPIs
• Up to two I 2 Cs
• Full-speed USB OTG controller with on-chip transceiver
• 3.3–5 V USB on-chip regulator
• Up to one I 2 S
• Reliability, safety, and security:
• Internal watchdog with independent clock source
• Timing and control:
• Powerful timer modules which support general-purpose, PWM, and motor control functions
• Periodic Interrupt Timer for RTOS task scheduler time base or trigger source for
ADC conversion and timer modules
• System:
• GPIO with pin interrupt functionality
• Wide operating voltage range from 1.71 V to 3.6 V with flash programmable down to 1.71 V with fully functional flash and analog peripherals
• Ambient operating temperature ranges from –40 °C to 85 °C for WLCSP package and 105 °C for all the other packages
2.1.2 KL26 sub-family introduction
The device is highly-integrated, market leading ultra low-power 32-bit microcontroller based on the enhanced Cortex-M0+ (CM0+) core platform. The features of the KL2x family derivatives are as follows.
• Core platform clock up to 48 MHz, bus clock up to 24 MHz
• Memory option is up to 256 KB flash and 32 KB RAM
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• Wide operating voltage ranges from 1.71–3.6 V with fully functional flash program/ erase/read operations
• Multiple package options from 64-pin to 121-pin
• Ambient operating temperature ranges from –40 °C to 85 °C for WLCSP package and –40 °C to 105 °C for all the others.
The family acts as an ultra low-power, cost-effective microcontroller to provide developers an appropriate entry-level 32-bit solution. The family is the next-generation
MCU solution for low-cost, low-power, high-performance devices applications. It’s valuable for cost-sensitive, portable applications requiring long battery life-time.
2.2 Module functional categories
The modules on this device are grouped into functional categories. Information found here describes the modules assigned to each category in more detail.
Module category
Table 2-1. Module functional categories
Description
• 32-bit MCU core from ARM’s Cortex-M class, 1.77 CoreMark ® single-cycle access memories, 48 MHz CPU frequency
/MHz from
• System integration module
• Power management and mode controllers
• Multiple power modes available based on run, wait, stop, and powerdown modes
• Miscellaneous control module
• Low-leakage wakeup unit
• Peripheral bridge
• Direct memory access (DMA) controller with multiplexer to increase available
DMA requests
• COP watchdog
• Internal memories include:
• Up to 256 KB flash memory
• Up to 32 KB SRAM
• Multiple clock generation options available from internally- and externallygenerated clocks
• MCG module with FLL and PLL for systems and CPU clock sources
• MCG_Lite module generates 48-MHz and /or 8/2 MHz internal reference clock for systems and CPU clock sources
• Low power 1 kHz RC oscillator for RTC and COP watchdog
• System oscillator to provide clock source for the MCU
• COP watchdog timer (COP)
• 16-bit analog-to-digital converters with DMA supported and four muxed differential pairs
• Comparator (CMP) with internal 6-bit digital-to-analog converter (DAC)
• 12-bit DAC with DMA support and two 16-bit data buffer
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Module functional categories
Table 2-1. Module functional categories (continued)
Module category
Human-Machine Interfaces (HMI)
Description
• One 6-channel TPM
• Two 2-channel TPMs
• 2-channel periodic interrupt timer
• Real time clock
• Low-power timer
• System tick timer
• Two serial peripheral interface
• USB OTG controller with built-in FS/LS transceiver
• USB voltage regulator
• Two inter-integrated circuit (I 2 C) modules
• One low power UART module
• General purpose input/output controller
• Capacitive touch sense input interface enabled in hardware
2.2.1 ARM Cortex-M0+ core modules
The following core modules are available on this device.
Table 2-2. Core modules
Module
Description
The ARM Cortex-M0+ is the newest member of the Cortex M Series of processors targeting microcontroller applications focused on very cost sensitive, deterministic, interrupt driven environments. The Cortex M0+ processor is based on the ARMv6
Architecture and Thumb®-2 ISA and is 100% instruction set compatible with its predecessor, the Cortex-M0 core, and upward compatible to Cortex-M3 and M4 cores.
The ARMv6-M exception model and nested-vectored interrupt controller (NVIC) implement a relocatable vector table supporting many external interrupts, a single non-maskable interrupt (NMI), and priority levels.
The NVIC replaces shadow registers with equivalent system and simplified programmability. The NVIC contains the address of the function to execute for a particular handler. The address is fetched via the instruction port allowing parallel register stacking and look-up. The first sixteen entries are allocated to ARM internal sources with the others mapping to MCU-defined interrupts.
The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is to detect asynchronous wake-up events in stop modes and signal to clock control logic to resume system clocking. After clock restart, the NVIC observes the pending interrupt and performs the normal interrupt or event processing.
For high-speed, single-cycle access to peripherals, the Cortex-M0+ processor implements a dedicated single-cycle I/O port.
Most of this device's debug is based on the ARM CoreSight debug interface is supported:
™ architecture. One
• Serial Wire Debug (SWD)
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2.2.2 System modules
The following system modules are available on this device.
Table 2-3. System modules
Module
System integration module (SIM)
Power management controller (PMC)
Miscellaneous control module (MCM)
Crossbar switch lite (AXBS-Lite)
Low-leakage wakeup unit (LLWU)
Description
The SIM includes integration logic and several module configuration settings.
The SMC provides control and protection on entry and exit to each power mode, control for the power management controller (PMC), and reset entry and exit for the complete MCU.
The PMC provides the user with multiple power options. Multiple modes are supported that allow the user to optimize power consumption for the level of functionality needed. Includes power-on-reset (POR) and integrated low voltage detect (LVD) with reset (brownout) capability and selectable LVD trip points.
The MCM includes integration logic and details.
The AXBS connects bus masters and bus slaves, allowing all bus masters to access different bus slaves simultaneously and providing arbitration among the bus masters when they access the same slave.
The LLWU module allows the device to wake from low leakage power modes (LLS and VLLS) through various internal peripheral and external pin sources.
The peripheral bridge converts the crossbar switch interface to an interface to access a majority of peripherals on the device.
The DMA multiplexer selects from many DMA requests down to 4 for the DMA controller.
Direct memory access (DMA) controller
The DMA controller provides programmable channels with transfer control descriptors for data movement via dual-address transfers for 8-, 16- and 32-bit data values.
Computer operating properly watchdog
The WDOG monitors internal system operation and forces a reset in case of failure. It can run from an independent 1 kHz low power oscillator with a programmable refresh window to detect deviations in program flow or system frequency.
2.2.3 Memories and memory interfaces
The following memories and memory interfaces are available on this device.
Module
Table 2-4. Memories and memory interfaces
Description
Program flash memory — up to 256 KB of the non-volatile flash memory that can execute program code.
Manages the interface between the device and the on-chip flash memory.
Up to 32 KB internal system RAM.
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Module functional categories
2.2.4 Clocks
The following clock modules are available on this device.
Table 2-5. Clock modules
Module
Multipurpose Clock Generator (MCG)
Description
MCG module containing a frequency-locked-loop (FLL) and phase-locked-loop
(PLL) controlled by internal or external reference oscillator.
The system oscillator, in conjunction with an external crystal or resonator, generates a reference clock for the MCU.
2.2.5 Security and integrity modules
The following security and integrity modules are available on this device:
Table 2-6. Security and integrity modules
Module
Description
Watchdog timer keeps a watch on the system functioning and resets it in case of its failure.
2.2.6 Analog modules
The following analog modules are available on this device:
Table 2-7. Analog modules
Module
Analog-to-digital converters (ADC)
Description
16-bit successive-approximation ADC module.
One comparator that compares two analog input voltages across the full range of the supply voltage and can trigger an ADC acquisition, TPM update, or CPU interrupt.
6-bit digital-to-analog converters (DAC)
64-tap resistor ladder network which provides a selectable voltage reference for comparator.
Supplies an accurate voltage output that is trimmable in 0.5 mV steps. The VREF can be used in medical applications, such as glucose meters, to provide a reference voltage to biosensors or as a reference to analog peripherals, such as the ADC, DAC, or CMP.
12-bit digital-to-analog converters (DAC)
Low-power general-purpose DAC, whose output can be placed on an external pin or set as one of the inputs to the analog comparator or ADC.
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2.2.7 Timer modules
The following timer modules are available on this device:
Table 2-8. Timer modules
Module
Periodic interrupt timers (PIT)
Description
• Selectable TPM clock mode
• Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128
• 16-bit free-running counter or modulo counter with counting be up or updown
• Six configurable channels for input capture, output compare, or edge-aligned
PWM mode
• Support the generation of an interrupt and/or DMA request per channel
• Support the generation of an interrupt and/or DMA request when the counter overflows
• Support selectable trigger input to optionally reset or cause the counter to start incrementing.
• Support the generation of hardware triggers when the counter overflows and per channel
• One general purpose interrupt timer
• Interrupt timers for triggering ADC conversions
• 32-bit counter resolution
• Clocked by bus clock frequency
• DMA support
• 16-bit time counter or pulse counter with compare
• Configurable clock source for prescaler/glitch filter
• Configurable input source for pulse counter
• 16-bit up-counter
• 16-bit modulo match limit
• Software controllable periodic interrupt on match
• Software selectable clock sources for input to prescaler with programmable
16-bit prescaler
• XOSC 32.678 kHz nominal
• LPO (~1 kHz)
• External RTC_CLKIN
2.2.8 Communication interfaces
The following communication interfaces are available on this device:
Module
Table 2-9. Communication modules
Description
USB 2.0 compliant module with support for host, device, and On-The-Go modes.
Includes an on-chip transceiver for full and low speeds.
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Orderable part numbers
Module
Table 2-9. Communication modules (continued)
Serial peripheral interface (SPI)
Inter-integrated circuit (I2C)
Universal asynchronous receiver/ transmitters (UART)
Description
Up to 5 V regulator input typically provided by USB VBUS power with 3.3 V regulated output that powers on-chip USB subsystem, capable of sourcing 120 mA to external board components.
Synchronous serial bus for communication to an external device
Allows communication between a number of devices. Also supports the System
Management Bus (SMBus) Specification, version 2.
One low power UART module that retains functional in stop modes.
The I 2 S is a full-duplex, serial port that allows the chip to communicate with a variety of serial devices, such as standard codecs, digital signal processors
(DSPs), microprocessors, peripherals, and audio codecs that implement the inter-
IC sound bus (I 2 S) and the Intel ® AC97 standards
2.2.9 Human-machine interfaces
The following human-machine interfaces (HMI) are available on this device:
Table 2-10. HMI modules
Module
General purpose input/output (GPIO)
Capacitive touch sense input (TSI)
Description
Some general purpose input or output (GPIO) pins are capable of interrupt and
DMA request generation.
Contains up to 16 channel inputs for capacitive touch sensing applications.
Operation is available in low-power modes via interrupts.
2.3 Orderable part numbers
The following table summarizes the part numbers of the devices covered by this document.
Freescale part number
MKL26Z256VLH4
MKL26Z256VMP4
MKL26Z128VLL4
MKL26Z256VLL4
MKL26Z128VMC4
MKL26Z256VMC4
Table 2-11. Orderable part numbers summary
CPU frequency
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
Pin count
64
64
100
100
121
121
Package Total flash memory
LQFP
BGA
LQFP
LQFP
BGA
BGA
256 KB
256 KB
128 KB
256 KB
128 KB
256 KB
RAM
32 KB
32 KB
16 KB
32 KB
16 KB
32 KB
Temperature range
-40 to 105 °C
-40 to 105 °C
-40 to 105 °C
-40 to 105 °C
-40 to 105 °C
-40 to 105 °C
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Chapter 2 Introduction
Freescale part number
MKL26Z32VFM4
MKL26Z64VFM4
MKL26Z128VFM4
MKL26Z32VFT4
MKL26Z64VFT4
MKL26Z128VFT4
MKL26Z32VLH4
MKL26Z64VLH4
MKL26Z128VLH4
Table 2-12. Orderable part numbers summary
CPU frequency
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
Pin count
48
48
64
64
32
32
32
48
64
Package Total flash memory
QFN
QFN
QFN
QFN
QFN
QFN
LQFP
LQFP
LQFP
32 KB
64 KB
128 KB
32 KB
64 KB
128 KB
32 KB
64 KB
128 KB
RAM
4 KB
8 KB
16 KB
4 KB
8 KB
16 KB
4 KB
8 KB
16 KB
Temperature range
-40 to 105 °C
-40 to 105 °C
-40 to 105 °C
-40 to 105 °C
-40 to 105 °C
-40 to 105 °C
-40 to 105 °C
-40 to 105 °C
-40 to 105 °C
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49
Orderable part numbers
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Chapter 3
Chip Configuration
This section provides details on the individual modules of the microcontroller.
3.1 Introduction
Information found here provides details on the individual modules of the microcontroller.
It includes:
• Module block diagrams showing immediate connections within the device
• Specific module-to-module interactions not necessarily discussed in the individual module chapters
• Links for more information
3.2 Module to module interconnects
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Module to module interconnects
3.2.1 Interconnection overview
The following table captures the module to module interconnections for this device.
Table 3-1. Module-to-module interconnects
Peripheral
TPM1
Signal
CH0F, CH1F
— to to
Peripheral
ADC
(Trigger)
Use Case
LPTMR
TPMx
PIT CHx
RTC
EXTRG_IN
CMP0
CMP0
CMP0
CMP0
CMP0
CMP0
LPTMR
LPTMR
TPMx
Hardware trigger (TCF)
TOF
TIF0, TIF1
Alarm (TAF) or seconds interrupt
EXTRG_IN to to to to to
ADC
(Trigger)
ADC
(Trigger)
ADC
(Trigger)
ADC
(Trigger)
ADC
(Trigger)
CMP0_OUT to ADC
(Trigger)
CMP0_OUT to LPTMR_ALT
0
CMP0_OUT to
CMP0_OUT to
CMP0_OUT to
CMP0_OUT to
Hardware trigger (TCF) to
TPM1 CH0
TPM2 CH0
UART0_RX
UART1_RX
CMPx
ADC
Triggering
(Aor B)
Count CMP events
Input capture
Input capture
IR interface
IR Interface
Hardware trigger (TCF)
TOF to to
TPMx
TPMx
Low power triggering of the comparator
TPM Trigger input
TPM Trigger input
ADC
Triggering (A or B)
ADC
Triggering (A or B)
ADC
Triggering (A or B)
ADC
Triggering (A or B)
ADC
Triggering (A or B)
Control Comment
ADC
Triggering (A
AND B)
SIM_SOPT7[ADC0ALTTRGEN] = 0 Ch0 is A, and Ch1 is
B, selecting this
ADC trigger is for supporting A and B triggering. In Stop and VLPS modes, the second trigger must be set to >10
µs after the first trigger
SIM_SOPT7[ADC0TRGSEL] and
SIM_SOPT7[ADC0PRETRGSEL] to select A or B
—
— SIM_SOPT7[ADC0TRGSEL],
SIM_SOPT7[ADC0PRETRGSEL] to select A or B
SIM_SOPT7[ADC0TRGSEL],
SIM_SOPT7[ADC0PRETRGSEL] to select A or B
SIM_SOPT7[ADC0TRGSEL],
SIM_SOPT7[ADC0PRETRGSEL] to select A or B
SIM_SOPT7[ADC0TRGSEL],
SIM_SOPT7[ADC0PRETRGSEL] to select A or B
—
—
—
SIM_SOPT7[ADC0TRGSEL],
SIM_SOPT7[ADC0PRETRGSEL] to select A or B
LPTMR_CSR[TPS]
—
—
SIM_SOPT4[TPM1CH0SRC]
SIM_SOPT4[TPM2CH0SRC]
SIM_SOPT5[UART0RXSRC]
SIM_SOPT5[UART1RXSRC]
CMP_CR1[TRIGM]
TPMx_CONF[TRGSEL] (4 bit field)
TPMx_CONF[TRGSEL] (4-bit field)
—
—
—
—
—
Table continues on the next page...
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Peripheral
TPM1
PIT CHx
Chapter 3 Chip Configuration
Table 3-1. Module-to-module interconnects (continued)
Signal
Timebase
— to to
Peripheral
TPMx
Use Case Control Comment
TIF0, TIF1
RTC Alarm (TAF) or seconds interrupt
EXTRG_IN EXTRG_IN to to to
TPMx
TPMx
TPMx
TPM Global timebase input
TPM Trigger input
TPM Trigger input
TPMx_CONF[GTBEEN] —
TPMx_CONF[TRGSEL] (4-bit field) If PIT is triggering the TPM, the TPM clock must be faster than Bus clock.
TPMx_CONF[TRGSEL] (4-bit field) —
—
CMP0
LPTMR
CMP0_OUT to to
TPMx
TSI
TPM Trigger input
TPM Trigger input
TSI triggering
TPMx_CONF[TRGSEL] (4-bit field)
TPMx_CONF[TRGSEL] (4-bit field)
TSI selects HW trigger
—
—
UART0
Hardware trigger (TCF)
UART0_TX SIM_SOPT5[UART0TXSRC]
UART0
UART1
UART1
PIT
PIT
PIT
UART0_TX
UART1_TX
UART1_TX
TIF0
TIF0
TIF1 to Modulated by
TPM1 CH0 to Modulated by
TPM2 CH0 to Modulated by
TPM1 CH0 to Modulated by
TPM2 CH0 to DAC to to
DMA CH0
DMA CH1
UART modulation
UART modulation
UART modulation
UART modulation
Advance
DAC FIFO
DMA HW
Trigger
DMA HW
Trigger
SIM_SOPT5[UART0TXSRC]
SIM_SOPT5[UART1TXSRC]
SIM_SOPT5[UART1TXSRC]
DAC HWTRG Select
DMA MUX register option
DMA MUX register option
—
—
—
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Core modules
3.2.2 Analog reference options
Several analog blocks have selectable reference voltages as shown in
options allow analog peripherals to share or have separate analog references. Care should be taken when selecting analog references to avoid cross talk noise.
Module
16-bit SAR ADC
12-bit DAC
CMP with 6-bit DAC
Table 3-2. Analog reference options
Reference option
1 - VREFH
2 - VDDA
3 - Reserved
1 - VREFH
2 - VDDA
Vin1 - VREFH
Vin2 - VDD
Comment/ Reference selection
Selected by ADCx_SC2[REFSEL]
Selected by DACx_C0[DACRFS] bit
Selected by CMPx_DACCR[VRSEL]
1. Use this option for the best ADC operation.
3.3 Core modules
3.3.1 ARM Cortex-M0+ core configuration
This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at arm.com
.
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Debug Interrupts
Chapter 3 Chip Configuration
Crossbar switch
ARM Cortex-M0+
Core
Figure 3-1. Core configuration
Topic
Full description
System memory map
Clocking
Power management
System/instruction/data bus module
Debug
Interrupts
Table 3-3. Reference links to related information
Related module
ARM Cortex-M0+ core, r0p0
Reference
ARM Cortex-M0+ Technical Reference Manual, r0p0
Crossbar switch
Serial wire debug
(SWD)
Nested vectored interrupt controller
(NVIC)
Miscellaneous control module (MCM)
3.3.1.1 ARM Cortex M0+ core
The ARM Cortex M0+ parameter settings are as follows:
Table 3-4. ARM Cortex-M0+ parameter settings
Parameter
Arch Clock Gating
DAP Slave Port Support
DAP ROM Table Base
Endianess
Breakpoints
Debug Support
Verilog name
ACG
AHBSLV
Value
1 = Present
1
BASEADDR
BE
BKPT
DBG
0xF000_2003
0
2
1 = Present
Table continues on the next page...
Description
Implements architectural clock gating
Supports any AHB debug access port (like the
CM4 DAP)
Base address for DAP ROM table
Little endian control for data transfers
Implements 2 breakpoints
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Core modules
Table 3-4. ARM Cortex-M0+ parameter settings (continued)
Parameter
Halt Event Support
I/O Port
IRQ Mask Enable
Debug Port Protocol
Core Memory Protection
Number of IRQs
Reset all registers
Multiplier
Multi-drop Support
System Tick Timer
DAP Target ID
User/Privileged
Vector Table Offset Register
WIC Support
WIC Requests
Watchpoints
Verilog name
HALTEV
IOP
IRQDIS
JTAGnSW
MPU
NUMIRQ
RAR
SMUL
SWMD
SYST
TARGETID
USER
VTOR
WIC
WICLINES
WPT
Value
1 = Present
1 = Present
0x00000000
0 = SWD
0 = Absent
32
0 = Standard
0 = Fast Mul
0 = Absent
1 = Present
0
1 = Present
1 = Present
1 = Present
34
2
Description
—
Implements single-cycle ld/st accesses to special address space
Assume (for now) all 32 IRQs are used (set if
IRQ is disabled)
SWD protocol, not JTAG
No MPU
Assume full NVIC request vector
Do not force all registers to be async reset
Implements single-cycle multiplier
Do not include serial wire support for multidrop
Implements system tick timer (for CM4 compatibility)
—
Implements processor operating modes
Implements relocation of exception vector table
Implements WIC interface
Exact number of wake-up IRQs is 34
Implements two watchpoints
For details on the ARM Cortex-M0+ processor core, see the ARM website: arm.com
.
3.3.1.2 Buses, interconnects, and interfaces
The ARM Cortex-M0+ core has two bus interfaces:
• Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all system memory, which includes flash memory and RAM
• Single 32-bit I/O port bus interfacing to the GPIO with 1-cycle loads and stores
3.3.1.3 System tick timer
The CLKSOURCE field in SysTick Control and Status register selects either the core clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock (when
CLKSOURCE = 0). Because the timing reference is a variable frequency, the TENMS field in the SysTick Calibration Value Register is always 0.
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Chapter 3 Chip Configuration
3.3.1.4 Debug facilities
This device supports standard ARM 2-pin SWD debug port.
3.3.1.5 Core privilege levels
The core on this device is implemented with both privileged and unprivileged levels. The
ARM documentation uses different terms than this document to distinguish between privilege levels.
If you see this term...
Privileged
Unprivileged or user it also means this term...
Supervisor
User
3.3.2 Nested vectored interrupt controller (NVIC) configuration
This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at arm.com
.
Interrupts
Topic
Full description
PPB
Nested Vectored
Interrupt Controller
(NVIC)
Module
Module
System memory map
Clocking
Power management
Private peripheral bus
(PPB)
Module
Figure 3-2. NVIC configuration
Table 3-5. Reference links to related information
Related module
Nested vectored interrupt controller
(NVIC)
—
—
—
ARM Cortex-M0+ core
Reference
ARM Cortex-M0+ Technical Reference Manual
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Core modules
3.3.2.1 Interrupt priority levels
This device supports four priority levels for interrupts. Therefore, in the NVIC, each source in the IPR registers contains two bits. For example, IPR0 is shown below:
R
W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRQ3
0 0 0 0 0 0
IRQ2
0 0 0 0 0 0
IRQ1
0 0 0 0 0 0
IRQ0
0 0 0 0 0 0
3.3.2.2 Non-maskable interrupt
The non-maskable interrupt request to the NVIC is controlled by the external NMI signal.
The pin the NMI signal is multiplexed on, must be configured for the NMI function to generate the non-maskable interrupt request.
3.3.2.3 Interrupt channel assignments
The interrupt vector assignments are defined in the following table.
• Vector number — the value stored on the stack when an interrupt is serviced.
• IRQ number — non-core interrupt source count, which is the vector number minus
16.
The IRQ number is used within ARM's NVIC documentation.
NOTE
The NVIC wake-up sources in the following table support only down to VLPS.
Address
0x0000_0000
0x0000_0004
0x0000_0008
0x0000_000C
0x0000_0010
0x0000_0014
0x0000_0018
0
3
4
1
2
5
6
Vector
—
—
—
—
—
—
—
Table 3-7. Interrupt vector assignments
—
—
—
—
—
—
NVIC
IPR register number
Source module Source description
ARM core system handler vectors
— ARM core Initial stack pointer
ARM core
ARM core
ARM core
—
—
—
Initial program counter
Non-maskable interrupt (NMI)
Hard fault
—
—
—
Table continues on the next page...
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Address
0x0000_001C
0x0000_0020
0x0000_0024
0x0000_0028
0x0000_002C
0x0000_0030
0x0000_0034
0x0000_0038
10
11
12
13
7
8
9
14
15
Chapter 3 Chip Configuration
Table 3-7. Interrupt vector assignments (continued)
Vector
Source description
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
NVIC
IPR register number
Source module
—
—
—
—
ARM core
—
—
ARM core
— ARM core
—
—
—
—
Supervisor call (SVCall)
—
—
Pendable request for system service
(PendableSrvReq)
System tick timer (SysTick)
0x0000_006C
0x0000_0070
0x0000_0074
0x0000_0078
0x0000_007C
0x0000_0080
0x0000_0084
0x0000_0088
0x0000_008C
0x0000_0090
0x0000_0094
0x0000_0098
0x0000_009C
0x0000_00A0
0x0000_00A4
0x0000_00A8
0x0000_003C
Non-Core Vectors
0x0000_0040
0x0000_0044
0x0000_0048
0x0000_004C
0x0000_0050
0x0000_0054
0x0000_0058
0x0000_005C
0x0000_0060
0x0000_0064
0x0000_0068
35
36
37
38
31
32
33
34
39
40
41
42
27
28
29
30
23
24
25
26
19
20
21
22
16
17
18
19
20
21
22
15
16
17
18
23
24
25
26
11
12
13
14
7
8
9
10
5
6
3
4
0
1
2
5
5
4
5
4
4
3
4
6
6
5
6
3
3
2
3
2
2
1
2
1
1
0
1
0
0
0
SPI1
UART0
UART1
UART2
ADC0
CMP0
TPM0
TPM1
DMA
DMA
DMA
DMA
—
FTFA
PMC
LLWU
I 2 C0
I 2 C1
SPI0
TPM2
RTC
RTC
PIT
I 2 S0
USB OTG
DAC0
TSI0
Table continues on the next page...
DMA channel 0 transfer complete and error
DMA channel 1 transfer complete and error
DMA channel 2 transfer complete and error
DMA channel 3 transfer complete and error
—
Command complete and read collision
Low-voltage detect, low-voltage warning
Low Leakage Wakeup
—
—
Single interrupt vector for all sources
Single interrupt vector for all sources
Status and error
Status and error
Status and error
—
—
—
—
—
Alarm interrupt
Seconds interrupt
Single interrupt vector for all channels
Single interrupt vector for all sources
—
—
—
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Core modules
Address
0x0000_00AC
0x0000_00B0
0x0000_00B4
0x0000_00B8
0x0000_00BC
43
44
45
46
47
Table 3-7. Interrupt vector assignments (continued)
Vector
27
28
29
30
31
7
7
6
7
7
NVIC
IPR register number
Source module Source description
MCG
LPTMR0
—
—
— —
Port control module Pin detect (Port A)
Port control module Pin detect (Single interrupt vector for Port C and Port D)
1. Indicates the NVIC's interrupt source number.
2. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4
3.3.2.3.1 Determining the bitfield and register location for configuring a particular interrupt
Suppose you need to configure the SPI0 interrupt. The following table is an excerpt of the
SPI0 row from Interrupt priority levels
.
Address
0x0000_0068
Vector
26
Table 3-8. Interrupt vector assignments
10
NVIC IPR register
2
Source module
SPI0
Source description
Single interrupt vector for all sources
1. Indicates the NVIC's interrupt source number.
2. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4.
• The NVIC registers you would use to configure the interrupt are:
• NVICIPR2
• To determine the particular IRQ's field location within these particular registers:
• NVICIPR2 field starting location = 8 * (IRQ mod 4) + 6 = 22
Since the NVICIPR fields are 2-bit wide (4 priority levels), the NVICIPR2 field range is 22–23.
Therefore, the following field locations are used to configure the SPI0 interrupts:
• NVICIPR2[23:22]
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Chapter 3 Chip Configuration
3.3.2.4 Serialization of memory operations when clearing interrupt flags
When clearing flags associated with an interrupt source in the interrupt service routine
(ISR), the flag must be read back before exiting the ISR to ensure the flag is cleared.
Otherwise, the interrupt could still be pending, causing the ISR to be entered again inadvertently.
3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration
This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at arm.com
.
Clock logic
Wake-up requests
Asynchronous
Wake-up Interrupt
Controller (AWIC)
Module
Module
Figure 3-3. Asynchronous wake-up interrupt controller configuration
Topic
System memory map
Clocking
Power management
Wake-up requests
Table 3-9. Reference links to related information
Related module
—
—
—
Nested vectored interrupt controller
(NVIC)
—
Reference
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System modules
3.3.3.1 Wake-up sources
The device uses the following internal and external inputs to the AWIC module.
Table 3-10. AWIC stop wake-up sources
Wake-up source
Available system resets
Low-voltage detect
Low-voltage warning
Pin interrupts
ADC
CMP0
I 2 Cx
UART0
UART1, UART2
RTC
TSI
NMI
TPMx
LPTMR
SPI
Description
RESET_b pin when LPO is its clock source
Power management controller—functional in Stop mode
Power management controller—functional in Stop mode
Port control module—any enabled pin interrupt is capable of waking the system.
The ADC is functional when using internal clock source.
Interrupt in normal or trigger mode
Address match wakeup
Any enabled interrupt can be a source as long as the module remains clocked.
Active edge on RXD
Alarm or seconds interrupt
Any enabled interrupt can be a source as long as the module remains clocked.
NMI_b pin
Any enabled interrupt can be a source as long as the module remains clocked.
Any enabled interrupt can be a source as long as the module remains clocked.
Slave mode interrupt
3.4 System modules
3.4.1 SIM configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Chapter 3 Chip Configuration
Peripheral bridge
Register access
System integration module (SIM)
Topic
Full description
System memory map
Clocking
Power management
Figure 3-4. SIM configuration
Table 3-11. Reference links to related information
Related module
SIM
—
—
—
Reference
3.4.2 System mode controller (SMC) configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bridge
Register access
Resets
System Mode
Controller (SMC)
Topic
Full description
System memory map
Power management
Figure 3-5. System mode controller configuration
Table 3-12. Reference links to related information
Related module
System mode controller
(SMC)
—
—
Reference
Table continues on the next page...
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System modules
Topic
—
—
Table 3-12. Reference links to related information (continued)
Related module
Power management controller (PMC)
Low-leakage wakeup unit (LLWU)
Reset control module
(RCM)
Reference
3.4.2.1 VLLS2 not supported
VLLS2 power mode is not supported on this device.
3.4.3 PMC configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bridge
Register access
Module signals Power Management
Controller (PMC)
Module signals
Figure 3-6. PMC configuration
Topic
Full description
System memory map
Power management
Full description
—
Table 3-13. Reference links to related information
Related module
PMC
—
—
System mode controller
(SMC)
Low-leakage wakeup unit (LLWU)
Reset control module
(RCM)
Reference
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Chapter 3 Chip Configuration
3.4.4 Low-Leakage Wake-up Unit (LLWU) Configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bridge 0
Register access
Wake-up requests
Low-Leakage Wake-up
Unit (LLWU)
Module
Module
Topic
Full description
System memory map
Clocking
Power management
Wake-up requests
Figure 3-7. Low-Leakage Wake-up Unit configuration
Table 3-14. Reference links to related information
Related module
LLWU
Reference
Power Management Controller (PMC)
Power Management
Controller (PMC)
System Mode
Controller (SMC)
3.4.4.1 LLWU interrupt
NOTE
Do not mask the LLWU interrupt when in LLS mode. Masking the interrupt prevents the device from exiting stop mode when a wakeup is detected.
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System modules
3.4.4.2 Wake-up Sources
The device uses the following internal peripheral and external pin inputs as wakeup sources to the LLWU module. LLWU_Px are external pin inputs, and LLWU_M0IF-
M7IF are connections to the internal peripheral interrupt flags.
NOTE
In addition to the LLWU wakeup sources, the device also wakes from low power modes when NMI or RESET pins are enabled and the respective pin is asserted.
LLWU pin
LLWU_P5
LLWU_P6
LLWU_P7
LLWU_P8
LLWU_P9
LLWU_P10
LLWU_P14
LLWU_P15
LLWU_M0IF
LLWU_M1IF
LLWU_M2IF
LLWU_M3IF
LLWU_M4IF
LLWU_M5IF
LLWU_M6IF
LLWU_M7IF
Table 3-15. Wakeup Sources
Module source or pin name
PTB0
PTC1
PTC3
PTC4
PTC5
PTC6
PTD4
PTD6
LPTMR0
CMP0
Reserved
Reserved
TSI0
RTC Alarm
Reserved
RTC Seconds
3.4.5 MCM configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Chapter 3 Chip Configuration
Transfers
Miscellaneous
Control Module
(MCM)
Transfers
Topic
Full description
System memory map
Clocking
Power management
Private peripheral bus
(PPB)
Transfer
Figure 3-8. MCM configuration
Table 3-16. Reference links to related information
Related module
Miscellaneous control module (MCM)
—
—
—
ARM Cortex-M0+ core
Reference
Flash memory controller
3.4.6 Crossbar-light switch configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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System modules
Crossbar Switch
Flash controller
GPIO controller
ARM core unified bus
DMA
SRAML
SRAMU
USB
Peripheral bridge 0
Peripherals
Master Modules Slave Modules
Figure 3-9. Crossbar-light switch integration
Table 3-17. Reference links to related information
Topic Related module
Full description
System memory map
Crossbar switch
—
Clocking —
Crossbar switch master ARM Cortex-M0+ core
Crossbar switch master
Crossbar switch master
Crossbar switch slave
Crossbar switch slave
Crossbar switch slave
2-ported peripheral
DMA controller
USB FS/LS
Flash memory controller
SRAM controller
Peripheral bridge
GPIO controller
Reference
3.4.6.1 Crossbar-light switch master assignments
The masters connected to the crossbar switch are assigned as follows:
Master module
ARM core unified bus
DMA
USB OTG
2
3
0
Master port number
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Chapter 3 Chip Configuration
3.4.6.2 Crossbar switch slave assignments
This device contains 3 slaves connected to the crossbar switch.
The slave assignment is as follows:
Slave module
Flash memory controller
SRAM controller
Peripheral bridge 0
0
1
2
Slave port number
3.4.7 Peripheral bridge configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Transfers AIPS-Lite peripheral bridge
Transfers
Topic
Full description
System memory map
Clocking
Crossbar switch
Figure 3-10. Peripheral bridge configuration
Table 3-18. Reference links to related information
Related module
Peripheral bridge
(AIPS-Lite)
—
—
Crossbar switch
Reference
3.4.7.1 Number of peripheral bridges
This device contains one peripheral bridge.
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System modules
3.4.7.2 Memory maps
The peripheral bridges are used to access the registers of most of the modules on this device. See
for the memory slot assignment for each module.
3.4.8 DMA request multiplexer configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bridge 0
Topic
Full description
System memory map
Clocking
Power management
Channel request
Requests
Register access
Requests
DMA controller
Channel request DMA Request
Multiplexer
Module
Module
Module
Figure 3-11. DMA request multiplexer configuration
Table 3-19. Reference links to related information
Related module
DMA request multiplexer
Reference
DMA controller
3.4.8.1 DMA MUX Request Sources
This device includes a DMA request mux that allows up to 63 DMA request signals to be mapped to any of the 4 DMA channels. Because of the mux there is no hard correlation between any of the DMA request sources and a specific DMA channel. Some of the modules support Asynchronous DMA operation as indicated by the last column in the following DMA source assignment table.
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23
24
25
26
19
20
21
22
15
16
17
18
11
12
13
14
Source number
0
1
2
7
8
9
10
5
6
3
4
31
32
33
34
27
28
29
30
35
36
37
38
Chapter 3 Chip Configuration
Table 3-20. DMA request sources - MUX 0
Source module Source description Async DMA capable
—
Reserved
UART0
UART0
UART1
UART1
UART2
UART2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
I 2 S0
I 2 S0
SPI0
SPI0
SPI1
SPI1
Reserved
Reserved
I 2 C0
I 2 C1
TPM0
TPM0
TPM0
TPM0
TPM0
TPM0
Reserved
Reserved
TPM1
TPM1
TPM2
TPM2
Reserved
Reserved
Reserved
Transmit
Receive
Transmit
Receive
Transmit
—
—
—
—
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
—
Not used
Receive
Transmit
Receive
Transmit
Receive
Transmit
—
—
—
—
—
—
Receive
—
Channel 0
Channel 1
Channel 0
Channel 1
—
—
—
Table continues on the next page...
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
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System modules
Source number
51
52
53
54
47
48
49
50
43
44
45
46
39
40
41
42
59
60
61
62
55
56
57
58
63
Table 3-20. DMA request sources - MUX 0 (continued)
Source module
Reserved
ADC0
Reserved
CMP0
Reserved
Reserved
DAC0
Reserved
Reserved
Reserved
Port control module
Reserved
Port control module
Port control module
Reserved
TPM0
TPM1
TPM2
TSI
Reserved
Reserved
DMA MUX
DMA MUX
DMA MUX
DMA MUX
Source description
—
—
Port A
—
Port C
Port D
—
Overflow
—
—
—
—
—
—
—
—
Overflow
Overflow
—
—
—
Always enabled
Always enabled
Always enabled
Always enabled
1. Configuring a DMA channel to select source 0 or any of the reserved sources disables that DMA channel.
Async DMA capable
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
3.4.8.2 DMA transfers via PIT trigger
The PIT module can trigger a DMA transfer on the first two DMA channels. The assignments are detailed at
PIT/DMA periodic trigger assignments .
3.4.9 DMA Controller Configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Chapter 3 Chip Configuration
Peripheral bridge 0
Register access
Transfers
DMA Controller
Requests
Topic
Full description
System memory map
Clocking
Power management
Crossbar switch
Requests
Figure 3-12. DMA Controller configuration
Table 3-21. Reference links to related information
Related module
DMA controller
Crossbar switch
Reference
3.4.10 Computer operating properly (COP) watchdog configuration
This section summarizes how the module has been configured in the chip.
Peripheral bridge 0
Register access
WDOG
Topic
Clocking
Power management
Figure 3-13. COP watchdog configuration
Table 3-22. Reference links to related information
Related module
—
—
Table continues on the next page...
Reference
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System modules
Table 3-22. Reference links to related information (continued)
Topic
Programming model
Related module
System integration module (SIM)
Reference
3.4.10.1 COP clocks
The multiple clock inputs for the COP are:
• 1 kHz clock
• bus clock
3.4.10.2 COP watchdog operation
The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), the application software must reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter before it times out, a system reset is generated to force the system back to a known starting point.
After any reset, the COP watchdog is enabled. If the COP watchdog is not used in an application, it can be disabled by clearing SIM_COPC[COPT].
The COP counter is reset by writing 0x55 and 0xAA (in that order) to the address of the
SIM's Service COP (SRVCOP) register during the selected timeout period. Writes do not affect the data in the SRVCOP register. As soon as the write sequence is complete, the
COP timeout period is restarted. If the program fails to perform this restart during the timeout period, the microcontroller resets. Also, if any value other than 0x55 or 0xAA is written to the SRVCOP register, the microcontroller immediately resets.
SIM_COPC[COPCLKS] select the clock source used for the COP timer. The clock source options are either the bus clock or an internal 1 kHz clock source. With each clock source, the associated timeouts are controlled by SIM_COPC[COPT]. The following table summarizes the control functions of SIM_COPCTRL[COPCLKS] and
SIM_COPC[COPT] fields. The COP watchdog defaults to operation from the 1 kHz clock source and the longest timeout is 2 10 cycles.
Table 3-23. COP configuration options
Control bits
SIM_COPC[COPCLKS] SIM_COPC[COPT]
N/A 00
Clock source
COP window opens
(SIM_COPC[COPW]=1)
N/A
Table continues on the next page...
N/A
COP overflow count
COP is disabled.
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Chapter 3 Chip Configuration
Table 3-23. COP configuration options (continued)
Control bits
SIM_COPC[COPCLKS] SIM_COPC[COPT]
1
1
1
0
0
0
01
10
11
01
10
11
Clock source
1 kHz
1 kHz
1 kHz
Bus
Bus
Bus
COP window opens
(SIM_COPC[COPW]=1)
N/A
N/A
N/A
6,144 cycles
49,152 cycles
196,608 cycles
COP overflow count
2 5 cycles (32 ms)
2 8 cycles (256 ms)
2 10 cycles (1024 ms)
2 13 cycles
2 16 cycles
2 18 cycles
After the bus clock source is selected, windowed COP operation is available by setting
SIM_COPC[COPW]. In this mode, writes to SIM_SRVCOP to clear the COP timer must occur in the last 25% of the selected timeout period. A premature write immediately resets the chip. When the 1 kHz clock source is selected, windowed COP operation is not available.
The COP counter is initialized by the first writes to SIM_COPC and after any system reset. Subsequent writes to SIM_COPC have no effect on COP operation. Even if an application uses the reset default settings of SIM_COPC[COPT],
SIM_COPC[COPCLKS], and SIM_COPC[COPW] fields, the user should write to the write-once SIM_COPC register during reset initialization to lock in the settings. This approach prevents accidental changes if the application program becomes lost.
The write to SIM_SRVCOP that services (clears) the COP counter should not be placed in an interrupt service routine (ISR) because the ISR could continue to be executed periodically even if the main application program fails.
If the selected clock is not the 1 kHz clock source, the COP counter does not increment while the microcontroller is in Debug mode or while the system is in Stop (including
VLPS or LLS) mode. The COP counter resumes when the microcontroller exits Debug or
Stop mode.
If the 1 kHz clock source is selected, the COP counter is re-initialized to 0 upon entry to either Debug mode or Stop (including VLPS or LLS) mode. The counter begins from 0 upon exit from Debug mode or Stop mode.
Regardless of the clock selected, the COP is disabled when the chip enters a VLLSx mode. Upon a reset that wakes the chip from the VLLSx mode, the COP is reinitialized and enabled as for any reset.
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Clock modules
3.4.10.3 Clock gating
This family of devices includes clock gating control for each peripheral, that is, the clock to each peripheral can explicitly be gated on or off, using clock-gate control bits in the
SIM module.
3.5 Clock modules
3.5.1 MCG configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bridge
Register access
Multipurpose Clock
Generator (MCG)
Topic
Full description
System memory map
Clocking
Power management
Signal multiplexing
Figure 3-14. MCG configuration
Table 3-24. Reference links to related information
Related module
MCG
—
—
—
Port control
Reference
3.5.1.1 MCG FLL modes
The MCGFLLCLK frequency is limited to 48 MHz at maximum in this device. The digitally-controller oscillator (DCO) is limited to the two lowest range settings, that is,
MCG_C4[DRST_DRS] must be set to either 0b00 or 0b01.
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Chapter 3 Chip Configuration
3.5.2 OSC configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bridge
Register access
System oscillator
Module signals
Topic
Full description
System memory map
Clocking
Power management
Signal multiplexing
Full description
Figure 3-15. OSC configuration
Table 3-25. Reference links to related information
Related module
OSC
—
—
—
Port control
MCG
Reference
3.5.2.1 OSC modes of operation with MCG and RTC
The most common method of controlling the OSC block is through MCG_C1[CLKS] and the fields of MCG_C2 register to configure the oscillator frequency range, gain-mode, and for crystal or external clock operation. OSC_CR also provides control for enabling the OSC module and configuring internal load capacitors for the EXTAL and XTAL pins. See the
MCG chapters for more details.
RTC_CR[OSCE] has overriding control over the MCG and OSC_CR enable functions.
When RTC_CR[OSCE] is set, the OSC is configured for low frequency, low power and
RTC_CR[SCxP] override OSC_CR[SCxP] to control the internal capacitance configuration. See the RTC chapter for more details.
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Memories and memory interfaces
3.6 Memories and memory interfaces
3.6.1 Flash memory configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bus controller 0
Register access
Transfers
Flash memory
Topic
Full description
System memory map
Clocking
Transfers
Register access
Figure 3-16. Flash memory configuration
Table 3-26. Reference links to related information
Related module
Flash memory
—
—
Flash memory controller
Peripheral bridge
Reference
3.6.1.1 Flash memory sizes
The devices covered in this document contain either 1 or 2 program flash blocks, each consisting of 1 KB sectors.
The amounts of flash memory for the devices covered in this document are:
Device
MKL26Z256VLH4
MKL26Z256VMP4
MKL26Z128VLL4
Table 3-27. KL26 flash memory size
Program flash (KB) Block 0 (P-Flash) address range
256
256
128
Table continues on the next page...
Block 1 (P-Flash) address range
0x0000_0000 – 0x0001_FFFF 0x0002_0000 – 0x0003_FFFF
0x0000_0000 – 0x0001_FFFF 0x0002_0000 – 0x0003_FFFF
0x0000_0000 – 0x0000_FFFF 0x0001_0000 – 0x0001_FFFF
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Device
MKL26Z256VLL4
MKL26Z128VMC4
MKL26Z256VMC4
Chapter 3 Chip Configuration
Table 3-27. KL26 flash memory size (continued)
Program flash (KB)
256
128
256
Block 0 (P-Flash) address range
Block 1 (P-Flash) address range
0x0000_0000 – 0x0001_FFFF 0x0002_0000 – 0x0003_FFFF
0x0000_0000 – 0x0000_FFFF 0x0001_0000 – 0x0001_FFFF
0x0000_0000 – 0x0002_FFFF 0x0002_0000 – 0x0003_FFFF
Device
MKL26Z32VFM4
MKL26Z64VFM4
MKL26Z128VFM4
MKL26Z32VFT4
MKL26Z64VFT4
MKL26Z128VFT4
MKL26Z32VLH4
MKL26Z64VLH4
MKL26Z128VLH4
Table 3-28. KL26 flash memory size
Program flash (KB)
32
64
128
32
64
128
32
64
128
Block 0 (P-Flash) address range
0x0000_0000 – 0x0000_7FFF
0x0000_0000 – 0x0000_FFFF
0x0000_0000 – 0x0001_FFFF
0x0000_0000 – 0x0000_7FFF
0x0000_0000 – 0x0000_FFFF
0x0000_0000 – 0x0001_FFFF
0x0000_0000 – 0x0000_7FFF
0x0000_0000 – 0x0000_FFFF
0x0000_0000 – 0x0001_FFFF
3.6.1.2 Flash memory map
The flash memory and the flash registers are located at different base addresses as shown in the figure found here.
The base address for each is specified in System memory map .
Flash memory base address
Registers
Flash base address
Flash configuration field
Flash
Figure 3-17. Flash memory map
The on-chip flash memory is implemented in a portion of the allocated Flash range to form a contiguous block in the memory map beginning at address 0x0000_0000. See
Flash memory sizes for details of supported ranges.
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Memories and memory interfaces
Access to the flash memory ranges outside the amount of flash on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master. Read collision events in which flash memory is accessed while a flash memory resource is being manipulated by a flash command also generate a bus error response.
When software needs to access the flash memory while a flash memory resource is being manipulated by a flash command, software can enable a stall mechanism to avoid a read collision. The stall mechanism allows software to execute code from the same block on which flash operations are being performed. However, software must ensure the sector the flash operations are being performed on is not the same sector from which the code is executing.
The MCM_PLACR[ESFC] bit enables the stall mechanism. This bit must be set only just before the flash operation is executed and must be cleared when the operation completes.
3.6.1.3 Flash security
For information on how flash security is implemented on this device, see Chip Security .
3.6.1.4 Flash modes
The flash memory chapter defines two modes of operation: NVM normal and NVM special modes. On this device, the flash memory only operates in NVM normal mode. All references to NVM special mode must be ignored.
3.6.1.5 Erase all flash contents
In addition to software, the entire flash memory may be erased external to the flash memory via the SW-DP debug port by setting MDM-AP CONTROL[0]. MDM-AP
STATUS[0] is set to indicate the mass erase command has been accepted. MDM-AP
STATUS[0] is cleared when the mass erase completes.
3.6.1.6 FTFA_FOPT register
The flash memory's FTFA_FOPT register allows the user to customize the operation of
the MCU at boot time. See FOPT boot options
for details of its definition.
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Chapter 3 Chip Configuration
3.6.2 Flash memory controller configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
See MCM_PLACR register description for details on the reset configuration of the FMC.
MCM
Transfers
Flash memory controller
Transfers
Topic
Full description
System memory map
Clocking
Transfers
Transfers
Register access
Figure 3-18. Flash memory controller configuration
Table 3-29. Reference links to related information
Related module
Flash memory controller
—
—
Flash memory
Crossbar switch
MCM
Reference
3.6.3 SRAM configuration
This section summarizes how the module has been configured in the chip.
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Memories and memory interfaces
Cortex-M0+ core crossbar switch
SRAM controller
Transfers
SRAM upper
SRAM lower
Topic
Full description
System memory map
Clocking
ARM Cortex-M0+ core
Figure 3-19. SRAM configuration
Table 3-30. Reference links to related information
Related module
SRAM
—
—
—
Reference
3.6.3.1 SRAM sizes
This device contains SRAM which could be accessed by bus masters through the crossbar switch. The amount of SRAM for the devices covered in this document is shown in the following table.
Table 3-31. KL26 SRAM memory size
Device
MKL26Z256VMC4
MKL26Z128VMC4
MKL26Z256VLL4
MKL26Z128VLL4
MKL26Z256VMP4
MKL26Z256VLH4
MKL26Z128VLH4
MKL26Z64VLH4
MKL26Z32VLH4
MKL26Z128VFT4
MKL26Z64VFT4
MKL26Z32VFT4
MKL26Z128VFM4
MKL26Z64VFM4
MKL26Z32VFM4
SRAM (KB)
32
16
32
16
8
8
4
16
32
32
16
4
16
8
4
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Chapter 3 Chip Configuration
3.6.3.2 SRAM ranges
The on-chip SRAM is a single contiguous block split into two ranges: 1/4 is allocated to
SRAM_L, and 3/4 is allocated to SRAM_U. Regardless of the block size, the SRAM is implemented such that:
• SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending address.
• SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning address.
Valid address ranges for SRAM_L and SRAM_U are then defined as:
• SRAM_L = [0x2000_0000–(SRAM_size/4)] to 0x1FFF_FFFF
• SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size*(3/4))-1]
This is illustrated in the following figure.
0x2000_0000 – SRAM_size/4
SRAM_L
0x1FFF_FFFF
0x2000_0000
SRAM_U
0x2000_0000 + SRAM_size(3/4) - 1
Figure 3-20. SRAM blocks memory map
For example, for a device containing 16 KB of SRAM, the ranges are:
• SRAM_L: 0x1FFF_F000 – 0x1FFF_FFFF
• SRAM_U: 0x2000_0000 – 0x2000_2FFF
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Analog
3.6.3.3 SRAM retention in low power modes
The SRAM is retained down to VLLS3 mode. In VLLS1 and VLLS0, no SRAM is retained.
3.6.4 System Register File Configuration
This section summarizes how the module has been configured in the chip.
Peripheral bridge 0
Register access
Register file
Topic
Full description
System memory map
Clocking
Power management
Figure 3-21. System Register file configuration
Table 3-32. Reference links to related information
Related module
Register file
Reference
3.6.4.1 System Register file
This device includes a 32-byte register file that is powered in all power modes.
Also, it retains contents during low-voltage detect (LVD) events and is only reset during a power-on reset.
Base address of this register file is 0x4004_1000. ( see Table "Peripheral bridge 0 slot assignment").
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Chapter 3 Chip Configuration
3.7 Analog
3.7.1 16-bit SAR ADC configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bus controller 0
Register access
Other peripherals
16-bit SAR ADC
Module signals
Topic
Full description
System memory map
Clocking
Power management
Signal multiplexing
Figure 3-22. 16-bit SAR ADC configuration
Table 3-33. Reference links to related information
Related module
16-bit SAR ADC
—
—
—
Port control
Reference
3.7.1.1 ADC instantiation information
This device contains one 16-bit successive approximation ADC with up to 16 channels.
The ADC supports both software and hardware triggers. The hardware trigger sources are
listed in the Module-to-Module section .
The number of ADC channels present on the device is determined by the pinout of the specific device package and is shown in the following table.
Table 3-34. Number of KL26 ADC channels
Device
MKL26Z32VFM4
MKL26Z64VFM4
Number of ADC channels
7
7
Table continues on the next page...
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Analog
Table 3-34. Number of KL26 ADC channels (continued)
Device
MKL26Z128VFM4
MKL26Z32VFT4
MKL26Z64VFT4
MKL26Z128VFT4
MKL26Z32VLH4
MKL26Z64VLH4
MKL26Z128VLH4
MKL26Z256VLH4
MKL26Z256VMP4
MKL26Z128VLL4
MKL26Z256VLL4
MKL26Z128VMC4
MKL26Z256VMC4
Number of ADC channels
7
13
13
14
14
16
13
13
13
13
16
16
16
3.7.1.2 DMA Support on ADC
Applications may require continuous sampling of the ADC that may have considerable load on the CPU. The ADC supports DMA request functionality for higher performance when the ADC is sampled at a very high rate. The ADC can trigger the DMA (via DMA req) on conversion completion.
3.7.1.3 ADC0 connections/channel assignment
NOTE
As indicated by the following sections, each ADCx_DPx input and certain ADCx_DMx inputs may operate as single-ended
ADC channels in single-ended mode.
00000
00001
00010
00011
00100
ADC channel
(SC1n[ADCH])
DAD0
DAD1
DAD2
DAD3
AD4a
Table 3-35. ADC0 channel assignment
Channel Input signal (SC1n[DIFF]=
1)
Input signal (SC1n[DIFF]=
0)
ADC0_DP0 and ADC0_DM0 ADC0_DP0/ADC0_SE0
ADC0_DP1 and ADC0_DM1 ADC0_DP1/ADC0_SE1
ADC0_DP2 and ADC0_DM2 ADC0_DP2/ADC0_SE2
ADC0_DP3 and ADC0_DM3 ADC0_DP3/ADC0_SE3
Reserved ADC0_DM0/ADC0_SE4a
Table continues on the next page...
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11000
11001
11010
11011
11100
11101
11110
11111
01101
01110
01111
10000
10001
10010
10011
10100
00101
00110
00111
00100
00101
00110
00111
01000
01001
01010
01011
01100
10101
10110
10111
ADC channel
(SC1n[ADCH])
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD5a
AD6a
AD7a
AD4b
AD5b
AD6b
AD7b
AD8
AD17
AD18
AD19
AD20
AD21
AD22
AD23
Chapter 3 Chip Configuration
Table 3-35. ADC0 channel assignment (continued)
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
Channel Input signal (SC1n[DIFF]=
1)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Temperature Sensor (Diff)
Reserved
-VREFH (Diff)
Reserved
Module Disabled
Input signal (SC1n[DIFF]=
0)
ADC0_DM1/ADC0_SE5a
ADC0_DM2/ADC0_SE6a
ADC0_DM3/ADC0_SE7a
ADC0_SE4b
ADC0_SE5b
ADC0_SE6b
ADC0_SE7b
ADC0_SE8
ADC0_SE9
Reserved
ADC0_SE11
ADC0_SE12
ADC0_SE13
ADC0_SE14
ADC0_SE15
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
12-bit DAC0 Output/
ADC0_SE23
Reserved
Reserved
Temperature Sensor (S.E)
Bandgap (S.E)
Reserved
VREFH (S.E)
VREFL
Module Disabled
1. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter for details.
2. This is the PMC bandgap 1V reference voltage. Prior to reading from this ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (V
BG specification.
)
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3.7.1.4 ADC analog supply and reference connections
This device includes dedicated VDDA and VSSA pins.
This device contains separate VREFH and VREFL pins on 48-pin and higher devices.
These pins are internally connected to VDDA and VSSA respectively, on 32-pin devices.
V
ALTH
and V
ALTL
are internally connected to VDDA and VSSA respectively.
3.7.1.5 Alternate clock
For this device, the alternate clock is connected to the external reference clock
(OSCERCLK).
NOTE
This clock option is only usable when OSCERCLK is in the
MHz range. A system with OSCERCLK in the kHz range has the optional clock source below minimum ADC clock operating frequency.
3.7.2 CMP configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bridge 0
Register access
Module signals
Other peripherals
CMP
88
Topic
Full description
System memory map
Clocking
Power management
Figure 3-23. CMP configuration
Table 3-36. Reference links to related information
Related module
Comparator (CMP)
—
—
—
Table continues on the next page...
Reference
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Chapter 3 Chip Configuration
Table 3-36. Reference links to related information (continued)
Topic
Signal multiplexing
Related module
Port control
Reference
3.7.2.1 CMP instantiation information
The device includes one high-speed comparator and two 8-input multiplexers for both the inverting and non-inverting inputs of the comparator. Each CMP input channel connects to both muxes. Two of the channels are connected to internal sources, leaving resources to support up to 6 input pins. See the channel assignment table for a summary of CMP input connections for this device.
The CMP also includes one 6-bit DAC with a 64-tap resistor ladder network, which provides a selectable voltage reference for applications where voltage reference is needed for internal connection to the CMP.
The CMP can be optionally on in all modes except VLLS0.
The CMP has several module-to-module interconnects in order to facilitate ADC triggering, TPM triggering, and UART IR interfaces. For complete details on the CMP module interconnects, see the
The CMP does not support window compare function and a 0 must always be written to
CMP_CR1[WE]. The sample function has limited functionality since the SAMPLE input to the block is not connected to a valid input. Usage of sample operation is limited to a divided version of the bus clock (CMP_CR1[SE] = 0).
Due to the pin number limitation, the CMP pass through mode is not supported by this device, so the CMPx_MUXCR[PSTM] must be left as 0.
3.7.2.2 CMP input connections
The following table shows the fixed internal connections to the CMP.
CMP inputs
IN0
IN1
IN2
IN3
Table 3-37. CMP input connections
CMP0
CMP0_IN0
CMP0_IN1
CMP0_IN2
CMP0_IN3
Table continues on the next page...
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Analog
Table 3-37. CMP input connections (continued)
CMP inputs
IN4
IN5
CMP0
12-bit DAC0 reference/ CMP0_IN4
CMP0_IN5
IN6
IN7
6-bit DAC0 reference
1. This is the PMC bandgap 1V reference voltage. Prior to using as CMP input, ensure that you enable the bandgap buffer by setting PMC_REGSC[BGBE]. See the device data sheet for the bandgap voltage (V
BG
) specification.
3.7.2.3 CMP external references
The 6-bit DAC sub-block supports selection of two references. For this device, the references are connected as follows:
• VREFH–V in1
input. When using VREFH, any ADC conversion using this same reference at the same time is negatively impacted.
• VDD–V in2
input
3.7.2.4 CMP trigger mode
The CMP and 6-bit DAC sub-block supports trigger mode operation when
CMP_CR1[TRIGM] is set. When trigger mode is enabled, the trigger event will initiate a compare sequence that must first enable the CMP and DAC prior to performing a CMP operation and capturing the output. In this device, control for this two-staged sequencing is provided from the LPTMR. The LPTMR triggering output is always enabled when the
LPTMR is enabled. The first signal is supplied to enable the CMP and DAC and is asserted at the same time as the TCF flag is set. The delay to the second signal that triggers the CMP to capture the result of the compare operation is dependent on the
LPTMR configuration.
• In Time Counter mode with prescaler enabled, the delay is 1/2 Prescaler output period.
• In Time Counter mode with prescaler bypassed, the delay is 1/2 Prescaler clock period.
The delay between the first signal from LPTMR and the second signal from LPTMR must be greater than the analog comparator initialization delay as defined in the device datasheet.
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Chapter 3 Chip Configuration
3.7.3 12-bit DAC configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bus controller 0
Register access
Module signals
Other peripherals
12-bit DAC
Topic
Full description
System memory map
Clocking
Power management
Signal multiplexing
Figure 3-24. 12-bit DAC configuration
Table 3-38. Reference links to related information
Related module
12-bit DAC
Port control
Reference
3.7.3.1 12-bit DAC instantiation information
This device contains one 12-bit digital-to-analog converter (DAC) with programmable reference generator output. The DAC includes a two word FIFO for DMA support.
3.7.3.2 12-bit DAC output
The output of the DAC can be placed on an external pin or selected as an input to the analog comparator or ADC.
3.7.3.3 12-bit DAC Analog Supply and Reference Connections
This device includes dedicated VDDA and VSSA pins.
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Timers
This device contains separate VREFH and VREFL pins on 48-pin and higher devices.
These pins are internally connected to VDDA and VSSA respectively, on 32-pin devices.
3.7.3.4 12-bit DAC reference
For this device VREFH and VDDA are selectable as the DAC reference. VREFH is connected to the DACREF_1 input and VDDA is connected to the DACREF_2 input.
Use DACx_C0[DACRFS] control bit to select between these two options.
NOTE
If the DAC and ADC use the same reference simultaneously, some degradation of ADC accuracy is to be expected due to
DAC switching.
3.8 Timers
3.8.1 Timer/PWM module configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bus controller 0
Register access
Module signals
Other peripherals
TPM
Topic
Full description
System memory map
Clocking
Power management
Signal multiplexing
Figure 3-25. TPM configuration
Table 3-39. Reference links to related information
Related module
Timer/PWM module
—
—
—
Port control
Reference
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Chapter 3 Chip Configuration
3.8.1.1 TPM instantiation information
This device contains three low power TPM modules (TPM). All TPM modules in the device are configured only as basic TPM function, do not support quadrature decoder function, and all can be functional in Stop/VLPS mode. The clock source is either external or internal in Stop/VLPS mode.
The following table shows how these modules are configured.
TPM instance
TPM0
TPM1
TPM2
Table 3-40. TPM configuration
Number of channels
6
2
2
Features/usage
Basic TPM,functional in Stop/VLPS mode
Basic TPM,functional in Stop/VLPS mode
Basic TPM,functional in Stop/VLPS mode
There are several connections to and from the TPMs in order to facilitate customer use cases. For complete details on the TPM module interconnects please refer to the
3.8.1.2 Clock options
The TPM blocks are clocked from a single TPM clock that can be selected from
OSCERCLK, MCGIRCLK, MCGPLLCLK/2, or MCGFLLCLK . The selected source is controlled by SIM_SOPT2[TPMSRC] and SIM_SOPT2[PLLFLLSEL].
Each TPM also supports an external clock mode (TPM_SC[CMOD]=1x) in which the counter increments after a synchronized (to the selected TPM clock source) rising edge detect of an external clock input. The available external clock (either TPM_CLKIN0 or
TPM_CLKIN1) is selected by SIM_SOPT4[TPMxCLKSEL] control register. To guarantee valid operation the selected external clock must be less than half the frequency of the selected TPM clock source.
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Timers
3.8.1.3 Trigger options
Each TPM has a selectable trigger input source controlled by TPMx_CONF[TRGSEL] to use for starting the counter and/or reloading the counter. The options available are shown in the following table.
Table 3-41. TPM trigger options
TPMx_CONF[TRGSEL]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Selected source
External trigger pin input (EXTRG_IN)
CMP0 output
Reserved
Reserved
PIT trigger 0
PIT trigger 1
Reserved
Reserved
TPM0 overflow
TPM1 overflow
TPM2 overflow
Reserved
RTC alarm
RTC seconds
LPTMR trigger
Reserved
3.8.1.4 Global timebase
Each TPM has a global timebase feature controlled by TPMx_CONF[GTBEEN]. TPM1 is configured as the global time when this option is enabled.
3.8.1.5 TPM interrupts
The TPM has multiple sources of interrupt. However, these sources are OR'd together to generate a single interrupt request to the interrupt controller. When an TPM interrupt occurs, read the TPM status registers to determine the exact interrupt source.
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Chapter 3 Chip Configuration
3.8.2 PIT Configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bridge
Register access
Periodic interrupt timer
Topic
Full description
System memory map
Clocking
Power management
Figure 3-26. PIT configuration
Table 3-42. Reference links to related information
Related module
PIT
Reference
3.8.2.1 PIT/DMA periodic trigger assignments
The PIT generates periodic trigger events to the DMA channel mux as shown in this table.
PIT Channel 0
PIT Channel 1
Table 3-43. PIT channel assignments for periodic DMA triggering
PIT channel DMA channel number
DMA Channel 0
DMA Channel 1
3.8.2.2 PIT/ADC triggers
PIT triggers are selected as ADCx trigger sources using the bits of
SIM_SOPT7[ADCxTRGSEL]. For more details, see the SIM chapter.
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Timers
3.8.2.3 PIT/TPM Triggers
PIT triggers are selected as TPMx trigger sources using the TPMx_CONF[TRGSEL] bits in the TPM module. For more details, refer to TPM chapter.
3.8.2.4 PIT/DAC triggers
PIT Channel 0 is configured as the DAC hardware trigger source. For more details, see the
chapter.
3.8.3 Low-power timer configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bridge
Register access
Low-power timer
Module signals
Topic
Full description
System memory map
Clocking
Power management
Signal Multiplexing
Figure 3-27. LPT configuration
Table 3-44. Reference links to related information
Related module
Low-power timer
—
—
—
Port control
Reference
3.8.3.1 LPTMR instantiation information
The low-power timer (LPTMR) allows operation during all power modes. The LPTMR can operate as a real-time interrupt or pulse accumulator. It includes a 2 N prescaler (realtime interrupt mode) or glitch filter (pulse accumulator mode).
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Chapter 3 Chip Configuration
The LPTMR can be clocked from the internal reference clock, the internal 1 kHz LPO,
OSCERCLK, or an external 32.768 kHz crystal. In VLLS0 mode, the clocking option is limited to an external pin with the OSC configured for bypass (external clock) operation.
An interrupt is generated (and the counter may reset) when the counter equals the value in the 16-bit compare register.
3.8.3.2 LPTMR pulse counter input options
LPTMR_CSR[TPS] configures the input source used in pulse counter mode. The following table shows the chip-specific input assignments for this field.
LPTMR_CSR[TPS]
00
01
10
11
2
3
0
1
Pulse counter input number Chip input
CMP0 output
LPTMR_ALT1 pin
LPTMR_ALT2 pin
LPTMR_ALT3 pin
3.8.3.3 LPTMR prescaler/glitch filter clocking options
The prescaler and glitch filter of the LPTMR module can be clocked from one of four sources determined by LPTMR0_PSR[PCS]. The following table shows the chip-specific clock assignments for this field.
NOTE
The chosen clock must remain enabled if the LPTMR is to continue operating in all required low-power modes.
LPTMR0_PSR[PCS] Prescaler/glitch filter clock number
Chip clock
00
01
10
11
0
1
2
3
MCGIRCLK—internal reference clock
(not available in LLS and VLLS modes)
LPO—1 kHz clock (not available in
VLLS0 mode)
ERCLK32K (not available in VLLS0 mode when using 32 kHz oscillator)
OSCERCLK—external reference clock
(not available in VLLS0 mode)
See
Clock Distribution for more details on these clocks.
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Timers
3.8.4 RTC configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bridge
Register access
Real-time clock
Module signals
Topic
Full description
System memory map
Clocking
Power management
Figure 3-28. RTC configuration
Table 3-45. Reference links to related information
Related module
RTC
Reference
3.8.4.1 RTC Instantiation Information
RTC prescaler is clocked by ERCLK32K.
RTC is reset on POR Only.
RTC_CR[OSCE] can override the configuration of the System OSC, configuring the
OSC for 32 kHz crystal operation in all power modes except VLLS0, and through any
System Reset. When OSCE is enabled, the RTC also overrides the capacitor configurations.
If the RTC is used to configure the oscillator and the OSCERCLK is being used, the
OSCx_CR[ERCLKEN] and MCG_C2[EREFS0] bits must both be set to 1.
If an external square wave clock is being used to clock the RTC, the RTC_CLKIN path must be used.
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Chapter 3 Chip Configuration
3.8.4.2 RTC_CLKOUT options
RTC_CLKOUT pin can be driven either with the RTC 1 Hz output or with the
OSCERCLK on-chip clock source. Control for this option is through
SIM_SOPT2[RTCCLKOUTSEL].
When SIM_SOPT2[RTCCLKOUTSEL] = 0, the RTC 1 Hz clock is output is selected on the RTC_CLKOUT pin. When SIM_SOPT2[RTCCLKOUTSEL] = 1, OSCERCLK clock is output on the RTC_CLKOUT pin.
3.9 Communication interfaces
3.9.1 Universal Serial Bus (USB) FS Subsystem
The USB FS subsystem includes these components:
• Dual-role USB OTG-capable (On-The-Go) controller that supports a full-speed (FS) device or FS/LS host. The module complies with the USB 2.0 specification.
• USB transceiver that includes internal 15 k Ω pulldowns on the D+ and D- lines for host mode functionality.
• A 3.3 V regulator.
• VBUS detect signal: To detect a valid VBUS in device mode, use a GPIO signal that can wake the chip in all power modes.
USB controller
USB voltage regulator
FS/LS transceiver
VREGIN VOUT33 D+ D-
Figure 3-29. USB Subsystem Overview
3.9.1.1 USB Wakeup
When the USB detects that there is no activity on the USB bus for more than 3 ms, the
INT_STAT[SLEEP] bit is set. This bit can cause an interrupt and software decides the appropriate action.
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Communication interfaces
Waking from a low power mode (except in LLS/VLLS mode where USB is not powered) occurs through an asynchronous interrupt triggered by activity on the USB bus. Setting the USBTRC0[USBRESMEN] bit enables this function.
3.9.1.2 USB Power Distribution
This chip includes an internal 5 V to 3.3 V USB regulator that powers the USB transceiver or the MCU (depending on the application).
3.9.1.2.1 AA/AAA cells power supply
The chip can be powered by two AA/AAA cells. In this case, the MCU is powered through VDD which is within the 1.8 to 3.0 V range. After USB cable insertion is detected, the USB regulator is enabled to power the USB transceiver.
2 AA Cells
VDD
VOUT33
TYPE A
VBUS
D+
D-
Cstab
VREGIN
USB0_DP
USB0_DM
To PMC and Pads
Chip
USB
Regulator
USB
XCVR
USB
Controller
Figure 3-30. USB regulator AA cell usecase
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Chapter 3 Chip Configuration
3.9.1.2.2 Li-Ion battery power supply
The chip can also be powered by a single Li-ion battery. In this case, VOUT33 is connected to VDD. The USB regulator must be enabled by default to power the MCU.
When connected to a USB host, the input source of this regulator is switched to the USB bus supply from the Li-ion battery. To charge the battery, the MCU can configure the battery charger.
VDD
VOUT33
C stab
TYPE A
VBUS
Charger
Si2301
VREGIN
D+
D-
VSS Li-Ion
USB0_DP
USB0_DM
To PMC and Pads
Chip
USB
XCVR
USB
Controller
Figure 3-31. USB regulator Li-ion usecase
3.9.1.2.3 USB bus power supply
The chip can also be powered by the USB bus directly. In this case, VOUT33 is connected to VDD. The USB regulator must be enabled by default to power the MCU, then to power USB transceiver or external sensor.
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VDD
Cstab
VOUT33
TYPE A
VBUS
D+
D-
VREGIN
USB0_DP
USB0_DM
To PMC and Pads
Chip
USB
Regulator
XCVR
USB
USB
Controller
Figure 3-32. USB regulator bus supply
3.9.1.3 USB power management
The regulator should be put into STANDBY mode whenever the chip is in Stop mode.
3.9.1.4 USB controller configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bridge 0
Register access
Transfers
USB controller
Module signals
102
Topic
Full description
Figure 3-33. USB controller configuration
Table 3-46. Reference links to related information
Related module
USB controller
Table continues on the next page...
Reference
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Chapter 3 Chip Configuration
Table 3-46. Reference links to related information (continued)
Topic
System memory map
Clocking
Transfers
Signal Multiplexing
Related module
Crossbar switch
Port control
Reference
NOTE
When USB is not used in the application, it is recommended that the USB regulator VREGIN and VOUT33 pins remain floating.
3.9.1.5 USB Voltage Regulator Configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
USB Voltage
Regulator
Module signals
Topic
Full description
System memory map
Clocking
Signal Multiplexing
Figure 3-34. USB Voltage Regulator configuration
Table 3-47. Reference links to related information
Related module
USB Voltage Regulator
USB controller
Port control
Reference
NOTE
When USB is not used in the application, it is recommended that the USB regulator VREGIN and VOUT33 pins remain floating.
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3.9.2 SPI configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bridge
Register access
SPI
Module signals
Signal multiplexing
Topic
Full description
System memory map
Clocking
Signal multiplexing
Figure 3-35. SPI configuration
Table 3-48. Reference links to related information
Related module
SPI
—
—
Port control
Reference
SPI
3.9.2.1 SPI instantiation information
The number of SPI modules on this device is: two
The supported data length is: 16-bit
SPI1 includes a 4-deep FIFO of 16-bit entries.
SPI0 is clocked on the bus clock. That is, the SPI0 module clock is connected to the chiplevel bus clock.
SPI1 is clocked from the system clock. That is, the SPI1 module clock is connected to the chip-level system clock. SPI1 is therefore disabled in Partial Stop Mode.
The SPI supports DMA request and can operate in VLPS mode. When the SPI is operating in VLPS mode, it will operate as a slave.
SPI can wake the MCU from VLPS mode upon reception of SPI data in slave mode.
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Chapter 3 Chip Configuration
3.9.3 I2C configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bridge
Register access
Module signals
Topic
Full description
System memory map
Clocking
Power management
Signal multiplexing
Figure 3-36. I2C configuration
Table 3-49. Reference links to related information
Related module
I 2 C
—
—
—
Port control
Reference
3.9.3.1 I2C instantiation information
This device has two I2C modules. I2C0 is clocked by the bus clock (so the I2C module clock is the bus clock), and I2C1 is clocked by the system clock (so the I2C module clock is the system clock). Clocking I2C1 at the faster system clock is needed to support standard I2C communication rates of 100 kbit/s in VLPR mode.
When the package pins associated with I2C have their mux select configured for I2C operation, the pins (SCL and SDA) are driven either by true open drain or in a pseudo open drain configuration.
The digital glitch filter implemented in the I2C0 module, controlled by the
I2C0_FLT[FLT] registers, is clocked from the bus clock and thus has filter granularity in bus clock cycle counts.
The digital glitch filter implemented in the I2C1 module, controlled by the
I2C1_FLT[FLT] registers, is clocked from the system clock and thus has filter granularity in system clock cycle counts.
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Communication interfaces
NOTE
The I2Cx_C2[HDRS] bit has no effect on the drive strength of the I2C signals. To use high drive strength, enable it in the appropriate PORTx_PCRn register. See the chip-specific GPIO information to determine which pins have high current capability.
3.9.4 UART configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bridge
Register access
Module signals
UART
Topic
Full description
Full description
System memory map
Clocking
Power management
Signal multiplexing
Figure 3-37. UART configuration
Table 3-50. Reference links to related information
Related module
UART1 and UART2
UART0
—
—
—
Port control
Reference
3.9.4.1 UART0 overview
The UART0 module supports basic UART with DMA interface function, x4 to x32 oversampling of baud-rate.
This module supports LIN slave operation.
The module can remain functional in VLPS mode provided the clock it is using remains enabled.
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Chapter 3 Chip Configuration
ISO7816 protocol is intended to be handled in software for this product. To support smart card reading, TxD pin can be configured as pseudo open drain for 1-wire half-duplex like
ISO7816 communication via SIM_SOPT5[UART0ODE].
3.9.4.2 UART1 and UART2 Overview
This device contains two basic universal asynchronous receiver/transmitter (UART) modules with DMA function support. Generally, these modules are used in RS-232,
RS-485, and other communications. This module supports LIN Slave operation.
3.9.5 I 2 S configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bridge
Register access
Module signals
Topic
Full description
System memory map
Clocking
Power management
Signal multiplexing
Figure 3-38. I 2 S configuration
Table 3-51. Reference links to related information
Related module
I 2 S
Port control
Reference
3.9.5.1 Instantiation information
This device contains one I 2 S module.
As configured on the device, module features include:
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Communication interfaces
• TX data lines: 1
• RX data lines: 1
• FIFO size (words): 1
• Maximum words per frame: 2
• Maximum bit clock divider: 512
3.9.5.2 I2S Interrupts
The I2S0 has receive and transmit sources of interrupt requests. However, these sources are OR'd together to generate a single interrupt request to the interrupt controller. When an I2S0 interrupt occurs, read the I2S0_RCSR and I2S0_TCSR to determine the exact interrupt source.
3.9.5.3 I 2 S/SAI clocking
3.9.5.3.1 Audio Master Clock
The audio master clock (MCLK) is used to generate the bit clock when the receiver or transmitter is configured for an internally generated bit clock. The audio master clock can also be output to or input from a pin. The transmitter and receiver have the same audio master clock inputs.
3.9.5.3.2 Bit Clock
The I 2 S/SAI transmitter and receiver support asynchronous bit clocks (BCLKs) that can be generated internally from the audio master clock or supplied externally. The module also supports the option for synchronous operation between the receiver and transmitter.
3.9.5.3.3 Bus Clock
The bus clock is used by the control registers and to generate synchronous interrupts and
DMA requests.
3.9.5.3.4 I 2 S/SAI clock generation
Each SAI peripheral can control the input clock selection, pin direction and divide ratio of one audio master clock.
The MCLK Input Clock Select bit of the MCLK Control Register (MCR[MICS]) selects the clock input to the I 2 S/SAI module’s MCLK.
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00
01
10
11
Chapter 3 Chip Configuration
The following table shows the input clock selection options on this device.
Table 3-52. I2S0 MCLK input clock selection
MCR[MICS] Clock Selection
System clock
OSCERCLK
Not supported
MCGPLLCLK/2 or MCGFLLCLK
00
01
10
11
The module's MCLK Divide Register (MDR) is not used to control MCLK generation.
The module's MCLK Output Enable bit of the MCLK Control Register (MCR[MOE]) controls the direction of the MCLK pin. MCLK is input from the pin when MOE is 0, and MCLK is output from the internal clock select when MOE is 1.
The transmitter and receiver can independently select between the bus clock and the audio master clock to generate the bit clock. The module's Clocking Mode field of the
Transmit Configuration 2 Register and Receive Configuration 2 Register (TCR2[MSEL] and RCR2[MSEL]) selects the master clock.
The following table shows the TCR2[MSEL] and RCR2[MSEL] field settings for this device.
Table 3-53. I2S0 master clock settings
TCR2[MSEL], RCR2[MSEL] Master Clock
Bus Clock
I2S0_MCLK
Not supported
Not supported
3.9.5.3.5 Clock gating and I 2 S/SAI initialization
The clock to the I 2 S/SAI module can be gated using a bit in the SIM. To minimize power consumption, these bits are cleared after any reset, which disables the clock to the corresponding module. The clock enable bit should be set by software at the beginning of the module initialization routine to enable the module clock before initialization of any of the I 2 S/SAI registers.
3.9.5.4 I 2 S/SAI operation in low power modes
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Human-machine interfaces (HMI)
3.9.5.4.1 Stop and very low power modes
In Stop mode, the SAI transmitter and/or receiver can continue operating provided the appropriate Stop Enable bit is set (TCSR[STOPE] and/or RCSR[STOPE], respectively), and provided the transmitter and/or receiver is/are using an externally generated bit clock or an Audio Master Clock that remains operating in Stop mode. The SAI transmitter and/ or receiver can generate an asynchronous interrupt to wake the CPU from Stop mode.
In VLPS mode, the module behaves as it does in stop mode if VLPS mode is entered from run mode. However, if VLPS mode is entered from VLPR mode, the FIFO might underflow or overflow before wakeup from stop mode due to the limits in bus bandwidth.
In VLPW and VLPR modes, the module is limited by the maximum bus clock frequencies.
When operating from an internally generated bit clock or Audio Master Clock that is disabled in stop modes:
In Stop mode, if the Transmitter Stop Enable (TCSR[STOPE]) bit is clear, the transmitter is disabled after completing the current transmit frame, and, if the Receiver Stop Enable
(RCSR[STOPE]) bit is clear, the receiver is disabled after completing the current receive frame. Entry into Stop mode is prevented–not acknowledged–while waiting for the transmitter and receiver to be disabled at the end of the current frame.
3.9.5.4.2 Low-leakage modes
When entering low-leakage modes, the Stop Enable (TCSR[STOPE] and
RCSR[STOPE]) bits are ignored and the SAI is disabled after completing the current transmit and receive Frames. Entry into stop mode is prevented (not acknowledged) while waiting for the transmitter and receiver to be disabled at the end of the current frame.
3.10 Human-machine interfaces (HMI)
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3.10.1 GPIO configuration
Peripheral bridge
Register access
Register access
GPIO controller
Module signals
Chapter 3 Chip Configuration
Topic
Full description
System memory map
Clocking
Power management
Crossbar switch
Signal multiplexing
Figure 3-39. GPIO configuration
Table 3-54. Reference links to related information
Related module
GPIO
—
—
—
Crossbar switch
Port control
Reference
3.10.1.1 GPIO instantiation information
The device includes a number of pins, PTB0, PTB1, and PTD6, PTD7 with high current drive capability. These pins can be used to drive LED or power MOSFET directly. The high drive capability applies to all functions which are multiplexed on these pins.
3.10.1.1.1 Pull devices and directions
The pull devices are enabled out of POR only for RESET_b, NMI_b, and the SWD signals. Coming out of POR:
• RESET_b, NMI_b and SWD_DIO are pulled up.
• SWD_CLK is pulled down.
The pull devices for other pins are not enabled out of POR. They can be enabled by writing to PORTx_PCRn[PE].
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Human-machine interfaces (HMI)
All the pins have controllable pull direction using the PORTx_PCRn[PS] field. All the pins default to pullup except for SWD_CLK, when enabled.
3.10.1.2 Port control and interrupt summary
The following table provides more information regarding the Port Control and Interrupt configurations .
Table 3-55. Ports summary
Feature Port A
Pull select control Yes
Pull select after reset
PTA0=Pull down,
Others=Pull up
Pull enable control Yes
Pull enable after reset
PTA0/PTA3/PTA4/
RESET_b=Enabled
; Others=Disabled
Yes Slew rate enable control
Slew rate enable after reset
Passive filter enable control
PTA3/PTA14/
PTA15/PTA16/
PTA17=Disabled;
Others=Enabled
PTA4 and
RESET_b only
Passive filter enable after reset
Open drain enable
Open drain enable after reset
Drive strength enable control
RESET_b=Enabled
; Others=Disabled
No
Disabled
No
Drive strength enable after reset
Disabled
Pin mux control Yes
Pin mux after reset PTA0/PTA3/
PTA4=ALT7;
Others=ALT0
Lock bit
Interrupt and DMA request
No
Yes
Digital glitch filter No
Port B
Yes
Pull up
Yes
Disabled
Yes
PTB10/PTB11/
PTB16/PTB17 =
Disabled;
Others=Enabled
No
Disabled
No
Disabled
PTB0/PTB1 only
Disabled
Yes
ALT0
No
No
No
Port C
Yes
Pull up
Yes
Disabled
Yes
Port D
Yes
Pull up
Yes
Disabled
Yes
Port E
Yes
Pull up
Yes
Disabled
Yes
PTC3/PTC4/PTC5/
PTC6/
PTC7=Disabled;
Others=Enabled
No
PTD4/PTD5/PTD6/
PTD7=Disabled;
Others=Enabled
No
PTE16/PTE17/
PTE18/
PTE19=Disabled;
Others=Enabled
No
Disabled
No
Disabled
No
Disabled
Yes
ALT0
No
Yes
No
Disabled
No
Disabled
PTD6/PTD7 only
Disabled
Yes
ALT0
No
Yes
No
Disabled
No
Disabled
No
Disabled
Yes
ALT0
No
No
No
1. UART signals can be configured for open-drain using SIM_SOPT5 register. I2C signals are automatically enabled for open drain when selected.
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Chapter 3 Chip Configuration
3.10.1.3 GPIO accessibility in the memory map
The GPIO is multi-ported and can be accessed directly by the core with zero wait states at base address 0xF800_0000. It can also be accessed by the core and DMA masters through the cross bar/AIPS interface at 0x400F_F000 and at an aliased slot (15) at address 0x4000_F000. All BME operations to the GPIO space can be accomplished referencing the aliased slot (15) at address 0x4000_F000. Only some of the BME operations can be accomplished referencing GPIO at address 0x400F_F000.
3.10.2 TSI configuration
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bridge
Register access
Touch sense input module
Module signals
Topic
Full description
System memory map
Clocking
Power management
Signal Multiplexing
Figure 3-40. TSI configuration
Table 3-56. Reference links to related information
Related module
TSI
Port control
Reference
3.10.2.1 TSI instantiation information
This device includes one TSI module containing the channels as shown in the following table. In Stop, VLPS, LLS, and VLLSx modes any one channel can be enabled to be the wake-up source.
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Human-machine interfaces (HMI)
TSI hardware trigger is from the LPTMR. For complete details on the LPTMR module
interconnects, see the Module-to-Module section.
The number of TSI channels present on the device is determined by the pinout of the specific device package and is shown in the following table.
Table 3-57. Number of KL26 TSI channels
Device
MKL26Z256VLH4
MKL26Z256VLK4
MKL26Z128VLL4
MKL26Z256VLL4
MKL26Z128VMC4
MKL26Z256VMC4
TSI channels
16
16
16
16
16
16
3.10.2.2 TSI Interrupts
The TSI has multiple sources of interrupt requests. However, these sources are OR'd together to generate a single interrupt request. When a TSI interrupt occurs, read the TSI status register to determine the exact interrupt source.
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Chapter 4
Memory Map
This section describes the memory and peripheral locations within the memory space of this device.
4.1 Introduction
This device contains various memories and memory-mapped peripherals which are located in a 4 GB memory space.
This chapter describes the memory and peripheral locations within that memory space.
4.2 System memory map
The table found here shows the high-level device memory map.
Table 4-1. System memory map
System 32-bit address range
0x0000_0000–0x07FF_FFFF
0x0800_0000–0x1FFF_DFFF
0x2000_0000–0x2000_5FFF
0x2000_6000–0x3FFF_FFFF
0x4000_0000–0x4007_FFFF
0x4008_0000–0x400F_EFFF
0x400F_F000–0x400F_FFFF
0x4010_0000–0x43FF_FFFF
0x4400_0000–0x5FFF_FFFF
Destination slave
Program flash and read-only data
Access
All masters
(Includes exception vectors in first 196 bytes)
Reserved
SRAM_L: Lower SRAM
SRAM_U: Upper SRAM
Reserved
AIPS Peripherals
Reserved
General-purpose input/output (GPIO)
—
All masters
All masters
–
Cortex-M0+ core &
DMA
–
Cortex-M0+ core &
DMA
Reserved
Bit Manipulation Engine (BME) access to AIPS Peripherals for
–
Cortex-M0+ core
Table continues on the next page...
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Flash memory map
System 32-bit address range
0x6000_0000–0xDFFF_FFFF
0xE000_0000–0xE00F_FFFF
0xE010_0000–0xEFFF_FFFF
0xF000_0000–0xF000_0FFF
0xF000_1000–0xF000_1FFF
0xF000_2000–0xF000_2FFF
0xF000_3000–0xF000_3FFF
0xF000_4000–0xF7FF_FFFF
0xF800_0000–0xFFFF_FFFF
Table 4-1. System memory map (continued)
Reserved
Private Peripherals
Destination slave
Reserved
Micro Trace Buffer (MTB) registers
MTB Data Watchpoint and Trace (MTBDWT) registers
ROM table
Miscellaneous Control Module (MCM)
Reserved
IOPORT: GPIO (single cycle)
Access
–
Cortex-M0+ core
–
Cortex-M0+ core
Cortex-M0+ core
Cortex-M0+ core
Cortex-M0+ core
–
Cortex-M0+ core
1. The program flash always begins at 0x0000_0000 but the end of implemented flash varies depending on the amount of
flash implemented for a particular device. See Flash memory sizes
for details.
2. This range varies depending on SRAM sizes. See SRAM ranges
for details.
3. Includes BME operations to GPIO at slot 15 (based at 0x4000_F000).
4.3 Flash memory map
The flash memory and the flash registers are located at different base addresses as shown in the figure found here.
The base address for each is specified in System memory map .
Flash memory base address
Registers
Flash base address
Flash configuration field
Flash
Figure 4-1. Flash memory map
The on-chip flash memory is implemented in a portion of the allocated Flash range to form a contiguous block in the memory map beginning at address 0x0000_0000. See
Flash memory sizes for details of supported ranges.
Access to the flash memory ranges outside the amount of flash on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master. Read collision events in which flash memory is accessed while a flash memory resource is being manipulated by a flash command also generate a bus error response.
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Chapter 4 Memory Map
When software needs to access the flash memory while a flash memory resource is being manipulated by a flash command, software can enable a stall mechanism to avoid a read collision. The stall mechanism allows software to execute code from the same block on which flash operations are being performed. However, software must ensure the sector the flash operations are being performed on is not the same sector from which the code is executing.
The MCM_PLACR[ESFC] bit enables the stall mechanism. This bit must be set only just before the flash operation is executed and must be cleared when the operation completes.
4.3.1 Alternate non-volatile IRC user trim description
The following non-volatile locations (4 bytes) are reserved for custom IRC user trim supported by some development tools. An alternate IRC trim to the factory loaded trim can be stored at this location. To override the factory trim, the user software must load new values into the MCG trim registers.
Non-volatile byte address
0x0000_03FC
0x0000_03FD
0x0000_03FE (bit 0)
0x0000_03FE (bit 4:1)
0x0000_03FE (bit 6)
0x0000_03FF
Alternate IRC Trim Value
Reserved
Reserved
SCFTRIM
FCTRIM
FCFTRIM
SCTRIM
4.4 SRAM memory map
The on-chip RAM is split between SRAM_L and SRAM_U. The RAM is also implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in the memory map.
See
for details.
Access to the SRAM_L and SRAM_U memory ranges outside the amount of RAM on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master.
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Peripheral bridge (AIPS-Lite) memory map
4.5 Bit Manipulation Engine
The Bit Manipulation Engine (BME) provides hardware support for atomic read-modifywrite memory operations to the peripheral address space.
By combining the basic load and store instruction support in the Cortex-M instruction set architecture with the concept of decorated storage provided by the BME, the resulting implementation provides a robust and efficient read-modify-write capability to this class
of ultra low-end microcontrollers. See the Bit Manipulation Engine Block Guide (BME)
for a detailed description of BME functionality.
4.6 Peripheral bridge (AIPS-Lite) memory map
The peripheral memory map is accessible via one slave port on the crossbar in the
0x4000_0000–0x400F_FFFF region. The device implements one peripheral bridge that defines a 1024 KB address space.
The three regions associated with this space are:
• A 128 KB region, partitioned as 32 spaces, each 4 KB in size and reserved for onplatform peripheral devices. The AIPS controller generates unique module enables for all 32 spaces.
• A 384 KB region, partitioned as 96 spaces, each 4 KB in size and reserved for offplatform modules. The AIPS controller generates unique module enables for all 96 spaces.
• The last slot is a 4 KB region beginning at 0x400F_F000 for accessing the GPIO module. The GPIO slot (slot 128) is an alias of slot 15. This block is also directly interfaced to the core and provides direct access without incurring wait states associated with accesses via the AIPS controller.
Modules that are disabled via their clock gate control bits in the SIM registers disable the associated AIPS slots. Access to any address within an unimplemented or disabled peripheral bridge slot results in a transfer error termination.
For programming model accesses via the peripheral bridges, there is generally only a small range within the 4 KB slots that is implemented. Accessing an address that is not implemented in the peripheral results in a transfer error termination.
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Chapter 4 Memory Map
4.6.1 Read-after-write sequence and required serialization of memory operations
In some situations, a write to a peripheral must be completed fully before a subsequent action can occur. Examples of such situations include:
• Exiting an interrupt service routine (ISR)
• Changing a mode
• Configuring a function
In these situations, the application software must perform a read-after-write sequence to guarantee the required serialization of the memory operations:
1. Write the peripheral register.
2. Read the written peripheral register to verify the write.
3. Continue with subsequent operations.
4.6.2 Peripheral bridge (AIPS-Lite) memory map
Table 4-2. Peripheral bridge 0 slot assignments
System 32-bit base address
0x4000_0000
0x4000_1000
0x4000_2000
0x4000_3000
0x4000_4000
0x4000_5000
0x4000_6000
0x4000_7000
0x4000_8000
0x4000_9000
0x4000_A000
0x4000_B000
0x4000_C000
0x4000_D000
0x4000_E000
0x4000_F000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_4000
Slot number
0
1
2
9
10
7
8
5
6
3
4
15
16
17
18
11
12
13
14
19
20
—
—
—
—
—
—
—
—
DMA controller
—
—
—
—
—
—
Module
GPIO controller (aliased to 0x400F_F000)
—
—
—
—
—
Table continues on the next page...
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0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_9000
0x4002_A000
0x4002_B000
0x4002_C000
0x4002_D000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4001_5000
0x4001_6000
0x4001_7000
0x4001_8000
0x4001_9000
0x4001_A000
0x4001_B000
0x4001_C000
0x4001_D000
0x4001_E000
0x4001_F000
0x4002_0000
0x4002_1000
0x4002_2000
0x4002_3000
0x4003_4000
0x4003_5000
0x4003_6000
0x4003_7000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
Peripheral bridge (AIPS-Lite) memory map
Table 4-2. Peripheral bridge 0 slot assignments (continued)
System 32-bit base address
44
45
46
47
40
41
42
43
36
37
38
39
32
33
34
35
Slot number
21
22
23
28
29
30
31
24
25
26
27
52
53
54
55
48
49
50
51
56
57
58
59
Module
—
—
—
—
—
—
—
I2S0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Flash memory
DMA channel mutiplexer 0
—
—
—
—
—
Periodic interrupt timers (PIT)
Timer'/PWM (TPM) 0
Timer'/PWM (TPM) 1
Timer'/PWM (TPM) 2
Analog-to-digital converter 0(ADC0)
Table continues on the next page...
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0x4004_B000
0x4004_C000
0x4004_D000
0x4004_E000
0x4004_F000
0x4005_0000
0x4005_1000
0x4005_2000
0x4005_3000
0x4005_4000
0x4005_5000
0x4005_6000
0x4005_7000
0x4005_8000
0x4005_9000
0x4005_A000
0x4003_C000
0x4003_D000
0x4003_E000
0x4003_F000
0x4004_0000
0x4004_1000
0x4004_2000
0x4004_3000
0x4004_4000
0x4004_5000
0x4004_6000
0x4004_7000
0x4004_8000
0x4004_9000
0x4004_A000
0x4005_B000
0x4005_C000
0x4005_D000
0x4005_E000
0x4005_F000
0x4006_0000
0x4006_1000
0x4006_2000
Chapter 4 Memory Map
Table 4-2. Peripheral bridge 0 slot assignments (continued)
System 32-bit base address
—
—
—
—
—
—
—
—
—
Real-time clock (RTC)
—
DAC0
Low-power timer (LPTMR)
System register file
—
—
—
Touch sense interface (TSI)
—
SIM low-power logic
System integration module (SIM)
Port A multiplexing control
Port B multiplexing control
—
—
—
—
—
—
—
—
—
—
—
—
Port C multiplexing control
Port D multiplexing control
Port E multiplexing control
—
Table continues on the next page...
83
84
85
86
79
80
81
82
75
76
77
78
71
72
73
74
Slot number
60
61
62
67
68
69
70
63
64
65
66
91
92
93
94
87
88
89
90
95
96
97
98
Module
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Peripheral bridge (AIPS-Lite) memory map
Table 4-2. Peripheral bridge 0 slot assignments (continued)
System 32-bit base address
0x4007_3000
0x4007_4000
0x4007_5000
0x4007_6000
0x4007_7000
0x4007_8000
0x4007_9000
0x4007_A000
0x4007_B000
0x4007_C000
0x4007_D000
0x4007_E000
0x4007_F000
0x400F_F000
0x4006_3000
0x4006_4000
0x4006_5000
0x4006_6000
0x4006_7000
0x4006_8000
0x4006_9000
0x4006_A000
0x4006_B000
0x4006_C000
0x4006_D000
0x4006_E000
0x4006_F000
0x4007_0000
0x4007_1000
0x4007_2000
Slot number
123
124
125
126
127
128
119
120
121
122
115
116
117
118
111
112
113
114
107
108
109
110
103
104
105
106
99
100
101
102
Module
—
Multi-purpose clock generator (MCG)
System oscillator (OSC)
I 2 C0
I 2 C1
—
—
UART0
UART1
UART2
—
—
—
—
—
USB OTG FS/LS
Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC)
—
—
SPI0
SPI1
—
—
—
—
Low-leakage wakeup unit (LLWU)
Power management controller (PMC)
System mode controller (SMC)
Reset control module (RCM)
GPIO controller
4.6.3 Modules restricted access in user mode
In user mode, for MCG, RCM, SIM (slot 71 and 72), SMC, LLWU, and PMC, reads are allowed, but writes are blocked and generate bus error.
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Chapter 4 Memory Map
4.7 Private Peripheral Bus (PPB) memory map
The PPB is part of the defined ARM bus architecture and provides access to select processor-local modules. These resources are only accessible from the core; other system masters do not have access to them.
Table 4-3. PPB memory map
System 32-bit Address Range
0xE000_0000–0xE000_DFFF
0xE000_E000–0xE000_EFFF
0xE000_F000–0xE00F_EFFF
0xE00F_F000–0xE00F_FFFF
Resource
Reserved
System Control Space
(SCS)
Additional Range Detail
Reserved
Core ROM Space (CRS)
0xE000_E000–0xE000_E00F
0xE000_E010–0xE000_E0FF
0xE000_E100–0xE000_ECFF
0xE000_ED00–0xE000_ED8F
0xE000_ED90–0xE000_EDEF
0xE000_EDF0–0xE000_EEFF
0xE000_EF00–0xE000_EFFF
Resource
Reserved
SysTick
NVIC
System Control Block
Reserved
Debug
Reserved
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Private Peripheral Bus (PPB) memory map
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Chapter 5
Clock Distribution
5.1 Introduction
The information found here presents the clock architecture for the device, the overview of the clocks, and includes a terminology section.
ARM Cortex M0+ core resides within a synchronous core platform, where the processor and bus masters, flash memory, and peripheral clocks can be configured independently.
The clock distribution figure shows how clocks from the MCG and XOSC modules are distributed to the microcontroller’s other function units. Some modules in the microcontroller have selectable clock input.
See AN4503: Power Management for Kinetis and ColdFire+ MCUs for further details on the system clocks and their use.
5.2 Programming model
The selection and multiplexing of system clock sources is controlled and programmed via the MCG module.
The setting of clock dividers and module clock gating for the system are programmed via
the SIM module. Refer to the MCG
sections for detailed register and bit descriptions.
5.3 High-level device clocking diagram
The following
module registers control the multiplexers, dividers, and clock gates shown in the following figure:
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Clock definitions
Multiplexers
Dividers
Clock gates
OSC
MCG_C x
—
OSC_CR
MCG
MCG_C x
MCG_C x
MCG_C1
SIM
SIM_SOPT1, SIM_SOPT2
SIM_CLKDIV x
SIM_SCGC x
EXTAL0
XTAL0
RTC_CLKIN
4 MHz IRC
32 kHz IRC
MCG
FCRDIV
FLL
CG
SIM
MCGIRCLK
OUTDIV1 CG
Clock options for some peripherals
(see note)
Core clock, platform clock, and system clock
MCGOUTCLK
PLL
FRDIV MCGFLLCLK
MCGPLLCLK
÷2
OUTDIV4 CG
MCGPLLCLK/
MCGFLLCLK
Bus clock/
Flash clock
System oscillator
OSCCLK
OSC logic
XTAL_CLK
OSC32KCLK
CG
OSCERCLK
ERCLK32K
PMC
PMC logic
LPO
Counter logic
RTC
1Hz
RTC_CLKOUT
CG — Clock gate
Note: See subsequent sections for details on where these clocks are used.
Figure 5-1. Clocking diagram
5.4 Clock definitions
The table found here describes the clocks in the block diagram.
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Clock name
Core clock
Platform clock
System clock
Bus clock
Flash clock
MCGIRCLK
MCGOUTCLK
MCGFLLCLK
MCGPLLCLK
OSCCLK
OSCERCLK
OSC32KCLK
ERCLK32K
LPO
Chapter 5 Clock Distribution
Description
MCGOUTCLK divided by OUTDIV1
Clocks the ARM Cortex-M0+ core.
MCGOUTCLK divided by OUTDIV1
Clocks the crossbar switch and NVIC.
MCGOUTCLK divided by OUTDIV1
Clocks the bus masters directly.
System clock divided by OUTDIV4.
Clocks the bus slaves and peripherals.
Flash memory clock
On this device, it is the same as Bus clock.
MCG output of the slow or fast internal reference clock
MCG output of either IRC, MCGFLLCLK, MCGPLLCLK, or
MCG's external reference clock that sources the core, system, bus, and flash clock.
MCG output of the FLL
MCGFLLCLK or MCGPLLCLK may clock some modules. In addition, this clock is used for USBFS,
UART0 and TPM modules.
MCG output of the PLL. MCGFLLCLK or MCGPLLCLK may clock some modules. In addition, this clock is used for
USBFS, UART0 and TPM modules.
System oscillator output of the internal oscillator or sourced directly from EXTAL. Used as MCG external reference clock.
System oscillator output sourced from OSCCLK that may clock some on-chip modules
System oscillator 32 kHz output. The OSC32KCLK is available only when the oscillator is configured for very low power mode (VLP), which is RANGE = 0 and HGO = 0.
Clock source for some modules that is chosen as
OSC32KCLK or RTC_CLKIN or LPO
PMC 1 kHz output
5.4.1 Device clock summary
The following table provides more information regarding the on-chip clocks.
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Clock definitions
Clock name
MCGOUTCLK
MCGFLLCLK
MCGPLLCLK
Core clock
Platform clock
System clock
Bus clock
SWD Clock
Flash clock
Run mode clock frequency
Up to 100 MHz
Up to 48 MHz
Up to 100 MHz
Up to 48 MHz
Up to 48 MHz
Up to 48 MHz
Up to 24 MHz
Up to 24 MHz
Up to 24 MHz
Table 5-1. Clock summary
VLPR mode clock frequency
Up to 4 MHz
Clock source
MCG
Internal reference
(MCGIRCLK)
30–40 kHz Slow IRC or 4 MHz Fast IRC
N/A
N/A
Up to 4 MHz
Up to 4 MHz
Up to 4 MHz
Up to 1 MHz
Up to 1 MHz
Up to 1 MHz in BLPE
Up to 800 kHz in BLPI
4 MHz Fast IRC only
MCG
MCG
MCGOUTCLK clock divider
MCGOUTCLK clock divider
MCGOUTCLK clock divider
MCGOUTCLK clock divider
SWD_CLK pin
MCGOUTCLK clock divider
MCG
Clock is disabled when…
In all stop modes except for partial stop modes and during PLL locking when
MCGOUTCLK derived from PLL.
MCG clock controls are not enabled and in all stop modes
MCG clock controls do not enable, in Stop mode but
PLLSTEN=0, or in VLPS, LLS and
VLLSx modes
In all wait and stop modes
In all stop modes
In all stop modes and
Compute Operation
In all stop modes except for partial
STOP2 mode, and
Compute Operation
In all stop modes
In all stop modes except for partial
STOP2 mode
MCG_C1[IRCLKEN] cleared,
Stop mode and
MCG_C1[IREFSTEN] cleared, or
LLS/VLLS mode.
VLPS mode: The Slow
IRC is always disabled, and the Fast IRC is controlled by
MCG_C1[IREFSTEN].
Table continues on the next page...
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Chapter 5 Clock Distribution
Clock name
External reference
(OSCERCLK)
External reference
32kHz
(ERCLK32K)
Table 5-1. Clock summary (continued)
Run mode clock frequency
Up to 48 MHz (bypass),
30–40 kHz or
3-32 MHz (crystal)
VLPR mode clock frequency
Up to 16 MHz (bypass),
30–40 kHz (low-range crystal) or
3-16 MHz (high-range crystal)
Clock source
System OSC
30–40 kHz
Up to 25 MHz
30–40 kHz System OSC
, or RTC_CLKIN
Clock is disabled when…
OSC_CR[ERCLKEN] cleared, or
Stop mode and
OSC_CR[EREFSTEN] cleared or VLLS0 and oscillator not in external clock mode.
OSC_CR[ERCLKEN] cleared and RTC_CR[OSCE] cleared or VLLS0 and oscillator not in external clock mode.
Clock is disabled in LLS and VLLSx modes in VLLS0
SIM_SOPT2[TPMSRC
]=00 or selected clock source disabled.
RTC_CLKOUT
RTC 1Hz,
OSCERCLK
1 kHz
Up to 48 MHz
Up to 48 MHz
48 MHz
RTC 1Hz,
OSCERCLK
1 kHz
Up to 8 MHz
Up to 8 MHz
N/A
Up to 16 MHz
RTC 1Hz,
OSCERCLK
PMC
MCGIRCLK,
MCGPLLCLK/2,
MCGFLLCLK, or
OSCERCLK
MCGIRCLK,
MCGPLLCLK/2,
MCGFLLCLK, or
OSCERCLK
MCGPLLCLK/2 or
MCGFLLCLK, or
USB_CLKIN
System clock,
MCGPLLCLK,
OSCERCLK or
I2S_CLKIN
I
SIM_SOPT2[UART0SR
C]=00 or selected clock source disabled.
USB FS OTG is disabled
2 S is disabled
1. If in BLPI mode, where clocking is derived from the fast internal reference clock, the Bus clock and flash clock frequency needs to be limited to 800 kHz if executing from flash.
5.5 Internal clocking requirements
The clock dividers are programmed via the CLKDIV registers of the SIM module.
The following requirements must be met when configuring the clocks for this device:
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Internal clocking requirements
• The core, platform, and system clock are programmable from a divide-by-1 through divide-by-16 setting. The core, platform, and system clock frequencies must be 48
MHz or slower.
• The frequency of bus clock and flash clock is divided by the system clock and is programmable from a divide-by-1 through divide-by-8 setting. The bus clock and flash clock must be programmed to 24 MHz or slower.
The following is a common clock configuration for this device:
Clock
Core clock
Platform clock
System clock
Bus clock
Flash clock
Frequency
48 MHz
48 MHz
48 MHz
24 MHz
24 MHz
5.5.1 Clock divider values after reset
Each clock divider is programmed via the CLKDIV1 registers of the SIM module. Two bits in the flash memory's FTFA_FOPT register control the reset value of the core clock, system clock, bus clock, and flash clock dividers as shown in this table.
FTFA_FOPT [4,0]
00
01
10
11
Core/system clock
0x7 (divide by 8)
0x3 (divide by 4)
0x1 (divide by 2)
0x0 (divide by 1)
Bus/Flash clock
0x1 (divide by 2)
0x1 (divide by 2)
0x1 (divide by 2)
0x1 (divide by 2)
Description
Low power boot
Low power boot
Low power boot
Fast clock boot
This gives the user flexibility in selecting between a lower frequency, low-power boot option and higher frequency, higher power during and after reset.
The flash erased state defaults to fast clocking mode, since these bits reside in flash, which is logic 1 in the flash erased state. To enable a lower power boot option, program the appropriate bits in FTFA_FOPT. During the reset sequence, if either of the control bits is cleared, the system is in a slower clock configuration. Upon any system reset, the clock dividers return to this configurable reset state.
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5.5.2 VLPR mode clocking
The clock dividers cannot be changed while in VLPR mode. These dividers must be programmed prior to entering VLPR mode to guarantee operation. Maximum frequency limitations for VLPR mode is as follows :
• the core/system clocks are less than or equal to 4 MHz, and
• the bus and flash clocks are less than or equal to 1 MHz
NOTE
When the MCG is in BLPI and clocking is derived from the
Fast IRC, the clock divider controls (MCG_SC[FCRDIV],
SIM_CLKDIV1[OUTDIV1], and SIM_CLKDIV1[OUTDIV4]) must be programmed such that the resulting flash clock nominal frequency is 800 kHz or less. In this case, one example of correct configuration is MCG_SC[FCRDIV] = 000b,
SIM_CLKDIV1[OUTDIV1] = 0000b, and
SIM_CLKDIV1[OUTDIV4] = 100b, resulting in a divide-by-5 setting.
5.6 Clock gating
The clock to each module can be individually gated on and off using bits of the SCGCx registers of the SIM module.
These bits are cleared after any reset, which disables the clock to the corresponding module to conserve power. Prior to initializing a module, set the corresponding bit in the
SCGCx register to enable the clock. Before turning off the clock, make sure to disable the module.
Any bus access to a peripheral that has its clock disabled generates an error termination.
5.7 Module clocks
The table found here summarizes the clocks associated with each module.
Table 5-2. Module clocks
Module
ARM Cortex-M0+ core
Bus interface clock
Core modules
Internal clocks
Platform clock Core clock
Table continues on the next page...
I/O interface clocks
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Module clocks
132
Module
NVIC
DAP
DMA
DMA Mux
Port control
Crossbar Switch
Peripheral bridges
LLWU, PMC, SIM, RCM
Mode controller
MCM
Watchdog timer
MCG
OSC
Flash Controller
Flash memory
ADC
CMP
DAC
TPM
PIT
LPTMR
RTC
USB FS OTG
SPI0
SPI1
I 2 C0
I 2 C1
UART0
UART1 , UART2
I 2 S
Table 5-2. Module clocks (continued)
Bus interface clock
Platform clock
Platform clock
System modules
System clock
Bus clock
Bus clock
Platform clock
System clock
Bus clock
Internal clocks
—
—
—
—
—
—
Bus clock
LPO
Bus clock
Platform clock
Bus clock
Clocks
Bus clock MCGOUTCLK, MCGPLLCLK,
MCGFLLCLK, MCGIRCLK,
OSCERCLK
Bus clock OSCERCLK
Memory and memory interfaces
Platform clock Flash clock
Flash clock —
Analog
—
—
LPO
Bus clock
Bus clock
Bus clock
OSCERCLK
—
—
Timers
Bus clock
Bus clock
—
Bus clock LPO, OSCERCLK,
MCGIRCLK, ERCLK32K
Bus clock ERCLK32K
Communication interfaces
System clock
Bus clock
System clock
—
—
Bus clock
System clock
Bus clock
Bus clock
Bus clock
—
—
—
I/O interface clocks
—
SWD_CLK
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TPM_CLKIN0, TPM_CLKIN1
—
—
RTC_CLKOUT
—
SPI0_SCK
SPI1_SCK
I2C0_SCL
I2C1_SCL
—
—
I2S_TX_BCLK,
I2S_RX_BCLK
Human-machine interfaces
Table continues on the next page...
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Module
GPIO
TSI
Table 5-2. Module clocks (continued)
Bus interface clock
Platform clock
Bus clock
Internal clocks
—
—
Chapter 5 Clock Distribution
I/O interface clocks
—
—
5.7.1 PMC 1-kHz LPO clock
The Power Management Controller (PMC) generates a 1-kHz clock that is enabled in all modes of operation, including all low-power modes except VLLS0. This 1-kHz source is commonly referred to as LPO clock or 1-kHz LPO clock.
5.7.2 COP clocking
The COP may be clocked from two clock sources as shown in the following figure.
LPO
COP clock
Bus clock
SIM_COPCTRL[COPCLKS]
Figure 5-2. COP clock generation
5.7.3 RTC clocking
The RTC module can be clocked as shown in the following figure.
NOTE
The chosen clock must remain enabled if the RTC is to continue operating in all required low-power modes.
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Module clocks
LPO
RTC_CLKIN
OSC32KCLK
ERCLK32K
(to RTC)
SIM_SOPT1[OSC32KSEL]
Figure 5-3. RTC clock generation
5.7.4 LPTMR clocking
The prescaler and glitch filters in each of the LPTMRx modules can be clocked as shown in the following figure.
NOTE
The chosen clock must remain enabled if the LPTMRx is to continue operating in all required low-power modes.
RTC_CLKIN
LPO
MCGIRCLK
LPO
ERCLK32K
OSCERCLK
LPTMRx prescaler/glitch filter clock
OSC32KCLK
SIM_SOPT1[OSC32KSEL] LPTMRx_PSR[PCS]
Figure 5-4. LPTMRx prescaler/glitch filter clock generation
5.7.5 TPM clocking
The counter for the TPM modules has a selectable clock as shown in the following figure.
NOTE
The chosen clock must remain enabled if the TPMx is to continue operating in all required low-power modes.
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MCGIRCLK
OSCERCLK
MCGFLLCLK
MCGPLLCLK
TPM clock
÷2
SIM_SOPT2[PLLFLLSEL] SIM_SOPT2[TPMSRC]
Figure 5-5. TPM clock generation
5.7.6 USB FS OTG Controller clocking
The USB FS OTG controller is a bus master attached to the crossbar switch. As such, its clock is connected to the system clock.
NOTE
For the USB FS OTG controller to operate, the minimum system clock frequency is 20 MHz.
The USB OTG controller also requires a 48 MHz clock. The clock source options are shown below.
USB_CLKIN
USB 48MHz
MCGFLLCLK
MCGPLLCLK ÷2
SIM_SOPT2[PLLFLLSEL] SIM_SOPT2[USBSRC]
Figure 5-6. USB 48 MHz clock source
NOTE
The MCGFLLCLK does not meet the USB jitter specifications for certification.
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Module clocks
5.7.7 SPI clocking
SPI0 is clocked from the bus clock. That is, the SPI0 module clock is connected to the chip-level bus clock.
SPI1 is clocked from the system clock. That is, the SPI1 module clock is connected to the chip-level system clock. SPI1 is therefore disabled in "Partial Stop Mode".
5.7.8 I2C clocking
I2C0 is clocked from the bus clock.
I2C1 is clocked from the system clock. Clocking I2C1 at the faster system clock is needed to support standard I2C communication rates of 100 kbit/s in VLPR mode.
5.7.9 UART clocking
The UART0 module has a selectable clock as shown in the following figure. UART1 and
UART2 modules operate from the bus clock.
NOTE
The chosen clock must remain enabled if the UART0 is to continue operating in all required low-power modes.
MCGIRCLK
OSCERCLK
MCGFLLCLK
MCGPLLCLK ÷2
SIM_SOPT2[PLLFLLSEL] SIM_SOPT2[UART0SRC]
Figure 5-7. UART0 clock generation
UART0 clock
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Chapter 5 Clock Distribution
5.7.10 I 2 S/SAI clocking
The audio master clock (MCLK) is used to generate the bit clock when the receiver or transmitter is configured for an internally generated bit clock. The audio master clock can also be output to or input from a pin. The transmitter and receiver have the same audio master clock inputs.
Each SAI peripheral can control the input clock selection, pin direction and divide ratio of one audio master clock.
The I 2 S/SAI transmitter and receiver support asynchronous bit clocks (BCLKs) that can be generated internally from the audio master clock or supplied externally. The module also supports the option for synchronous operation between the receiver and transmitter.
The transmitter and receiver can independently select between the bus clock and the audio master clock to generate the bit clock.
The MCLK and BCLK source options appear in the following figure.
MCGPLLCLK
MCGFLLCLK
÷2 1
0
Clock Generation
OSCERCLK
System Clock
11
10
01
00
SIM_SOPT2[PLLFLLSEL]
1
0
MCLK
I2S/SAI
I2Sx_TCR2/RCR2
Bus Clock
11
10
01
00
Bit
Clock
Divider
[MSEL]
I2Sx_MCR[MOE]
[DIV]
I2Sx_MDR[FRACT,DIVIDE]
I2Sx_MCR[MICS]
MCLK_IN MCLK_OUT Direction
Control
Pad Interface Logic
Figure 5-8. I 2 S/SAI clock generation
BCLK_OUT
1
BCLK_IN 0
[BCD]
BCLK
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Module clocks
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Chapter 6
Reset and Boot
This section describes the basic reset and boot mechanisms and sources for this device.
6.1 Introduction
The reset sources supported in this MCU are listed in the table found here.
Table 6-1. Reset sources
Reset sources
POR reset
System resets
Debug reset
Description
•
•
•
•
Computer operating properly (COP) watchdog reset
•
Low leakage wakeup (LLWU) reset
•
Multipurpose clock generator loss of clock (LOC) reset
•
Multipurpose clock generator loss of lock (LOL) reset
•
Stop mode acknowledge error (SACKERR)
•
•
•
•
Each of the system reset sources has an associated bit in the System Reset Status (SRS)
registers. See the Reset Control Module for register details.
The MCU can exit and reset in functional mode where the CPU is executing code
(default) or the CPU is in a debug halted state. There are several boot options that can be
configured. See Boot information
for more details.
6.2 Reset
The information found here discusses basic reset mechanisms and sources.
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Reset
Some modules that cause resets can be configured to cause interrupts instead. Consult the individual peripheral chapters for more information.
6.2.1 Power-on reset (POR)
When power is initially applied to the MCU or when the supply voltage drops below the power-on reset re-arm voltage level (V
POR condition.
), the POR circuit causes a POR reset
As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has risen above the LVD low threshold (V
LVDL
Status Register are set following a POR.
). The POR and LVD fields in the Reset
6.2.2 System reset sources
Resetting the MCU provides a way to start processing from a known set of initial conditions. System reset begins with the on-chip regulator in full regulation and system clocking generation from an internal reference. When the processor exits reset, it performs the following:
• Reads the start SP (SP_main) from vector-table offset 0
• Reads the start program counter (PC) from vector-table offset 4
• Link register (LR) is set to 0xFFFF_FFFF.
The on-chip peripheral modules are disabled and the non-analog I/O pins are initially configured as disabled. The pins with analog functions assigned to them default to their analog function after reset.
During and following a reset, the SWD pins have their associated input pins configured as:
• SWD_CLK in pulldown (PD)
• SWD_DIO in pullup (PU)
6.2.2.1 External pin reset (RESET_b)
This pin is open drain and has an internal pullup device. Asserting RESET_b wakes the device from any mode.
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The RESET_b pin can be disabled by programming RESET_PIN_CFG option bit to 0.
When this option is selected, there could be a short period of contention during a POR ramp where the device drives the pin-out low prior to establishing the setting of this option and releasing the reset function on the pin. When the RESET pin is disabled and configured as a GPIO output, it operates as a pseudo open drain output.
6.2.2.1.1 RESET pin filter
The RESET pin filter supports filtering from both the 1 kHz LPO clock and the bus clock. RCM_RPFC[RSTFLTSS], RCM_RPFC[RSTFLTSRW], and
RCM_RPFW[RSTFLTSEL] control this functionality; see the
chapter. The filters are asynchronously reset by Chip POR. The reset value for each filter assumes the
RESET pin is negated.
For all stop modes where LPO clock is still active (Stop, VLPS, LLS, VLLS3, and
VLLS1), the only filtering option is the LPO-based digital filter. The filtering logic either switches to bypass operation or has continued filtering operation depending on the filtering mode selected. When entering VLLS0, the RESET pin filter is disabled and bypassed.
The LPO filter has a fixed filter value of 3. Due to a synchronizer on the input data, there is also some associated latency (2 cycles). As a result, 5 cycles are required to complete a transition from low to high or high to low.
6.2.2.2 Low-voltage detect (LVD)
The chip includes a system for managing low-voltage conditions to protect memory contents and control MCU system states during supply voltage variations. The system consists of a power-on reset (POR) circuit and an LVD circuit with a user-selectable trip voltage. The LVD system is always enabled in Normal Run, Wait, or Stop mode. The
LVD system is disabled when entering VLPx, LLS, or VLLSx modes.
The LVD can be configured to generate a reset upon detection of a low-voltage condition by setting PMC_LVDSC1[LVDRE] to 1. The low-voltage detection threshold is determined by PMC_LVDSC1[LVDV]. After an LVD reset has occurred, the LVD system holds the MCU in reset until the supply voltage has risen above the low voltage detection threshold. RCM_SRS0[LVD] is set following either an LVD reset or POR.
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Reset
6.2.2.3 Computer operating properly (COP) watchdog timer
The computer operating properly (COP) watchdog timer (WDOG) monitors the operation of the system by expecting periodic communication from the software. This communication is generally known as servicing (or refreshing) the COP watchdog. If this periodic refreshing does not occur, the watchdog issues a system reset. The COP reset causes RCM_SRS0[WDOG] to set.
6.2.2.4 Low leakage wakeup (LLWU)
The LLWU module provides the means for a number of external pins and a number of internal peripherals to wake the MCU from low leakage power modes. The LLWU module is functional only in low leakage power modes. In VLLSx modes, all enabled inputs to the LLWU can generate a system reset.
After a system reset, the LLWU retains the flags indicating the input source of the last wakeup until the user clears them.
NOTE
Some flags are cleared in the LLWU and some flags are required to be cleared in the peripheral module. Refer to the individual peripheral chapters for more information.
6.2.2.5 Multipurpose clock generator loss-of-clock (LOC)
The MCG module supports an external reference clock.
If MCG_C6[CME] is set, the clock monitor is enabled. If the external reference falls below f loc_low
or f loc_high
, as controlled by MCG_C2[RANGE], the MCU resets.
RCM_SRS0[LOC] is set to indicate this reset source.
NOTE
To prevent unexpected loss of clock reset events, all clock monitors must be disabled before entering any low-power modes, including VLPR and VLPW.
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6.2.2.6 MCG loss-of-lock (LOL) reset
The MCG includes a PLL loss-of-lock detector. The detector is enabled when configured for PEE and lock has been achieved. If MCG_C8[LOLRE] is set and the PLL Lock
Status bit (MCG_S[LOLS0]) becomes set, the MCU resets. RCM_SRS0[LOL] is set to indicate this reset source.
NOTE
This reset source does not cause a reset if the chip is in any stop mode.
6.2.2.7 Stop mode acknowledge error (SACKERR)
This reset is generated if the core attempts to enter Stop mode or Compute Operation, but not all modules acknowledge Stop mode within 1025 cycles of the 1 kHz LPO clock.
A module might not acknowledge the entry to Stop mode if an error condition occurs.
The error can be caused by a failure of an external clock input to a module.
6.2.2.8 Software reset (SW)
The SYSRESETREQ field in the NVIC Application Interrupt and Reset Control register can be set to force a software reset on the device. (See ARM's NVIC documentation for the full description of the register fields, especially the VECTKEY field requirements.)
Setting SYSRESETREQ generates a software reset request. This reset forces a system reset of all major components except for the debug module. A software reset causes
RCM_SRS1[SW] to set.
6.2.2.9 Lockup reset (LOCKUP)
The LOCKUP gives immediate indication of seriously errant kernel software. This is the result of the core being locked because of an unrecoverable exception following the activation of the processor’s built in system state protection hardware.
The LOCKUP condition causes a system reset and also causes RCM_SRS1[LOCKUP] to set.
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Reset
6.2.2.10 MDM-AP system reset request
Set the System Reset Request field in the MDM-AP control register to initiate a system reset. This is the primary method for resets via the SWD interface. The system reset is held until this field is cleared.
Set the Core Hold Reset field in the MDM-AP control register to hold the core in reset as the rest of the chip comes out of system reset.
6.2.3 MCU resets
A variety of resets are generated by the MCU to reset different modules.
6.2.3.1 POR Only
The POR Only reset asserts on the POR reset source only. It resets the PMC and RTC.
The POR Only reset also causes all other reset types to occur.
6.2.3.2 Chip POR not VLLS
The Chip POR not VLLS reset asserts on POR and LVD reset sources. It resets parts of the SMC and SIM. It also resets the LPTMR.
The Chip POR not VLLS reset also causes these resets to occur: Chip POR, Chip Reset not VLLS, and Chip Reset (including Early Chip Reset).
6.2.3.3 Chip POR
The Chip POR asserts on POR, LVD, and VLLS Wakeup reset sources. It resets the
Reset Pin Filter registers and parts of the SIM and MCG.
The Chip POR also causes the Chip Reset (including Early Chip Reset) to occur.
6.2.3.4 Chip Reset not VLLS
The Chip Reset not VLLS reset asserts on all reset sources except a VLLS Wakeup that does not occur via the RESET pin. It resets parts of the SMC, LLWU, and other modules that remain powered during VLLS mode.
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The Chip Reset not VLLS reset also causes the Chip Reset (including Early Chip Reset) to occur.
6.2.3.5 Early Chip Reset
The Early Chip Reset asserts on all reset sources. It resets only the flash memory module.
It negates before flash memory initialization begins ("earlier" than when the Chip Reset negates).
6.2.3.6 Chip Reset
Chip Reset asserts on all reset sources and only negates after flash initialization has completed and the RESET pin has also negated. It resets the remaining modules (the modules not reset by other reset types).
6.2.4 RESET_b pin
For all reset sources except a VLLS Wakeup that does not occur via the RESET_b pin, the RESET_b pin is driven low by the MCU for at least 128 bus clock cycles and until flash initialization has completed.
After flash initialization has completed, the RESET_b pin is released, and the internal
Chip Reset negates after the RESET_b pin is pulled high. Keeping the RESET_b pin asserted externally delays the negation of the internal Chip Reset.
The RESET_b pin can be disabled by programming FTFA_FOPT[RESET_PIN_CFG]
option bit to 0 (See Table 6-2
). When this option is selected, there could be a short period of contention during a POR ramp where the device drives the pin low prior to establishing the setting of this option and releasing the reset function on the pin. When the RESET pin is disabled and configured as a GPIO output, it operates as a pseudo open drain output.
6.2.5 Debug resets
The following sections detail the debug resets available on the device.
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6.2.5.1 Resetting the Debug subsystem
Use the CDBGRSTREQ field within the DP CTRL/STAT register to reset the debug modules. However, as explained below, using the CDBGRSTREQ field does not reset all debug-related registers.
CDBGRSTREQ resets the debug-related registers within the following modules:
• SW-DP
• AHB-AP
• MDM-AP (MDM control and status registers)
CDBGRSTREQ does not reset the debug-related registers within the following modules:
• CM0+ core (core debug registers: DHCSR, DCRSR, DCRDR, DEMCR)
• BPU
• DWT
• NVIC
6.3 Boot
The information found here describes the boot sequence, including sources and options.
Some configuration information such as clock trim values stored in factory programmed flash locations is autoloaded.
6.3.1 Boot sources
The CM0+ core adds support for a programmable Vector Table Offset Register (VTOR) to relocate the exception vector table. This device supports booting from internal flash and RAM.
This device supports booting from internal flash with the reset vectors located at addresses 0x0 (initial SP_main), 0x4 (initial PC), and RAM with relocating the exception vector table to RAM.
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1. CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available during System Reset.
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Chapter 6 Reset and Boot
6.3.2 FOPT boot options
The Flash Option (FOPT) register in the Flash Memory module (FTFA_FOPT) allows the user to customize the operation of the MCU at boot time. The register contains readonly bits that are loaded from the NVM's option byte in the flash configuration field. The default setting for all values in the FTFA_FOPT register is logic 1 since it is copied from the option byte residing in flash, which has all bits as logic 1 in the flash erased state. To configure for alternate settings, program the appropriate bits in the NVM option byte.
The new settings will take effect on subsequent POR, VLLSx recoveries, and any system reset. For more details on programming the option byte, see the flash memory chapter.
The MCU uses FTFA_FOPT to configure the device at reset as shown in the following table.
Bit
Num
7-6
5
Field
Reserved
FAST_INIT
3
Table 6-2. Flash Option Register (FTFA_FOPT) definition
Value Definition
RESET_PIN_CFG
Reserved for future expansion.
Selects initialization speed on POR, VLLSx, and any system reset.
0
1
Slower initialization: The flash initialization will be slower with the benefit of reduced average current during this time. The duration of the recovery will be controlled by the clock divider selection determined by the LPBOOT setting.
Fast Initialization: The flash has faster recoveries at the expense of higher current during these times.
Enables/disables control for the RESET pin.
0 RESET_b pin is disabled following a POR and cannot be enabled as reset function. When this option is selected, there could be a short period of contention during a POR ramp where the device drives the pin low prior to establishing the setting of this option and releasing the reset function on the pin. When the RESET pin is disabled and configured as a GPIO output, it operates as a pseudo open drain output.
1
This bit is preserved through system resets and low-power modes. When
RESET_b pin function is disabled, it cannot be used as a source for low-power mode wake-up.
NOTE: When the reset pin has been disabled and security has been enabled by means of the FSEC register, a mass erase can be performed only by setting both the Mass Erase and System Reset Request fields in the
MDM-AP register.
RESET_b pin is dedicated. The port is configured with pullup enabled, open drain, passive filter enabled.
Table continues on the next page...
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Table 6-2. Flash Option Register (FTFA_FOPT) definition
(continued)
Value Definition
2
Bit
Num
NMI_DIS
Field
1
4,0
Reserved
LPBOOT
Enables/disables control for the NMI function.
0 NMI interrupts are always blocked. The associated pin continues to default to
NMI_b pin controls with internal pullup enabled. When NMI_b pin function is disabled, it cannot be used as a source for low-power mode wake-up.
00
01
10
11
1
If the NMI function is not required, either for an interrupt or wake up source, it is recommended that the NMI function be disabled by clearing NMI_DIS.
NMI_b pin/interrupts reset default to enabled.
Reserved for future expansion.
Controls the reset value of OUTDIV1 value in SIM_CLKDIV1 register. Larger divide value selections produce lower average power consumption during POR, VLLSx recoveries and reset sequencing and after reset exit. The recovery times are also extended if the
FAST_INIT option is not selected.
Core and system clock divider (OUTDIV1) is 0x7 (divide by 8).
Core and system clock divider (OUTDIV1) is 0x3 (divide by 4).
Core and system clock divider (OUTDIV1) is 0x1 (divide by 2).
Core and system clock divider (OUTDIV1) is 0x0 (divide by 1).
6.3.3 Boot sequence
At power up, the on-chip regulator holds the system in a POR state until the input supply exceeds the POR threshold. The system continues to be held in this static state until the internally regulated supplies have reached a safe operating voltage as determined by the
LVD. The Reset Controller logic then controls a sequence to exit reset.
1. A system reset is held on internal logic, the RESET pin is driven out low, and the
MCGis enabled in its default clocking mode.
2. Required clocks are enabled (system clock, flash clock, and any bus clocks that do not have clock gate control reset to disabled).
3. The system reset on internal logic continues to be held, but the Flash Controller is released from reset and begins initialization operation while the Reset Control logic continues to drive the RESET pin out low.
4. Early in reset sequencing, the NVM option byte is read and stored to the FOPT register of the Flash Memory module (FTFA_FOPT). If the bits associated with
FTFA_FOPT[LPBOOT] are programmed for an alternate clock divider reset value, the system/core clock is switched to a slower clock speed. If
FTFA_FOPT[FAST_INIT] is programmed clear, the flash initialization switches to slower clock resulting longer recovery times.
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5. When flash Initialization completes, the RESET pin is released. If RESET continues to be asserted (an indication of a slow rise time on the RESET pin or external drive in low), the system continues to be held in reset. Once the RESET pin is detected high, the core clock is enabled and the system is released from reset.
6. When the system exits reset, the processor sets up the stack, program counter (PC), and link register (LR). The processor reads the start SP (SP_main) from vector-table offset 0. The core reads the start PC from vector-table offset 4. LR is set to
0xFFFF_FFFF. The next sequence of events depends on the NMI input and
FTFA_FOPT[NMI_DIS] (See Table 6-2
) :
• If the NMIinput is high or the NMI function is disabled in FTFA_FOPT, the
CPU begins execution at the PC location.
• If the NMI input is low and the NMI function is enabled in FTFA_FOPT, this results in an NMI interrupt. The processor executes an Exception Entry and reads the NMI interrupt handler address from vector-table offset 8. The CPU begins execution at the NMI interrupt handler.
NOTE
If the NMI function is not required, either for an interrupt or wake up source, it is recommended that the NMI function be disabled by clearing NMI_DIS in the FOPT register.
Subsequent system resets follow this same reset flow.
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Chapter 7
Power Management
This section describes the various chip power modes and the functionality of the individual modules in these modes.
7.1 Introduction
Information about the various chip power modes and functionality of the individual modules in these modes can be found here.
See AN4503: Power Management for Kinetis and ColdFire+ MCUs for further details on power management techniques.
7.2 Clocking modes
Information found here describes the various clocking modes supported on this device.
7.2.1 Partial Stop
Partial Stop is a clocking option that can be taken instead of entering Stop mode and is configured in the SMC Stop Control Register (SMC_STOPCTRL). The Stop mode is only partially entered, which leaves some additional functionality alive at the expense of higher power consumption. Partial Stop can be entered from either Run mode or VLP
Run mode.
When configured for PSTOP2, only the core and system clocks are gated and the bus clock remains active. The bus masters and bus slaves clocked by the system clock enter
Stop mode, but the bus slaves clocked by bus clock remain in Run (or VLP Run) mode.
The clock generators in the MCG and the on-chip regulator in the PMC also remain in
Run (or VLP Run) mode. Exit from PSTOP2 can be initiated by a reset, an asynchronous interrupt from a bus master or bus slave clocked by the system clock, or a synchronous
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Clocking modes interrupt from a bus slave clocked by the bus clock. If configured, a DMA request (using the asynchronous DMA wakeup) can also be used to exit Partial Stop for the duration of a
DMA transfer before the device is transitioned back into PSTOP2.
When configured for PSTOP1, both the system clock and bus clock are gated. All bus masters and bus slaves enter Stop mode, but the clock generators in the MCG and the onchip regulator in the PMC remain in Run (or VLP Run) mode. Exit from PSTOP1 can be initiated by a reset or an asynchronous interrupt from a bus master or bus slave. If configured, an asynchronous DMA request can also be used to exit Partial Stop for the duration of a DMA transfer before the device is transitioned back into PSTOP1.
PSTOP1 is functionally similar to Stop mode, but offers faster wake-up at the expense of higher power consumption. Another benefit is that it keeps all of the MCG clocks enabled, which can be useful for some of the asynchronous peripherals that can remain functional in Stop modes.
7.2.2 DMA Wakeup
The DMA can be configured to wake the device on a DMA request whenever it is placed in Stop mode. The wake-up is configured per DMA channel and is supported in Compute
Operation, PSTOP, STOP, and VLPS low power modes.
When a DMA wake-up is detected in PSTOP, STOP or VLPS then the device will initiate a normal exit from the low power mode. This can include restoring the on-chip regulator and internal power switches, enabling the clock generators in the MCG, enabling the system and bus clocks (but not the core clock) and negating the stop mode signal to the bus masters and bus slaves. The only difference is that the CPU will remain in the low power mode with the CPU clock disabled.
During Compute Operation, a DMA wake-up will initiate a normal exit from Compute
Operation. This includes enabling the clocks and negating the stop mode signal to the bus masters and bus slaves. The core clock always remains enabled during Compute
Operation.
Since the DMA wakeup will enable the clocks and negate the stop mode signals to all bus masters and slaves, software needs to ensure that bus masters and slaves that are not involved with the DMA wake-up and transfer remain in a known state. That can be accomplished by disabling the modules before entry into the low power mode or by setting the Doze enable bit in selected modules.
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Once the DMA request that initiated the wake-up negates and the DMA completes the current transfer, the device will transition back to the original low-power mode. This includes requesting all non-CPU bus masters to enter Stop mode and then requesting bus slaves to enter Stop mode. In STOP and VLPS modes the MCG and PMC would then also enter their appropriate modes.
NOTE
If the requested DMA transfer cannot cause the DMA request to negate then the device will remain in a higher power state until the low power mode is fully exited.
An enabled DMA wake-up can cause an aborted entry into the low power mode, if the
DMA request asserts during the stop mode entry sequence (or reentry if the request asserts during a DMA wakeup) and can cause the SMC to assert its Stop Abort flag. Once the DMA wake-up completes, entry into the low power mode will restart.
An interrupt that occurs during a DMA wake-up will cause an immediate exit from the low power mode (this is optional for Compute Operation) without impacting the DMA transfer.
A DMA wake-up can be generated by either a synchronous DMA request or an asynchronous DMA request. Not all peripherals can generate an asynchronous DMA request in stop modes, although in general if a peripheral can generate synchronous DMA requests and also supports asynchronous interrupts in stop modes, then it can generate an asynchronous DMA request.
7.2.3 Compute Operation
Compute Operation is an execution or compute-only mode of operation that keeps the
CPU enabled with full access to the SRAM and Flash read port, but places all other bus masters and bus slaves into their stop mode. Compute Operation can be enabled in either
Run mode or VLP Run mode.
NOTE
Do not enter any Stop mode without first exiting Compute
Operation.
Because Compute Operation reuses the Stop mode logic (including the staged entry with bus masters disabled before bus slaves), any bus master or bus slave that can remain functional in Stop mode also remains functional in Compute Operation, including generation of asynchronous interrupts and DMA requests. When enabling Compute
Operation in Run mode, module functionality for bus masters and slaves is the equivalent of STOP mode. When enabling Compute Operation in VLP Run mode, module
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Clocking modes functionality for bus masters and slaves is the equivalent of VLPS mode. The MCG,
PMC, SRAM, and Flash read port are not affected by Compute Operation, although the
Flash register interface is disabled.
During Compute Operation, the AIPS peripheral space is disabled and attempted accesses generate bus errors. The private peripheral space remains accessible during Compute
Operation, including the MCM, NVIC, IOPORT, and SysTick. Although access to the
GPIO registers via the IOPORT is supported, the GPIO Port Data Input registers do not return valid data since clocks are disabled to the Port Control and Interrupt modules. By writing to the GPIO Port Data Output registers, it is possible to control those GPIO ports that are configured as output pins.
Compute Operation is controlled by the CPO register in the MCM (MCM_CPO), which is only accessible to the CPU. Setting or clearing MCM_CPO[CPOREQ] initiates entry or exit into Compute Operation. Compute Operation can also be configured to exit automatically on detection of an interrupt, which is required in order to service most interrupts. Only the core system interrupts (exceptions, including NMI and SysTick) and any edge-sensitive interrupts can be serviced without exiting Compute Operation.
• When entering Compute Operation, the CPOACK status field in the CPO register of
MCM module (MCM_CPO[CPOACK]) indicates when entry has completed.
• When exiting Compute Operation in Run mode, MCM_CPO[CPOACK] negates immediately.
• When exiting Compute Operation in VLP Run mode, the exit is delayed to allow the
PMC to handle the change in power consumption. This delay means that
MCM_CPO[CPOACK] is polled to determine when the AIPS peripheral space can be accessed without generating a bus error.
The DMA wake-up is also supported during Compute Operation and causes
MCM_CPO[CPOACK] to clear and the AIPS peripheral space to be accessible for the duration of the DMA wakeup. At the completion of the DMA wake-up, the device transitions back into Compute Operation.
7.2.4 Peripheral Doze
Several peripherals support a Peripheral Doze mode, where a register bit can be used to disable the peripheral for the duration of a low-power mode. The flash memory can also be placed in a low-power state during Peripheral Doze via a register bit in the SIM.
Peripheral Doze is defined to include all of the modes of operation listed below.
• The CPU is in Wait mode.
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• The CPU is in Stop mode, including the entry sequence and for the duration of a
DMA wakeup.
• The CPU is in Compute Operation, including the entry sequence and for the duration of a DMA wakeup.
Peripheral Doze can therefore be used to disable selected bus masters or slaves for the duration of WAIT or VLPW mode. It can also be used to disable selected bus slaves immediately on entry into any stop mode (or Compute Operation), instead of waiting for the bus masters to acknowledge the entry as part of the stop entry sequence. Finally, it can be used to disable selected bus masters or slaves that should remain inactive during a
DMA wakeup.
If the flash memory is not being accessed during WAIT and PSTOP modes, then the
Flash Doze mode can be used to reduce power consumption, at the expense of a slightly longer wake-up when executing code and vectors from flash. It can also be used to reduce power consumption during Compute Operation when executing code and vectors from
SRAM.
7.2.5 Clock gating
To conserve power, the clocks to most modules can be turned off using the SCGCx registers in the SIM module. The bits of these registers are cleared after any reset, which disables the clock to the corresponding module. Prior to initializing a module, set the corresponding bit in the SCGCx register to enable the clock. Before turning off the clock, make sure to disable the module. For more details, see the
chapters.
7.3 Power modes
The Power Management Controller (PMC) provides multiple power options to allow the user to optimize power consumption for the level of functionality needed.
Depending on the stop requirements of the user application, a variety of stop modes are available that provide state retention, partial power-down or full power-down of certain logic and/or memory. I/O states are held in all modes of operation. The following table compares the various power modes available.
For each run mode, there is a corresponding Wait and Stop mode. Wait modes are similar to ARM Sleep modes. Stop modes (VLPS, STOP) are similar to ARM Sleep Deep mode.
The Very Low Power Run (VLPR) operating mode can drastically reduce runtime power when the maximum bus frequency is not required to handle the application needs.
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Power modes
The three primary modes of operation are Run, Wait, and Stop. The WFI instruction invokes both Wait and Stop modes for the chip. The primary modes are augmented in a number of ways to provide lower power based on application needs.
Table 7-1. Chip power modes
Chip mode Description Core mode
Run
Normal recovery method
— Normal Run Allows maximum performance of chip.
• Default mode out of reset
• On-chip voltage regulator is on.
Normal Wait via WFI
Allows peripherals to function while the core is in Sleep mode, reducing power.
• NVIC remains sensitive to interrupts
• Peripherals continue to be clocked.
Normal Stop via WFI
Places chip in static state. Lowest power mode that retains all registers while maintaining LVD protection.
• NVIC is disabled.
• AWIC is used to wake up from interrupt.
• Peripheral clocks are stopped.
VLPR (Very
Low-Power Run)
On-chip voltage regulator is in a low-power mode that supplies only enough power to run the chip at a reduced frequency. Only MCG modes BLPI and BLPE can be used in VLPR.
• Reduced frequency Flash access mode (1 MHz)
• LVD off
• In BLPI clock mode, only the fast internal reference oscillator is available to provide a low power nominal 4 MHz source for the core with the nominal bus and flash clock required to be <800 kHz
• Alternatively, BLPE clock mode can be used with an external clock or the crystal oscillator providing the clock source.
VLPW (Very
Low-Power
Wait) -via WFI
VLPS (Very
Low-Power
Stop)-via WFI
Same as VLPR but with the core in Sleep mode to further reduce power.
• NVIC remains sensitive to interrupts (FCLK = ON).
• On-chip voltage regulator is in a low-power mode that supplies only enough power to run the chip at a reduced frequency.
Places chip in static state with LVD operation off. Lowest power mode with ADC and pin interrupts functional.
• Peripheral clocks are stopped, but OSC, LPTMR, RTC, CMP,
TSI can be used.
• TPM and UART can optionally be enabled if their clock source is enabled.
• NVIC is disabled (FCLK = OFF); AWIC is used to wake up from interrupt.
• On-chip voltage regulator is in a low-power mode that supplies only enough power to run the chip at a reduced frequency.
• All SRAM is operating (content retained and I/O states held).
Table continues on the next page...
Sleep
Sleep Deep
Run
Sleep
Sleep Deep
Interrupt
Interrupt
—
Interrupt
Interrupt
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Chip mode Description
Table 7-1. Chip power modes (continued)
Chapter 7 Power Management
Core mode
Sleep Deep
Normal recovery method
Wake-up
LLS (Low-
Leakage Stop)
VLLS3 (Very
Low-Leakage
Stop3)
VLLS1 (Very
Low-Leakage
Stop1)
VLLS0 (Very
Low-Leakage
Stop 0)
State retention power mode
• Most peripherals are in state retention mode (with clocks stopped), but OSC, LLWU,LPTMR, RTC, CMP, TSI can be used.
• NVIC is disabled; LLWU is used to wake up.
NOTE: The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an LLS recovery
• All SRAM is operating (content retained and I/O states held).
• Most peripherals are disabled (with clocks stopped), but OSC,
LLWU, LPTMR, RTC, CMP, TSI can be used.
• NVIC is disabled; LLWU is used to wake up.
• SRAM_U and SRAM_L remain powered on (content retained and I/O states held).
• Most peripherals are disabled (with clocks stopped), but OSC,
LLWU, LPTMR, RTC, CMP, TSI can be used.
• NVIC is disabled; LLWU is used to wake up.
• All of SRAM_U and SRAM_L are powered off.
• The 32-byte system register file remains powered for customercritical data
• Most peripherals are disabled (with clocks stopped), but LLWU,
LPTMR, RTC, TSI can be used.
• NVIC is disabled; LLWU is used to wake up.
• All of SRAM_U and SRAM_L are powered off.
• The 32-byte system register file remains powered for customercritical data
• LPO disabled, optional POR brown-out detection
Sleep Deep Wake-up Reset
Sleep Deep Wake-up Reset
Sleep Deep Wake-up Reset
1. Resumes Normal Run mode operation by executing the LLWU interrupt service routine.
2. Follows the reset flow with the LLWU interrupt flag set for the NVIC.
7.4 Entering and exiting power modes
The WFI instruction invokes wait and stop modes for the chip. The processor exits the low-power mode via an interrupt.
For LLS and VLLS modes, the wake-up sources are limited to LLWU generated wakeups,NMI_b pin, or RESET_b pin assertions. When the NMI_b pin or RESET_b pin have been disabled through associated FTFA_FOPT settings, then these pins are ignored as wakeup sources. The wake-up flow from VLLSx is always through reset.
Before executing the WFI instruction, the last register written to must be read back. This ensures that all register writes associated with setting up the low power mode being entered have completed before the MCU enters the low power mode. Failure to do this may result in the low power mode not being entered correctly.
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Module operation in low-power modes
NOTE
The WFE instruction can have the side effect of entering a lowpower mode, but that is not its intended usage. See ARM documentation for more on the WFE instruction.
On VLLS recoveries, the I/O pins continue to be held in a static state after code execution begins, allowing software to reconfigure the system before unlocking the I/O. RAM is retained in VLLS3 only.
7.5 Module operation in low-power modes
The table found here illustrates the functionality of each module while the chip is in each of the low power modes.
The standard behavior is shown with some exceptions for Compute Operation (CPO) and
Partial Stop2 (PSTOP2).
Debug modules are discussed separately; see
. Number ratings (such as 4 MHz and 1 Mbit/s) represent the maximum frequencies or maximum data rates per mode. Following is list of terms also used in the table.
• FF = Full functionality. In VLPR and VLPW, the system frequency is limited, but if a module does not have a limitation in its functionality, it is still listed as FF.
• Async operation = Fully functional with alternate clock source, provided the selected clock source remains enabled
• static = Module register states and associated memories are retained.
• powered = Memory is powered to retain contents.
• low power = Memory is powered to retain contents in a lower power state
• OFF = Modules are powered off; module is in reset state upon wake-up. For clocks,
OFF means disabled.
• wakeup = Modules can serve as a wake-up source for the chip.
Modules
NVIC
Mode Controller
LLWU
Regulator
VLPR
FF
Table 7-2. Module operation in low power modes
FF static low power
VLPW
FF
FF static low power
Stop
Core modules static
System modules
FF static
ON
VLPS static
FF static low power
LLS static
FF
FF low power
VLLSx
OFF
FF
low power in
VLLS3, OFF in
VLLS0/1
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LVD
Modules
Brown-out
Detection
DMA
Watchdog
1kHz LPO
System oscillator (OSC)
MCG
Core clock
Platform clock
System clock
Bus clock
Flash
SRAM_U and
SRAM_L
Chapter 7 Power Management
Table 7-2. Module operation in low power modes (continued)
VLPR disabled
ON
VLPW disabled
ON
FF
Stop
ON
ON
VLPS disabled
ON
Async operation Async operation
LLS disabled
ON static
VLLSx disabled
ON in VLLS1/3, optionally disabled in
OFF FF
Async operation in CPO
FF static in CPO
ON
FF
ON static
FF in PSTOP2
Clocks
ON static
ON static OFF
OSCERCLK max of 16MHz crystal
4 MHz IRC
4 MHz max
4 MHz max
4 MHz max
OFF in CPO
1 MHz max
OFF in CPO
OSCERCLK max of 16MHz crystal
4 MHz IRC
OFF
4 MHz max
4 MHz max
OSCERCLK optional static -
MCGIRCLK optional; PLL optional
OFF
OFF
OFF
OSCERCLK max of 16MHz crystal static -
MCGIRCLK optional
OFF
OFF
OFF
ON
OSCERCLK max of 16MHz crystal static - no clock output
ON in VLLS1/3, optional be disabled by
SMC_STOPCT
RL [LPOPO] ,
OFF in VLLS0
OSCERCLK max of 16MHz crystal in
VLLS1/3, OFF in
VLLS0
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF 1 MHz max OFF OFF
24 MHz max in
PSTOP2 from
RUN
1 MHz max in
PSTOP2 from
VLPR
Memory and memory interfaces low power low power low power OFF OFF 1 MHz max access - no program
No register access in CPO low power low power low power low power low power low power in
VLLS3, OFF in
VLLS0/1
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Table 7-2. Module operation in low power modes (continued)
Modules
System Register
File
VLPR powered
VLPW powered
Stop powered
VLPS powered
LLS powered
USB FS
USB Voltage
Regulator
UART0 static optional static
Communication interfaces static static optional optional optional
Async operation
FF in PSTOP2
Async operation static optional static
UART1, UART2
SPI0
SPI1
I 2 C0
I 2 C1
I 2 S
1 Mbit/s
Async operation in CPO
62.5 kbit/s static, wakeup on edge in CPO master mode
500 kbit/s, slave mode 250 kbit/s static, slave mode receive in
CPO master mode 2
Mbit/s, slave mode 1
Mbit/s static, slave mode receive in
CPO
50 kbit/s static, address match wakeup in CPO
100 kbps static, address match wakeup in CPO
FF
Async operation in CPO
1 Mbit/s
62.5 kbit/s master mode
500 kbit/s, slave mode 250 kbit/s master mode 2
Mbit/s, slave mode 1
Mbit/s
50 kbit/s
100 kbps
FF static, wakeup on edge
FF in PSTOP2 static, slave mode receive
FF in PSTOP2 static, slave mode receive static, address match wakeup
FF in PSTOP2 static, address match wakeup static, wakeup on edge static, slave mode receive static, slave mode receive static, address match wakeup static, address match wakeup
Async operation
FF in PSTOP2
Async operation static static static static static static
TPM
PIT
FF
Async operation in CPO
FF static in CPO
FF
FF
Timers
Async operation
FF in PSTOP2
Async operation static static static static
Table continues on the next page...
VLLSx powered
OFF optional
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
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Modules
LPTMR
RTC
16-bit ADC
6-bit DAC
12-bit DAC
GPIO
TSI
Chapter 7 Power Management
Table 7-2. Module operation in low power modes (continued)
VLPR
FF
FF
Async operation in CPO
VLPW
FF
FF
Stop
Async operation
FF in PSTOP2
Async operation
FF in PSTOP2
VLPS LLS
Async operation Async operation
Async operation Async operation
VLLSx
Async
Async
FF
Analog
ADC internal clock only
FF in PSTOP2
ADC internal clock only static OFF FF
ADC internal clock only in
CPO
FF
HS or LS compare in CPO
FF static in CPO
FF static in CPO
FF
IOPORT write only in CPO
FF
Async operation in CPO
FF
FF
FF
FF
Async
HS or LS compare
FF in PSTOP2
Async
FF in PSTOP2
HS or LS compare
FF in PSTOP2 static
FF in PSTOP2 static static static
FF in PSTOP2
Human-machine interfaces static output, wakeup input static output, wakeup input
Async
LS compare static static static, pins latched
Async
LS compare in
VLLS1/3, OFF in
VLLS0 static, OFF in
VLLS0 static
OFF, pins latched
Async
1. Using the LLWU module, the external pins available for this chip do not require the associated peripheral function to be enabled. It only requires the function controlling the pin (GPIO or peripheral) to be configured as an input to allow a transition to occur to the LLWU.
2. Since LPO clock source is disabled, filters will be bypassed during VLLS0.
3. STOPCTRL[PORPO] in the SMC module controls this option.
4. LPO clock source is not available in VLLS0. Also, to use system OSC in VLLS0 it must be configured for bypass (external clock) operation. Pulse counting is available in all modes.
5. In VLLS0 the only clocking option is from RTC_CLKIN.
6. CMP in stop or VLPS supports high speed or low speed external pin to pin or external pin to DAC compares. CMP in LLS or VLLSx only supports low speed external pin to pin or external pin to DAC compares.
7. TSI wake-up from all low-power modes is limited to a single selectable pin.
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Module operation in low-power modes
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Chapter 8
Security
This section provides an overview of flash security and details the effects of security on non-flash modules.
8.1 Introduction
This device implements security based on the mode selected from the flash module.
The following sections provide an overview of flash security and details the effects of security on non-flash modules.
8.1.1 Flash security
The flash module provides security information to the MCU based on the state held by
FTFA_FSEC[SEC]. The MCU, in turn, confirms the security request and limits access to flash resources. During reset, the flash module initializes FTFA_FSEC using data read from the security byte of the flash configuration field.
NOTE
The security features apply only to external accesses: debug.
CPU accesses to the flash are not affected by the status of
FTFA_FSEC.
In the unsecured state, all flash commands are available on the programming interfaces either from the debug port (SWD) or user code execution. When the flash is secured
(FTFA_FSEC[SEC] = 00, 01, or 11), the programmer interfaces are only allowed to launch mass erase operations. Additionally, in this mode, the debug port has no access to memory locations.
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Introduction
8.1.2 Security interactions with other modules
The flash security settings are used by the system to determine what resources are available. The following sections describe the interactions between modules and the flash security settings or the impact that the flash security has on non-flash modules.
8.1.2.1 Security interactions with Debug
When flash security is active, the SWD port cannot access the memory resources of the
MCU.
Although most debug functions are disabled, the debugger can write to the Flash Mass
Erase in Progress field of the MDM-AP Control register to trigger a mass erase (Erase
All Blocks) command. A mass erase via the debugger is allowed even when some memory locations are protected.
When mass erase is disabled, mass erase via the debugger is blocked.
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Chapter 9
Debug
This section describes the debug architecture and components of this device.
9.1 Introduction
This debug of this device is based on the ARM CoreSight ™ architecture and is configured to provide the maximum flexibility as allowed by the restrictions of the pinout and other available resources.
It provides register and memory accessibility from the external debugger interface, basic run/halt control plus 2 breakpoints and 2 watchpoints.
Only one debug interface is supported:
• Serial Wire Debug (SWD)
9.2 Debug port pin descriptions
The debug port pins default after POR to their SWD functionality.
Table 9-1. Serial wire debug pin description
Pin name
SWD_CLK
SWD_DIO
Type
Input
Input / Output
Description
Serial Wire Clock
This pin is the clock for debug logic when in the Serial Wire Debug mode.
This pin is pulled down internally.
Serial Wire Debug Data Input/Output
The SWD_DIO pin is used by an external debug tool for communication and device control. This pin is pulled up internally.
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SWD status and control registers
9.3 SWD status and control registers
Through the ARM Debug Access Port (DAP), the debugger has access to the status and control elements, implemented as registers on the DAP bus as shown in the figure found here.
These registers provide additional control and status for low power mode recovery and typical run-control scenarios. The status register bits also provide a means for the debugger to get updated status of the core without having to initiate a bus transaction across the crossbar switch, thus remaining less intrusive during a debug session.
It is important to note that these DAP control and status registers are not memory mapped within the system memory map and are only accessible via the Debug Access Port using
SWD. The MDM-AP is accessible as Debug Access Port 1 with the available registers shown in this table.
Table 9-2. MDM-AP register summary
Address
0x0100_0000
0x0100_0004
0x0100_00FC
Register
Status
Control
IDR
Description
Read-only identification register that always reads as 0x001C_0020
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Chapter 9 Debug
DPACC
Data[31:0] A[3:2] RnW
APACC
Data[31:0] A[3:2] RnW
SW-DP
See the ARM Debug Interface v5p1 Supplement.
APSEL
Decode
AHB Access Port
(AHB-AP)
Bus Matrix
Data[31:0]
Generic
Debug Port
(DP)
A[7:4] A[3:2] RnW
SELECT[31:24] (APSEL) selects the AP
SELECT[7:4] (APBANKSEL) selects the bank
A[3:2] from the APACC selects the register within the bank
AHB-AP
SELECT[31:24] = 0x00 selects the AHB-AP
See ARM documentation for further details
MDM-AP
MDM-AP
SELECT[31:24] = 0x01 selects the MDM-AP
SELECT[7:4] = 0x0 selects the bank with Status and Ctrl
A[3:2] = 2’b00 selects the Status Register
A[3:2] = 2’b01 selects the Control Register
See Control and Status Register
Descriptions
Figure 9-1. MDM AP addressing
SELECT[7:4] = 0xF selects the bank with IDR
A[3:2] = 2’b11 selects the IDR Register
(IDR register reads 0x001C_0020)
9.3.1 MDM-AP Control Register
Table 9-3. MDM-AP Control register assignments
Bit Name
0 Flash Mass Erase in Progress Y
Description
Set to cause mass erase. Cleared by hardware after mass erase operation completes.
When mass erase is disabled (via MEEN and SEC settings), the erase request does not occur and the Flash Mass Erase in Progress bit continues to assert until the next system reset.
NOTE: When the reset pin has been disabled and security has been enabled by means of the FSEC register, a mass erase can be performed only by setting both the mass erase and system reset request bits in the MDM-AP register.
Table continues on the next page...
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SWD status and control registers
Table 9-3. MDM-AP Control register assignments (continued)
Bit
1
2
3
4
5
6
7
Debug Disable
Name
Debug Request
System Reset Request
Core Hold Reset
VLLSx Debug Request
(VLLDBGREQ)
VLLSx Debug Acknowledge
(VLLDBGACK)
LLS, VLLSx Status Acknowledge
N
N
Y
N
N
N
N
Description
Set to disable debug. Clear to allow debug operation. When set, it overrides the C_DEBUGEN bit within the DHCSR and force disables
Debug logic.
Set to force the core to halt.
If the core is in a Stop or Wait mode, this bit can be used to wake the core and transition to a halted state.
Set to force a system reset. The system remains held in reset until this bit is cleared.
Configuration bit to control core operation at the end of system reset sequencing.
0 Normal operation: Release the core from reset along with the rest of the system at the end of system reset sequencing.
1 Suspend operation: Hold the core in reset at the end of reset sequencing. Once the system enters this suspended state, clearing this control bit immediately releases the core from reset and CPU operation begins.
Set to configure the system to be held in reset after the next recovery from a VLLSx mode. This bit is ignored on a VLLS wakeup via the
Reset pin. During a VLLS wakeup via the Reset pin, the system can be held in reset by holding the reset pin asserted allowing the debugger to reinitialize the debug modules.
This bit holds the system in reset when VLLSx modes are exited to allow the debugger time to re-initialize debug IP before the debug session continues.
The Mode Controller captures this bit logic on entry to VLLSx modes.
Upon exit from VLLSx modes, the Mode Controller will hold the system in reset until VLLDBGACK is asserted.
VLLDBGREQ clears automatically due to the POR reset generated as part of the VLLSx recovery.
Set to release a system being held in reset following a VLLSx recovery
This bit is used by the debugger to release the system reset when it is being held on VLLSx mode exit. The debugger re-initializes all debug
IP and then assert this control bit to allow the Mode Controller to release the system from reset and allow CPU operation to begin.
VLLDBGACK is cleared by the debugger or can be left set because it clears automatically due to the POR reset generated as part of the next VLLSx recovery.
Set this bit to acknowledge the DAP LLS and VLLS Status bits have been read. This acknowledge automatically clears the status bits.
This bit is used by the debugger to clear the sticky LLS and VLLSx mode entry status bits. This bit is asserted and cleared by the debugger.
8 –
31
Reserved for future use N
1. Command available in secure mode
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Chapter 9 Debug
9.3.2 MDM-AP Status Register
Table 9-4. MDM-AP Status register assignments
Bit
0
1
2
3
4
5
6
7
8
Name Description
Flash Mass Erase Acknowledge The Flash Mass Erase Acknowledge bit is cleared after any system reset.
The bit is also cleared at launch of a mass erase command due to write of
Flash Mass Erase in Progress bit in MDM AP Control Register. The Flash
Mass Erase Acknowledge is set after Flash control logic has started the mass erase operation.
Flash Ready
System Security
System Reset
When mass erase is disabled (via MEEN and SEC settings), an erase request due to setting of Flash Mass Erase in Progress bit is not acknowledged.
Indicates Flash has been initialized and debugger can be configured even if system is continuing to be held in reset via the debugger.
Indicates the security state. When secure, the debugger does not have access to the system bus or any memory mapped peripherals. This bit indicates when the part is locked and no system bus access is possible.
Indicates the system reset state.
0 System is in reset.
1 System is not in reset.
Reserved
Mass Erase Enable Indicates if the MCU can be mass erased or not
0 Mass erase is disabled.
Backdoor Access Key Enable
LP Enabled
1 Mass erase is enabled .
Indicates if the MCU has the backdoor access key enabled.
0 Disabled
1 Enabled
Decode of SMC_PMCTRL[STOPM] field to indicate that VLPS, LLS, or
VLLSx are the selected power mode the next time the ARM Core enters
Deep Sleep.
0 Low Power Stop Mode is not enabled.
Very Low Power Mode
1 Low Power Stop Mode is enabled.
Usage intended for debug operation in which Run to VLPS is attempted.
Per debug definition, the system actually enters the Stop state. A debugger should interpret deep sleep indication (with SLEEPDEEP and
SLEEPING asserted), in conjunction with this bit asserted as the debugger-VLPS status indication.
Indicates current power mode is VLPx. This bit is not ‘sticky’ and should always represent whether VLPx is enabled or not.
This bit is used to throttle SWD_CLK frequency up/down.
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Debug resets
Bit
9
10
11 – 15
16
17
18
19 – 31
Table 9-4. MDM-AP Status register assignments (continued)
Name
LLS Mode Exit
VLLSx Modes Exit
Reserved for future use
Core Halted
Core SLEEPDEEP
Core SLEEPING
Reserved for future use
Description
This bit indicates an exit from LLS mode has occurred. The debugger will lose communication while the system is in LLS (including access to this register). Once communication is reestablished, this bit indicates that the system had been in LLS. Since the debug modules held their state during
LLS, they do not need to be reconfigured.
This bit is set during the LLS recovery sequence. The LLS Mode Exit bit is held until the debugger has had a chance to recognize that LLS was exited and is cleared by a write of 1 to the LLS, VLLSx Status Acknowledge bit in
MDM AP Control register.
This bit indicates an exit from VLLSx mode has occurred. The debugger will lose communication while the system is in VLLSx (including access to this register). Once communication is reestablished, this bit indicates that the system had been in VLLSx. Since the debug modules lose their state during VLLSx modes, they need to be reconfigured.
This bit is set during the VLLSx recovery sequence. The VLLSx Mode Exit bit is held until the debugger has had a chance to recognize that a VLLS mode was exited and is cleared by a write of 1 to the LLS, VLLSx Status
Acknowledge bit in MDM AP Control register.
Always read 0.
Indicates the core has entered Debug Halt mode
Indicates the core has entered a low-power mode
SLEEPING==1 and SLEEPDEEP==0 indicates wait or VLPW mode.
SLEEPING==1 and SLEEPDEEP==1 indicates stop or VLPS mode.
Always read 0.
9.4 Debug resets
The debug system receives the following sources of reset:
• Debug reset (the CDBGRSTREQ field within the DP CTRL/STAT register) that allows the debugger to reset the debug logic.
• System POR reset
Conversely, the debug system is capable of generating system reset using the following mechanism:
• A system reset in the DAP control register which allows the debugger to hold the system in reset.
• SYSRESETREQ field in the NVIC Application Interrupt and Reset control register
• A system reset in the DAP control register which allows the debugger to hold the core in reset.
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Chapter 9 Debug
9.5 Micro Trace Buffer (MTB)
The Micro Trace Buffer (MTB) provides a simple execution trace capability for the
Cortex-M0+ processor.
When enabled, the MTB records changes in program flow reported by the Cortex-M0+ processor, via the execution trace interface, into a configurable region of the SRAM.
Subsequently, an off-chip debugger may extract the trace information, which would allow reconstruction of an instruction flow trace. The MTB does not include any form of load/store data trace capability or tracing of any other information.
In addition to providing the trace capability, the MTB also operates as a simple AHB-Lite
SRAM controller. The system bus masters, including the processor, have read/write access to all of the SRAM via the AHB-Lite interface, allowing the memory to be also used to store program and data information. The MTB simultaneously stores the trace information into an attached SRAM and allows bus masters to access the memory. The
MTB ensures that trace information write accesses to the SRAM take priority over accesses from the AHB-Lite interface.
The MTB includes trace control registers for configuring and triggering the MTB functions. The MTB also supports triggering via TSTART and TSTOP control functions in the MTB DWT module.
9.6 Debug in low-power modes
In low-power modes, in which the debug modules are kept static or powered off, the debugger cannot gather any debug data for the duration of the low-power mode.
• In the case that the debugger is held static, the debug port returns to full functionality as soon as the low-power mode exits and the system returns to a state with active debug.
• In the case that the debugger logic is powered off, the debugger is reset on recovery and must be reconfigured once the low-power mode is exited.
Power mode entry logic monitors Debug Power Up and System Power Up signals from the debug port as indications that a debugger is active. These signals can be changed in
RUN, VLPR, WAIT and VLPW. If the debug signal is active and the system attempts to enter Stop or VLPS, FCLK continues to run to support core register access. In these modes in which FCLK is left active the debug modules have access to core registers but not to system memory resources accessed via the crossbar.
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Debug and security
With debug enabled, transitions from Run directly to VLPS result in the system entering
Stop mode instead. Status bits within the MDM-AP Status register can be evaluated to determine this pseudo-VLPS state.
NOTE
With the debug enabled, transitions from Run --> VLPR -->
VLPS are still possible.
In VLLS mode, all debug modules are powered off and reset at wakeup. In LLS mode, the debug modules retain their state but no debug activity is possible.
Going into a VLLSx mode causes all the debug controls and settings to be reset. To give time to the debugger to sync up with the HW, the MDM-AP Control register can be configured to hold the system in reset on recovery so that the debugger can regain control and reconfigure debug logic prior to the system exiting reset and resuming operation.
9.7 Debug and security
When flash security is enabled, the debug port capabilities are limited in order to prevent exploitation of secure data.
In the secure state, the debugger still has access to the status register and can determine the current security state of the device. In the case of a secure device, the debugger has the capability of only performing a mass erase operation.
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Chapter 10
Signal Multiplexing and Signal Descriptions
This section illustrates which of this device’s signals are multiplexed on which external pin.
10.1 Introduction
To optimize functionality in small packages, pins have several functions available via signal multiplexing. Information found here illustrates which of this device's signals are multiplexed on which external pin.
The
block controls which signal is present on the external pin. Refer to that chapter to find which register controls the operation of a specific pin.
10.2 Signal multiplexing integration
Information found here summarizes how the module is integrated into the device. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Signal multiplexing integration
Topic
Full description
System memory map
Clocking
Register access
Peripheral bus controller 1
Register access
Transfers Transfers
Module
Module
Signal Multiplexing/
Port Control
Module
Figure 10-1. Signal multiplexing integration
Table 10-1. Reference links to related information
Related module
Port control
Peripheral bus controller
Reference
10.2.1 Port control and interrupt module features
• 32-pin ports
NOTE
Not all pins are available on the device. See the following section for details.
• Port A is assigned a dedicated interrupt and Port C and Port D share an interrupt. For
DMA requests, Port A, Port C, and Port D each have a dedicated input to the DMA
MUX.
The reset state and read/write characteristics of the fields within the PORTx_PCRn registers is summarized in the table below.
Table 10-2. Port control register configuration summary
This field of
PORTx_PC
Rn
PS 1
Generally resets to
PTA0
Except for
0
Resets to
PE 0 PTA0 and PTA2 1
Configurability
Yes—All GPIOs are configurable.
Yes— All GPIOs are configurable.
Table continues on the next page...
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Chapter 10 Signal Multiplexing and Signal Descriptions
Table 10-2. Port control register configuration summary (continued)
Resets to Configurability This field of
PORTx_PC
Rn
DSE 0
Generally resets to
Except for
No exceptions—all DSE are cleared on reset.
—
SRE
MUX
1
000
PTA3, PTA14, PTA15, PTA16, PTA17, PTB10,
PTB11, PTB16, PTB17, PTC3, PTC4, PTC5, PTC6,
PTC7, PTD4, PTD5, PTD6, PTD7
PTA0, PTA3, and PTA4
0
111
4 pins are configurable for
High Drive (PTB0 , PTB1,
PTD6 , PTD7). All others are fixed for Normal Drive and the associated DSE bit is read only.
Yes— All GPIO are configurable.
PFE
IRQC
ISF
0
000
0
No exceptions—all PFE are cleared on reset.
No exceptions—all are cleared on reset.
No exceptions—all are cleared on reset.
—
—
—
Yes— All GPIO are configurable.
The GPIO shared with
NMI_b pin is configurable.
All other GPIOs are fixed and read only.
Only implemented for ports that support interrupt and DMA functionality.
Only implemented for ports that support interrupt and DMA functionality.
1. The RESET_b pin has the passive analog filter fixed enabled when functioning as the RESET_b pin
(FOPT[RESET_PIN_CFG] = 1) and fixed disabled when configured for other shared functions.
10.2.2 Clock gating
The clock to the port control module can be gated on and off using the SCGC5[PORTx] bits in the SIM module. These bits are cleared after any reset, which disables the clock to the corresponding module to conserve power. Prior to initializing the corresponding module, set SIM_SCGC5[PORTx] to enable the clock. Before turning off the clock, make sure to disable the module. For more details, see the
chapter.
10.2.3 Signal multiplexing constraints
1. A given peripheral function must be assigned to a maximum of one package pin. Do not program the same function to more than one pin.
2. To ensure the best signal timing for a given peripheral's interface, choose the pins in closest proximity to each other.
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Pinout
10.3 Pinout
E3
H7
G4
E2
F4
F3
10.3.1 KL26 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin.
ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 121
BGA
E4
100
LQFP
1
64
BGA
A1
64
LQFP
1
48
QFN
—
32
QFN
Pin Name
1 PTE0
Default
DISABLED PTE0 CMP0_OUT I2C1_SDA
6
5
4
3
2
7
B1 2 —
— — —
— — —
— — —
— — —
— — —
— PTE1
— PTE2
— PTE3
— PTE4
— PTE5
— PTE6
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
PTE1
PTE2
PTE3
PTE4
PTE5
PTE6
SPI1_MISO UART1_TX RTC_
CLKOUT
SPI1_MOSI UART1_RX
SPI1_SCK
SPI1_MISO
SPI1_PCS0
SPI1_MISO I2C1_SCL
SPI1_MOSI
I2S0_MCLK audioUSB_
SOF_OUT
E6 8 — 3 1
G7 9
L6 —
F1 10 E1
F2 11 D1
C4 4 2
— — —
5
6 4
3
G1 12 E2
G2 13 D2
7
8
H1 14 — — —
6
5
H2 15 — — —
J1 16 — — —
J2 17 — — —
K1 18 G1 9
K2 19 F1 10
L1 20 G2 11 —
L2 21 F2 12 —
F5 22 F4 13 9
8
7
— VDD VDD VDD
2 VSS
— VSS
VSS
VSS
VSS
VSS
3 USB0_DP USB0_DP USB0_DP
4 USB0_DM USB0_DM USB0_DM
5 VOUT33
6 VREGIN
— PTE16
—
—
—
—
—
—
—
7
PTE17
PTE18
PTE19
PTE20
PTE21
PTE22
PTE23
VDDA
VOUT33
VREGIN
ADC0_DP1/
ADC0_SE1
ADC0_DM1/
ADC0_SE5a
ADC0_DP2/
ADC0_SE2
ADC0_DM2/
ADC0_SE6a
ADC0_DP0/
ADC0_SE0
ADC0_DM0/
ADC0_SE4a
ADC0_DP3/
ADC0_SE3
ADC0_DM3/
ADC0_SE7a
VDDA
VOUT33
VREGIN
ADC0_DP1/
ADC0_SE1
ADC0_DM1/
ADC0_SE5a
ADC0_DP2/
ADC0_SE2
ADC0_DM2/
ADC0_SE6a
ADC0_DP0/
ADC0_SE0
ADC0_DM0/
ADC0_SE4a
ADC0_DP3/
ADC0_SE3
ADC0_DM3/
ADC0_SE7a
VDDA
PTE16
PTE17
PTE18
PTE19
PTE20
PTE21
PTE22
PTE23
SPI0_PCS0 UART2_TX TPM_
CLKIN0
SPI0_SCK UART2_RX TPM_
CLKIN1
SPI0_MOSI I2C0_SDA SPI0_MISO
LPTMR0_
ALT3
SPI0_MISO I2C0_SCL SPI0_MOSI
TPM1_CH0 UART0_TX
TPM1_CH1 UART0_RX
TPM2_CH0 UART2_TX
TPM2_CH1 UART2_RX
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BGA
100
LQFP
64
BGA
64
LQFP
48
QFN
32
QFN
Pin Name
G5 23 G4 14 10 — VREFH
G6 24 G3 15 11 — VREFL
F6 25 F3 16 12 8 VSSA
L3 26 H1 17 13 — PTE29
K5 27 H2 18 14
L4 28 H3 19 —
L5 29 — — —
K6 30 — — —
J5
H6
32
33
H5
—
21
—
16
—
9 PTE30
— PTE31
— VSS
— VDD
H5 31 H4 20 15 — PTE24
—
—
PTE25
PTE26
Default ALT0
DISABLED
VSS
VDD
DISABLED
DISABLED
DISABLED
VREFH
VREFL
VSSA
CMP0_IN5/
ADC0_SE4b
DAC0_OUT/
ADC0_
SE23/
CMP0_IN4
VREFH
VREFL
VSSA
CMP0_IN5/
ADC0_SE4b
DAC0_OUT/
ADC0_
SE23/
CMP0_IN4
PTE29
PTE30
PTE31
VSS
VDD
PTE24
PTE25
PTE26
ALT1
Chapter 10 Signal Multiplexing and Signal Descriptions
ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
TPM0_CH2 TPM_
TPM0_CH3 TPM_
TPM0_CH4
TPM0_CH0
TPM0_CH1
TPM0_CH5
CLKIN0
CLKIN1
I2C0_SCL
I2C0_SDA
RTC_
CLKOUT
USB_CLKIN
J6 34 D3 22 17 10 PTA0
H8 35 D4 23 18 11 PTA1
J7 36 E5 24 19 12 PTA2
H9 37 D5 25 20 13 PTA3
J8 38 G5 26 21 14 PTA4
K7 39 F5 27 — — PTA5
SWD_CLK TSI0_CH1 PTA0
DISABLED TSI0_CH2 PTA1
DISABLED TSI0_CH3 PTA2
SWD_DIO TSI0_CH4 PTA3
NMI_b
DISABLED
TSI0_CH5 PTA4
PTA5
TPM0_CH5
UART0_RX TPM2_CH0
UART0_TX TPM2_CH1
I2C1_SCL TPM0_CH0
I2C1_SDA TPM0_CH1
USB_CLKIN TPM0_CH2 I2S0_TX_
BCLK
SWD_CLK
SWD_DIO
NMI_b
E5 —
G3 —
— — —
— — —
K3 40 — — —
H4 41 — — —
K8 42 H6 28 —
L8 43 G6 29 —
K9 44 — — —
L9
J10
H10
K11
45
46
47
51
—
—
—
G8
—
—
—
33
—
—
—
25
— VDD
— VSS
— PTA6
— PTA7
— PTA12
— PTA13
— PTA14
— PTA15
— PTA16
—
18
PTA17
L10 48 G7 30 22 15 VDD
K10 49 H7 31 23 16 VSS
L11 50 H8 32 24 17 PTA18
PTA19
VDD
VSS
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
VDD
VSS
EXTAL0
XTAL0
VDD
VSS
VDD
VSS
EXTAL0
XTAL0
PTA6
PTA7
PTA12
PTA13
PTA14
PTA15
PTA16
PTA17
PTA18
PTA19
SPI0_PCS0 UART0_TX
SPI0_SCK
SPI0_MOSI
SPI0_MISO
TPM0_CH3
TPM0_CH4
TPM1_CH0
TPM1_CH1
UART0_RX
UART1_RX TPM_
CLKIN0
UART1_TX TPM_
CLKIN1
I2S0_TXD0
I2S0_TX_FS
I2S0_RX_
BCLK
LPTMR0_
ALT1
I2S0_TXD0
I2S0_RXD0
SPI0_MISO I2S0_RX_FS I2S0_RXD0
SPI0_MOSI I2S0_MCLK
J11 52 F8 34 26 19 PTA20
G11 53 F7 35 27 20 PTB0/
LLWU_P5
RESET_b
ADC0_SE8/
TSI0_CH0
ADC0_SE8/
TSI0_CH0
PTA20
PTB0/
LLWU_P5
I2C0_SCL TPM1_CH0
RESET_b
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177
Pinout
121
BGA
100
LQFP
64
BGA
64
LQFP
48
QFN
32
QFN
Pin Name
G10 54 F6 36 28 21 PTB1
Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6
G9
G8
55
56
E7
E8
37
38
29
30
E11 57 — — —
D11 58 — — —
E10 59 — — —
D10 60 — — —
C10 61 — — — — PTB11
B10 62 E6 39 31 — PTB16
E9
D9
63
64
D7
D6
40
41
32
—
—
—
—
—
—
—
—
—
PTB2
PTB3
PTB7
PTB8
PTB9
PTB10
PTB17
PTB18
ADC0_SE9/
TSI0_CH6
ADC0_
SE12/
TSI0_CH7
ADC0_
SE13/
TSI0_CH8
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
TSI0_CH9
ADC0_SE9/
TSI0_CH6
ADC0_
SE12/
TSI0_CH7
ADC0_
SE13/
TSI0_CH8
TSI0_CH9
PTB1
PTB2
PTB3
PTB7
PTB8
PTB9
PTB10
PTB11
PTB16
TSI0_CH10 TSI0_CH10 PTB17
TSI0_CH11 TSI0_CH11 PTB18
I2C0_SDA
I2C0_SCL
I2C0_SDA
TPM1_CH1
TPM2_CH0
TPM2_CH1
SPI1_PCS0 EXTRG_IN
SPI1_SCK
SPI1_PCS0
SPI1_SCK
SPI1_MOSI UART0_RX TPM_
CLKIN0
SPI1_MISO UART0_TX TPM_
CLKIN1
TPM2_CH0 I2S0_TX_
BCLK
TPM2_CH1 I2S0_TX_FS
SPI1_MISO
SPI1_MOSI
C9
F10
65
66
C7
—
42
—
—
—
F9 67 — — —
F8 68 — — —
E8 69 — — —
—
—
PTB19
PTB20
— PTB21
— PTB22
— PTB23
B9 70 D8 43 33 — PTC0
D8 71 C6 44 34 22 PTC1/
LLWU_P6/
RTC_CLKIN
C8 72 B7 45 35 23 PTC2
B8 73 C8 46 36 24 PTC3/
F7 74 E3 47 —
E7 75 E4 48 —
A10 —
A9 —
B11 —
— — —
— — —
— — —
—
—
—
LLWU_P7
VSS
VDD
PTC20
— PTC21
— PTC22
C11 — — — — — PTC23
A8 76 B8 49 37 25 PTC4/
LLWU_P8
D7 77 A8 50 38 26 PTC5/
LLWU_P9
TSI0_CH12 TSI0_CH12 PTB19
DISABLED PTB20
DISABLED
DISABLED
DISABLED
ADC0_
SE14/
TSI0_CH13
ADC0_
SE15/
TSI0_CH14
ADC0_
SE11/
TSI0_CH15
DISABLED
ADC0_
SE14/
TSI0_CH13
ADC0_
SE15/
TSI0_CH14
ADC0_
SE11/
TSI0_CH15
PTB21
PTB22
PTB23
PTC0
PTC1/
LLWU_P6/
RTC_CLKIN
PTC2
PTC3/
LLWU_P7
VSS
VDD
DISABLED
VSS
VDD
PTC20
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
PTC21
PTC22
PTC23
PTC4/
LLWU_P8
PTC5/
LLWU_P9
I2C1_SCL
I2C1_SDA
EXTRG_IN
SPI0_SCK LPTMR0_
ALT2 audioUSB_
SOF_OUT
TPM0_CH0
TPM0_CH1
CMP0_OUT I2S0_TXD0
UART1_RX TPM0_CH2 CLKOUT
SPI0_PCS0 UART1_TX TPM0_CH3 I2S0_MCLK
I2S0_RXD0
CMP0_OUT
I2S0_TXD0
I2S0_TX_FS
I2S0_TX_
BCLK
CMP0_OUT
ALT7
178
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121
BGA
100
LQFP
64
BGA
64
LQFP
48
QFN
32
QFN
Pin Name
C7 78 A7 51 39 27 PTC6/
LLWU_P10
B7 79 B6 52 40 28 PTC7
A7
D6
C6
C5
B6
A6
80
81
82
83
84
85
A6
B5
B4
A5
—
—
53
54
55
56
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PTC8
PTC9
PTC10
PTC11
PTC12
PTC13
Default
CMP0_IN2
CMP0_IN3
DISABLED
DISABLED
DISABLED
DISABLED
ALT0
CMP0_IN2
CMP0_IN3
ALT1
PTC8
PTC9
PTC10
PTC11
PTC12
PTC13
Chapter 10 Signal Multiplexing and Signal Descriptions
CMP0_IN0 CMP0_IN0 PTC6/
LLWU_P10
CMP0_IN1 CMP0_IN1 PTC7
ALT2 ALT3 ALT4
SPI0_MOSI EXTRG_IN I2S0_RX_
SPI0_MISO audioUSB_
SOF_OUT
BCLK
I2C0_SCL TPM0_CH4 I2S0_MCLK
I2C0_SDA TPM0_CH5 I2S0_RX_
BCLK
I2C1_SCL
I2C1_SDA
I2S0_RX_FS
I2S0_RXD0
TPM_
CLKIN0
TPM_
CLKIN1
ALT5
SPI0_MISO I2S0_MCLK
I2S0_RX_FS SPI0_MOSI
ALT6 ALT7
D5 90 — — —
C4 91 — — —
B4 92 — — —
— PTC16
— PTC17
— PTC18
D4 93 C3 57 41 — PTD0
D3 94 A4 58 42 — PTD1
C3 95 C2 59 43 — PTD2
B3 96 B3 60 44 — PTD3
A3 97 A3 61 45 29 PTD4/
LLWU_P14
A2 98 C1 62 46 30 PTD5
B2 99 B2 63 47 31 PTD6/
LLWU_P15
A1 100 A2 64 48 32 PTD7
J9 —
J4 —
H11 —
F11 —
A5 —
B5 —
A4 —
B1 —
C2 —
A11 86 C5 — —
— 87 — — —
— 88 — — —
— 89 — — —
J3 —
H3 —
K4 —
L7 —
—
—
—
—
—
—
—
—
—
—
—
—
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— — —
— NC
— NC
— NC
— NC
— NC
— NC
— NC
— NC
— NC
— NC
— NC
— NC
— NC
— NC
— NC
— NC
— NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DISABLED
DISABLED
DISABLED
PTC16
PTC17
PTC18
DISABLED PTD0
ADC0_SE5b ADC0_SE5b PTD1
DISABLED
DISABLED
PTD2
PTD3
DISABLED PTD4/
LLWU_P14
ADC0_SE6b ADC0_SE6b PTD5
ADC0_SE7b ADC0_SE7b PTD6/
LLWU_P15
DISABLED PTD7
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SPI0_PCS0
SPI0_SCK
TPM0_CH0
TPM0_CH1
SPI0_MOSI UART2_RX TPM0_CH2 SPI0_MISO
SPI0_MISO UART2_TX TPM0_CH3 SPI0_MOSI
SPI1_PCS0 UART2_RX TPM0_CH4
SPI1_SCK UART2_TX
SPI1_MOSI UART0_RX
SPI1_MISO UART0_TX
TPM0_CH5
SPI1_MISO
SPI1_MOSI
KL26 Sub-Family Reference Manual, Rev. 3.2, October 2013
Freescale Semiconductor, Inc.
179
Pinout
121
BGA
100
LQFP
C1 —
D2 —
D1 —
E1 —
64
BGA
64
LQFP
48
QFN
— — —
— — —
— — —
— — —
32
QFN
Pin Name
— NC
— NC
— NC
— NC
NC
NC
NC
NC
Default
NC
NC
NC
NC
ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
10.3.2 KL26 pinouts
The following figures show the pinout diagrams for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals
can be used on which pin, see KL26 Signal Multiplexing and Pin Assignments .
180
A
1
PTD7
B
C
D
E
NC
NC
NC
2
PTD5
3
PTD4/
LLWU_P14
NC
PTD6/
LLWU_P15
PTD3
4
NC
PTC18
5
NC
NC
6
PTC13
7
PTC8
8 9
PTC4/
LLWU_P8
PTC21
10
PTC20
11
NC A
PTC12 PTC7
PTC3/
LLWU_P7
PTC0 PTB16 PTC22 B
NC
NC
PTE2
PTD2
PTD1
PTC17 PTC11 PTC10
PTC6/
LLWU_P10
PTC2
PTD0 PTC16
PTB19 PTB11
PTC9
PTC5/
LLWU_P9
PTC1/
LLWU_P6/
RTC_CLKIN
PTB18 PTB10
PTC23 C
PTB8 D
PTE1 PTE0 VDD VDD VDD PTB23 PTB17 PTB9 PTB7 E
F USB0_DP USB0_DM PTE6 PTE3 VDDA VSSA VSS PTB22 PTB21 PTB20 NC F
G VOUT33 VREGIN VSS PTE5 VREFH VREFL VSS PTB3 PTB2 PTB1
PTB0/
LLWU_P5
G
H PTE16 PTE17 NC PTA7 PTE24 PTE26 PTE4 PTA1 PTA3 PTA17 NC H
J PTE18 PTE19 NC NC PTE25 PTA0 PTA2 PTA4 NC PTA16 PTA20 J
K PTE20 PTE21 PTA6 NC PTE30 VDD PTA5 PTA12 PTA14 VSS PTA19 K
L PTE22 PTE23 PTE29 PTE31
1 2 3 4
VSS
5
VSS
6
NC
7
PTA13 PTA15
8 9
VDD
10
PTA18 L
11
Figure 10-2. KL26 121-pin BGA pinout diagram
KL26 Sub-Family Reference Manual, Rev. 3.2, October 2013
Freescale Semiconductor, Inc.
Chapter 10 Signal Multiplexing and Signal Descriptions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PTE0
PTE1
PTE2
PTE3
PTE4
PTE5
PTE6
VDD
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
PTE16
PTE17
PTE18
PTE19
PTE20
PTE21
PTE22
PTE23
VDDA
VREFH
VREFL
VSSA
Figure 10-3. KL26 100-pin LQFP pinout diagram
66
65
64
70
69
68
67
75
74
73
72
71
56
55
54
59
58
57
53
52
51
63
62
61
60
PTB16
PTB11
PTB10
PTB9
PTB8
PTB7
PTB3
PTB2
PTB1
PTB0/LLWU_P5
PTA20
PTA19
PTB23
PTB22
PTB21
PTB20
PTB19
PTB18
PTB17
VDD
VSS
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6/RTC_CLKIN
PTC0
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Freescale Semiconductor, Inc.
181
Pinout
3
4
5
6
1
2
7
8
9
10
11
12
13
14
15
16
PTE0
PTE1
VDD
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
PTE20
PTE21
PTE22
PTE23
VDDA
VREFH
VREFL
VSSA
36
35
38
37
34
33
40
39
42
41
46
45
48
47
44
43
VDD
VSS
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6/RTC_CLKIN
PTC0
PTB19
PTB18
PTB17
PTB16
PTB3
PTB2
PTB1
PTB0/LLWU_P5
PTA20
PTA19
Figure 10-4. KL26 64-pin LQFP pinout diagram
182
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Freescale Semiconductor, Inc.
Chapter 10 Signal Multiplexing and Signal Descriptions
A
1
PTE0
2 3 4
PTD7
PTD4
/LLWU_P14
PTD1
5
PTC11
6 7 8
PTC8
PTC6
/LLWU_P10
PTC5
/LLWU_P9
A
B PTE1
PTD6
/LLWU_P15
PTD3
C PTD5 PTD2 PTD0
D USB0_DM VREGIN PTA0
PTC10
VSS
PTA1
PTC9
NC
PTC7 PTC2
PTC4
/LLWU_P8
B
PTC1
/LLWU_P6
/RTC
_CLKIN
PTB19
PTC3
/LLWU_P7
C
PTA3 PTB18 PTB17 PTC0 D
E USB0_DP VOUT33 VSS VDD PTA2 PTB16 PTB2 PTB3 E
F PTE21 PTE23 VSSA VDDA PTA5 PTB1
PTB0
/LLWU_P5
PTA20 F
G PTE20 PTE22 VREFL VREFH PTA4 PTA13 VDD PTA19 G
H PTE29 PTE30 PTE31 PTE24 PTE25 PTA12
1 2 3 4 5 6
VSS
7
PTA18 H
8
Figure 10-5. KL26 64-pin MAPBGA pinout diagram
KL26 Sub-Family Reference Manual, Rev. 3.2, October 2013
Freescale Semiconductor, Inc.
183
Pinout
VDD
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
PTE20
PTE21
VDDA
VREFH
VREFL
VSSA
5
6
7
8
9
10
11
12
1
2
3
4
28
27
30
29
26
25
36
33
32
35
34
31
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6/RTC_CLKIN
PTC0
PTB17
PTB16
PTB3
PTB2
PTB1
PTB0/LLWU_P5
PTA20
PTA19
Figure 10-6. KL26 48-pin QFN pinout diagram
184
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Chapter 10 Signal Multiplexing and Signal Descriptions
PTE0
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
VDDA
VSSA
1
2
3
4
5
6
7
8
21
20
19
18
17
24
23
22
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6/RTC_CLKIN
PTB1
PTB0/LLWU_P5
PTA20
PTA19
PTA18
Figure 10-7. KL26 32-pin QFN pinout diagram
10.4 Module Signal Description Tables
The following sections correlate the chip-level signal name with the signal name used in the module's chapter. They also briefly describe the signal function and direction.
KL26 Sub-Family Reference Manual, Rev. 3.2, October 2013
Freescale Semiconductor, Inc.
185
Module Signal Description Tables
10.4.1 Core modules
Table 10-3. SWD signal descriptions
Chip signal name Description
SWD_DIO
Module signal name
SWD_DIO
SWD_CLK SWD_CLK
Serial Wire Debug Data Input/Output
The SWD_DIO pin is used by an external debug tool for communication and device control. This pin is pulled up internally.
Serial Wire Clock
This pin is the clock for debug logic when in the Serial Wire Debug mode. This pin is pulled down internally.
I/O
Input /
Output
Input
10.4.2 System modules
Table 10-4. System signal descriptions
Chip signal name Description
NMI_b
Module signal name
—
RESET_b
VDD
VSS
—
—
—
Non-maskable interrupt
Driving the NMI_b signal low forces a non-maskable interrupt, if the
NMI function is selected on the corresponding pin.
NOTE: If the NMI function is not required, either for an interrupt or wake-up source, it is recommended that the NMI function be disabled by clearing NMI_DIS.
Reset bidirectional signal
MCU power
MCU ground
I/O
I
I
I/O
I
10.4.3 Clock modules
Table 10-5. OSC signal descriptions
Chip signal name Description
EXTAL0
XTAL0
Module signal name
EXTAL
XTAL
External clock/Oscillator input
Oscillator output
I/O
I
O
10.4.4 Memories and memory interfaces
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Chapter 10 Signal Multiplexing and Signal Descriptions
10.4.5 Analog
This table presents the signal descriptions of the ADC0 module.
Table 10-6. ADC0 signal descriptions
Chip signal name
ADC0_DPn
ADC0_DMn
ADC0_SEn
VREFH
VREFL
VDDA
VSSA
Module signal name
Description
DADP3–DADP0 Differential Analog Channel Inputs
DADM3–DADM0 Differential Analog Channel Inputs
AD n Single-Ended Analog Channel Inputs
V
REFSH
V
REFSL
V
DDA
V
SSA
Voltage Reference Select High
Voltage Reference Select Low
Analog Power Supply
Analog Ground
This table presents the signal descriptions of the CMP0 module.
Table 10-7. CMP0 signal descriptions
Chip signal name
CMP0_IN[5:0]
CMP0_OUT
Module signal name
IN[5:0]
CMPO
Description
Analog voltage inputs
Comparator output
This table presents the signal descriptions of the DAC0 module.
Chip signal name
DAC0_OUT
Table 10-8. DAC0 signal descriptions
Module signal name
—
Description
DAC output
I/O
I
O
I/O
O
I/O
I
I
I
I
I
I
I
10.4.6 Timer Modules
Table 10-9. TPM0 signal descriptions
Chip signal name Description
TPM_CLKIN[1:0]
Module signal name
EXTCLK
TPM0_CH[5:0] CHn
External clock. FTM external clock can be selected to drive the
FTM counter.
FTM channel (n), where n can be 7-0
KL26 Sub-Family Reference Manual, Rev. 3.2, October 2013
Freescale Semiconductor, Inc.
I/O
I
I/O
187
Module Signal Description Tables
Table 10-10. TPM1 signal descriptions
Chip signal name
TPM_CLKIN[1:0]
Module signal name
TPM_EXTCLK
Description
TPM1_CH[1:0] TPM_CHn
External clock. TPM external clock can be selected to increment the
TPM counter on every rising edge synchronized to the counter clock.
TPM channel (n = 5 to 0) I/O
I/O
I
Chip signal name
TPM_CLKIN[1:0]
TPM2_CH[1:0]
Table 10-11. TPM2 signal descriptions
Module signal name
TPM_EXTCLK
Description
TPM_CHn
External clock. TPM external clock can be selected to increment the
TPM counter on every rising edge synchronized to the counter clock.
TPM channel (n = 5 to 0) I/O
I/O
I
Chip signal name
LPTMR0_ALT[2:1]
Table 10-12. LPTMR0 signal descriptions
Module signal name
LPTMR_ALT n
Description
Pulse Counter Input pin
Chip signal name
RTC_CLKOUT
Table 10-13. RTC signal descriptions
Module signal name
RTC_CLKOUT
Description
1 Hz square-wave output
1. RTC_CLKOUT can also be driven with OSCERCLK via SIM control bit SIM_SOPT[RCTCLKOUTSEL]
I/O
I
I/O
O
10.4.7 Communication interfaces
Table 10-14. USB FS OTG Signal Descriptions
Chip signal name Description
USB0_DM
USB0_DP
USB_CLKIN
Module signal name usb_dm usb_dp
—
USB D- analog data signal on the USB bus.
USB D+ analog data signal on the USB bus.
Alternate USB clock input
I/O
I/O
I/O
I
188
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Freescale Semiconductor, Inc.
Chip signal name
VOUT33
VREGIN
Chapter 10 Signal Multiplexing and Signal Descriptions
Table 10-15. USB VREG Signal Descriptions
Module signal name reg33_out reg33_in
Description
Regulator output voltage
Unregulated power supply
I/O
O
I
Chip signal name
SPI0_MISO
SPI0_MOSI
SPI0_SCLK
SPI0_PCS0
Table 10-16. SPI0 signal descriptions
Module signal name
MISO
MOSI
SPSCK
SS
Description
Master Data In, Slave Data Out
Master Data Out, Slave Data In
SPI Serial Clock
Slave Select
I/O
I/O
I/O
I/O
I/O
Chip signal name
SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_PCS0
Table 10-17. SPI1 signal descriptions
Module signal name
MISO
MOSI
SPSCK
SS
Description
Master Data In, Slave Data Out
Master Data Out, Slave Data In
SPI Serial Clock
Slave Select
Chip signal name
I2C0_SCL
I2C0_SDA
Table 10-18. I 2 C0 signal descriptions
Module signal name
SCL
SDA
Description
Bidirectional serial clock line of the I 2 C system.
Bidirectional serial data line of the I 2 C system.
Chip signal name
I2C1_SCL
I2C1_SDA
Table 10-19. I 2 C1 signal descriptions
Module signal name
SCL
SDA
Description
Bidirectional serial clock line of the I 2 C system.
Bidirectional serial data line of the I 2 C system.
Chip signal name
UART0_TX
Table 10-20. UART0 signal descriptions
Module signal name
TxD
Description
Transmit data
Table continues on the next page...
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Freescale Semiconductor, Inc.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
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Module Signal Description Tables
Table 10-20. UART0 signal descriptions (continued)
Chip signal name
UART0_RX
Module signal name
RxD
Description
Receive data
Chip signal name
UART1_TX
UART1_RX
Table 10-21. UART1 signal descriptions
Module signal name
TxD
RxD
Description
Transmit data
Receive data
Chip signal name
UART2_TX
UART2_RX
Table 10-22. UART2 signal descriptions
Module signal name
TxD
RxD
Description
Transmit data
Receive data
10.4.8 Human-machine interfaces (HMI)
Table 10-23. GPIO Signal Descriptions
Chip signal name
PTA[31:0]
PTB[31:0]
PTE[31:0]
Module signal name
Description
PORTA31–PORTA0 General-purpose input/output
PORTB31–PORTB0 General-purpose input/output
PORTC31–PORTC0 General-purpose input/output
PORTD31–PORTD0 General-purpose input/output
PORTE31–PORTE0 General-purpose input/output
1. The available GPIO pins depend on the specific package. See the signal multiplexing section for which exact GPIO signals are available.
Chip signal name
TSI0_CH[15:0]
Table 10-24. TSI Signal Descriptions
Module signal name
TSI[15:0]
Description
TSI capacitive pins. Switches driver that connects directly to the electrode pins TSI[15:0] can operate as GPIO pins.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
O
I
I/O
O
I
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Chapter 11
Port control and interrupt (PORT)
The port control and interrupt (PORT) module provides support for port control, and external interrupt functions.
11.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
11.2 Overview
The Port Control and Interrupt (PORT) module provides support for port control, and external interrupt functions.
Most functions can be configured independently for each pin in the 32-bit port and affect the pin regardless of its pin muxing state.
There is one instance of the PORT module for each port. Not all pins within each port are implemented on a specific device.
11.2.1 Features
The PORT module has the following features:
• Pin interrupt on selected pins
• Interrupt flag and enable registers for each pin
• Support for edge sensitive (rising, falling, both) or level sensitive (low, high) configured per pin
• Support for interrupt or DMA request configured per pin
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External signal description
• Asynchronous wake-up in low-power modes
• Pin interrupt is functional in all digital pin muxing modes
• Port control
• Individual pull control fields with pullup, pulldown, and pull-disable support on selected pins
• Individual drive strength field supporting high and low drive strength on selected pins
• Individual slew rate field supporting fast and slow slew rates on selected pins
• Individual input passive filter field supporting enable and disable of the individual input passive filter on selected pins
• Individual mux control field supporting analog or pin disabled, GPIO, and up to six chip-specific digital functions
• Pad configuration fields are functional in all digital pin muxing modes.
11.2.2 Modes of operation
11.2.2.1 Run mode
In Run mode, the PORT operates normally.
11.2.2.2 Wait mode
In Wait mode, PORT continues to operate normally and may be configured to exit the
Low-Power mode if an enabled interrupt is detected. DMA requests are still generated during the Wait mode, but do not cause an exit from the Low-Power mode.
11.2.2.3 Stop mode
In Stop mode, the PORT can be configured to exit the Low-Power mode via an asynchronous wake-up signal if an enabled interrupt is detected.
11.2.2.4 Debug mode
In Debug mode, PORT operates normally.
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Chapter 11 Port control and interrupt (PORT)
11.3 External signal description
The table found here describes the PORT external signal.
Table 11-1. Signal properties
Name
PORTx[31:0]
Function
External interrupt
I/O
I/O
Reset
0
Pull
-
NOTE
Not all pins within each port are implemented on each device.
11.4 Detailed signal description
The table found here contains the detailed signal description for the PORT interface.
Signal
PORTx[31:0]
Table 11-2. PORT interface—detailed signal description
I/O Description
I/O External interrupt.
State meaning
Timing
Asserted—pin is logic 1.
Negated—pin is logic 0.
Assertion—may occur at any time and can assert asynchronously to the system clock.
Negation—may occur at any time and can assert asynchronously to the system clock.
11.5 Memory map and register definition
Any read or write access to the PORT memory space that is outside the valid memory map results in a bus error. All register accesses complete with zero wait states.
PORT memory map
Absolute address
(hex)
Register name
4004_9000 Pin Control Register n (PORTA_PCR0)
4004_9004 Pin Control Register n (PORTA_PCR1)
4004_9008 Pin Control Register n (PORTA_PCR2)
4004_900C Pin Control Register n (PORTA_PCR3)
4004_9010 Pin Control Register n (PORTA_PCR4)
Width
(in bits)
Table continues on the next page...
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32
Access Reset value
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Memory map and register definition
PORT memory map (continued)
Absolute address
(hex)
Register name
4004_9014 Pin Control Register n (PORTA_PCR5)
4004_9018 Pin Control Register n (PORTA_PCR6)
4004_901C Pin Control Register n (PORTA_PCR7)
4004_9020 Pin Control Register n (PORTA_PCR8)
4004_9024 Pin Control Register n (PORTA_PCR9)
4004_9028 Pin Control Register n (PORTA_PCR10)
4004_902C Pin Control Register n (PORTA_PCR11)
4004_9030 Pin Control Register n (PORTA_PCR12)
4004_9034 Pin Control Register n (PORTA_PCR13)
4004_9038 Pin Control Register n (PORTA_PCR14)
4004_903C Pin Control Register n (PORTA_PCR15)
4004_9040 Pin Control Register n (PORTA_PCR16)
4004_9044 Pin Control Register n (PORTA_PCR17)
4004_9048 Pin Control Register n (PORTA_PCR18)
4004_904C Pin Control Register n (PORTA_PCR19)
4004_9050 Pin Control Register n (PORTA_PCR20)
4004_9054 Pin Control Register n (PORTA_PCR21)
4004_9058 Pin Control Register n (PORTA_PCR22)
4004_905C Pin Control Register n (PORTA_PCR23)
4004_9060 Pin Control Register n (PORTA_PCR24)
4004_9064 Pin Control Register n (PORTA_PCR25)
4004_9068 Pin Control Register n (PORTA_PCR26)
4004_906C Pin Control Register n (PORTA_PCR27)
4004_9070 Pin Control Register n (PORTA_PCR28)
4004_9074 Pin Control Register n (PORTA_PCR29)
4004_9078 Pin Control Register n (PORTA_PCR30)
4004_907C Pin Control Register n (PORTA_PCR31)
Width
(in bits)
Access Reset value
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4004_9080 Global Pin Control Low Register (PORTA_GPCLR)
4004_9084 Global Pin Control High Register (PORTA_GPCHR)
32
32
4004_90A0 Interrupt Status Flag Register (PORTA_ISFR)
4004_A000 Pin Control Register n (PORTB_PCR0)
4004_A004 Pin Control Register n (PORTB_PCR1)
4004_A008 Pin Control Register n (PORTB_PCR2)
4004_A00C Pin Control Register n (PORTB_PCR3)
4004_A010 Pin Control Register n (PORTB_PCR4)
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32
32
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Chapter 11 Port control and interrupt (PORT)
PORT memory map (continued)
Absolute address
(hex)
Register name
4004_A014 Pin Control Register n (PORTB_PCR5)
4004_A018 Pin Control Register n (PORTB_PCR6)
4004_A01C Pin Control Register n (PORTB_PCR7)
4004_A020 Pin Control Register n (PORTB_PCR8)
4004_A024 Pin Control Register n (PORTB_PCR9)
4004_A028 Pin Control Register n (PORTB_PCR10)
4004_A02C Pin Control Register n (PORTB_PCR11)
4004_A030 Pin Control Register n (PORTB_PCR12)
4004_A034 Pin Control Register n (PORTB_PCR13)
4004_A038 Pin Control Register n (PORTB_PCR14)
4004_A03C Pin Control Register n (PORTB_PCR15)
4004_A040 Pin Control Register n (PORTB_PCR16)
4004_A044 Pin Control Register n (PORTB_PCR17)
4004_A048 Pin Control Register n (PORTB_PCR18)
4004_A04C Pin Control Register n (PORTB_PCR19)
4004_A050 Pin Control Register n (PORTB_PCR20)
4004_A054 Pin Control Register n (PORTB_PCR21)
4004_A058 Pin Control Register n (PORTB_PCR22)
4004_A05C Pin Control Register n (PORTB_PCR23)
4004_A060 Pin Control Register n (PORTB_PCR24)
4004_A064 Pin Control Register n (PORTB_PCR25)
4004_A068 Pin Control Register n (PORTB_PCR26)
4004_A06C Pin Control Register n (PORTB_PCR27)
4004_A070 Pin Control Register n (PORTB_PCR28)
4004_A074 Pin Control Register n (PORTB_PCR29)
4004_A078 Pin Control Register n (PORTB_PCR30)
4004_A07C Pin Control Register n (PORTB_PCR31)
4004_A080 Global Pin Control Low Register (PORTB_GPCLR)
4004_A084 Global Pin Control High Register (PORTB_GPCHR)
Width
(in bits)
Access Reset value
4004_A0A0 Interrupt Status Flag Register (PORTB_ISFR)
4004_B000 Pin Control Register n (PORTC_PCR0)
4004_B004 Pin Control Register n (PORTC_PCR1)
4004_B008 Pin Control Register n (PORTC_PCR2)
4004_B00C Pin Control Register n (PORTC_PCR3)
4004_B010 Pin Control Register n (PORTC_PCR4)
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Memory map and register definition
PORT memory map (continued)
Absolute address
(hex)
Register name
4004_B014 Pin Control Register n (PORTC_PCR5)
4004_B018 Pin Control Register n (PORTC_PCR6)
4004_B01C Pin Control Register n (PORTC_PCR7)
4004_B020 Pin Control Register n (PORTC_PCR8)
4004_B024 Pin Control Register n (PORTC_PCR9)
4004_B028 Pin Control Register n (PORTC_PCR10)
4004_B02C Pin Control Register n (PORTC_PCR11)
4004_B030 Pin Control Register n (PORTC_PCR12)
4004_B034 Pin Control Register n (PORTC_PCR13)
4004_B038 Pin Control Register n (PORTC_PCR14)
4004_B03C Pin Control Register n (PORTC_PCR15)
4004_B040 Pin Control Register n (PORTC_PCR16)
4004_B044 Pin Control Register n (PORTC_PCR17)
4004_B048 Pin Control Register n (PORTC_PCR18)
4004_B04C Pin Control Register n (PORTC_PCR19)
4004_B050 Pin Control Register n (PORTC_PCR20)
4004_B054 Pin Control Register n (PORTC_PCR21)
4004_B058 Pin Control Register n (PORTC_PCR22)
4004_B05C Pin Control Register n (PORTC_PCR23)
4004_B060 Pin Control Register n (PORTC_PCR24)
4004_B064 Pin Control Register n (PORTC_PCR25)
4004_B068 Pin Control Register n (PORTC_PCR26)
4004_B06C Pin Control Register n (PORTC_PCR27)
4004_B070 Pin Control Register n (PORTC_PCR28)
4004_B074 Pin Control Register n (PORTC_PCR29)
4004_B078 Pin Control Register n (PORTC_PCR30)
4004_B07C Pin Control Register n (PORTC_PCR31)
Width
(in bits)
Access Reset value
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4004_B080 Global Pin Control Low Register (PORTC_GPCLR)
4004_B084 Global Pin Control High Register (PORTC_GPCHR)
32
32
4004_B0A0 Interrupt Status Flag Register (PORTC_ISFR)
4004_C000 Pin Control Register n (PORTD_PCR0)
4004_C004 Pin Control Register n (PORTD_PCR1)
4004_C008 Pin Control Register n (PORTD_PCR2)
4004_C00C Pin Control Register n (PORTD_PCR3)
4004_C010 Pin Control Register n (PORTD_PCR4)
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Chapter 11 Port control and interrupt (PORT)
PORT memory map (continued)
Absolute address
(hex)
Register name
4004_C014 Pin Control Register n (PORTD_PCR5)
4004_C018 Pin Control Register n (PORTD_PCR6)
4004_C01C Pin Control Register n (PORTD_PCR7)
4004_C020 Pin Control Register n (PORTD_PCR8)
4004_C024 Pin Control Register n (PORTD_PCR9)
4004_C028 Pin Control Register n (PORTD_PCR10)
4004_C02C Pin Control Register n (PORTD_PCR11)
4004_C030 Pin Control Register n (PORTD_PCR12)
4004_C034 Pin Control Register n (PORTD_PCR13)
4004_C038 Pin Control Register n (PORTD_PCR14)
4004_C03C Pin Control Register n (PORTD_PCR15)
4004_C040 Pin Control Register n (PORTD_PCR16)
4004_C044 Pin Control Register n (PORTD_PCR17)
4004_C048 Pin Control Register n (PORTD_PCR18)
4004_C04C Pin Control Register n (PORTD_PCR19)
4004_C050 Pin Control Register n (PORTD_PCR20)
4004_C054 Pin Control Register n (PORTD_PCR21)
4004_C058 Pin Control Register n (PORTD_PCR22)
4004_C05C Pin Control Register n (PORTD_PCR23)
4004_C060 Pin Control Register n (PORTD_PCR24)
4004_C064 Pin Control Register n (PORTD_PCR25)
4004_C068 Pin Control Register n (PORTD_PCR26)
4004_C06C Pin Control Register n (PORTD_PCR27)
4004_C070 Pin Control Register n (PORTD_PCR28)
4004_C074 Pin Control Register n (PORTD_PCR29)
4004_C078 Pin Control Register n (PORTD_PCR30)
4004_C07C Pin Control Register n (PORTD_PCR31)
4004_C080 Global Pin Control Low Register (PORTD_GPCLR)
4004_C084 Global Pin Control High Register (PORTD_GPCHR)
Width
(in bits)
Access Reset value
4004_C0A0 Interrupt Status Flag Register (PORTD_ISFR)
4004_D000 Pin Control Register n (PORTE_PCR0)
4004_D004 Pin Control Register n (PORTE_PCR1)
4004_D008 Pin Control Register n (PORTE_PCR2)
4004_D00C Pin Control Register n (PORTE_PCR3)
4004_D010 Pin Control Register n (PORTE_PCR4)
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Memory map and register definition
PORT memory map (continued)
Absolute address
(hex)
Register name
4004_D014 Pin Control Register n (PORTE_PCR5)
4004_D018 Pin Control Register n (PORTE_PCR6)
4004_D01C Pin Control Register n (PORTE_PCR7)
4004_D020 Pin Control Register n (PORTE_PCR8)
4004_D024 Pin Control Register n (PORTE_PCR9)
4004_D028 Pin Control Register n (PORTE_PCR10)
4004_D02C Pin Control Register n (PORTE_PCR11)
4004_D030 Pin Control Register n (PORTE_PCR12)
4004_D034 Pin Control Register n (PORTE_PCR13)
4004_D038 Pin Control Register n (PORTE_PCR14)
4004_D03C Pin Control Register n (PORTE_PCR15)
4004_D040 Pin Control Register n (PORTE_PCR16)
4004_D044 Pin Control Register n (PORTE_PCR17)
4004_D048 Pin Control Register n (PORTE_PCR18)
4004_D04C Pin Control Register n (PORTE_PCR19)
4004_D050 Pin Control Register n (PORTE_PCR20)
4004_D054 Pin Control Register n (PORTE_PCR21)
4004_D058 Pin Control Register n (PORTE_PCR22)
4004_D05C Pin Control Register n (PORTE_PCR23)
4004_D060 Pin Control Register n (PORTE_PCR24)
4004_D064 Pin Control Register n (PORTE_PCR25)
4004_D068 Pin Control Register n (PORTE_PCR26)
4004_D06C Pin Control Register n (PORTE_PCR27)
4004_D070 Pin Control Register n (PORTE_PCR28)
4004_D074 Pin Control Register n (PORTE_PCR29)
4004_D078 Pin Control Register n (PORTE_PCR30)
4004_D07C Pin Control Register n (PORTE_PCR31)
Width
(in bits)
Access Reset value
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4004_D080 Global Pin Control Low Register (PORTE_GPCLR)
4004_D084 Global Pin Control High Register (PORTE_GPCHR)
4004_D0A0 Interrupt Status Flag Register (PORTE_ISFR)
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Chapter 11 Port control and interrupt (PORT)
11.5.1 Pin Control Register n (PORTx_PCRn)
NOTE
See the Signal Multiplexing and Pin Assignment chapter for the reset value of this device.
See the GPIO Configuration section for details on the available functions for each pin.
Do not modify pin configuration registers associated with pins not available in your selected package. All unbonded pins not available in your package will default to DISABLE state for lowest power consumption.
Address: Base address + 0h offset + (4d × i), where i=0d to 31d
Bit
R
31 30 29 28
27 26 25
W
Reset 0 0 0 0 0 0 0
24
0
23 22
21 20 19 18
17
0 0 0 0 0 0 0
Bit
R
15 14 13
12 11 10 9 8 7
6 5
4 3
2 1
W
Reset 0 0 0 0 0
0
0
0
•
•
•
•
•
* Notes:
• MUX field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.
DSE field: Varies by port. See the Signal Multiplexing and Signal Descriptions chapter for reset values per port.
PFE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.
SRE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.
PE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.
PS field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port.
16
0
0
Field
31–25
Reserved
24
ISF
PORTx_PCRn field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Interrupt Status Flag
This field is read-only for pins that do not support interrupt generation.
The pin interrupt configuration is valid in all digital pin muxing modes.
Table continues on the next page...
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Memory map and register definition
PORTx_PCRn field descriptions (continued)
Field
23–20
Reserved
19–16
IRQC
Description
0 Configured interrupt is not detected.
1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer.
Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
This field is reserved.
This read-only field is reserved and always has the value 0.
Interrupt Configuration
This field is read-only for pins that do not support interrupt generation.
The pin interrupt configuration is valid in all digital pin muxing modes. The corresponding pin is configured to generate interrupt/DMA request as follows:
15–11
Reserved
10–8
MUX
0000 Interrupt/DMA request disabled.
0001 DMA request on rising edge.
0010 DMA request on falling edge.
0011 DMA request on either edge.
1000 Interrupt when logic 0.
1001 Interrupt on rising-edge.
1010 Interrupt on falling-edge.
1011 Interrupt on either edge.
1100 Interrupt when logic 1.
Others Reserved.
This field is reserved.
This read-only field is reserved and always has the value 0.
Pin Mux Control
Not all pins support all pin muxing slots. Unimplemented pin muxing slots are reserved and may result in configuring the pin for a different pin muxing slot.
The corresponding pin is configured in the following pin muxing slot as follows:
7
Reserved
6
DSE
000 Pin disabled (analog).
001 Alternative 1 (GPIO).
010 Alternative 2 (chip-specific).
011 Alternative 3 (chip-specific).
100 Alternative 4 (chip-specific).
101 Alternative 5 (chip-specific).
110 Alternative 6 (chip-specific).
111 Alternative 7 (chip-specific).
This field is reserved.
This read-only field is reserved and always has the value 0.
Drive Strength Enable
This field is read-only for pins that do not support a configurable drive strength.
Drive strength configuration is valid in all digital pin muxing modes.
0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
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Field
5
Reserved
4
PFE
3
Reserved
2
SRE
1
PE
0
PS
Chapter 11 Port control and interrupt (PORT)
PORTx_PCRn field descriptions (continued)
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Passive Filter Enable
This field is read-only for pins that do not support a configurable passive input filter.
Passive filter configuration is valid in all digital pin muxing modes.
0 Passive input filter is disabled on the corresponding pin.
1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
This field is reserved.
This read-only field is reserved and always has the value 0.
Slew Rate Enable
This field is read-only for pins that do not support a configurable slew rate.
Slew rate configuration is valid in all digital pin muxing modes.
0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
Pull Enable
This field is read-only for pins that do not support a configurable pull resistor. Refer to the Chapter of
Signal Multiplexing and Signal Descriptions for the pins that support a configurable pull resistor.
Pull configuration is valid in all digital pin muxing modes.
0 Internal pullup or pulldown resistor is not enabled on the corresponding pin.
1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
Pull Select
This bit is read only for pins that do not support a configurable pull resistor direction.
Pull configuration is valid in all digital pin muxing modes.
0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)
Only 32-bit writes are supported to this register.
Address: Base address + 80h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Memory map and register definition
Field
31–16
GPWE
PORTx_GPCLR field descriptions
Description
Global Pin Write Enable
Selects which Pin Control Registers (15 through 0) bits [15:0] update with the value in GPWD.
15–0
GPWD
0 Corresponding Pin Control Register is not updated with the value in GPWD.
1 Corresponding Pin Control Register is updated with the value in GPWD.
Global Pin Write Data
Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE.
11.5.3 Global Pin Control High Register (PORTx_GPCHR)
Only 32-bit writes are supported to this register.
Address: Base address + 84h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–16
GPWE
PORTx_GPCHR field descriptions
Description
Global Pin Write Enable
Selects which Pin Control Registers (31 through 16) bits [15:0] update with the value in GPWD.
15–0
GPWD
0 Corresponding Pin Control Register is not updated with the value in GPWD.
1 Corresponding Pin Control Register is updated with the value in GPWD.
Global Pin Write Data
Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE.
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)
The corresponding bit is read only for pins that do not support interrupt generation.
The pin interrupt configuration is valid in all digital pin muxing modes. The Interrupt
Status Flag for each pin is also visible in the corresponding Pin Control Register, and each flag can be cleared in either location.
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Chapter 11 Port control and interrupt (PORT)
Address: Base address + A0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
ISF
PORTx_ISFR field descriptions
Description
Interrupt Status Flag
Each bit in the field indicates the detection of the configured interrupt of the same number as the field.
0 Configured interrupt is not detected.
1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer.
Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
11.6 Functional description
11.6.1 Pin control
Each port pin has a corresponding Pin Control register, PORT_PCRn, associated with it.
The upper half of the Pin Control register configures the pin's capability to either interrupt the CPU or request a DMA transfer, on a rising/falling edge or both edges as well as a logic level occurring on the port pin. It also includes a flag to indicate that an interrupt has occurred.
The lower half of the Pin Control register configures the following functions for each pin within the 32-bit port.
• Pullup or pulldown enable on selected pins
• Drive strength and slew rate configuration on selected pins
• Passive input filter enable on selected pins
• Pin Muxing mode
The functions apply across all digital pin muxing modes and individual peripherals do not override the configuration in the Pin Control register. For example, if an I 2 C function is enabled on a pin, that does not override the pullup configuration for that pin.
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Functional description
When the Pin Muxing mode is configured for analog or is disabled, all the digital functions on that pin are disabled. This includes the pullup and pulldown enables, and passive filter enable.
The configuration of each Pin Control register is retained when the PORT module is disabled.
11.6.2 Global pin control
The two global pin control registers allow a single register write to update the lower half of the pin control register on up to 16 pins, all with the same value.
The global pin control registers are designed to enable software to quickly configure multiple pins within the one port for the same peripheral function. However, the interrupt functions cannot be configured using the global pin control registers.
The global pin control registers are write-only registers, that always read as 0.
11.6.3 External interrupts
The external interrupt capability of the PORT module is available in all digital pin muxing modes provided the PORT module is enabled.
Each pin can be individually configured for any of the following external interrupt modes:
• Interrupt disabled, default out of reset
• Active high level sensitive interrupt
• Active low level sensitive interrupt
• Rising edge sensitive interrupt
• Falling edge sensitive interrupt
• Rising and falling edge sensitive interrupt
• Rising edge sensitive DMA request
• Falling edge sensitive DMA request
• Rising and falling edge sensitive DMA request
The interrupt status flag is set when the configured edge or level is detected on the pin .
When not in Stop mode, the input is first synchronized to the bus clock to detect the configured level or edge transition.
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Chapter 11 Port control and interrupt (PORT)
The PORT module generates a single interrupt that asserts when the interrupt status flag is set for any enabled interrupt for that port. The interrupt negates after the interrupt status flags for all enabled interrupts have been cleared by writing a logic 1 to the ISF flag in either the PORT_ISFR or PORT_PCRn registers.
The PORT module generates a single DMA request that asserts when the interrupt status flag is set for any enabled DMA request in that port. The DMA request negates after the
DMA transfer is completed, because that clears the interrupt status flags for all enabled
DMA requests.
During Stop mode, the interrupt status flag for any enabled interrupt is asynchronously set if the required level or edge is detected. This also generates an asynchronous wake-up signal to exit the Low-Power mode.
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Functional description
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Chapter 12
System Integration Module (SIM)
The System Integration Module (SIM) provides system control and chip configuration registers. This module contains several fields for selecting the clock source and dividers for various module clocks.
12.1 Introduction
The system integration module (SIM) provides system control and chip configuration registers.
12.1.1 Features
• System clocking configuration
• System clock divide values
• Architectural clock gating control
• ERCLK32K clock selection
• USB clock selection
• UART0 and TPM clock selection
• Flash and System RAM size configuration
• USB regulator configuration
• TPM external clock and input capture selection
• UART receive/transmit source selection/configuration
12.2 Memory map and register definition
The SIM module contains many bitfields for selecting the clock source and dividers for various module clocks.
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Memory map and register definition
NOTE
The SIM registers can be written only in supervisor mode. In user mode, write accesses are blocked and will result in a bus error.
NOTE
The SIM_SOPT1 and SIM_SOPT1CFG registers are located at a different base address than the other SIM registers.
SIM memory map
Absolute address
(hex)
Register name
4004_7000 System Options Register 1 (SIM_SOPT1)
4004_7004 SOPT1 Configuration Register (SIM_SOPT1CFG)
4004_8004 System Options Register 2 (SIM_SOPT2)
4004_800C System Options Register 4 (SIM_SOPT4)
4004_8010 System Options Register 5 (SIM_SOPT5)
4004_8018 System Options Register 7 (SIM_SOPT7)
4004_8024 System Device Identification Register (SIM_SDID)
4004_8034 System Clock Gating Control Register 4 (SIM_SCGC4)
4004_8038 System Clock Gating Control Register 5 (SIM_SCGC5)
4004_803C System Clock Gating Control Register 6 (SIM_SCGC6)
4004_8040 System Clock Gating Control Register 7 (SIM_SCGC7)
4004_8044 System Clock Divider Register 1 (SIM_CLKDIV1)
4004_804C Flash Configuration Register 1 (SIM_FCFG1)
4004_8050 Flash Configuration Register 2 (SIM_FCFG2)
4004_8058 Unique Identification Register Mid-High (SIM_UIDMH)
4004_805C Unique Identification Register Mid Low (SIM_UIDML)
4004_8060 Unique Identification Register Low (SIM_UIDL)
4004_8100 COP Control Register (SIM_COPC)
4004_8104 Service COP (SIM_SRVCOP)
Width
(in bits)
Access Reset value
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Section/ page
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
F000_0030h
0000_0182h
0000_0001h
0000_0100h
R
R
R
R
R/W 0000_000Ch
W 0000_0000h
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Chapter 12 System Integration Module (SIM)
12.2.1 System Options Register 1 (SIM_SOPT1)
NOTE
The SOPT1 register is only reset on POR or LVD.
Address: 4004_7000h base + 0h offset = 4004_7000h
Bit 31 30 29 28 27 26 25
R
24
23 22 21 20 19 18
17
16
W
Reset
Bit
R
1
15
0
14
0
13
0
12
W
Reset 0 0 0 0
* Notes:
• Reserved field: Device specific value.
0
0
11
0
10
0
0
9
0
0
8
0
0
7
0
0
6
0
0
5
0
4
0
3
0
2
0
1
0
0
Field
31
USBREGEN
30
USBSSTBY
29
USBVSTBY
28–20
Reserved
SIM_SOPT1 field descriptions
Description
USB voltage regulator enable
Controls whether the USB voltage regulator is enabled.
0 USB voltage regulator is disabled.
1 USB voltage regulator is enabled.
USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes.
Controls whether the USB voltage regulator is placed in standby mode during Stop, VLPS, LLS and VLLS modes.
0 USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes.
1 USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
USB voltage regulator in standby mode during VLPR and VLPW modes
Controls whether the USB voltage regulator is placed in standby mode during VLPR and VLPW modes.
0 USB voltage regulator not in standby during VLPR and VLPW modes.
1 USB voltage regulator in standby during VLPR and VLPW modes.
This field is reserved.
This read-only field is reserved and always has the value 0.
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Memory map and register definition
SIM_SOPT1 field descriptions (continued)
Field
19–18
OSC32KSEL
Description
32K Oscillator Clock Select
Selects the 32 kHz clock source (ERCLK32K) for RTC and LPTMR. This field is reset only on POR/LVD.
17–16
Reserved
15–6
Reserved
5–0
Reserved
00 System oscillator (OSC32KCLK)
01 Reserved
10 RTC_CLKIN
11 LPO 1kHz
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)
NOTE
The SOPT1CFG register is reset on System Reset not VLLS.
Address: 4004_7000h base + 4h offset = 4004_7004h
Bit 31 30 29 28 27 26 25
R
24 23 22 21 20
19 18
W
Reset
Bit
R
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
W
Reset 0
Field
31–27
Reserved
26
USSWE
0 0 0 0 0 0 0 0 0 0
SIM_SOPT1CFG field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
USB voltage regulator stop standby write enable
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0
4
0
0
3
0 0
0
2
17
0
0
1
16
0
0
0
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Field
25
UVSWE
24
URWE
23–0
Reserved
Chapter 12 System Integration Module (SIM)
SIM_SOPT1CFG field descriptions (continued)
Description
Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written. This register bit clears after a write to USBSSTBY.
0 SOPT1 USBSSTB cannot be written.
1 SOPT1 USBSSTB can be written.
USB voltage regulator VLP standby write enable
Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written. This register bit clears after a write to USBVSTBY.
0 SOPT1 USBVSTB cannot be written.
1 SOPT1 USBVSTB can be written.
USB voltage regulator enable write enable
Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This register bit clears after a write to USBREGEN.
0 SOPT1 USBREGEN cannot be written.
1 SOPT1 USBREGEN can be written.
This field is reserved.
This read-only field is reserved and always has the value 0.
12.2.3 System Options Register 2 (SIM_SOPT2)
SOPT2 contains the controls for selecting many of the module clock source options on this device. See the Clock Distribution chapter for more information including clocking diagrams and definitions of device clocks.
Address: 4004_7000h base + 1004h offset = 4004_8004h
Bit 31 30 29 28 27 26 25
R
24
W
23
22 21 20
19 18 17
16
Reset
Bit
R
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Memory map and register definition
Field
31–30
Reserved
29–28
Reserved
27–26
UART0SRC
SIM_SOPT2 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
UART0 Clock Source Select
Selects the clock source for the UART0 transmit and receive clock.
25–24
TPMSRC
00 Clock disabled
01 MCGFLLCLK clock, or MCGPLLCLK/2
10 OSCERCLK clock
11 MCGIRCLK clock
TPM Clock Source Select
23–22
Reserved
21–19
Reserved
18
USBSRC
Selects the clock source for the TPM counter clock
00 Clock disabled
01 MCGFLLCLK clock, or MCGPLLCLK/2
10 OSCERCLK clock
11 MCGIRCLK clock
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
USB clock source select
17
Reserved
16
PLLFLLSEL
Selects the clock source for the USB 48 MHz clock.
0 External bypass clock (USB_CLKIN).
1 MCGFLLCLK clock, or MCGPLLCLK/2 clock
This field is reserved.
This read-only field is reserved and always has the value 0.
PLL/FLL clock select
Selects the MCGPLLCLK or MCGFLLCLK clock for various peripheral clocking options.
15–8
Reserved
7–5
CLKOUTSEL
0 MCGFLLCLK clock
1 MCGPLLCLK clock with fixed divide by 2
This field is reserved.
This read-only field is reserved and always has the value 0.
CLKOUT select
Selects the clock to output on the CLKOUT pin.
000 Reserved
001 Reserved
010 Bus clock
011 LPO clock (1 kHz)
100 MCGIRCLK
101 Reserved
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Chapter 12 System Integration Module (SIM)
SIM_SOPT2 field descriptions (continued)
Field Description
4
RTCCLKOUTSEL
110 OSCERCLK
111 Reserved
RTC Clock Out Select
Selects either the RTC 1 Hz clock or the OSC clock to be output on the RTC_CLKOUT pin.
3–0
Reserved
0 RTC 1 Hz clock is output on the RTC_CLKOUT pin.
1 OSCERCLK clock is output on the RTC_CLKOUT pin.
This field is reserved.
This read-only field is reserved and always has the value 0.
12.2.4 System Options Register 4 (SIM_SOPT4)
Address: 4004_7000h base + 100Ch offset = 4004_800Ch
Bit 31 30 29 28 27 26 25
R
24 23 22
21 20 19 18 17
16
W
Reset
Bit
R
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
W
Reset 0
Field
31–27
Reserved
26
TPM2CLKSEL
0 0 0 0 0 0 0 0 0
SIM_SOPT4 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
TPM2 External Clock Pin Select
0 0 0 0 0
Selects the external pin used to drive the clock to the TPM2 module.
NOTE: The selected pin must also be configured for the TPM external clock function through the appropriate Pin Control Register in the Port Control module.
25
TPM1CLKSEL
0 TPM2 external clock driven by TPM_CLKIN0 pin.
1 TPM2 external clock driven by TPM_CLKIN1 pin.
TPM1 External Clock Pin Select
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Memory map and register definition
SIM_SOPT4 field descriptions (continued)
Field Description
Selects the external pin used to drive the clock to the TPM1 module.
NOTE: The selected pin must also be configured for the TPM external clock function through the appropriate pin control register in the port control module.
24
TPM0CLKSEL
0 TPM1 external clock driven by TPM_CLKIN0 pin.
1 TPM1 external clock driven by TPM_CLKIN1 pin.
TPM0 External Clock Pin Select
Selects the external pin used to drive the clock to the TPM0 module.
NOTE: The selected pin must also be configured for the TPM external clock function through the appropriate pin control register in the port control module.
23–21
Reserved
20
TPM2CH0SRC
0 TPM0 external clock driven by TPM_CLKIN0 pin.
1 TPM0 external clock driven by TPM_CLKIN1 pin.
This field is reserved.
This read-only field is reserved and always has the value 0.
TPM2 Channel 0 Input Capture Source Select
Selects the source for TPM2 channel 0 input capture.
NOTE: When TPM2 is not in input capture mode, clear this field.
19–18
TPM1CH0SRC
0 TPM2_CH0 signal
1 CMP0 output
TPM1 channel 0 input capture source select
Selects the source for TPM1 channel 0 input capture.
NOTE: When TPM1 is not in input capture mode, clear this field.
17–0
Reserved
00 TPM1_CH0 signal
01 CMP0 output
10 Reserved
11 USB start of frame pulse
This field is reserved.
This read-only field is reserved and always has the value 0.
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12.2.5 System Options Register 5 (SIM_SOPT5)
Address: 4004_7000h base + 1010h offset = 4004_8010h
Bit 31 30 29 28 27 26 25
R
24 23 22 21 20 19
18 17 16
W
Reset
Bit
R
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
W
Reset 0 0 0 0 0 0 0 0 0 0
Field
31–20
Reserved
19
Reserved
18
UART2ODE
SIM_SOPT5 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
UART2 Open Drain Enable
0 Open drain is disabled on UART2
1 Open drain is enabled on UART2
UART1 Open Drain Enable 17
UART1ODE
0 Open drain is disabled on UART1.
1 Open drain is enabled on UART1
UART0 Open Drain Enable 16
UART0ODE
15–7
Reserved
6
UART1RXSRC
0 Open drain is disabled on UART0.
1 Open drain is enabled on UART0.
This field is reserved.
This read-only field is reserved and always has the value 0.
UART1 Receive Data Source Select
Selects the source for the UART1 receive data.
0
5–4
UART1TXSRC
0 UART1_RX pin
1 CMP0 output
UART1 Transmit Data Source Select
Selects the source for the UART1 transmit data.
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0 0
0
1
0
0
0 0
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Memory map and register definition
SIM_SOPT5 field descriptions (continued)
Field
3
Reserved
2
UART0RXSRC
Description
00 UART1_TX pin
01 UART1_TX pin modulated with TPM1 channel 0 output
10 UART1_TX pin modulated with TPM2 channel 0 output
11 Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
UART0 Receive Data Source Select
Selects the source for the UART0 receive data.
1–0
UART0TXSRC
0 UART_RX pin
1 CMP0 output
UART0 Transmit Data Source Select
Selects the source for the UART0 transmit data.
00 UART0_TX pin
01 UART0_TX pin modulated with TPM1 channel 0 output
10 UART0_TX pin modulated with TPM2 channel 0 output
11 Reserved
12.2.6 System Options Register 7 (SIM_SOPT7)
Address: 4004_7000h base + 1018h offset = 4004_8018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20
R
19 18 17 16
W
Reset
Bit
R
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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SIM_SOPT7 field descriptions
Field
31–8
Reserved
7
ADC0ALTTRGEN
This field is reserved.
This read-only field is reserved and always has the value 0.
ADC0 Alternate Trigger Enable
Description
Enables alternative conversion triggers for ADC0.
6–5
Reserved
4
ADC0PRETRGSEL
0 TPM1 channel 0 (A) and channel 1 (B) triggers selected for ADC0.
1 Alternate trigger selected for ADC0.
This field is reserved.
This read-only field is reserved and always has the value 0.
ADC0 Pretrigger Select
Selects the ADC0 pre-trigger source when alternative triggers are enabled through ADC0ALTTRGEN.
3–0
ADC0TRGSEL
0 Pre-trigger A
1 Pre-trigger B
ADC0 Trigger Select
Selects the ADC0 trigger source when alternative triggers are functional in stop and VLPS modes.
0000 External trigger pin input (EXTRG_IN)
0001 CMP0 output
0010 Reserved
0011 Reserved
0100 PIT trigger 0
0101 PIT trigger 1
0110 Reserved
0111 Reserved
1000 TPM0 overflow
1001 TPM1 overflow
1010 TPM2 overflow
1011 Reserved
1100 RTC alarm
1101 RTC seconds
1110 LPTMR0 trigger
1111 Reserved
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Memory map and register definition
12.2.7 System Device Identification Register (SIM_SDID)
Address: 4004_7000h base + 1024h offset = 4004_8024h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FAMID SUBFAMID SERIESID SRAMSIZE
W
Reset
0 0 0 0
0 0 0 0 0 0 0 0
•
•
•
•
•
* Notes:
FAMID field: Device specific value.
SUBFAMID field: Device specific value.
SRAMSIZE field: Device specific value.
REVID field: Device specific value.
PINID field: Device specific value.
Field
31–28
FAMID
27–24
SUBFAMID
23–20
SERIESID
19–16
SRAMSIZE
SIM_SDID field descriptions
Description
Kinetis family ID
Specifies the Kinetis family of the device.
0000 KL0x Family (low end)
0001 KL1x Family (basic)
0010 KL2x Family (USB)
0011 KL3x Family (Segment LCD)
0100 KL4x Family (USB and Segment LCD)
Kinetis Sub-Family ID
Specifies the Kinetis sub-family of the device.
0010 KLx2 Subfamily
0011 KLx3 Subfamily
0100 KLx4 Subfamily
0101 KLx5 Subfamily
0110 KLx6 Subfamily
0111 KLx7 Subfamily
Kinetis Series ID
Specifies the Kinetis family of the device.
0001 KL family
System SRAM Size
Specifies the size of the System SRAM
0000 0.5 KB
0001 1 KB
0010 2 KB
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Field
15–12
REVID
11–7
DIEID
6–4
Reserved
3–0
PINID
Chapter 12 System Integration Module (SIM)
SIM_SDID field descriptions (continued)
Description
0011 4 KB
0100 8 KB
0101 16 KB
0110 32 KB
0111 64 KB
Device Revision Number
Specifies the silicon implementation number for the device.
Device Die Number
Specifies the silicon implementation number for the device.
This field is reserved.
This read-only field is reserved and always has the value 0.
Pincount Identification
Specifies the pincount of the device.
0000 16-pin
0001 24-pin
0010 32-pin
0011 36-pin
0100 48-pin
0101 64-pin
0110 80-pin
0111 Reserved
1000 100-pin
1001 Reserved
1010 Reserved
1011 Custom pinout (WLCSP)
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
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Memory map and register definition
12.2.8 System Clock Gating Control Register 4 (SIM_SCGC4)
Address: 4004_7000h base + 1034h offset = 4004_8034h
Bit 31 30 29 28 27 26 25
R
24 23 22 21
20
19 18 17
W
16
Reset
Bit
R
1
15
1
14
1
13
1
12
0
11
0
10
0
9
0
8
0
7
0
6
W
Reset 0
Field
31–28
Reserved
27–24
Reserved
23
SPI1
22
SPI0
21
Reserved
20
Reserved
19
CMP
18
USBOTG
0 0 0 0 0 0 0 0 0
SIM_SCGC4 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 1.
This field is reserved.
This read-only field is reserved and always has the value 0.
SPI1 Clock Gate Control
1
Controls the clock gate to the SPI1 module.
0 Clock disabled
1 Clock enabled
SPI0 Clock Gate Control
Controls the clock gate to the SPI0 module.
0 Clock disabled
1 Clock enabled
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
Comparator Clock Gate Control
Controls the clock gate to the comparator module.
0 Clock disabled
1 Clock enabled
USB Clock Gate Control
0
5
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0
4
1
0
3
0
0
2
0
0
1
0 0
0
0
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Field
17–14
Reserved
13
Reserved
12
UART2
11
UART1
10
UART0
9
Reserved
8
Reserved
7
I2C1
6
I2C0
5–4
Reserved
3–0
Reserved
Chapter 12 System Integration Module (SIM)
SIM_SCGC4 field descriptions (continued)
Description
This bit controls the clock gate to the USB module.
0 Clock disabled
1 Clock enabled
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
UART2 Clock Gate Control
Controls the clock gate to the UART2 module.
0 Clock disabled
1 Clock enabled
UART1 Clock Gate Control
Controls the clock gate to the UART1 module.
0 Clock disabled
1 Clock enabled
UART0 Clock Gate Control
Controls the clock gate to the UART0 module.
0 Clock disabled
1 Clock enabled
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
I2C1 Clock Gate Control
Controls the clock gate to the I 2 C1 module.
0 Clock disabled
1 Clock enabled
I2C0 Clock Gate Control
Controls the clock gate to the I 2 C0 module.
0 Clock disabled
1 Clock enabled
This field is reserved.
This read-only field is reserved and always has the value 1.
This field is reserved.
This read-only field is reserved and always has the value 0.
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Memory map and register definition
12.2.9 System Clock Gating Control Register 5 (SIM_SCGC5)
Address: 4004_7000h base + 1038h offset = 4004_8038h
Bit 31 30 29 28 27 26 25
R
24 23 22 21
20
19
18 17
16
W
Reset
Bit
R
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
W
Reset 0
Field
31
Reserved
30–22
Reserved
21
Reserved
20
Reserved
19
Reserved
18–14
Reserved
13
PORTE
12
PORTD
11
PORTC
0 0 0 0 0 0 1 1 0
SIM_SCGC5 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
Port E Clock Gate Control
0
Controls the clock gate to the Port E module.
0 Clock disabled
1 Clock enabled
Port D Clock Gate Control
Controls the clock gate to the Port D module.
0 Clock disabled
1 Clock enabled
Port C Clock Gate Control
Controls the clock gate to the Port C module.
Table continues on the next page...
0
4
0
0
3
0
0
2
0
0
1
1
0
0
0
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Field
10
PORTB
9
PORTA
8–7
Reserved
6
Reserved
5
TSI
4–2
Reserved
1
Reserved
0
LPTMR
Chapter 12 System Integration Module (SIM)
SIM_SCGC5 field descriptions (continued)
Description
0 Clock disabled
1 Clock enabled
Port B Clock Gate Control
Controls the clock gate to the Port B module.
0 Clock disabled
1 Clock enabled
Port A Clock Gate Control
Controls the clock gate to the Port A module.
0 Clock disabled
1 Clock enabled
This field is reserved.
This read-only field is reserved and always has the value 1.
This field is reserved.
This read-only field is reserved and always has the value 0.
TSI Access Control
Controls software access to the TSI module.
0 Access disabled
1 Access enabled
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 1.
Low Power Timer Access Control
Controls software access to the Low Power Timer module.
0 Access disabled
1 Access enabled
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Memory map and register definition
12.2.10 System Clock Gating Control Register 6 (SIM_SCGC6)
Address: 4004_7000h base + 103Ch offset = 4004_803Ch
Bit 31 30 29 28 27 26 25
R
W
24 23
22 21
20 19 18
17
16
Reset
Bit
R
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
W
Reset 0
Field
31
DAC0
30
Reserved
29
RTC
28
Reserved
27
ADC0
26
TPM2
0 0 0 0 0 0 0 0 0
SIM_SCGC6 field descriptions
Description
DAC0 Clock Gate Control
0
This bit controls the clock gate to the DAC0 module.
0 Clock disabled
1 Clock enabled
This field is reserved.
This read-only field is reserved and always has the value 0.
RTC Access Control
Controls software access and interrupts to the RTC module.
0 Access and interrupts disabled
1 Access and interrupts enabled
This field is reserved.
This read-only field is reserved and always has the value 0.
ADC0 Clock Gate Control
Controls the clock gate to the ADC0 module.
0 Clock disabled
1 Clock enabled
TPM2 Clock Gate Control
Controls the clock gate to the TPM2 module.
0 Clock disabled
1 Clock enabled
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0
5
0
4
0
0
3
0
0
2
0
0
1
0
0
0
1
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Field
25
TPM1
24
TPM0
23
PIT
22–19
Reserved
18
Reserved
17–16
Reserved
15
I2S
14–2
Reserved
1
DMAMUX
0
FTF
Chapter 12 System Integration Module (SIM)
SIM_SCGC6 field descriptions (continued)
Description
TPM1 Clock Gate Control
Controls the clock gate to the TPM1 module.
0 Clock disabled
1 Clock enabled
TPM0 Clock Gate Control
Controls the clock gate to the TPM0 module.
0 Clock disabled
1 Clock enabled
PIT Clock Gate Control
This bit controls the clock gate to the PIT module.
0 Clock disabled
1 Clock enabled
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
I2S Clock Gate Control
This bit controls the clock gate to the I 2 S module.
0 Clock disabled
1 Clock enabled
This field is reserved.
This read-only field is reserved and always has the value 0.
DMA Mux Clock Gate Control
Controls the clock gate to the DMA Mux module.
0 Clock disabled
1 Clock enabled
Flash Memory Clock Gate Control
Controls the clock gate to the flash memory. Flash reads are still supported while the flash memory is clock gated, but entry into low power modes is blocked.
0 Clock disabled
1 Clock enabled
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Memory map and register definition
12.2.11 System Clock Gating Control Register 7 (SIM_SCGC7)
Address: 4004_7000h base + 1040h offset = 4004_8040h
31 30 29 28 27 26 25 Bit
R
W
Reset 0 0 0 0 0 0 0
Bit
R
W
Reset
15
0
Field
31–9
Reserved
8
DMA
7–0
Reserved
14
0
13 12
11 10 9
24
0
8
1
23
0
7
22
0
6
0 0 0 0 0 0 0
SIM_SCGC7 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
DMA Clock Gate Control
Controls the clock gate to the DMA module.
0 Clock disabled
1 Clock enabled
This field is reserved.
This read-only field is reserved and always has the value 0.
21
0
5
0
20
0
4
0
19
0
3
0
18
0
2
0
17
0
1
0
16
0
0
0
12.2.12 System Clock Divider Register 1 (SIM_CLKDIV1)
NOTE
The CLKDIV1 register cannot be written to when the device is in VLPR mode.
NOTE
Reset value loaded during System Reset from
FTFA_FOPT[LPBOOT] (See
Address: 4004_7000h base + 1044h offset = 4004_8044h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
* Notes:
• OUTDIV1 field: The reset value depends on the FTFA_FOPT[LPBOOT]. It is loaded with 0000 (divide by 1), 0001 (divide by
2), 0011 (divide by 4, or 0111 (divide by 8).
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Field
31–28
OUTDIV1
27–19
Reserved
18–16
OUTDIV4
15–0
Reserved
Chapter 12 System Integration Module (SIM)
SIM_CLKDIV1 field descriptions
Description
Clock 1 Output Divider value
Sets the divide value for the core/system clock, as well as the bus/flash clocks. At the end of reset, it is loaded with 0000 (divide by one), 0001 (divide by two), 0011 (divide by four), or 0111 (divide by eight)
depending on the setting of the FTFA_FOPT[LPBOOT] (See Table 6-2
).
0000 Divide-by-1.
0001 Divide-by-2.
0010 Divide-by-3.
0011 Divide-by-4.
0100 Divide-by-5.
0101 Divide-by-6.
0110 Divide-by-7.
0111 Divide-by-8.
1000 Divide-by-9.
1001 Divide-by-10.
1010 Divide-by-11.
1011 Divide-by-12.
1100 Divide-by-13.
1101 Divide-by-14.
1110 Divide-by-15.
1111 Divide-by-16.
This field is reserved.
This read-only field is reserved and always has the value 0.
Clock 4 Output Divider value
Sets the divide value for the bus and flash clock and is in addition to the System clock divide ratio. At the end of reset, it is loaded with 0001 (divide by 2).
000 Divide-by-1.
001 Divide-by-2.
010 Divide-by-3.
011 Divide-by-4.
100 Divide-by-5.
101 Divide-by-6.
110 Divide-by-7.
111 Divide-by-8.
This field is reserved.
This read-only field is reserved and always has the value 0.
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Memory map and register definition
12.2.13 Flash Configuration Register 1 (SIM_FCFG1)
Address: 4004_7000h base + 104Ch offset = 4004_804Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset
Bit
0
15
0
14
0
13
0
12
11
10
9
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
Reset 0 0 0 0
* Notes:
• PFSIZE field: Device specific value.
0 0 0 0 0 0 0 0 0 0 0 0
Field
31–28
Reserved
27–24
PFSIZE
SIM_FCFG1 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Program Flash Size
Specifies the amount of program flash memory available on the device . Undefined values are reserved.
0000 8 KB of program flash memory, 0.25 KB protection region
0001 16 KB of program flash memory, 0.5 KB protection region
0011 32 KB of program flash memory, 1 KB protection region
0101 64 KB of program flash memory, 2 KB protection region
0111 128 KB of program flash memory, 4 KB protection region
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Field
23–2
Reserved
1
FLASHDOZE
0
FLASHDIS
Chapter 12 System Integration Module (SIM)
SIM_FCFG1 field descriptions (continued)
Description
1001 256 KB of program flash memory, 8 KB protection region
1111 128 KB of program flash memory, 4 KB protection region256 KB of program flash memory, 8 KB protection region
This field is reserved.
This read-only field is reserved and always has the value 0.
Flash Doze
When set, flash memory is disabled for the duration of Doze mode. This field must be clear during VLP modes. The flash will be automatically enabled again at the end of Doze mode so interrupt vectors do not need to be relocated out of flash memory. The wake-up time from Doze mode is extended when this field is set. An attempt by the DMA or other bus master to access the flash memory when the flash is disabled will result in a bus error.
0 Flash remains enabled during Doze mode.
1 Flash is disabled for the duration of Doze mode.
Flash Disable
Flash accesses are disabled (and generate a bus error) and the flash memory is placed in a low-power state. This field should not be changed during VLP modes. Relocate the interrupt vectors out of Flash memory before disabling the Flash.
0 Flash is enabled.
1 Flash is disabled.
12.2.14 Flash Configuration Register 2 (SIM_FCFG2)
Address: 4004_7000h base + 1050h offset = 4004_8050h
Bit
R
31
30 29 28 27
26 25
W
Reset 0
24 23
22 21
1
Bit
R
15 14 13 12 11 10 9 8
7 6 5
W
Reset 0 0 0 0 0 0 0 0 0 0
* Notes:
• MAXADDR0 field: Device specific value indicating amount of implemented flash.
• MAXADDR1 field: Device specific value indicating amount of implemented flash.
0
4
20 19
18
0
3
0 0
2
17
0
1
16
0
0
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Memory map and register definition
Field
31
Reserved
30–24
MAXADDR0
23
Reserved
22–16
MAXADDR1
15–0
Reserved
SIM_FCFG2 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Max Address lock
This field concatenated with leading zeros indicates the first invalid address of program flash (block 0).
For example, if MAXADDR0 = 0x10, the first invalid address of program flash (block 0) is 0x0002_0000.
This would be the MAXADDR0 value for a device with 128 KB program flash in flash block 0.
This field is reserved.
This read-only field is reserved and always has the value 1.
This field concatenated with leading zeros plus the value of the MAXADDR1 field indicates the first invalid address of the second program flash block (flash block 1).
For example, if MAXADDR0 = MAXADDR1 = 0x10 the first invalid address of flash block 1 is 0x2_0000 +
0x2_0000. This would be the MAXADDR1 value for a device with 256 KB program flash memory across two flash blocks.
This field is reserved.
This read-only field is reserved and always has the value 0.
12.2.15 Unique Identification Register Mid-High (SIM_UIDMH)
Address: 4004_7000h base + 1058h offset = 4004_8058h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
* * * * * * * * * * * * * * * *
* Notes:
• UID field: Device specific value.
Field
31–16
Reserved
15–0
UID
SIM_UIDMH field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Unique Identification
Unique identification for the device.
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Chapter 12 System Integration Module (SIM)
12.2.16 Unique Identification Register Mid Low (SIM_UIDML)
Address: 4004_7000h base + 105Ch offset = 4004_805Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Notes:
• UID field: Device specific value.
Field
31–0
UID
SIM_UIDML field descriptions
Description
Unique Identification
Unique identification for the device.
12.2.17 Unique Identification Register Low (SIM_UIDL)
Address: 4004_7000h base + 1060h offset = 4004_8060h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Notes:
• UID field: Device specific value.
Field
31–0
UID
SIM_UIDL field descriptions
Description
Unique Identification
Unique identification for the device.
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Memory map and register definition
12.2.18 COP Control Register (SIM_COPC)
All of the bits in this register can be written only once after a reset.
Address: 4004_7000h base + 1100h offset = 4004_8100h
Bit 31 30 29 28 27 26 25
R
24
23 22 21 20 19 18 17 16
W
Reset
Bit
R
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
W
Reset 0
Field
31–4
Reserved
3–2
COPT
1
COPCLKS
0
COPW
0 0 0 0 0 0 0 0 0
SIM_COPC field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
COP Watchdog Timeout
0 0 1 1 0
This write-once field selects the timeout period of the COP. COPT along with the COPCLKS field define the COP timeout period.
00 COP disabled
01 COP timeout after 2 5 LPO cycles or 2 13 bus clock cycles
10 COP timeout after 2 8 LPO cycles or 2 16 bus clock cycles
11 COP timeout after 2 10 LPO cycles or 2 18 bus clock cycles
COP Clock Select
0
This write-once field selects the clock source of the COP watchdog.
0 Internal 1 kHz clock is source to COP.
1 Bus clock is source to COP.
COP Windowed Mode
Windowed mode is supported only when COP is running from the bus clock. The COP window is opened three quarters through the timeout period.
0 Normal mode
1 Windowed mode
0
0
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Chapter 12 System Integration Module (SIM)
12.2.19 Service COP (SIM_SRVCOP)
Address: 4004_7000h base + 1104h offset = 4004_8104h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–8
Reserved
7–0
SRVCOP
This field is reserved.
SIM_SRVCOP field descriptions
Description
Service COP Register
Write 0x55 and then 0xAA (in that order) to reset the COP timeout counter, writing any other value will generate a system reset.
12.3 Functional description
See
section.
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Functional description
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Chapter 13
System Mode Controller (SMC)
13.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
The System Mode Controller (SMC) is responsible for sequencing the system into and out of all low-power Stop and Run modes.
Specifically, it monitors events to trigger transitions between power modes while controlling the power, clocks, and memories of the system to achieve the power consumption and functionality of that mode.
This chapter describes all the available low-power modes, the sequence followed to enter/ exit each mode, and the functionality available while in each of the modes.
The SMC is able to function during even the deepest low power modes.
See AN4503: Power Management for Kinetis and ColdFire+ MCUs for further details on using the SMC.
13.2 Modes of operation
The ARM CPU has three primary modes of operation:
• Run
• Sleep
• Deep Sleep
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Modes of operation
The WFI or WFE instruction is used to invoke Sleep and Deep Sleep modes. Run, Wait, and Stop are the common terms used for the primary operating modes of Freescale microcontrollers.
The following table shows the translation between the ARM CPU modes and the
Freescale MCU power modes.
ARM CPU mode
Sleep
Deep Sleep
MCU mode
Wait
Stop
Accordingly, the ARM CPU documentation refers to sleep and deep sleep, while the
Freescale MCU documentation normally uses wait and stop.
In addition, Freescale MCUs also augment Stop, Wait, and Run modes in a number of ways. The power management controller (PMC) contains a run and a stop mode regulator. Run regulation is used in normal run, wait and stop modes. Stop mode regulation is used during all very low power and low leakage modes. During stop mode regulation, the bus frequencies are limited in the very low power modes.
The SMC provides the user with multiple power options. The Very Low Power Run
(VLPR) mode can drastically reduce run time power when maximum bus frequency is not required to handle the application needs. From Normal Run mode, the Run Mode
(RUNM) field can be modified to change the MCU into VLPR mode when limited frequency is sufficient for the application. From VLPR mode, a corresponding wait
(VLPW) and stop (VLPS) mode can be entered.
Depending on the needs of the user application, a variety of stop modes are available that allow the state retention, partial power down or full power down of certain logic and/or memory. I/O states are held in all modes of operation. Several registers are used to configure the various modes of operation for the device.
The following table describes the power modes available for the device.
RUN
WAIT
STOP
VLPR
Mode
Table 13-1. Power modes
Description
The MCU can be run at full speed and the internal supply is fully regulated, that is, in run regulation.
This mode is also referred to as Normal Run mode.
The core clock is gated off. The system clock continues to operate. Bus clocks, if enabled, continue to operate. Run regulation is maintained.
The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid.
The core, system, bus, and flash clock maximum frequencies are restricted in this mode. See the
Power Management chapter for details about the maximum allowable frequencies.
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VLPW
Mode
VLPS
LLS
VLLS3
VLLS1
VLLS0
Chapter 13 System Mode Controller (SMC)
Table 13-1. Power modes (continued)
Description
The core clock is gated off. The system, bus, and flash clocks continue to operate, although their maximum frequency is restricted. See the Power Management chapter for details on the maximum allowable frequencies.
The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid.
The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by reducing the voltage to internal logic. All system RAM contents, internal logic and
I/O states are retained.
The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic. All system RAM contents are retained and I/O states are held. Internal logic states are not retained.
The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic and all system RAM. I/O states are held. Internal logic states are not retained.
The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic and all system RAM. I/O states are held. Internal logic states are not retained. The 1kHz LPO clock is disabled and the power on reset (POR) circuit can be optionally enabled using STOPCTRL[PORPO].
13.3 Memory map and register descriptions
Information about the registers related to the system mode controller can be found here.
Different SMC registers reset on different reset types. Each register's description provides details. For more information about the types of reset on this chip, refer to the Reset section details.
NOTE
The SMC registers can be written only in supervisor mode.
Write accesses in user mode are blocked and will result in a bus error.
NOTE
Before executing the WFI instruction, the last register written to must be read back. This ensures that all register writes associated with setting up the low power mode being entered have completed before the MCU enters the low power mode.
Failure to do this may result in the low power mode not being entered correctly.
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Memory map and register descriptions
SMC memory map
Absolute address
(hex)
Register name
4007_E000 Power Mode Protection register (SMC_PMPROT)
4007_E001 Power Mode Control register (SMC_PMCTRL)
4007_E002 Stop Control Register (SMC_STOPCTRL)
4007_E003 Power Mode Status register (SMC_PMSTAT)
Width
(in bits)
Access Reset value
8
8
8
8
R/W
R/W
R/W
R
00h
00h
03h
01h
Section/ page
13.3.1 Power Mode Protection register (SMC_PMPROT)
This register provides protection for entry into any low-power run or stop mode. The enabling of the low-power run or stop mode occurs by configuring the Power Mode
Control register (PMCTRL).
The PMPROT register can be written only once after any system reset.
If the MCU is configured for a disallowed or reserved power mode, the MCU remains in its current power mode. For example, if the MCU is in normal RUN mode and AVLP is
0, an attempt to enter VLPR mode using PMCTRL[RUNM] is blocked and
PMCTRL[RUNM] remains 00b, indicating the MCU is still in Normal Run mode.
NOTE
This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Reset section details for more information.
Address: 4007_E000h base + 0h offset = 4007_E000h
Bit
Read
Write
Reset
Field
7
Reserved
6
Reserved
5
AVLP
7
6
5
0
4
3
0 0 0 0
SMC_PMPROT field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
Allow Very-Low-Power Modes
2
0
1
0
0
0
Provided the appropriate control bits are set up in PMCTRL, this write-once field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
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Field
4
Reserved
3
ALLS
2
Reserved
1
AVLLS
0
Reserved
Chapter 13 System Mode Controller (SMC)
SMC_PMPROT field descriptions (continued)
Description
0 VLPR, VLPW, and VLPS are not allowed.
1 VLPR, VLPW, and VLPS are allowed.
This field is reserved.
This read-only field is reserved and always has the value 0.
Allow Low-Leakage Stop Mode
Provided the appropriate control bits are set up in PMCTRL, this write-once field allows the MCU to enter any low-leakage stop mode (LLS).
0 LLS is not allowed
1 LLS is allowed
This field is reserved.
This read-only field is reserved and always has the value 0.
Allow Very-Low-Leakage Stop Mode
Provided the appropriate control bits are set up in PMCTRL, this write once bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
0 Any VLLSx mode is not allowed
1 Any VLLSx mode is allowed
This field is reserved.
This read-only field is reserved and always has the value 0.
13.3.2 Power Mode Control register (SMC_PMCTRL)
The PMCTRL register controls entry into low-power Run and Stop modes, provided that the selected power mode is allowed via an appropriate setting of the protection
(PMPROT) register.
NOTE
This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See the Reset section details for more information.
Address: 4007_E000h base + 1h offset = 4007_E001h
7 6 5 Bit
Read
Write
Reset
0 0
0
4
0
3
0
2
0
1
0
0
0
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Memory map and register descriptions
SMC_PMCTRL field descriptions
Field
7
Reserved
Reserved.
Description
6–5
RUNM
This field is reserved.
This bit is reserved for future expansion and should always be written zero for deterministic operation.
Run Mode Control
When written, causes entry into the selected run mode. Writes to this field are blocked if the protection level has not been enabled using the PMPROT register. This field is cleared by hardware on any exit to normal RUN mode.
NOTE: RUNM may be set to VLPR only when PMSTAT=RUN. After being written to VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR.
4
Reserved
3
STOPA
00 Normal Run mode (RUN)
01 Reserved
10 Very-Low-Power Run mode (VLPR)
11 Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Stop Aborted
When set, this read-only status bit indicates an interrupt or reset occured during the previous stop mode entry sequence, preventing the system from entering that mode. This field is cleared by hardware at the beginning of any stop mode entry sequence and is set if the sequence was aborted.
2–0
STOPM
0 The previous stop mode entry was successsful.
1 The previous stop mode entry was aborted.
Stop Mode Control
When written, controls entry into the selected stop mode when Sleep-Now or Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are blocked if the protection level has not been enabled using the PMPROT register. After any system reset, this field is cleared by hardware on any successful write to the PMPROT register.
NOTE: When set to VLLSx, the VLLSM field in the STOPCTRL register is used to further select the particular VLLS submode which will be entered.
NOTE: When set to STOP, the PSTOPO bits in the STOPCTRL register can be used to select a Partial
Stop mode if desired.
000 Normal Stop (STOP)
001 Reserved
010 Very-Low-Power Stop (VLPS)
011 Low-Leakage Stop (LLS)
100 Very-Low-Leakage Stop (VLLSx)
101 Reserved
110 Reseved
111 Reserved
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13.3.3 Stop Control Register (SMC_STOPCTRL)
The STOPCTRL register provides various control bits allowing the user to fine tune power consumption during the stop mode selected by the STOPM field.
NOTE
This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See the Reset section details for more information.
Address: 4007_E000h base + 2h offset = 4007_E002h
Bit
Read
Write
Reset
Field
7–6
PSTOPO
7
6 5
0
4
3
2 1
1
0
0 0 0 0 0 1
SMC_STOPCTRL field descriptions
Description
Partial Stop Option
These bits control whether a Partial Stop mode is entered when STOPM=STOP. When entering a Partial
Stop mode from RUN mode, the PMC, MCG and flash remain fully powered, allowing the device to wakeup almost instantaneously at the expense of higher power consumption. In PSTOP2, only system clocks are gated allowing peripherals running on bus clock to remain fully functional. In PSTOP1, both system and bus clocks are gated.
5
PORPO
00 STOP - Normal Stop mode
01 PSTOP1 - Partial Stop with both system and bus clocks disabled
10 PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
11 Reserved
POR Power Option
This bit controls whether the POR detect circuit is enabled in VLLS0 mode.
4
Reserved
3
Reserved
2–0
VLLSM
0 POR detect circuit is enabled in VLLS0
1 POR detect circuit is disabled in VLLS0
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
VLLS Mode Control
This field controls which VLLS sub-mode to enter if STOPM=VLLSx.
000 VLLS0
001
VLLS1
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Memory map and register descriptions
SMC_STOPCTRL field descriptions (continued)
Field Description
010
Reserved
011
VLLS3
100 Reserved
101 Reserved
110 Reserved
111 Reserved
13.3.4 Power Mode Status register (SMC_PMSTAT)
PMSTAT is a read-only, one-hot register which indicates the current power mode of the system.
NOTE
This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See the Reset section details for more information.
Address: 4007_E000h base + 3h offset = 4007_E003h
Bit
Read
Write
Reset
7
0
6
0
5
0
Field
7
Reserved
6–0
PMSTAT
4 3
0 0
SMC_PMSTAT field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
2
0
1
0
NOTE: When debug is enabled, the PMSTAT will not update to STOP or VLPS
NOTE: When a PSTOP mode is enabled, the PMSTAT will not update to STOP or VLPS
000_0001 Current power mode is RUN.
000_0010 Current power mode is STOP.
000_0100 Current power mode is VLPR.
000_1000 Current power mode is VLPW.
001_0000 Current power mode is VLPS.
010_0000 Current power mode is LLS.
100_0000 Current power mode is VLLS.
0
1
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Chapter 13 System Mode Controller (SMC)
13.4 Functional description
13.4.1 Power mode transitions
The following figure shows the power mode state transitions available on the chip. Any reset always brings the MCU back to the normal run state.
Any RESET
WAIT
STOP
2
1
VLPW
5
10
RUN
8
3
7
VLPR
6
VLPS
4
LLS
VLLS
3, 1, 0
9
11
Figure 13-5. Power mode state diagram
The following table defines triggers for the various state transitions shown in the previous figure.
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Functional description
244
Transition #
1
2
3
4
5
6
7
8
Table 13-7. Power mode transition triggers
From
RUN
WAIT
RUN
STOP
RUN
VLPR
VLPR
VLPW
VLPW
VLPR
VLPS
RUN
VLPS
RUN
VLLSx
To
WAIT
RUN
STOP
RUN
VLPR
RUN
VLPW
VLPR
RUN
VLPS
VLPR
VLPS
RUN
VLLSx
RUN
Trigger conditions
Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, controlled in System Control Register in ARM core.
Interrupt or Reset
PMCTRL[RUNM]=00, PMCTRL[STOPM]=000
Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core.
Interrupt or Reset
The core, system, bus and flash clock frequencies and MCG clocking mode are restricted in this mode. See the Power
Management chapter for the maximum allowable frequencies and MCG modes supported.
Set PMPROT[AVLP]=1, PMCTRL[RUNM]=10.
Set PMCTRL[RUNM]=00 or
Reset.
Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, which is controlled in System Control Register in ARM core.
Interrupt
Reset
PMCTRL[STOPM]=000
or 010,
Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core.
Interrupt
NOTE: If VLPS was entered directly from RUN, hardware will not allow this transition and will force exit back to
RUN
PMPROT[AVLP]=1, PMCTRL[STOPM]=010,
Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core.
Interrupt and VLPS mode was entered directly from RUN or
Reset
PMPROT[AVLLS]=1, PMCTRL[STOPM]=100,
STOPCTRL[VLLSM]=x (VLLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in
System Control Register in ARM core.
Wakeup from enabled LLWU input source or RESET pin
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Transition #
9
10
11
Chapter 13 System Mode Controller (SMC)
Table 13-7. Power mode transition triggers (continued)
From
VLPR
RUN
LLS
VLPR
To
VLLSx
LLS
RUN
LLS
Trigger conditions
PMPROT[AVLLS]=1, PMCTRL[STOPM]=100,
STOPCTRL[VLLSM]=x (VLLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in
System Control Register in ARM core.
PMPROT[ALLS]=1, PMCTRL[STOPM]=011, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core.
Wakeup from enabled LLWU input source or
RESET pin.
PMPROT[ALLS]=1, PMCTRL[STOPM]=011, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core.
1. If debug is enabled, the core clock remains to support debug.
2. If PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=01 or 10, then only a Partial Stop mode is entered instead of STOP
3. If PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=00, then VLPS mode is entered instead of STOP. If
PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=01 or 10, then only a Partial Stop mode is entered instead of VLPS
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Functional description
13.4.2 Power mode entry/exit sequencing
When entering or exiting low-power modes, the system must conform to an orderly sequence to manage transitions safely.
The SMC manages the system's entry into and exit from all power modes. This diagram illustrates the connections of the SMC with other system components in the chip that are necessary to sequence the system through all power modes.
Low-
Leakage
Wakeup
(LLWU)
Reset
Control
Module
(RCM)
CPU
LP exit Stop/Wait
LP exit
System
Mode
Controller
(SMC)
CCM low power bus
Clock
Control
Module
(CCM)
Bus masters low power bus (non-CPU)
Bus slaves low power bus
PMC low power bus
MCG enable Flash low power bus
System
Power
(PMC)
System
Clocks
(MCG)
Flash
Memory
Module
Figure 13-6. Low-power system components and connections
13.4.2.1 Stop mode entry sequence
Entry into a low-power stop mode (Stop, VLPS, LLS, VLLSx) is initiated by CPU execution of the WFI instruction. After the instruction is executed, the following sequence occurs:
1. The CPU clock is gated off immediately.
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2. Requests are made to all non-CPU bus masters to enter Stop mode.
3. After all masters have acknowledged they are ready to enter Stop mode, requests are made to all bus slaves to enter Stop mode.
4. After all slaves have acknowledged they are ready to enter Stop mode, all system and bus clocks are gated off.
5. Clock generators are disabled in the MCG.
6. The on-chip regulator in the PMC and internal power switches are configured to meet the power consumption goals for the targeted low-power mode.
13.4.2.2 Stop mode exit sequence
Exit from a low-power stop mode is initiated either by a reset or an interrupt event. The following sequence then executes to restore the system to a run mode (RUN or VLPR):
1. The on-chip regulator in the PMC and internal power switches are restored.
2. Clock generators are enabled in the MCG.
3. System and bus clocks are enabled to all masters and slaves.
4. The CPU clock is enabled and the CPU begins servicing the reset or interrupt that initiated the exit from the low-power stop mode.
13.4.2.3 Aborted stop mode entry
If an interrupt or a reset occurs during a stop entry sequence, the SMC can abort the transition early and return to RUN mode without completely entering the stop mode. An aborted entry is possible only if the reset or interrupt occurs before the PMC begins the transition to stop mode regulation. After this point, the interrupt or reset is ignored until the PMC has completed its transition to stop mode regulation. When an aborted stop mode entry sequence occurs, SMC_PMCTRL[STOPA] is set to 1.
13.4.2.4 Transition to wait modes
For wait modes (WAIT and VLPW), the CPU clock is gated off while all other clocking continues, as in RUN and VLPR mode operation. Some modules that support stop-inwait functionality have their clocks disabled in these configurations.
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Functional description
13.4.2.5 Transition from stop modes to Debug mode
The debugger module supports a transition from STOP, WAIT, VLPS, and VLPW back to a Halted state when the debugger has been enabled. As part of this transition, system clocking is re-established and is equivalent to the normal RUN and VLPR mode clocking configuration.
13.4.3 Run modes
The run modes supported by this device can be found here.
• Run (RUN)
• Very Low-Power Run (VLPR)
13.4.3.1 RUN mode
This is the normal operating mode for the device.
This mode is selected after any reset. When the ARM processor exits reset, it sets up the stack, program counter (PC), and link register (LR):
• The processor reads the start SP (SP_main) from vector-table offset 0x000
• The processor reads the start PC from vector-table offset 0x004
• LR is set to 0xFFFF_FFFF.
To reduce power in this mode, disable the clocks to unused modules using their corresponding clock gating control bits in the SIM's registers.
13.4.3.2 Very-Low Power Run (VLPR) mode
In VLPR mode, the on-chip voltage regulator is put into a stop mode regulation state. In this state, the regulator is designed to supply enough current to the MCU over a reduced frequency. To further reduce power in this mode, disable the clocks to unused modules using their corresponding clock gating control bits in the SIM's registers.
Before entering this mode, the following conditions must be met:
• The MCG must be configured in a mode which is supported during VLPR. See the
Power Management details for information about these MCG modes.
• All clock monitors in the MCG must be disabled.
• The maximum frequencies of the system, bus, flash, and core are restricted. See the
Power Management details about which frequencies are supported.
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• Mode protection must be set to allow VLP modes, that is, PMPROT[AVLP] is 1.
• PMCTRL[RUNM] is set to 10b to enter VLPR.
• Flash programming/erasing is not allowed.
NOTE
Do not change the clock frequency while in VLPR mode, because the regulator is slow responding and cannot manage fast load transitions. In addition, do not modify the clock source in the MCG module, the module clock enables in the SIM, or any clock divider registers.
To reenter Normal Run mode, clear PMCTRL[RUNM]. PMSTAT is a read-only status register that can be used to determine when the system has completed an exit to RUN mode. When PMSTAT=RUN, the system is in run regulation and the MCU can run at full speed in any clock mode. If a higher execution frequency is desired, poll PMSTAT until it is set to RUN when returning from VLPR mode.
Any reset always causes an exit from VLPR and returns the device to RUN mode after the MCU exits its reset flow.
13.4.4 Wait modes
This device contains two different wait modes which are listed here.
• Wait
• Very-Low Power Wait (VLPW)
13.4.4.1 WAIT mode
WAIT mode is entered when the ARM core enters the Sleep-Now or Sleep-On-Exit modes while SLEEDEEP is cleared. The ARM CPU enters a low-power state in which it is not clocked, but peripherals continue to be clocked provided they are enabled. Clock gating to the peripheral is enabled via the SIM module.
When an interrupt request occurs, the CPU exits WAIT mode and resumes processing in
RUN mode, beginning with the stacking operations leading to the interrupt service routine.
A system reset will cause an exit from WAIT mode, returning the device to normal RUN mode.
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Functional description
13.4.4.2 Very-Low-Power Wait (VLPW) mode
VLPW is entered by the entering the Sleep-Now or Sleep-On-Exit mode while
SLEEPDEEP is cleared and the MCU is in VLPR mode.
In VLPW, the on-chip voltage regulator remains in its stop regulation state. In this state, the regulator is designed to supply enough current to the MCU over a reduced frequency.
To further reduce power in this mode, disable the clocks to unused modules by clearing the peripherals' corresponding clock gating control bits in the SIM.
VLPR mode restrictions also apply to VLPW.
When an interrupt from VLPW occurs, the device returns to VLPR mode to execute the interrupt service routine.
A system reset will cause an exit from VLPW mode, returning the device to normal RUN mode.
13.4.5 Stop modes
This device contains a variety of stop modes to meet your application needs.
The stop modes range from:
• a stopped CPU, with all I/O, logic, and memory states retained, and certain asynchronous mode peripherals operating to:
• a powered down CPU, with only I/O and a small register file retained, very few asynchronous mode peripherals operating, while the remainder of the MCU is powered down.
The choice of stop mode depends upon the user's application, and how power usage and state retention versus functional needs and recovery time may be traded off.
NOTE
All clock monitors must be disabled before entering these lowpower modes: Stop, VLPS, VLPR, VLPW, LLS, and VLLSx.
The various stop modes are selected by setting the appropriate fields in PMPROT and
PMCTRL. The selected stop mode is entered during the sleep-now or sleep-on-exit entry with the SLEEPDEEP bit set in the System Control Register in the ARM core.
The available stop modes are:
• Normal Stop (STOP)
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• Very-Low Power Stop (VLPS)
• Low-Leakage Stop (LLS)
• Very-Low-Leakage Stop (VLLSx)
13.4.5.1 STOP mode
STOP mode is entered via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core.
The MCG module can be configured to leave the reference clocks running.
A module capable of providing an asynchronous interrupt to the device takes the device out of STOP mode and returns the device to normal RUN mode. Refer to the device's
Power Management chapter for peripheral, I/O, and memory operation in STOP mode.
When an interrupt request occurs, the CPU exits STOP mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine.
A system reset will cause an exit from STOP mode, returning the device to normal RUN mode via an MCU reset.
13.4.5.2 Very-Low-Power Stop (VLPS) mode
The two ways in which VLPS mode can be entered are listed here.
• Entry into stop via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the
System Control Register in the ARM core while the MCU is in VLPR mode and
PMCTRL[STOPM] = 010 or 000.
• Entry into stop via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the
System Control Register in the ARM core while the MCU is in normal RUN mode and PMCTRL[STOPM] = 010. When VLPS is entered directly from RUN mode, exit to VLPR is disabled by hardware and the system will always exit back to RUN.
In VLPS, the on-chip voltage regulator remains in its stop regulation state as in VLPR.
A module capable of providing an asynchronous interrupt to the device takes the device out of VLPS and returns the device to VLPR mode.
A system reset will also cause a VLPS exit, returning the device to normal RUN mode.
13.4.5.3 Low-Leakage Stop (LLS) mode
Low-Leakage Stop (LLS) mode can be entered from normal RUN or VLPR modes.
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Functional description
The MCU enters LLS mode if:
• In Sleep-Now or Sleep-On-Exit mode, SLEEPDEEP is set in the System Control
Register in the ARM core, and
• The device is configured as shown in
.
In LLS, the on-chip voltage regulator is in stop regulation. Most of the peripherals are put in a state-retention mode that does not allow them to operate while in LLS.
Before entering LLS mode, the user should configure the Low-Leakage Wake-up
(LLWU) module to enable the desired wake-up sources. The available wake-up sources in LLS are detailed in the chip configuration details for this device.
After wakeup from LLS, the device returns to with a pending LLWU module interrupt. In the LLWU interrupt service routine (ISR), the user can poll the LLWU module wake-up flags to determine the source of the wakeup.
NOTE
The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit Stop mode on an LLS recovery.
An asserted RESET pin will cause an exit from LLS mode, returning the device to normal RUN mode. When LLS is exiting via the RESET pin, RCM_SRS0[PIN] and
RCM_SRS0[WAKEUP] are set.
13.4.5.4 Very-Low-Leakage Stop (VLLSx) modes
This device contains these very low leakage modes:
• VLLS3
• VLLS1
• VLLS0
VLLSx is often used in this document to refer to all of these modes.
All VLLSx modes can be entered from normal RUN or VLPR modes.
The MCU enters the configured VLLS mode if:
• In Sleep-Now or Sleep-On-Exit mode, the SLEEPDEEP bit is set in the System
Control Register in the ARM core, and
• The device is configured as shown in
.
In VLLS, the on-chip voltage regulator is in its stop-regulation state while most digital logic is powered off.
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Before entering VLLS mode, the user should configure the Low-Leakage Wake-up
(LLWU) module to enable the desired wakeup sources. The available wake-up sources in
VLLS are detailed in the chip configuration details for this device.
After wakeup from VLLS, the device returns to normal RUN mode with a pending
LLWU interrupt. In the LLWU interrupt service routine (ISR), the user can poll the
LLWU module wake-up flags to determine the source of the wake-up.
When entering VLLS, each I/O pin is latched as configured before executing VLLS.
Because all digital logic in the MCU is powered off, all port and peripheral data is lost during VLLS. This information must be restored before PMC_REGSC[ACKISO] is set.
An asserted RESET pin will cause an exit from any VLLS mode, returning the device to normal RUN mode. When exiting VLLS via the RESET pin, RCM_SRS0[PIN] and
RCM_SRS0[WAKEUP] are set.
13.4.6 Debug in low power modes
When the MCU is secure, the device disables/limits debugger operation. When the MCU is unsecure, the ARM debugger can assert two power-up request signals:
• System power up, via SYSPWR in the Debug Port Control/Stat register
• Debug power up, via CDBGPWRUPREQ in the Debug Port Control/Stat register
When asserted while in RUN, WAIT, VLPR, or VLPW, the mode controller drives a corresponding acknowledge for each signal, that is, both CDBGPWRUPACK and
CSYSPWRUPACK. When both requests are asserted, the mode controller handles attempts to enter STOP and VLPS by entering an emulated stop state. In this emulated stop state:
• the regulator is in run regulation,
• the MCG-generated clock source is enabled,
• all system clocks, except the core clock, are disabled,
• the debug module has access to core registers, and
• access to the on-chip peripherals is blocked.
No debug is available while the MCU is in LLS or VLLS modes. LLS is a state-retention mode and all debug operation can continue after waking from LLS, even in cases where system wakeup is due to a system reset event.
Entering into a VLLS mode causes all of the debug controls and settings to be powered off. To give time to the debugger to sync with the MCU, the MDM AP Control Register includes a Very-Low-Leakage Debug Request (VLLDBGREQ) bit that is set to configure
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Functional description the Reset Controller logic to hold the system in reset after the next recovery from a VLLS mode. This bit allows the debugger time to reinitialize the debug module before the debug session continues.
The MDM AP Control Register also includes a Very Low Leakage Debug Acknowledge
(VLLDBGACK) bit that is set to release the ARM core being held in reset following a
VLLS recovery. The debugger reinitializes all debug IP, and then asserts the
VLLDBGACK control bit to allow the RCM to release the ARM core from reset and allow CPU operation to begin.
The VLLDBGACK bit is cleared by the debugger (or can be left set as is) or clears automatically due to the reset generated as part of the next VLLS recovery.
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Chapter 14
Power Management Controller (PMC)
14.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
The power management controller (PMC) contains the internal voltage regulator, power on reset (POR), and low voltage detect system.
See AN4503: Power Management for Kinetis and ColdFire+ MCUs for further details on using the PMC.
14.2 Features
A list of included PMC features can be found here.
• Internal voltage regulator
• Active POR providing brown-out detect
• Low-voltage detect supporting two low-voltage trip points with four warning levels per trip point
14.3 Low-voltage detect (LVD) system
This device includes a system to guard against low-voltage conditions. This protects memory contents and controls MCU system states during supply voltage variations.
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Low-voltage detect (LVD) system
The system is comprised of a power-on reset (POR) circuit and a LVD circuit with a user-selectable trip voltage: high (V
LVDH
) or low (V
LVDL
). The trip voltage is selected by
LVDSC1[LVDV]. The LVD is disabled upon entering VLPx, LLS, and VLLSx modes.
Two flags are available to indicate the status of the low-voltage detect system:
• The Low Voltage Detect Flag in the Low Voltage Status and Control 1 Register
(LVDSC1[LVDF]) operates in a level sensitive manner. LVDSC1[LVDF] is set when the supply voltage falls below the selected trip point (VLVD).
LVDSC1[LVDF] is cleared by writing 1 to LVDSC1[LVDACK], but only if the internal supply has returned above the trip point; otherwise, LVDSC1[LVDF] remains set.
• The Low Voltage Warning Flag (LVWF) in the Low Voltage Status and Control 2
Register (LVDSC2[LVWF]) operates in a level sensitive manner. LVDSC2[LVWF] is set when the supply voltage falls below the selected monitor trip point (VLVW).
LVDSC2[LVWF] is cleared by writing one to LVDSC2[LVWACK], but only if the internal supply has returned above the trip point; otherwise, LVDSC2[LVWF] remains set.
14.3.1 LVD reset operation
By setting LVDSC1[LVDRE], the LVD generates a reset upon detection of a low-voltage condition. The low-voltage detection threshold is determined by LVDSC1[LVDV]. After an LVD reset occurs, the LVD system holds the MCU in reset until the supply voltage rises above this threshold. The LVD field in the SRS register of the RCM module
(RCM_SRS0[LVD]) is set following an LVD or power-on reset.
14.3.2 LVD interrupt operation
By configuring the LVD circuit for interrupt operation (LVDSC1[LVDIE] set and
LVDSC1[LVDRE] clear), LVDSC1[LVDF] is set and an LVD interrupt request occurs upon detection of a low voltage condition. LVDSC1[LVDF] is cleared by writing 1 to
LVDSC1[LVDACK].
14.3.3 Low-voltage warning (LVW) interrupt operation
The LVD system contains a Low-Voltage Warning Flag (LVWF) in the Low Voltage
Detect Status and Control 2 Register to indicate that the supply voltage is approaching, but is above, the LVD voltage. The LVW also has an interrupt, which is enabled by
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Chapter 14 Power Management Controller (PMC) setting LVDSC2[LVWIE]. If enabled, an LVW interrupt request occurs when
LVDSC2[LVWF] is set. LVDSC2[LVWF] is cleared by writing 1 to
LVDSC2[LVWACK].
LVDSC2[LVWV] selects one of the four trip voltages:
• Highest: V
LVW4
• Two mid-levels: V
LVW3
• Lowest: V
LVW1
and V
LVW2
14.4 I/O retention
When in LLS mode, the I/O pins are held in their input or output state.
Upon wakeup, the PMC is re-enabled, goes through a power up sequence to full regulation, and releases the logic from state retention mode. The I/O are released immediately after a wake-up or reset event. In the case of LLS exit via a RESET pin, the
I/O default to their reset state.
When in VLLS modes, the I/O states are held on a wake-up event (with the exception of wake-up by reset event) until the wake-up has been acknowledged via a write to
REGSC[ACKISO]. In the case of VLLS exit via a RESET pin, the I/O are released and default to their reset state. In this case, no write to REGSC[ACKISO] is needed.
14.5 Memory map and register descriptions
Details about the PMC registers can be found here.
NOTE
Different portions of PMC registers are reset only by particular reset types. Each register's description provides details. For more information about the types of reset on this chip, refer to the Reset section details.
The PMC registers can be written only in supervisor mode.
Write accesses in user mode are blocked and will result in a bus error.
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Memory map and register descriptions
PMC memory map
Absolute address
(hex)
Register name
4007_D000
4007_D001
Low Voltage Detect Status And Control 1 register
(PMC_LVDSC1)
Low Voltage Detect Status And Control 2 register
(PMC_LVDSC2)
4007_D002 Regulator Status And Control register (PMC_REGSC)
Width
(in bits)
Access Reset value
8
8
8
R/W
R/W
R/W
10h
00h
04h
Section/ page
14.5.1 Low Voltage Detect Status And Control 1 register
(PMC_LVDSC1)
This register contains status and control bits to support the low voltage detect function.
This register should be written during the reset initialization program to set the desired controls even if the desired settings are the same as the reset settings.
While the device is in the very low power or low leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect systems that must have LVD always on, configure the Power Mode Protection (PMPROT) register of the SMC module
(SMC_PMPROT) to disallow any very low power or low leakage modes from being enabled.
See the device's data sheet for the exact LVD trip voltages.
NOTE
The LVDV bits are reset solely on a POR Only event. The register's other bits are reset on Chip Reset Not VLLS. For more information about these reset types, refer to the Reset section details.
Address: 4007_D000h base + 0h offset = 4007_D000h
Bit
Read
Write
Reset
7
0
6
0
0
5
0
Field
7
LVDF
4
3
1 0
PMC_LVDSC1 field descriptions
Description
Low-Voltage Detect Flag
This read-only status field indicates a low-voltage detect event.
Table continues on the next page...
2
0
1
0
0
0
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Field
6
LVDACK
5
LVDIE
4
LVDRE
3–2
Reserved
1–0
LVDV
Chapter 14 Power Management Controller (PMC)
PMC_LVDSC1 field descriptions (continued)
Description
0 Low-voltage event not detected
1 Low-voltage event detected
Low-Voltage Detect Acknowledge
This write-only field is used to acknowledge low voltage detection errors. Write 1 to clear LVDF. Reads always return 0.
Low-Voltage Detect Interrupt Enable
Enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling)
1 Request a hardware interrupt when LVDF = 1
Low-Voltage Detect Reset Enable
This write-once bit enables LVDF events to generate a hardware reset. Additional writes are ignored.
0 LVDF does not generate hardware resets
1 Force an MCU reset when LVDF = 1
This field is reserved.
This read-only field is reserved and always has the value 0.
Low-Voltage Detect Voltage Select
Selects the LVD trip point voltage (V
LVD
).
00 Low trip point selected (V
01 High trip point selected (V
LVD
= V
LVD
= V
LVDL
)
LVDH
)
10 Reserved
11 Reserved
14.5.2 Low Voltage Detect Status And Control 2 register
(PMC_LVDSC2)
This register contains status and control bits to support the low voltage warning function.
While the device is in the very low power or low leakage modes, the LVD system is disabled regardless of LVDSC2 settings.
See the device's data sheet for the exact LVD trip voltages.
NOTE
The LVW trip voltages depend on LVWV and LVDV.
NOTE
LVWV is reset solely on a POR Only event. The other fields of the register are reset on Chip Reset Not VLLS. For more
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Memory map and register descriptions information about these reset types, refer to the Reset section details.
Address: 4007_D000h base + 1h offset = 4007_D001h
Bit
Read
Write
Reset
Field
7
LVWF
7
0
6
0
0
5
0
4
0
3
0
PMC_LVDSC2 field descriptions
Description
Low-Voltage Warning Flag
2
0
1
0
0
0
This read-only status field indicates a low-voltage warning event. LVWF is set when V
Supply below the trip point, or after reset and V
Supply
is already below V
LVW
transitions
. LVWF may be 1 after power-on reset, therefore, to use LVW interrupt function, before enabling LVWIE, LVWF must be cleared by writing
LVWACK first.
6
LVWACK
5
LVWIE
4–2
Reserved
1–0
LVWV
0 Low-voltage warning event not detected
1 Low-voltage warning event detected
Low-Voltage Warning Acknowledge
This write-only field is used to acknowledge low voltage warning errors. Write 1 to clear LVWF. Reads always return 0.
Low-Voltage Warning Interrupt Enable
Enables hardware interrupt requests for LVWF.
0 Hardware interrupt disabled (use polling)
1 Request a hardware interrupt when LVWF = 1
This field is reserved.
This read-only field is reserved and always has the value 0.
Low-Voltage Warning Voltage Select
Selects the LVW trip point voltage (V
LVW
). The actual voltage for the warning depends on LVDSC1[LVDV].
00 Low trip point selected (V
LVW
= V
LVW1
)
01 Mid 1 trip point selected (V
LVW
= V
10 Mid 2 trip point selected (V
LVW
= V
LVW2
)
LVW3
)
11 High trip point selected (V
LVW
= V
LVW4
)
14.5.3 Regulator Status And Control register (PMC_REGSC)
The PMC contains an internal voltage regulator. The voltage regulator design uses a bandgap reference that is also available through a buffer as input to certain internal peripherals, such as the CMP and ADC. The internal regulator provides a status bit
(REGONS) indicating the regulator is in run regulation.
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Chapter 14 Power Management Controller (PMC)
NOTE
This register is reset on Chip Reset Not VLLS and by reset types that trigger Chip Reset not VLLS. See the Reset section details for more information.
Address: 4007_D000h base + 2h offset = 4007_D002h
Bit
Read
Write
Reset
Field
7–6
Reserved
5
Reserved
4
BGEN
7
0
6
0
5
0
4
0
3
0
PMC_REGSC field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
2
1
1
0
0
0
Bandgap Enable In VLPx Operation
BGEN controls whether the bandgap is enabled in lower power modes of operation (VLPx, LLS, and
VLLSx). When on-chip peripherals require the bandgap voltage reference in low power modes of operation, set BGEN to continue to enable the bandgap operation.
NOTE: When the bandgap voltage reference is not needed in low power modes, clear BGEN to avoid excess power consumption.
3
ACKISO
2
REGONS
1
Reserved
0 Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
1 Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
Acknowledge Isolation
Reading this field indicates whether certain peripherals and the I/O pads are in a latched state as a result of having been in a VLLS mode. Writing 1 to this field when it is set releases the I/O pads and certain peripherals to their normal run mode state.
NOTE: After recovering from a VLLS mode, user should restore chip configuration before clearing
ACKISO. In particular, pin configuration for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from being falsely set when ACKISO is cleared.
0 Peripherals and I/O pads are in normal run state.
1 Certain peripherals and I/O pads are in an isolated and latched state.
Regulator In Run Regulation Status
This read-only field provides the current status of the internal voltage regulator.
0 Regulator is in stop regulation or in transition to/from it
1 Regulator is in run regulation
This field is reserved.
0
BGBE
NOTE: This reserved bit must remain cleared (set to 0).
Bandgap Buffer Enable
Enables the bandgap buffer.
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Memory map and register descriptions
PMC_REGSC field descriptions (continued)
Field Description
0 Bandgap buffer not enabled
1 Bandgap buffer enabled
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Chapter 15
Low-Leakage Wakeup Unit (LLWU)
15.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
The LLWU module allows the user to select up to 16 external pin sources and up to 8 internal modules as a wake-up source from low-leakage power modes.
The input sources are described in the device's chip configuration details. Each of the available wake-up sources can be individually enabled.
The LLWU module also includes two optional digital pin filters for the external wakeup pins.
See AN4503: Power Management for Kinetis and ColdFire+ MCUs for further details on using the LLWU.
15.1.1 Features
The LLWU module features include:
• Support for up to 16 external input pins and up to 8 internal modules with individual enable bits
• Input sources may be external pins or from internal peripherals capable of running in
LLS or VLLS. See the chip configuration information for wakeup input sources for this device.
• External pin wake-up inputs, each of which is programmable as falling-edge, risingedge, or any change
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Introduction
• Wake-up inputs that are activated if enabled after MCU enters a low-leakage power mode
• Optional digital filters provided to qualify an external pin detect. Note that when the
LPO clock is disabled, the filters are disabled and bypassed.
15.1.2 Modes of operation
The LLWU module becomes functional on entry into a low-leakage power mode. After recovery from LLS, the LLWU is immediately disabled. After recovery from VLLS, the
LLWU continues to detect wake-up events until the user has acknowledged the wake-up via a write to PMC_REGSC[ACKISO].
15.1.2.1 LLS mode
The wake-up events due to external wake-up inputs and internal module wake-up inputs result in an interrupt flow when exiting LLS.
NOTE
The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit Stop mode on an LLS recovery.
15.1.2.2 VLLS modes
All wakeup events result in VLLS exit via a reset flow.
15.1.2.3 Non-low leakage modes
The LLWU is not active in all non-low leakage modes where detection and control logic are in a static state. The LLWU registers are accessible in non-low leakage modes and are available for configuring and reading status when bus transactions are possible.
When the wake-up pin filters are enabled, filter operation begins immediately. If a low leakage mode is entered within five LPO clock cycles of an active edge, the edge event will be detected by the LLWU.
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Chapter 15 Low-Leakage Wakeup Unit (LLWU)
15.1.2.4 Debug mode
When the chip is in Debug mode and then enters LLS or a VLLSx mode, no debug logic works in the fully-functional low-leakage mode. Upon an exit from the LLS or VLLSx mode, the LLWU becomes inactive.
15.1.3 Block diagram
The following figure is the block diagram for the LLWU module.
enter low leakge mode
WUME7
Module7 interrupt flag
(LLWU_M7IF)
Interrupt module flag detect
LLWU_MWUF7 occurred
Internal module sources
LLWU_P0
Module0 interrupt flag
(LLWU_M0IF)
LLWU_P15
Interrupt module flag detect
LLWU_MWUF0 occurred
FILT1[FILTSEL]
Synchronizer
Synchronizer
FILT2[FILTSEL]
WUPE15
2
Edge detect
WUME0
LPO
Pin filter 1
LPO
Pin filter 2
FILT1[FILTE]
Edge detect
Pin filter 1 wakeup occurred
FILT2[FILTE]
Edge detect
Pin filter 2 wakeup occurred
LLWU controller
LLWU_P15 wakeup occurred exit low leakge mode interrupt flow reset flow
LLWU_P0 wakeup occurred
External pin sources
Edge detect
2
WUPE0
Figure 15-1. LLWU block diagram
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LLWU signal descriptions
15.2 LLWU signal descriptions
The signal properties of LLWU are shown in the table found here.
The external wakeup input pins can be enabled to detect either rising-edge, falling-edge, or on any change.
Signal
LLWU_Pn
Table 15-1. LLWU signal descriptions
Description
Wakeup inputs (n = 0-15)
I/O
I
15.3 Memory map/register definition
The LLWU includes the following registers:
• Wake-up source enable registers
• Enable external pin input sources
• Enable internal peripheral sources
• Wake-up flag registers
• Indication of wakeup source that caused exit from a low-leakage power mode includes external pin or internal module interrupt
• Wake-up pin filter enable registers
NOTE
The LLWU registers can be written only in supervisor mode.
Write accesses in user mode are blocked and will result in a bus error.
All LLWU registers are reset by Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. Each register's displayed reset value represents this subset of reset types.
LLWU registers are unaffected by reset types that do not trigger
Chip Reset not VLLS. For more information about the types of reset on this chip, refer to the
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LLWU memory map
Chapter 15 Low-Leakage Wakeup Unit (LLWU)
Absolute address
(hex)
Register name
4007_C000 LLWU Pin Enable 1 register (LLWU_PE1)
4007_C001 LLWU Pin Enable 2 register (LLWU_PE2)
4007_C002 LLWU Pin Enable 3 register (LLWU_PE3)
4007_C003 LLWU Pin Enable 4 register (LLWU_PE4)
4007_C004 LLWU Module Enable register (LLWU_ME)
4007_C005 LLWU Flag 1 register (LLWU_F1)
4007_C006 LLWU Flag 2 register (LLWU_F2)
4007_C007 LLWU Flag 3 register (LLWU_F3)
4007_C008 LLWU Pin Filter 1 register (LLWU_FILT1)
4007_C009 LLWU Pin Filter 2 register (LLWU_FILT2)
Width
(in bits)
Access Reset value
8
8
8
8
8
8
8
8
8
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Section/ page
15.3.1 LLWU Pin Enable 1 register (LLWU_PE1)
LLWU_PE1 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P3–LLWU_P0.
NOTE
This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the
Introduction details for more information.
Address: 4007_C000h base + 0h offset = 4007_C000h
7 6 5 Bit
Read
Write
Reset 0
0 0
4
0
Field
7–6
WUPE3
3
0
LLWU_PE1 field descriptions
Description
Wakeup Pin Enable For LLWU_P3
Enables and configures the edge detection for the wakeup pin.
2
0
5–4
WUPE2
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
Wakeup Pin Enable For LLWU_P2
Enables and configures the edge detection for the wakeup pin.
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1
0
0
0
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Memory map/register definition
LLWU_PE1 field descriptions (continued)
Field
3–2
WUPE1
Description
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
Wakeup Pin Enable For LLWU_P1
Enables and configures the edge detection for the wakeup pin.
1–0
WUPE0
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
Wakeup Pin Enable For LLWU_P0
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
15.3.2 LLWU Pin Enable 2 register (LLWU_PE2)
LLWU_PE2 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P7–LLWU_P4.
NOTE
This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the
Introduction details for more information.
Address: 4007_C000h base + 1h offset = 4007_C001h
7 6 5 Bit
Read
Write
Reset 0
0 0
4
0
Field
7–6
WUPE7
3
0
LLWU_PE2 field descriptions
Description
Wakeup Pin Enable For LLWU_P7
Enables and configures the edge detection for the wakeup pin.
2
0
00 External input pin disabled as wakeup input
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1
0
0
0
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Field
5–4
WUPE6
3–2
WUPE5
1–0
WUPE4
Chapter 15 Low-Leakage Wakeup Unit (LLWU)
LLWU_PE2 field descriptions (continued)
Description
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
Wakeup Pin Enable For LLWU_P6
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
Wakeup Pin Enable For LLWU_P5
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
Wakeup Pin Enable For LLWU_P4
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
15.3.3 LLWU Pin Enable 3 register (LLWU_PE3)
LLWU_PE3 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P11–LLWU_P8.
NOTE
This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the
Introduction details for more information.
Address: 4007_C000h base + 2h offset = 4007_C002h
7 6 5 Bit
Read
Write
Reset 0
0 0
4
0
3
0
2
0
1
0
0
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Memory map/register definition
Field
7–6
WUPE11
LLWU_PE3 field descriptions
Description
Wakeup Pin Enable For LLWU_P11
Enables and configures the edge detection for the wakeup pin.
5–4
WUPE10
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
Wakeup Pin Enable For LLWU_P10
Enables and configures the edge detection for the wakeup pin.
3–2
WUPE9
1–0
WUPE8
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
Wakeup Pin Enable For LLWU_P9
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
Wakeup Pin Enable For LLWU_P8
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
15.3.4 LLWU Pin Enable 4 register (LLWU_PE4)
LLWU_PE4 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P15–LLWU_P12.
NOTE
This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the
Introduction details for more information.
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Address: 4007_C000h base + 3h offset = 4007_C003h
Bit
Read
Write
Reset
Field
7–6
WUPE15
7 6 5 4 3
0 0 0 0 0
LLWU_PE4 field descriptions
Description
Wakeup Pin Enable For LLWU_P15
2
0
Enables and configures the edge detection for the wakeup pin.
1
0
0
0
5–4
WUPE14
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
Wakeup Pin Enable For LLWU_P14
3–2
WUPE13
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
Wakeup Pin Enable For LLWU_P13
Enables and configures the edge detection for the wakeup pin.
1–0
WUPE12
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
Wakeup Pin Enable For LLWU_P12
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
15.3.5 LLWU Module Enable register (LLWU_ME)
LLWU_ME contains the bits to enable the internal module flag as a wakeup input source for inputs MWUF7–MWUF0.
NOTE
This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset
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Memory map/register definition types that do not trigger Chip Reset not VLLS. See the
Introduction details for more information.
Address: 4007_C000h base + 4h offset = 4007_C004h
Bit
Read
Write
Reset
Field
7
WUME7
7
0
6
0
5
0
4
0
3
0
LLWU_ME field descriptions
Description
Wakeup Module Enable For Module 7
Enables an internal module as a wakeup source input.
6
WUME6
0 Internal module flag not used as wakeup source
1 Internal module flag used as wakeup source
Wakeup Module Enable For Module 6
Enables an internal module as a wakeup source input.
5
WUME5
4
WUME4
3
WUME3
2
WUME2
1
WUME1
0 Internal module flag not used as wakeup source
1 Internal module flag used as wakeup source
Wakeup Module Enable For Module 5
Enables an internal module as a wakeup source input.
0 Internal module flag not used as wakeup source
1 Internal module flag used as wakeup source
Wakeup Module Enable For Module 4
Enables an internal module as a wakeup source input.
0 Internal module flag not used as wakeup source
1 Internal module flag used as wakeup source
Wakeup Module Enable For Module 3
Enables an internal module as a wakeup source input.
0 Internal module flag not used as wakeup source
1 Internal module flag used as wakeup source
Wakeup Module Enable For Module 2
Enables an internal module as a wakeup source input.
0 Internal module flag not used as wakeup source
1 Internal module flag used as wakeup source
Wakeup Module Enable for Module 1
Enables an internal module as a wakeup source input.
0 Internal module flag not used as wakeup source
1 Internal module flag used as wakeup source
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0
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Field
0
WUME0
Chapter 15 Low-Leakage Wakeup Unit (LLWU)
LLWU_ME field descriptions (continued)
Description
Wakeup Module Enable For Module 0
Enables an internal module as a wakeup source input.
0 Internal module flag not used as wakeup source
1 Internal module flag used as wakeup source
15.3.6 LLWU Flag 1 register (LLWU_F1)
LLWU_F1 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow.
For VLLS, this is the source causing the MCU reset flow.
The external wakeup flags are read-only and clearing a flag is accomplished by a write of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will remain set if the associated WUPEx bit is cleared.
NOTE
This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the
Introduction details for more information.
Address: 4007_C000h base + 5h offset = 4007_C005h
Bit
Read
Write
Reset
Field
7
WUF7
7
0
6
0
5
0
4
0
3
0
LLWU_F1 field descriptions
Description
Wakeup Flag For LLWU_P7
6
WUF6
2
0
1
0
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF7.
0 LLWU_P7 input was not a wakeup source
1 LLWU_P7 input was a wakeup source
Wakeup Flag For LLWU_P6
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF6.
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Memory map/register definition
Field
5
WUF5
LLWU_F1 field descriptions (continued)
0 LLWU_P6 input was not a wakeup source
1 LLWU_P6 input was a wakeup source
Wakeup Flag For LLWU_P5
Description
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF5.
4
WUF4
3
WUF3
2
WUF2
1
WUF1
0
WUF0
0 LLWU_P5 input was not a wakeup source
1 LLWU_P5 input was a wakeup source
Wakeup Flag For LLWU_P4
Indicates that an enabled external wake-up pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF4.
0 LLWU_P4 input was not a wakeup source
1 LLWU_P4 input was a wakeup source
Wakeup Flag For LLWU_P3
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF3.
0 LLWU_P3 input was not a wake-up source
1 LLWU_P3 input was a wake-up source
Wakeup Flag For LLWU_P2
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF2.
0 LLWU_P2 input was not a wakeup source
1 LLWU_P2 input was a wakeup source
Wakeup Flag For LLWU_P1
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF1.
0 LLWU_P1 input was not a wakeup source
1 LLWU_P1 input was a wakeup source
Wakeup Flag For LLWU_P0
Indicates that an enabled external wake-up pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF0.
0 LLWU_P0 input was not a wakeup source
1 LLWU_P0 input was a wakeup source
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15.3.7 LLWU Flag 2 register (LLWU_F2)
LLWU_F2 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow.
For VLLS, this is the source causing the MCU reset flow.
The external wakeup flags are read-only and clearing a flag is accomplished by a write of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will remain set if the associated WUPEx bit is cleared.
NOTE
This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the
Introduction details for more information.
Address: 4007_C000h base + 6h offset = 4007_C006h
Bit
Read
Write
Reset
Field
7
WUF15
7
0
6
0
5
0
4
0
3
0
LLWU_F2 field descriptions
Description
Wakeup Flag For LLWU_P15
6
WUF14
2
0
1
0
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF15.
0 LLWU_P15 input was not a wakeup source
1 LLWU_P15 input was a wakeup source
Wakeup Flag For LLWU_P14
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF14.
0
0
5
WUF13
0 LLWU_P14 input was not a wakeup source
1 LLWU_P14 input was a wakeup source
Wakeup Flag For LLWU_P13
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF13.
0 LLWU_P13 input was not a wakeup source
1 LLWU_P13 input was a wakeup source
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Memory map/register definition
Field
4
WUF12
LLWU_F2 field descriptions (continued)
Description
Wakeup Flag For LLWU_P12
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF12.
3
WUF11
2
WUF10
1
WUF9
0
WUF8
0 LLWU_P12 input was not a wakeup source
1 LLWU_P12 input was a wakeup source
Wakeup Flag For LLWU_P11
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF11.
0 LLWU_P11 input was not a wakeup source
1 LLWU_P11 input was a wakeup source
Wakeup Flag For LLWU_P10
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF10.
0 LLWU_P10 input was not a wakeup source
1 LLWU_P10 input was a wakeup source
Wakeup Flag For LLWU_P9
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF9.
0 LLWU_P9 input was not a wakeup source
1 LLWU_P9 input was a wakeup source
Wakeup Flag For LLWU_P8
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF8.
0 LLWU_P8 input was not a wakeup source
1 LLWU_P8 input was a wakeup source
15.3.8 LLWU Flag 3 register (LLWU_F3)
LLWU_F3 contains the wakeup flags indicating which internal wakeup source caused the
MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
For internal peripherals that are capable of running in a low-leakage power mode, such as a real time clock module or CMP module, the flag from the associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared in the peripheral instead of writing a 1 to the MWUFx bit.
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NOTE
This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the
Introduction details for more information.
Address: 4007_C000h base + 7h offset = 4007_C007h
Bit 7
Read
Write
Reset 0
Field
7
MWUF7
6
0
5
0
4
0
3
0
LLWU_F3 field descriptions
Description
Wakeup flag For module 7
2
0
1
0
0
0
Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism.
6
MWUF6
5
MWUF5
4
MWUF4
3
MWUF3
2
MWUF2
0 Module 7 input was not a wakeup source
1 Module 7 input was a wakeup source
Wakeup flag For module 6
Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism.
0 Module 6 input was not a wakeup source
1 Module 6 input was a wakeup source
Wakeup flag For module 5
Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism.
0 Module 5 input was not a wakeup source
1 Module 5 input was a wakeup source
Wakeup flag For module 4
Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism.
0 Module 4 input was not a wakeup source
1 Module 4 input was a wakeup source
Wakeup flag For module 3
Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism.
0 Module 3 input was not a wakeup source
1 Module 3 input was a wakeup source
Wakeup flag For module 2
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Memory map/register definition
Field
LLWU_F3 field descriptions (continued)
Description
Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism.
1
MWUF1
0 Module 2 input was not a wakeup source
1 Module 2 input was a wakeup source
Wakeup flag For module 1
Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism.
0
MWUF0
0 Module 1 input was not a wakeup source
1 Module 1 input was a wakeup source
Wakeup flag For module 0
Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism.
0 Module 0 input was not a wakeup source
1 Module 0 input was a wakeup source
15.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)
LLWU_FILT1 is a control and status register that is used to enable/disable the digital filter 1 features for an external pin.
NOTE
This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the
Introduction details for more information.
Address: 4007_C000h base + 8h offset = 4007_C008h
6 5 Bit
Read
Write
Reset
7
0 0
0
4
3
0 0
LLWU_FILT1 field descriptions
Description Field
7
FILTF
Filter Detect Flag
2
0
1
0
0
0
Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage power mode. To clear the flag write a one to FILTF.
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Field
6–5
FILTE
4
Reserved
3–0
FILTSEL
Chapter 15 Low-Leakage Wakeup Unit (LLWU)
LLWU_FILT1 field descriptions (continued)
Description
0 Pin Filter 1 was not a wakeup source
1 Pin Filter 1 was a wakeup source
Digital Filter On External Pin
Controls the digital filter options for the external pin detect.
00 Filter disabled
01 Filter posedge detect enabled
10 Filter negedge detect enabled
11 Filter any edge detect enabled
This field is reserved.
This read-only field is reserved and always has the value 0.
Filter Pin Select
Selects 1 out of the 16 wakeup pins to be muxed into the filter.
0000 Select LLWU_P0 for filter
...
...
1111 Select LLWU_P15 for filter
15.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)
LLWU_FILT2 is a control and status register that is used to enable/disable the digital filter 2 features for an external pin.
NOTE
This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the
Introduction details for more information.
Address: 4007_C000h base + 9h offset = 4007_C009h
6 5 Bit
Read
Write
Reset
7
0 0
4
3
0 0 0
LLWU_FILT2 field descriptions
Description Field
7
FILTF
Filter Detect Flag
2
0
1
0
0
0
Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage power mode. To clear the flag write a one to FILTF.
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Functional description
Field
6–5
FILTE
LLWU_FILT2 field descriptions (continued)
Description
0 Pin Filter 2 was not a wakeup source
1 Pin Filter 2 was a wakeup source
Digital Filter On External Pin
Controls the digital filter options for the external pin detect.
4
Reserved
3–0
FILTSEL
00 Filter disabled
01 Filter posedge detect enabled
10 Filter negedge detect enabled
11 Filter any edge detect enabled
This field is reserved.
This read-only field is reserved and always has the value 0.
Filter Pin Select
Selects 1 out of the 16 wakeup pins to be muxed into the filter.
0000 Select LLWU_P0 for filter
...
...
1111 Select LLWU_P15 for filter
15.4 Functional description
This on-chip peripheral module is called a low-leakage wakeup unit (LLWU) module because it allows internal peripherals and external input pins as a source of wakeup from low-leakage modes.
It is operational only in LLS and VLLSx modes.
The LLWU module contains pin enables for each external pin and internal module. For each external pin, the user can disable or select the edge type for the wakeup. Type options are:
• Falling-edge
• Rising-edge
• Either-edge
When an external pin is enabled as a wakeup source, the pin must be configured as an input pin.
The LLWU implements optional 3-cycle glitch filters, based on the LPO clock. A detected external pin is required to remain asserted until the enabled glitch filter times out. Additional latency of up to 2 cycles is due to synchronization, which results in a total
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Chapter 15 Low-Leakage Wakeup Unit (LLWU) of up to 5 cycles of delay before the detect circuit alerts the system to the wakeup or reset event when the filter function is enabled. Two wakeup detect filters are available for selected external pins. Glitch filtering is not provided on the internal modules.
For internal module wakeup operation, the WUMEx bit enables the associated module as a wakeup source.
15.4.1 LLS mode
Wakeup events triggered from either an external pin input or an internal module input result in a CPU interrupt flow to begin user code execution.
15.4.2 VLLS modes
In the case of a wakeup due to external pin or internal module wakeup, recovery is always via a reset flow and RCM_SRS[WAKEUP] is set indicating the low-leakage mode was active. State retention data is lost and I/O will be restored after
PMC_REGSC[ACKISO] has been written.
15.4.3 Initialization
For an enabled peripheral wakeup input, the peripheral flag must be cleared by software before entering LLS or VLLSx mode to avoid an immediate exit from the mode.
Flags associated with external input pins, filtered and unfiltered, must also be cleared by software prior to entry to LLS or VLLSx mode.
After enabling an external pin filter or changing the source pin, wait at least five LPO clock cycles before entering LLS or VLLSx mode to allow the filter to initialize.
NOTE
After recovering from a VLLS mode, user must restore chip configuration before clearing PMC_REGSC[ACKISO]. In particular, pin configuration for enabled LLWU wake-up pins must be restored to avoid any LLWU flag from being falsely set when PMC_REGSC[ACKISO] is cleared.
The signal selected as a wake-up source pin must be a digital pin, as selected in the pin mux control.
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Functional description
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Chapter 16
Reset Control Module (RCM)
16.1 Introduction
Information found here describes the registers of the Reset Control Module (RCM). The
RCM implements many of the reset functions for the chip. See the chip's reset chapter for more information.
See AN4503: Power Management for Kinetis and ColdFire+ MCUs for further details on using the RCM.
16.2 Reset memory map and register descriptions
The RCM Memory Map/Register Definition can be found here.
The Reset Control Module (RCM) registers provide reset status information and reset filter control.
NOTE
The RCM registers can be written only in supervisor mode.
Write accesses in user mode are blocked and will result in a bus error.
RCM memory map
Absolute address
(hex)
Register name
4007_F000 System Reset Status Register 0 (RCM_SRS0)
4007_F001 System Reset Status Register 1 (RCM_SRS1)
4007_F004 Reset Pin Filter Control register (RCM_RPFC)
4007_F005 Reset Pin Filter Width register (RCM_RPFW)
Width
(in bits)
Access Reset value
8
8
8
8
R
R
R/W
R/W
82h
00h
00h
00h
Section/ page
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Reset memory map and register descriptions
16.2.1 System Reset Status Register 0 (RCM_SRS0)
This register includes read-only status flags to indicate the source of the most recent reset. The reset state of these bits depends on what caused the MCU to reset.
NOTE
The reset value of this register depends on the reset source:
• POR (including LVD) — 0x82
• LVD (without POR) — 0x02
• VLLS mode wakeup due to RESET pin assertion — 0x41
• VLLS mode wakeup due to other wakeup sources — 0x01
• Other reset — a bit is set if its corresponding reset source caused the reset
Address: 4007_F000h base + 0h offset = 4007_F000h
Bit
Read
Write
Reset
7
1
6
0
5
4
3
0 0 0
RCM_SRS0 field descriptions
Description Field
7
POR
Power-On Reset
6
PIN
2
0
1
1
0
0
Indicates a reset has been caused by the power-on detection logic. Because the internal supply voltage was ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while the internal supply was below the LVD threshold.
0 Reset not caused by POR
1 Reset caused by POR
External Reset Pin
5
WDOG
Indicates a reset has been caused by an active-low level on the external RESET pin.
0 Reset not caused by external reset pin
1 Reset caused by external reset pin
Watchdog
Indicates a reset has been caused by the watchdog timer timing out. This reset source can be blocked by disabling the watchdog.
4
Reserved
0 Reset not caused by watchdog timeout
1 Reset caused by watchdog timeout
This field is reserved.
This read-only field is reserved and always has the value 0.
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Field
3
LOL
2
LOC
1
LVD
0
WAKEUP
Chapter 16 Reset Control Module (RCM)
RCM_SRS0 field descriptions (continued)
Description
Loss-of-Lock Reset
Indicates a reset has been caused by a loss of lock in the MCG PLL. See the MCG description for information on the loss-of-clock event.
0 Reset not caused by a loss of lock in the PLL
1 Reset caused by a loss of lock in the PLL
Loss-of-Clock Reset
Indicates a reset has been caused by a loss of external clock. The MCG clock monitor must be enabled for a loss of clock to be detected. Refer to the detailed MCG description for information on enabling the clock monitor.
0 Reset not caused by a loss of external clock.
1 Reset caused by a loss of external clock.
Low-Voltage Detect Reset
If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage, an LVD reset occurs.
This field is also set by POR.
0 Reset not caused by LVD trip or POR
1 Reset caused by LVD trip or POR
Low Leakage Wakeup Reset
Indicates a reset has been caused by an enabled LLWU module wakeup source while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx mode causes a reset. This bit is cleared by any reset except
WAKEUP.
0 Reset not caused by LLWU module wakeup source
1 Reset caused by LLWU module wakeup source
16.2.2 System Reset Status Register 1 (RCM_SRS1)
This register includes read-only status flags to indicate the source of the most recent reset. The reset state of these bits depends on what caused the MCU to reset.
NOTE
The reset value of this register depends on the reset source:
• POR (including LVD) — 0x00
• LVD (without POR) — 0x00
• VLLS mode wakeup — 0x00
• Other reset — a bit is set if its corresponding reset source caused the reset
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Reset memory map and register descriptions
Address: 4007_F000h base + 1h offset = 4007_F001h
Bit
Read
Write
Reset
7
6
5
Field
7
Reserved
6
Reserved
5
SACKERR
4
3
0 0 0 0 0
RCM_SRS1 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
Stop Mode Acknowledge Error Reset
4
Reserved
3
MDM_AP
2
0
1
0
0
0
Indicates that after an attempt to enter Stop mode, a reset has been caused by a failure of one or more peripherals to acknowledge within approximately one second to enter stop mode.
0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode
This field is reserved.
This read-only field is reserved and always has the value 0.
MDM-AP System Reset Request
2
SW
Indicates a reset has been caused by the host debugger system setting of the System Reset Request bit in the MDM-AP Control Register.
0 Reset not caused by host debugger system setting of the System Reset Request bit
1 Reset caused by host debugger system setting of the System Reset Request bit
Software
Indicates a reset has been caused by software setting of SYSRESETREQ bit in Application Interrupt and
Reset Control Register in the ARM core.
1
LOCKUP
0
Reserved
0 Reset not caused by software setting of SYSRESETREQ bit
1 Reset caused by software setting of SYSRESETREQ bit
Core Lockup
Indicates a reset has been caused by the ARM core indication of a LOCKUP event.
0 Reset not caused by core LOCKUP event
1 Reset caused by core LOCKUP event
This field is reserved.
This read-only field is reserved and always has the value 0.
16.2.3 Reset Pin Filter Control register (RCM_RPFC)
NOTE
The reset values of bits 2-0 are for Chip POR only. They are unaffected by other reset types.
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NOTE
The bus clock filter is reset when disabled or when entering stop mode. The LPO filter is reset when disabled .
Address: 4007_F000h base + 4h offset = 4007_F004h
Bit
Read
Write
Reset
Field
7–3
Reserved
2
RSTFLTSS
7 6 5
4 3
0 0 0 0 0
RCM_RPFC field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Reset Pin Filter Select in Stop Mode
2
0
1
0
0 0
Selects how the reset pin filter is enabled in Stop and VLPS modes , and also during LLS and VLLS modes. On exit from VLLS mode, this bit should be reconfigured before clearing PMC_REGSC[ACKISO].
1–0
RSTFLTSRW
0 All filtering disabled
1 LPO clock filter enabled
Reset Pin Filter Select in Run and Wait Modes
Selects how the reset pin filter is enabled in run and wait modes.
00 All filtering disabled
01 Bus clock filter enabled for normal operation
10 LPO clock filter enabled for normal operation
11 Reserved
16.2.4 Reset Pin Filter Width register (RCM_RPFW)
NOTE
The reset values of the bits in the RSTFLTSEL field are for
Chip POR only. They are unaffected by other reset types.
Address: 4007_F000h base + 5h offset = 4007_F005h
Bit
Read
Write
Reset
7
0
6
0
5
0
4
0
3
0
2
0 0
1 0
0
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RCM_RPFW field descriptions
Field
7–5
Reserved
4–0
RSTFLTSEL
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Reset Pin Filter Bus Clock Select
Selects the reset pin bus clock filter width.
00000 Bus clock filter count is 1
00001 Bus clock filter count is 2
00010 Bus clock filter count is 3
00011 Bus clock filter count is 4
00100 Bus clock filter count is 5
00101 Bus clock filter count is 6
00110 Bus clock filter count is 7
00111 Bus clock filter count is 8
01000 Bus clock filter count is 9
01001 Bus clock filter count is 10
01010 Bus clock filter count is 11
01011 Bus clock filter count is 12
01100 Bus clock filter count is 13
01101 Bus clock filter count is 14
01110 Bus clock filter count is 15
01111 Bus clock filter count is 16
10000 Bus clock filter count is 17
10001 Bus clock filter count is 18
10010 Bus clock filter count is 19
10011 Bus clock filter count is 20
10100 Bus clock filter count is 21
10101 Bus clock filter count is 22
10110 Bus clock filter count is 23
10111 Bus clock filter count is 24
11000 Bus clock filter count is 25
11001 Bus clock filter count is 26
11010 Bus clock filter count is 27
11011 Bus clock filter count is 28
11100 Bus clock filter count is 29
11101 Bus clock filter count is 30
11110 Bus clock filter count is 31
11111 Bus clock filter count is 32
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Chapter 17
Bit Manipulation Engine (BME)
The Bit Manipulation Engine (BME) provides hardware support for atomic read-modifywrite memory operations to the peripheral address space in ARM ® Cortex ™ -M0+ based microcontrollers. This architectural capability is also known as "decorated storage." By combining the basic load and store instructions of the Cortex-M instruction set architecture (v6M, v7M) with the concept of decorated storage provided by the BME, the resulting implementation provides a robust and efficient read-modify-write capability to this class of ultra low-end microcontrollers.
17.1 Introduction
The Bit Manipulation Engine (BME) provides hardware support for atomic read-modifywrite memory operations to the peripheral address space in Cortex-M0+ based microcontrollers.
This architectural capability is also known as "decorated storage" as it defines a mechanism for providing additional semantics for load and store operations to memorymapped peripherals beyond just the reading and writing of data values to the addressed memory locations. In the BME definition, the "decoration", that is, the additional semantic information, is encoded into the peripheral address used to reference the memory.
By combining the basic load and store instructions of the ARM Cortex-M instruction set architecture (v6M, v7M) with the concept of decorated storage provided by the BME, the resulting implementation provides a robust and efficient read-modify-write capability to this class of ultra low-end microcontrollers. The resulting architectural capability defined by this core platform function is targeted at the manipulation of n-bit fields in peripheral registers and is consistent with I/O hardware addressing in the Embedded C standard. For most BME commands, a single core read or write bus cycle is converted into an atomic read-modify-write, that is, an indivisible "read followed by a write" bus sequence.
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Introduction
BME decorated references are only available on system bus transactions generated by the processor core and targeted at the standard 512 KB peripheral address space based at
0x4000_0000
. The decoration semantic is embedded into address bits[28:19], creating a
448 MB space at addresses 0x4400_0000–0x5FFF_FFFF for AIPS; these bits are stripped out of the actual address sent to the peripheral bus controller and used by the
BME to define and control its operation.
17.1.1 Overview
The following figure is a generic block diagram of the processor core and platform for this class of ultra low-end microcontrollers.
Cortex-M0+ Core
Dbg Fetch
NVIC
AHB Bus
AGU
LD/ST
Dec
SHFT
ALU
IO Port
Rn
MUL
MTB Port
CM0+ Core Platform
32
PRAM
RAM
Array
GPIO
Alt-Master
DMA_4ch m0 s1 m3
AXBS
-Lite s2 m2 s0
BME PBRIDGE
32
Slave
Peripherals
32
FMC
NVM
Array
Note: BME can be accessed only by the core.
Figure 17-1. Cortex-M0+ core platform block diagram
As shown in the block diagram, the BME module interfaces to a crossbar switch AHB slave port as its primary input and sources an AHB bus output to the Peripheral Bridge
(PBRIDGE) controller. The BME hardware microarchitecture is a 2-stage pipeline design
1. To be perfectly accurate, the peripheral address space occupies a 516 KB region: 512 KB based at 0x4000_0000 plus a 4
KB space based at 0x400F_F000 for GPIO accesses. This organization provides compatibility with the Kinetis K Family.
Attempted accesses to the memory space located between 0x4008_0000 - 0x400F_EFFF are error terminated due to an illegal address.
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Chapter 17 Bit Manipulation Engine (BME) matching the protocol of the AMBA-AHB system bus interfaces. The PBRIDGE module converts the AHB system bus protocol into the IPS/APB protocol used by the attached slave peripherals.
17.1.2 Features
The key features of the BME include:
• Lightweight implementation of decorated storage for selected address spaces
• Additional access semantics encoded into the reference address
• Resides between a crossbar switch slave port and a peripheral bridge bus controller
• Two-stage pipeline design matching the AHB system bus protocol
• Combinationally passes non-decorated accesses to peripheral bridge bus controller
• Conversion of decorated loads and stores from processor core into atomic readmodify-writes
• Decorated loads support unsigned bit field extracts, load-and-{set,clear} 1-bit operations
• Decorated stores support bit field inserts, logical AND, OR, and XOR operations
• Support for byte, halfword and word-sized decorated operations
• Supports minimum signal toggling on AHB output bus to reduce power dissipation
17.1.3 Modes of operation
The BME module does not support any special modes of operation. As a memorymapped device located on a crossbar slave AHB system bus port, BME responds strictly on the basis of memory addresses for accesses to the peripheral bridge bus controller.
All functionality associated with the BME module resides in the core platform's clock domain; this includes its connections with the crossbar slave port and the PBRIDGE bus controller.
17.2 Memory map and register definition
The BME module provides a memory-mapped capability and does not include any programming model registers.
The exact set of functions supported by the BME are detailed in the Functional description
.
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Functional description
The peripheral address space occupies a 516 KB region: 512 KB based at 0x4000_0000 plus a 4 KB space based at 0x400F_F000 for GPIO accesses; the decorated address space is mapped to the 448 MB region located at 0x4400_0000–0x5FFF_FFFF.
17.3 Functional description
Information found here details the specific functions supported by the BME.
Recall the combination of the basic load and store instructions of the Cortex-M instruction set architecture (v6M, v7M) plus the concept of decorated storage provided by the BME, the resulting implementation provides a robust and efficient read-modify-write capability to this class of ultra low-end microcontrollers. The resulting architectural capability defined by this core platform function is targeted at the manipulation of n-bit fields in peripheral registers and is consistent with I/O hardware addressing in the
Embedded C standard. For most BME commands, a single core read or write bus cycle is converted into an atomic read-modify-write, that is, an indivisible "read followed by a write" bus sequence.
Consider decorated store operations first, then decorated loads.
17.3.1 BME decorated stores
The functions supported by the BME's decorated stores include three logical operators
(AND, OR, XOR) plus a bit field insert.
For all these operations, BME converts a single decorated AHB store transaction into a 2cycle atomic read-modify-write sequence, where the combined read-modify operation is performed in the first AHB data phase, and then the write is performed in the second
AHB data phase.
A generic timing diagram of a decorated store showing a peripheral bit field insert operation is shown as follows:
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CYCLE RULER hclk
BME AHB Input Bus mx_haddr mx_hattr mx_hwrite mx_hwdata mx_hrdata mx_hready
BME AHB Output Bus sx_haddr sx_hattr sx_hwrite sx_hwdata sx_hrdata sx_hready
BME States + Datapath control_state_dp1 control_state_dp2 reg_addr_data_dp x
5..v_wxyz
400v_wxyz x+1
400v_wxyz rdata
5..v_wxyz
next next next
Chapter 17 Bit Manipulation Engine (BME) x+2 x+3 wdata next next next wdata bfi rdata wdata bfi rdata
Figure 17-2. Decorated store: bit field insert timing diagram
All the decorated store operations follow the same execution template shown in Figure
, a two-cycle read-modify-write operation:
1. Cycle x, 1st AHB address phase: Write from input bus is translated into a read operation on the output bus using the actual memory address (with the decoration removed) and then captured in a register.
2. Cycle x+1, 2nd AHB address phase: Write access with the registered (but actual) memory address is output
3. Cycle x+1, 1st AHB data phase: Memory read data is modified using the input bus write data and the function defined by the decoration and captured in a data register; the input bus cycle is stalled.
4. Cycle x+2, 2nd AHB data phase: Registered write data is sourced onto the output write data bus.
NOTE
Any wait states inserted by the slave device are simply passed through the BME back to the master input bus, stalling the
AHB transaction cycle for cycle.
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Functional description
17.3.1.1 Decorated store logical AND (AND)
This command performs an atomic read-modify-write of the referenced memory location.
1. First, the location is read;
2. It is then modified by performing a logical AND operation using the write data operand sourced for the system bus cycle
3. Finally, the result of the AND operation is written back into the referenced memory location.
The data size is specified by the write operation and can be byte (8-bit), halfword (16-bit) or word (32-bit). The core performs the required write data lane replication on byte and halfword transfers.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ioandb 0 * * 0 0 1 mem_addr ioandh 0 * * 0 0 1 mem_addr 0 ioandw 0 * * 0 0 1 mem_addr 0 0
Figure 17-3. Decorated store address: logical AND
See
where addr[30:29] = 10 for peripheral, addr[28:26] = 001 specifies the
AND operation, and mem_addr[19:0] specifies the address offset into the space based at
0x4000_0000 for peripherals. The "-" indicates an address bit "don't care".
The decorated AND write operation is defined in the following pseudo-code as: ioand<sz>(accessAddress, wdata) // decorated store AND tmp = mem[accessAddress & 0xE00FFFFF, size] // memory read tmp = tmp & wdata // modify mem[accessAddress & 0xE00FFFFF, size] = tmp // memory write where the operand size <sz> is defined as b(yte, 8-bit), h(alfword, 16-bit) and w(ord, 32bit). This notation is used throughout the document.
In the cycle definition tables, the notations AHB_ap and AHB_dp refer to the address and data phases of the BME AHB transaction. The cycle-by-cycle BME operations are detailed in the following table.
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Table 17-1. Cycle definitions of decorated store: logical AND
Pipeline stage
BME AHB_ap
BME AHB_dp x
Forward addr to memory;
Decode decoration; Convert master_wt to slave_rd;
Capture address, attributes
<previous>
Cycle x+1
Recirculate captured addr + attr to memory as slave_wt
Perform memory read; Form
(rdata & wdata) and capture destination data in register x+2
<next>
Perform write sending registered data to memory
17.3.1.2 Decorated store logical OR (OR)
This command performs an atomic read-modify-write of the referenced memory location.
1. First, the location is read.
2. It is then modified by performing a logical OR operation using the write data operand sourced for the system bus cycle.
3. Finally, the result of the OR operation is written back into the referenced memory location.
The data size is specified by the write operation and can be byte (8-bit), halfword (16-bit) or word (32-bit). The core performs the required write data lane replication on byte and halfword transfers.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ioorb 0
* *
0 1 0 mem_addr ioorh 0 * * 0 1 0 mem_addr 0 ioorw 0 * * 0 1 0 mem_addr 0 0
Figure 17-4. Decorated address store: logical OR
See
,where addr[30:29] =10 for peripheral, addr[28:26] = 010 specifies the
OR operation, and mem_addr[19:0] specifies the address offset into the space based at
0x4000_0000 for peripherals. The "-" indicates an address bit "don't care".
The decorated OR write operation is defined in the following pseudo-code as: ioor<sz>(accessAddress, wdata) // decorated store OR tmp = mem[accessAddress & 0xE00FFFFF, size] // memory read tmp = tmp | wdata // modify mem[accessAddress & 0xE00FFFFF, size] = tmp // memory write
The cycle-by-cycle BME operations are detailed in the following table.
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Table 17-2. Cycle definitions of decorated store: logical OR
Pipeline stage
BME AHB_ap
BME AHB_dp x
Forward addr to memory;
Decode decoration; Convert master_wt to slave_rd;
Capture address, attributes
<previous>
Cycle x+1
Recirculate captured addr + attr to memory as slave_wt
Perform memory read; Form
(rdata | wdata) and capture destination data in register x+2
<next>
Perform write sending registered data to memory
17.3.1.3 Decorated store logical XOR (XOR)
This command performs an atomic read-modify-write of the referenced memory location.
1. First, the location is read.
2. It is then modified by performing a logical XOR (exclusive-OR) operation using the write data operand sourced for the system bus cycle.
3. Finally, the result of the XOR operation is written back into the referenced memory location.
The data size is specified by the write operation and can be byte (8-bit), halfword (16-bit) or word (32-bit). The core performs the required write data lane replication on byte and halfword transfers.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ioxorb 0
* *
0 1 1 mem_addr ioxorh 0 * * 0 1 1 mem_addr 0 ioxorw 0 * * 0 1 1 mem_addr 0 0
Figure 17-5. Decorated address store: logical XOR
See
, where addr[30:29] =10 for peripheral, addr[28:26] = 011 specifies the
XOR operation, and mem_addr[19:0] specifies the address offset into the peripheral space based at 0x4000_0000 for peripherals. The "-" indicates an address bit "don't care".
The decorated XOR write operation is defined in the following pseudo-code as: ioxor<sz>(accessAddress, wdata) // decorated store XOR tmp = mem[accessAddress & 0xE00FFFFF, size] // memory read tmp = tmp ^ wdata // modify mem[accessAddress & 0xE00FFFFF, size] = tmp // memory write
The cycle-by-cycle BME operations are detailed in the following table.
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Chapter 17 Bit Manipulation Engine (BME)
Table 17-3. Cycle definitions of decorated store: logical XOR
Pipeline Stage
BME AHB_ap
BME AHB_dp x
Forward addr to memory;
Decode decoration; Convert master_wt to slave_rd;
Capture address, attributes
<previous>
Cycle x+1
Recirculate captured addr + attr to memory as slave_wt
Perform memory read; Form
(rdata ^ wdata) and capture destination data in register x+2
<next>
Perform write sending registered data to memory
17.3.1.4 Decorated store bit field insert (BFI)
This command inserts a bit field contained in the write data operand, defined by LSB position (b) and the bit field width (w+1), into the memory "container" defined by the access size associated with the store instruction using an atomic read-modify-write sequence.
The data size is specified by the write operation and can be byte (8-bit), halfword (16-bit) or word (32-bit).
NOTE
For the word sized operation, the maximum bit field width is 16 bits. The core performs the required write data lane replication on byte and halfword transfers.
The BFI operation can be used to insert a single bit into a peripheral. For this case, the w field is simply set to 0, indicating a bit field width of 1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 iobfib 0
* *
1 b b b - w w w mem_addr iobfih 0 * * 1 b b b b w w w w mem_addr 0 iobfiw 0 * * 1 b b b b b w w w w mem_addr 0 0
Figure 17-6. Decorated address store: bit field insert where addr[30:29] =10 for peripheral,addr[28] = 1 signals a BFI operation, addr[27:23] is
"b", the LSB identifier, addr[22:19] is "w", the bit field width minus 1 identifier, and addr[18:0] specifies the address offset into the peripheral space based at 0x4000_0000 for peripherals. The "-" indicates an address bit "don't care". Note, unlike the other decorated store operations, BFI uses addr[19] as the least significant bit in the "w" specifier and not as an address bit.
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Functional description
The decorated BFI write operation is defined in the following pseudo-code as: iobfi<sz>(accessAddress, wdata) // decorated bit field insert tmp = mem[accessAddress & 0xE007FFFF, size] // memory read mask = ((1 << (w+1)) - 1) << b // generate bit mask tmp = tmp & ~mask // modify
| wdata & mask mem[accessAddress & 0xE007FFFF, size] = tmp // memory write
The write data operand (wdata) associated with the store instruction contains the bit field to be inserted. It must be properly aligned within a right-aligned container, that is, within the lower 8 bits for a byte operation, the lower 16 bits for a halfword, or the entire 32 bits for a word operation.
To illustrate, consider the following example of the insertion of the 3-bit field "xyz" into an 8-bit memory container, initially set to "abcd_efgh". For all cases, w is 2, signaling a bit field width of 3.
if b = 0 and the decorated store (strb) Rt register[7:0] = ----_-xyz,
then destination is "abcd_exyz" if b = 1 and the decorated store (strb) Rt register[7:0] = ----_xyz-,
then destination is "abcd_xyzh" if b = 2 and the decorated store (strb) Rt register[7:0] = ---x_yz--,
then destination is "abcx_yzgh" if b = 3 and the decorated store (strb) Rt register[7:0] = --xy_z---,
then destination is "abxy_zfgh" if b = 4 and the decorated store (strb) Rt register[7:0] = -xyz_----,
then destination is "axyz_efgh" if b = 5 and the decorated store (strb) Rt register[7:0] = xyz-_----,
then destination is "xyzd_efgh" if b = 6 and the decorated store (strb) Rt register[7:0] = yz--_----,
then destination is "yzcd_efgh" if b = 7 and the decorated store (strb) Rt register[7:0] = z---_----,
then destination is "zbcd_efgh"
Note from the example, when the starting bit position plus the field width exceeds the container size, only part of the source bit field is inserted into the destination memory location. Stated differently, if (b + w+1) > container_width, only the low-order
"container_width - b" bits are actually inserted.
The cycle-by-cycle BME operations are detailed in the following table.
Table 17-4. Cycle definitions of decorated store: bit field insert
Pipeline stage
BME AHB_ap
BME AHB_dp x
Forward addr to memory;
Decode decoration; Convert master_wt to slave_rd;
Capture address, attributes
<previous>
Cycle x+1
Recirculate captured addr + attr to memory as slave_wt
Perform memory read; Form bit mask; Form bitwise
((mask) ? wdata : rdata)) and capture destination data in register x+2
<next>
Perform write sending registered data to memory
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Chapter 17 Bit Manipulation Engine (BME)
17.3.2 BME decorated loads
The functions supported by the BME's decorated loads include two single-bit load-and-
{set, clear} operators plus unsigned bit field extracts.
For the two load-and-{set, clear} operations, BME converts a single decorated AHB load transaction into a two-cycle atomic read-modify-write sequence, where the combined read-modify operations are performed in the first AHB data phase, and then the write is performed in the second AHB data phase as the original read data is returned to the processor core. For an unsigned bit field extract, the decorated load transaction is stalled for one cycle in the BME as the data field is extracted, then aligned and returned to the processor in the second AHB data phase. This is the only decorated transaction that is not an atomic read-modify-write, as it is a simple data read.
A generic timing diagram of a decorated load showing a peripheral load-and-set 1-bit operation is shown as follows.
CYCLE RULER hclk
BME AHB Input Bus mx_haddr mx_hattr mx_hwrite mx_hwdata mx_hrdata mx_hready
BME AHB Output Bus sx_haddr sx_hattr sx_hwrite sx_hwdata sx_hrdata sx_hready
BME States + Datapath control_state_dp1 control_state_dp2 reg_addr_data_dp x
4c.v_wxyz
400v_wxyz x+1
400v_wxyz rdata
4c.v_wxyz
next next next x+2 orig_1bit next next next rdata + 1bit rdata + 1bit x+3
Figure 17-7. Decorated load: load-and-set 1-bit field insert timing diagram
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Functional description
Decorated load-and-{set, clear} 1-bit operations follow the execution template shown in the above figure: a 2-cycle read-modify-write operation:
1. Cycle x, first AHB address phase: Read from input bus is translated into a read operation on the output bus with the actual memory address (with the decoration removed) and then captured in a register
2. Cycle x+1, second AHB address phase: Write access with the registered (but actual) memory address is output
3. Cycle x+1, first AHB data phase: The "original" 1-bit memory read data is captured in a register, while the 1-bit field is set or clear based on the function defined by the decoration with the modified data captured in a register; the input bus cycle is stalled
4. Cycle x+2, second AHB data phase: The selected original 1-bit is right-justified, zero-filled and then driven onto the input read data bus, while the registered write data is sourced onto the output write data bus
NOTE
Any wait states inserted by the slave device are simply passed through the BME back to the master input bus, stalling the
AHB transaction cycle for cycle.
A generic timing diagram of a decorated load showing an unsigned peripheral bit field operation is shown in the following figure.
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Chapter 17 Bit Manipulation Engine (BME)
CYCLE RULER hclk
BME AHB Input Bus mx_haddr mx_hattr mx_hwrite mx_hwdata mx_hrdata mx_hready
BME AHB Output Bus sx_haddr sx_hattr sx_hwrite sx_hwdata sx_hrdata sx_hready
BME States + Datapath control_state_dp1 control_state_dp2 reg_addr_data_dp
1
5..v_wxyz
400v_wxyz
2 rdata
5..v_wxyz
next next next
3 ubfx next next next rdata
4
Figure 17-8. Decorated load: unsigned bit field insert timing diagram
The decorated unsigned bit field extract follows the same execution template shown in the above figure, a 2-cycle read operation:
• Cycle x, 1st AHB address phase: Read from input bus is translated into a read operation on the output bus with the actual memory address (with the decoration removed) and then captured in a register
• Cycle x+1, 2nd AHB address phase: Idle cycle
• Cycle x+1, 1st AHB data phase: A bit mask is generated based on the starting bit position and the field width; the mask is AND'ed with the memory read data to isolate the bit field; the resulting data is captured in a data register; the input bus cycle is stalled
• Cycle x+2, 2nd AHB data phase: Registered data is logically right-aligned for proper alignment and driven onto the input read data bus
NOTE
Any wait states inserted by the slave device are simply passed through the BME back to the master input bus, stalling the
AHB transaction cycle for cycle.
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17.3.2.1 Decorated load: load-and-clear 1 bit (LAC1)
This command loads a 1-bit field defined by the LSB position (b) into the core's general purpose destination register (Rt) and zeroes the bit in the memory space after performing an atomic read-modify-write sequence.
The extracted 1-bit data field from the memory address is right-justified and zero-filled in the operand returned to the core.
The data size is specified by the read operation and can be byte (8-bit), halfword (16-bit) or word (32-bit).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 iolac1b 0 * * 0 1 0 b b b mem_addr iolac1h 0 * * 0 1 0 b b b b iolac1w 0 * * 0 1 0 b b b b b mem_addr mem_addr
0
0 0
Figure 17-9. Decorated load address: load-and-clear 1 bit
See
where addr[30:29] = 10 for peripheral, addr[28:26] = 010 specifies the load-and-clear 1 bit operation, addr[25:21] is "b", the bit identifier, and mem_addr[19:0] specifies the address offset into the space based at 0x4000_0000 for peripheral. The "-" indicates an address bit "don't care".
The decorated load-and-clear 1-bit read operation is defined in the following pseudo-code as: rdata = iolac1<sz>(accessAddress) // decorated load-and-clear 1 tmp = mem[accessAddress & 0xE00FFFFF, size] // memory read mask = 1 << b // generate bit mask rdata = (tmp & mask) >> b // read data returned to core tmp = tmp & ~mask // modify mem[accessAddress & 0xE00FFFFF, size] = tmp // memory write
The cycle-by-cycle BME operations are detailed in the following table.
Table 17-5. Cycle definitions of decorated load: load-and-clear 1 bit
Pipeline Stage
BME AHB_ap
BME AHB_dp x
Forward addr to memory;
Decode decoration; Capture address, attributes
<previous>
Cycle x+1
Recirculate captured addr + attr to memory as slave_wt
Perform memory read; Form bit mask; Extract bit from rdata; Form (rdata & ~mask) and capture destination data in register x+2
<next>
Return extracted bit to master;
Perform write sending registered data to memory
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17.3.2.2 Decorated Load: Load-and-Set 1 Bit (LAS1)
This command loads a 1-bit field defined by the LSB position (b) into the core's general purpose destination register (Rt) and sets the bit in the memory space after performing an atomic read-modify-write sequence.
The extracted one bit data field from the memory address is right justified and zero filled in the operand returned to the core.
The data size is specified by the read operation and can be byte (8-bit), halfword (16-bit) or word (32-bit).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 iolas1b 0 * * 0 1 1 b b b mem_addr iolas1h 0 * * 0 1 1 b b b b iolas1w 0 * * 0 1 1 b b b b b -
mem_addr mem_addr
0
0 0
Figure 17-10. Decorated load address: load-and-set 1 bit where addr[30:29] = 10 for peripheral, addr[28:26] = 011 specifies the load-and-set 1 bit operation, addr[25:21] is "b", the bit identifier, and mem_addr[19:0] specifies the address offset into the space based at 0x4000_0000 for peripheral. The "-" indicates an address bit "don't care".
The decorated Load-and-Set 1 Bit read operation is defined in the following pseudo-code as: rdata = iolas1<sz>(accessAddress) // decorated load-and-set 1 tmp = mem[accessAddress & 0xE00FFFFF, size] // memory read mask = 1 << b // generate bit mask rdata = (tmp & mask) >> b // read data returned to core tmp = tmp | mask // modify mem[accessAddress & 0xE00FFFFF, size] = tmp // memory write
The cycle-by-cycle BME operations are detailed in the following table.
Table 17-6. Cycle definitions of decorated load: load-and-set 1-bit
Pipeline Stage
BME AHB_ap x
Forward addr to memory;
Decode decoration; Capture address, attributes
Cycle x+1
Recirculate captured addr + attr to memory as slave_wt
Table continues on the next page...
x+2
<next>
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Functional description
Table 17-6. Cycle definitions of decorated load: load-and-set 1-bit (continued)
Pipeline Stage
BME AHB_dp x
<previous>
Cycle x+1
Perform memory read; Form bit mask; Extract bit from rdata; Form (rdata | mask) and capture destination data in register x+2
Return extracted bit to master;
Perform write sending registered data to memory
17.3.2.3 Decorated load unsigned bit field extract (UBFX)
This command extracts a bit field defined by LSB position (b) and the bit field width (w
+1) from the memory "container" defined by the access size associated with the load instruction using a two-cycle read sequence.
The extracted bit field from the memory address is right-justified and zero-filled in the operand returned to the core. Recall this is the only decorated operation that does not perform a memory write, that is, UBFX only performs a read.
The data size is specified by the write operation and can be byte (8-bit), halfword (16-bit) or word (32-bit). Note for the word sized operation, the maximum bit field width is 16 bits.
The use of a UBFX operation is recommended to extract a single bit. For this case, the w field is simply set to 0, indicating a bit field width of 1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ioubfxb 0 * * 1 b b b - w w w mem_addr ioubfxh 0 * * 1 b b b b w w w w mem_addr 0 ioubfxw 0 * * 1 b b b b b w w w w mem_addr 0 0
Figure 17-11. Decorated load address: unsigned bit field extract
See
Figure 17-11 , where addr[30:29] = 10 for peripheral, addr[28] = 1 specifies the
unsigned bit field extract operation, addr[27:23] is "b", the LSB identifier, addr[22:19] is
"w", the bit field width minus 1 identifier, and mem_addr[18:0] specifies the address offset into the space based at 0x4000_0000 for peripheral. The "-" indicates an address bit "don't care". Note, unlike the other decorated load operations, UBFX uses addr[19] as the least significant bit in the "w" specifier and not as an address bit.
The decorated unsigned bit field extract read operation is defined in the following pseudo-code as:
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Chapter 17 Bit Manipulation Engine (BME) rdata = ioubfx<sz>(accessAddress) // unsigned bit field extract tmp = mem[accessAddress & 0xE007FFFF, size] // memory read mask = ((1 << (w+1)) - 1) << b // generate bit mask rdata = (tmp & mask) >> b // read data returned to core
Like the BFI operation, when the starting bit position plus the field width exceeds the container size, only part of the source bit field is extracted from the destination memory location. Stated differently, if (b + w+1) > container_width, only the low-order
"container_width - b" bits are actually extracted. The cycle-by-cycle BME operations are detailed in the following table.
Table 17-7. Cycle definitions of decorated load: unsigned bit field extract
Pipeline Stage
BME AHB_ap
BME AHB_dp x
Forward addr to memory;
Decode decoration; Capture address, attributes
<previous>
Cycle x+1
Idle AHB address phase x+2
<next>
Perform memory read; Form bit mask; Form (rdata & mask) and capture destination data in register
Logically right shift registered data; Return justified rdata to master
17.3.3 Additional details on decorated addresses and GPIO accesses
As previously noted, the peripheral address space occupies a 516 KB region: 512 KB based at 0x4000_0000 plus a 4 KB space based at 0x400F_F000 for GPIO accesses. This memory layout provides compatibility with the Kinetis K Family and provides 129 address "slots", each 4 KB in size.
The GPIO address space is multiply-mapped by the hardware: it appears at the "standard" system address 0x400F_F000 and is physically located in the address slot corresponding to address 0x4000_F000. Decorated loads and stores create a slight complication involving accesses to the GPIO. Recall the use of address[19] varies by decorated operation; for AND, OR, XOR, LAC1 and LAS1, this bit functions as a true address bit, while for BFI and UBFX, this bit defines the least significant bit of the "w" bit field specifier.
As a result, undecorated GPIO references and decorated AND, OR, XOR, LAC1 and
LAS1 operations can use the standard 0x400F_F000 base address, while decorated BFI and UBFX operations must use the alternate 0x4000_F000 base address. Another
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Application information implementation can simply use 0x400F_F000 as the base address for all undecorated
GPIO accesses and 0x4000_F000 as the base address for all decorated accesses. Both implementations are supported by the hardware.
Table 17-8. Decorated peripheral and GPIO address details
Peripheral address space Description
0x4000_0000–0x4007_FFFF Undecorated (normal) peripheral accesses
0x4008_0000–0x400F_EFFF Illegal addresses; attempted references are aborted and error terminated
0x400F_F000–0x400F_FFFF Undecorated (normal) GPIO accesses using standard address
0x4010_0000–0x43FF_FFFF Illegal addresses; attempted references are aborted and error terminated
0x4400_0000–0x4FFF_FFFF Decorated AND, OR, XOR, LAC1, LAS1 references to peripherals and GPIO based at either 0x4000_F000 or 0x400F_F000
0x5000_0000–0x5FFF_FFFF Decorated BFI, UBFX references to peripherals and GPIO only based at 0x4000_F000
17.4 Application information
In this section, GNU assembler macros with C expression operands are presented as examples of the required instructions to perform decorated operations.
This section specifically presents a partial bme.h file defining the assembly language expressions for decorated logical stores: AND, OR, and XOR. Comparable functions for
BFI and the decorated loads are more complex and available in the complete BME header file.
These macros use the same function names presented in Functional description .
#define IOANDW(ADDR,WDATA) \
__asm("ldr r3, =(1<<26);" \
"orr r3, %[addr];" \
"mov r2, %[wdata];" \
"str r2, [r3];" \
:: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3");
#define IOANDH(ADDR,WDATA) \
__asm("ldr r3, =(1<<26);" \
"orr r3, %[addr];" \
"mov r2, %[wdata];" \
"strh r2, [r3];" \
:: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3");
#define IOANDB(ADDR,WDATA) \
__asm("ldr r3, =(1<<26);" \
"orr r3, %[addr];" \
"mov r2, %[wdata];" \
"strb r2, [r3];" \
:: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3");
#define IOORW(ADDR,WDATA) \
__asm("ldr r3, =(1<<27);" \
"orr r3, %[addr];" \
"mov r2, %[wdata];" \
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"str r2, [r3];" \
:: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3");
#define IOORH(ADDR,WDATA) \
__asm("ldr r3, =(1<<27);" \
"orr r3, %[addr];" \
"mov r2, %[wdata];" \
"strh r2, [r3];" \
:: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3");
#define IOORB(ADDR,WDATA) \
__asm("ldr r3, =(1<<27);" \
"orr r3, %[addr];" \
"mov r2, %[wdata];" \
"strb r2, [r3];" \
:: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3");
#define IOXORW(ADDR,WDATA) \
__asm("ldr r3, =(3<<26);" \
"orr r3, %[addr];" \
"mov r2, %[wdata];" \
"str r2, [r3];" \
:: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3");
#define IOXORH(ADDR,WDATA) \
__asm("ldr r3, =(3<<26);" \
"orr r3, %[addr];" \
"mov r2, %[wdata];" \
"strh r2, [r3];" \
:: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3");
#define IOXORB(ADDR,WDATA) \
__asm("ldr r3, =(3<<26);" \
"orr r3, %[addr];" \
"mov r2, %[wdata];" \
"strb r2, [r3];" \
:: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3");
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Chapter 18
Miscellaneous Control Module (MCM)
The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control functions for the platform (RPP).
18.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control functions.
18.1.1 Features
The MCM includes the following features:
• Program-visible information on the platform configuration
• Crossbar master arbitration policy selection
• Flash controller speculation buffer and cache configurations
18.2 Memory map/register descriptions
The memory map and register descriptions found here describe the registers using byte addresses. The registers can be written only when in supervisor mode.
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Memory map/register descriptions
MCM memory map
Absolute address
(hex)
Register name
F000_3008
F000_300A
Crossbar Switch (AXBS) Slave Configuration
(MCM_PLASC)
Crossbar Switch (AXBS) Master Configuration
(MCM_PLAMC)
F000_300C Platform Control Register (MCM_PLACR)
F000_3040 Compute Operation Control Register (MCM_CPO)
Width
(in bits)
Access Reset value
16
16
32
32
R
R
R/W
R/W
0007h
000Dh
Section/ page
0000_0000h
0000_0000h
18.2.1 Crossbar Switch (AXBS) Slave Configuration
(MCM_PLASC)
PLASC is a 16-bit read-only register identifying the presence/absence of bus slave connections to the device’s crossbar switch.
Address: F000_3000h base + 8h offset = F000_3008h
15 14 13 12 11 10 Bit
Read
Write
Reset 0 0 0 0
0 0
9
0
Field
15–8
Reserved
7–0
ASC
8 7 6 5 4
3 2 1 0
0 0 0 0 0 0 1 1
MCM_PLASC field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
1
0 A bus slave connection to AXBS input port n is absent.
1 A bus slave connection to AXBS input port n is present.
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18.2.2 Crossbar Switch (AXBS) Master Configuration
(MCM_PLAMC)
PLAMC is a 16-bit read-only register identifying the presence/absence of bus master connections to the device's crossbar switch.
Address: F000_3000h base + Ah offset = F000_300Ah
15 14 13 12 11 10 Bit
Read
Write
Reset 0 0 0 0
0 0
9
0
Field
15–8
Reserved
7–0
AMC
8 7 6 5 4
3 2 1 0
0 0 0 0 0 1 1 0 1
MCM_PLAMC field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
0 A bus master connection to AXBS input port n is absent
1 A bus master connection to AXBS input port n is present
18.2.3 Platform Control Register (MCM_PLACR)
The PLACR register selects the arbitration policy for the crossbar masters and configures the flash memory controller.
The speculation buffer and cache in the flash memory controller is configurable via
PLACR[15:10].
The speculation buffer is enabled only for instructions after reset. It is possible to have these states for the speculation buffer:
0
DFCS
0
1
0
EFDS
1
X
Description
Speculation buffer is on for instruction and off for data.
Speculation buffer is on for instruction and on for data.
Speculation buffer is off.
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Memory map/register descriptions
The cache in flash controller is enabled and caching both instruction and data type fetches after reset. It is possible to have these states for the cache:
0
DFCC
0
0
0
1
0
DFCIC
0
1
1
X
0
DFCDA
1
0
1
X
Description
Cache is on for both instruction and data.
Cache is on for instruction and off for data.
Cache is off for instruction and on for data.
Cache is off for both instruction and data.
Cache is off.
Address: F000_3000h base + Ch offset = F000_300Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
R 0
0
9
0
8
W
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Reset 0
Field
31–17
Reserved
16
ESFC
0 0 0 0 0 0 0 0 0
MCM_PLACR field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Enable Stalling Flash Controller
Enables stalling flash controller when flash is busy.
Table continues on the next page...
0 0 0 0 0 0
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Field
15
DFCS
14
EFDS
13
DFCC
12
DFCIC
11
DFCDA
10
CFCC
9
ARB
8–0
Reserved
Chapter 18 Miscellaneous Control Module (MCM)
MCM_PLACR field descriptions (continued)
Description
When software needs to access the flash memory while a flash memory resource is being manipulated by a flash command, software can enable a stall mechanism to avoid a read collision. The stall mechanism allows software to execute code from the same block on which flash operations are being performed.
However, software must ensure the sector the flash operations are being performed on is not the same sector from which the code is executing.
ESFC enables the stall mechanism. This bit must be set only just before the flash operation is executed and must be cleared when the operation completes.
0 Disable stalling flash controller when flash is busy.
1 Enable stalling flash controller when flash is busy.
Disable Flash Controller Speculation
Disables flash controller speculation.
0 Enable flash controller speculation.
1 Disable flash controller speculation.
Enable Flash Data Speculation
Enables flash data speculation.
0 Disable flash data speculation.
1 Enable flash data speculation.
Disable Flash Controller Cache
Disables flash controller cache.
0 Enable flash controller cache.
1 Disable flash controller cache.
Disable Flash Controller Instruction Caching
Disables flash controller instruction caching.
0 Enable flash controller instruction caching.
1 Disable flash controller instruction caching.
Disable Flash Controller Data Caching
Disables flash controller data caching.
0 Enable flash controller data caching
1 Disable flash controller data caching.
Clear Flash Controller Cache
Writing a 1 to this field clears the cache. Writing a 0 to this field is ignored. This field always reads as 0.
Arbitration select
0 Fixed-priority arbitration for the crossbar masters
1 Round-robin arbitration for the crossbar masters
This field is reserved.
This read-only field is reserved and always has the value 0.
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Memory map/register descriptions
18.2.4 Compute Operation Control Register (MCM_CPO)
This register controls the Compute Operation.
Address: F000_3000h base + 40h offset = F000_3040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
Reset 0
Field
31–3
Reserved
2
CPOWOI
1
CPOACK
0
CPOREQ
0 0 0 0 0 0 0 0 0
MCM_CPO field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Compute Operation Wake-up on Interrupt
0 0 0 0
0 No effect.
1 When set, the CPOREQ is cleared on any interrupt or exception vector fetch.
Compute Operation Acknowledge
0 Compute operation entry has not completed or compute operation exit has completed.
1 Compute operation entry has completed or compute operation exit has not completed.
Compute Operation Request
This bit is auto-cleared by vector fetching if CPOWOI = 1.
Table continues on the next page...
0
314
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Field
Chapter 18 Miscellaneous Control Module (MCM)
MCM_CPO field descriptions (continued)
Description
0 Request is cleared.
1 Request Compute Operation.
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Chapter 19
Micro Trace Buffer (MTB)
This module explains how microcontrollers using the Cortex-M0+ processor core support
CoreSight Micro Trace Buffer to provide program trace capabilities. It also explains about change-of-flow data packets in a user-defined region of the system RAM and DWT
(Data Watchpoint and Trace) module that allows a user to define watchpoint addresses, or an address and data value, that when triggered can be used to start or stop the program trace recording.
19.1 Introduction
Microcontrollers using the Cortex-M0+ processor core include support for a CoreSight
Micro Trace Buffer to provide program trace capabilities.
The proper name for this function is the CoreSight Micro Trace Buffer for the Cortex-
M0+ Processor; in this document, it is simply abbreviated as the MTB.
The simple program trace function creates instruction address change-of-flow data packets in a user-defined region of the system RAM. Accordingly, the system RAM controller manages requests from two sources:
• AMBA-AHB reads and writes from the system bus
• program trace packet writes from the processor
As part of the MTB functionality, there is a DWT (Data Watchpoint and Trace) module that allows the user to define watchpoint addresses, or optionally, an address and data value, that when triggered, can be used to start or stop the program trace recording.
This document details the functionality of both the MTB_RAM and MTB_DWT capabilities.
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Introduction
19.1.1 Overview
A generic block diagram of the processor core and platform for this class of ultra low-end microcontrollers is shown as follows:
NVIC
Cortex-M0+ Core
Dbg
AHB Bus
Fetch
AGU
LD/ST
Dec
SHFT
ALU
IO Port
Rn
MUL
MTB Port
CM0+ Core Platform
32
PRAM
RAM
Array
GPIO
Alt-Master m3 m0 s1 s2
BME PBRIDGE
32
Slave
Peripherals
DMA_4ch m2 AXBS s0
FMC
32
NVM
Array
Figure 19-1. Generic Cortex-M0+ core platform block diagram
As shown in the block diagram, the platform RAM (PRAM) controller connects to two input buses:
• the crossbar slave port for system bus accesses
• a "private execution MTB port" from the core
The logical paths from the crossbar master input ports to the PRAM controller are highlighted along with the private execution trace port from the processor core. The private MTB port signals the instruction address information needed for the 64-bit program trace packets written into the system RAM. The PRAM controller output interfaces to the attached RAM array. In this document, the PRAM controller is the
MTB_RAM controller.
The following information is taken from the ARM CoreSight Micro Trace Buffer documentation.
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"The execution trace packet consists of a pair of 32-bit words that the MTB generates when it detects the processor PC value changes non-sequentially. A non-sequential PC change can occur during branch instructions or during exception entry.
The processor can cause a trace packet to be generated for any instruction.
The following figure shows how the execution trace information is stored in memory as a sequence of packets.
31
Nth destination address
Nth source address
1 0
S
A
Odd word address
Even word address
Incrementing
SRAM memory address 31
2nd destination address
2nd source address
1st destination address
1st source address
1 0
S
A
S
A
Start bit
Odd word address
Even word address
Atom bit
Figure 19-2. MTB execution trace storage format
The first, lower addressed, word contains the source of the branch, the address it branched from. The value stored only records bits[31:1] of the source address, because
Thumb instructions are at least halfword aligned. The least significant bit of the value is the A-bit. The A-bit indicates the atomic state of the processor at the time of the branch, and can differentiate whether the branch originated from an instruction in a program, an exception, or a PC update in Debug state. When it is zero the branch originated from an instruction, when it is one the branch originated from an exception or PC update in
Debug state. This word is always stored at an even word location.
The second, higher addressed word contains the destination of the branch, the address it branched to. The value stored only records bits[31:1] of the branch address. The least significant bit of the value is the S-bit. The S-bit indicates where the trace started. An Sbit value of 1 indicates where the first packet after the trace started and a value of 0 is used for other packets. Because it is possible to start and stop tracing multiple times in a trace session, the memory might contain several packets with the S-bit set to 1. This word is always stored in the next higher word in memory, an odd word address.
When the A-bit is set to 1, the source address field contains the architecturally-preferred return address for the exception. For example, if an exception was caused by an SVC instruction, then the source address field contains the address of the following instruction.
This is different from the case where the A-bit is set to 0. In this case, the source address contains the address of the branch instruction.
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Introduction
For an exception return operation, two packets are generated:
• The first packet has the:
• Source address field set to the address of the instruction that causes the exception return, BX or POP.
• Destination address field set to bits[31:1] of the EXC_RETURN value. See the
ARM v6-M Architecture Reference Manual.
• The A-bit set to 0.
• The second packet has the:
• Source address field set to bits[31:1] of the EXC_RETURN value.
• Destination address field set to the address of the instruction where execution commences.
• A-bit set to 1."
Given the recorded change-of-flow trace packets in system RAM and the memory image of the application, a debugger can read out the data and create an instruction-byinstruction program trace. In keeping with the low area and power implementation cost design targets, the MTB trace format is less efficient than other CoreSight trace modules, for example, the ETM (Embedded Trace Macrocell). Since each branch packet is 8 bytes in size, a 1 KB block of system RAM can contain 128 branches. Using the Dhrystone 2.1
benchmark's dynamic runtime as an example, this corresponds to about 875 instructions per KB of trace RAM, or with a zero wait state memory, this corresponds to approximately 1600 processor cycles per KB. This metric is obviously very sensitive to the runtime characteristics of the user code.
The MTB_DWT function (not shown in the core platform block diagram) monitors the processor address and data buses so that configurable watchpoints can be detected to trigger the appropriate response in the MTB recording.
19.1.2 Features
The key features of the MTB_RAM and MTB_DWT include:
• Memory controller for system RAM and Micro Trace Buffer for program trace packets
• Read/write capabilities for system RAM accesses, write-only for program trace packets
• Supports zero wait state response to system bus accesses when no trace data is being written
• Can buffer two AHB address phases and one data write for system RAM accesses
• Supports 64-bit program trace packets including source and destination instruction addresses
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• Program trace information in RAM available to MCU's application code or external debugger
• Program trace watchpoint configuration accessible by MCU's application code or debugger
• Location and size of RAM trace buffer is configured by software
• Two DWT comparators (addresses or address + data) provide programmable start/ stop recording
• CoreSight compliant debug functionality
19.1.3 Modes of operation
The MTB_RAM and MTB_DWT functions do not support any special modes of operation. The MTB_RAM controller, as a memory-mapped device located on the platform's slave AHB system bus, responds strictly on the basis of memory addresses for accesses to its attached RAM array. The MTB private execution bus provides program trace packet write information to the RAM controller. Both the MTB_RAM and
MTB_DWT modules are memory-mapped, so their programming models can be accessed.
All functionality associated with the MTB_RAM and MTB_DWT modules resides in the core platform's clock domain; this includes its connections with the RAM array.
19.2 External signal description
The MTB_RAM and MTB_DWT modules do not directly support any external interfaces.
The internal interface includes a standard AHB bus with a 32-bit datapath width from the appropriate crossbar slave port plus the private execution trace bus from the processor core. The signals in the private execution trace bus are detailed in the following table taken from the ARM CoreSight Micro Trace Buffer documentation. The signal direction is defined as viewed by the MTB_RAM controller.
Signal
LOCKUP
IAESEQ
Table 19-1. Private execution trace port from the core to MTB_RAM
Direction
Input
Input
Description
Indicates the processor is in the Lockup state. This signal is driven LOW for cycles when the processor is executing normally and driven HIGH for every cycle the processor is waiting in the Lockup state. This signal is valid on every cycle.
Indicates the next instruction address in execute, IAEX, is sequential, that is nonbranching.
Table continues on the next page...
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Table 19-1. Private execution trace port from the core to MTB_RAM (continued)
Signal
IAEXEN
IAEX[30:0]
ATOMIC
EDBGRQ
Direction
Input
Input
Input
Output
Description
IAEX register enable.
Registered address of the instruction in the execution stage, shifted right by one bit, that is, PC >> 1.
Indicates the processor is performing non-instruction related activities.
Request for the processor to enter the Debug state, if enabled, and halt.
In addition, there are two signals formed by the MTB_DWT module and driven to the
MTB_RAM controller: TSTART (trace start) and TSTOP (trace stop). These signals can be configured using the trace watchpoints to define programmable addresses and data values to affect the program trace recording state.
19.3 Memory map and register definition
The MTB_RAM and MTB_DWT modules each support a sparsely-populated 4 KB address space for their programming models. For each address space, there are a variety of control and configurable registers near the base address, followed by a large unused address space and finally a set of CoreSight registers to support dynamic determination of the debug configuration for the device.
Accesses to the programming model follow standard ARM conventions. Taken from the
ARM CoreSight Micro Trace Buffer documentation, these are:
• Do not attempt to access reserved or unused address locations. Attempting to access these locations can result in UNPREDICTABLE behavior.
• The behavior of the MTB is UNPREDICTABLE if the registers with UNKNOWN reset values are not programmed prior to enabling trace.
• Unless otherwise stated in the accompanying text:
• Do not modify reserved register bits
• Ignore reserved register bits on reads
• All register bits are reset to a logic 0 by a system or power-on reset
• Use only word size, 32-bit, transactions to access all registers
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Chapter 19 Micro Trace Buffer (MTB)
19.3.1 MTB_RAM Memory Map
MTB memory map
Absolute address
(hex)
Register name
F000_0000 MTB Position Register (MTB_POSITION)
F000_0004 MTB Master Register (MTB_MASTER)
F000_0008 MTB Flow Register (MTB_FLOW)
F000_000C MTB Base Register (MTB_BASE)
F000_0F00 Integration Mode Control Register (MTB_MODECTRL)
F000_0FA0 Claim TAG Set Register (MTB_TAGSET)
F000_0FA4 Claim TAG Clear Register (MTB_TAGCLEAR)
F000_0FB0 Lock Access Register (MTB_LOCKACCESS)
F000_0FB4 Lock Status Register (MTB_LOCKSTAT)
Width
(in bits)
Access Reset value
32
32
32
32
32
32
32
32
32
R
R
R
R
R/W
R/W
R/W
R
R
F000_0FB8 Authentication Status Register (MTB_AUTHSTAT)
F000_0FBC Device Architecture Register (MTB_DEVICEARCH)
F000_0FC8 Device Configuration Register (MTB_DEVICECFG)
F000_0FCC Device Type Identifier Register (MTB_DEVICETYPID)
F000_0FD0 Peripheral ID Register (MTB_PERIPHID4)
F000_0FD4 Peripheral ID Register (MTB_PERIPHID5)
F000_0FD8 Peripheral ID Register (MTB_PERIPHID6)
F000_0FDC Peripheral ID Register (MTB_PERIPHID7)
F000_0FE0 Peripheral ID Register (MTB_PERIPHID0)
F000_0FE4 Peripheral ID Register (MTB_PERIPHID1)
F000_0FE8 Peripheral ID Register (MTB_PERIPHID2)
F000_0FEC Peripheral ID Register (MTB_PERIPHID3)
F000_0FF0 Component ID Register (MTB_COMPID0)
F000_0FF4 Component ID Register (MTB_COMPID1)
F000_0FF8 Component ID Register (MTB_COMPID2)
F000_0FFC Component ID Register (MTB_COMPID3)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Section/ page
Undefined
Undefined
Undefined
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
4770_0A31h
0000_0000h
0000_0031h
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19.31.1 MTB Position Register (MTB_POSITION)
The MTB_POSITION register contains the Trace Write Address Pointer and Wrap fields.
This register can be modified by the explicit programming model writes. It is also automatically updated by the MTB hardware when trace packets are being recorded.
The base address of the system RAM in the memory map dictates special consideration for the placement of the MTB. Consider the following guidelines:
For the standard configuration where the size of the MTB is ≤ 25% of the total RAM capacity, it is recommended the MTB be based at the address defined by the MTB_BASE register. The read-only MTB_BASE register is defined by the expression (0x2000_0000 -
(RAM_Size/4)). For this configuration, the MTB_POSITION register is initialized to
MTB_BASE & 0x0000_7FF8.
If the size of the MTB is more than 25% but less than or equal to 50% of the total RAM capacity, it is recommended the MTB be based at address 0x2000_0000. In this configuration, the MTB_POSITION register is initialized to (0x2000_0000 &
0x0000_7FF8) = 0x0000_00000.
Following these two suggested placements provides a full-featured circular memory buffer containing program trace packets.
In the unlikely event an even larger trace buffer is required, a write-once capacity of 75% of the total RAM capacity can be based at address 0x2000_0000. The MTB_POSITION register is initialized to (0x2000_0000 & 0x0000_7FF8) = 0x0000_0000. However, this configuration cannot support operation as a circular queue and instead requires the use of the MTB_FLOW[WATERMARK] capability to automatically disable tracing or halting the processor as the number of packet writes approach the buffer capacity. See the
MTB_FLOW register description for more details.
Address: F000_0000h base + 0h offset = F000_0000h
Bit 31 30 29 28 27 26 25
R
24 23 22 21 20 19 18 17 16
W
Reset
Bit
R
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x*
0 0
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* Notes:
• x = Undefined at reset.
Field
31–3
POINTER
2
WRAP
1–0
Reserved
MTB_POSITION field descriptions
Description
Trace Packet Address Pointer[28:0]
Because a packet consists of two words, the POINTER field is the address of the first word of a packet.
This field contains bits[31:3] of the RAM address where the next trace packet is written. Therefore, it points to an unused location and is automatically incremented.
A debug agent can calculate the system memory map address for the current location in the MTB using the following "generic" equation:
Given mtb_size = 1 << (MTB_MASTER[MASK] + 4), systemAddress = MTB_BASE + (((MTB_POSITION & 0xFFFF_FFF8) + (mtb_size - (MTB_BASE &
(mtb_size-1)))) & 0x0000_7FF8);
For this device, a simpler expression also applies. See the following pseudo-code: if ((MTB_POSITION >> 13) == 0x3) systemAddress = (0x1FFF << 16) + (0x1 << 15) + (MTB_POSITION &
0x7FF8); else systemAddress = (0x2000 << 16) + (0x0 << 15) + (MTB_POSITION & 0x7FF8);
NOTE: The size of the RAM is parameterized and the most significant bits of the POINTER field are
RAZ/WI.
For these devices, POSITION[31:15] == POSITION[POINTER[28:12]] are RAZ/WI. Therefore, the active bits in this field are POSITION[14:3] == POSITION[POINTER[11:0]].
This field is set to 1 automatically when the POINTER value wraps as determined by the
MTB_MASTER[MASK] field in the MASTER Trace Control Register. A debug agent might use the WRAP field to determine whether the trace information above and below the pointer address is valid.
This field is reserved.
This read-only field is reserved and always has the value 0.
19.31.2 MTB Master Register (MTB_MASTER)
The MTB_MASTER register contains the main program trace enable plus other trace controls. This register can be modified by the explicit programming model writes.
MTB_MASTER[EN] and MTB_MASTER[HALTREQ] fields are also automatically updated by the MTB hardware.
Before MTB_MASTER[EN] or MTB_MASTER[TSTARTEN] are set to 1, the software must initialize the MTB_POSITION and MTB_FLOW registers.
If MTB_FLOW[WATERMARK] is used to stop tracing or to halt the processor,
MTB_MASTER[MASK] must still be set to a value that prevents
MTB_POSITION[POINTER] from wrapping before it reaches the
MTB_FLOW[WATERMARK] value.
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NOTE
The format of this mask field is different than
MTBDWT_MASKn[MASK].
Address: F000_0000h base + 4h offset = F000_0004h
Bit 31 30 29 28 27 26 25
R
W
Reset
Bit
R
0
15
0
14
0
13
0
12
0
11
0
10
0
9
24
0
8
0
7
23
22
0
6
21
0
5
W
Reset 0 0
* Notes:
• x = Undefined at reset.
0 0 0 0 0 0 1 0 0
20
0
4
19 18 17
0
3
0
2
0
1
16
0
0
Field
31
EN
30–10
Reserved
9
HALTREQ
8
RAMPRIV
MTB_MASTER field descriptions
Description
Main Trace Enable
When this field is 1, trace data is written into the RAM memory location addressed by
MTB_POSITION[POINTER]. The MTB_POSITION[POINTER] value auto increments after the trace data packet is written.
EN can be automatically set to 0 using the MTB_FLOW[WATERMARK] field and the
MTB_FLOW[AUTOSTOP] bit.
EN is automatically set to 1 if TSTARTEN is 1 and the TSTART signal is HIGH.
EN is automatically set to 0 if TSTOPEN is 1 and the TSTOP signal is HIGH.
NOTE: If EN is set to 0 because MTB_FLOW[WATERMARK] is set, then it is not automatically set to 1 if
TSTARTEN is 1 and the TSTART input is HIGH. In this case, tracing can only be restarted if
MTB_FLOW[WATERMARK] or MTB_POSITION[POINTER] value is changed by software.
This field is reserved.
This read-only field is reserved and always has the value 0.
Halt Request
This field is connected to the halt request signal of the trace logic, EDBGRQ. When HALTREQ is set to 1, the EDBFGRQ is asserted if DBGEN (invasive debug enable, one of the debug authentication interface signals) is also HIGH. HALTREQ can be automatically set to 1 using MTB_FLOW[WATERMARK].
RAM Privilege
If this field is 0, then user or privileged AHB read and write accesses to the RAM are permitted. If this field is 1, then only privileged AHB read and write accesses to the RAM are permitted and user accesses are
RAZ/WI. The HPROT[1] signal determines if an access is a user or privileged mode reference.
Table continues on the next page...
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Field
7
SFRWPRIV
6
TSTOPEN
5
TSTARTEN
4–0
MASK
Chapter 19 Micro Trace Buffer (MTB)
MTB_MASTER field descriptions (continued)
Description
Special Function Register Write Privilege
If this field is 0, then user or privileged AHB read and write accesses to the MTB_RAM Special Function
Registers (programming model) are permitted. If this field is 1, then only privileged write accesses are permitted; user write accesses are ignored. The HPROT[1] signal determines if an access is user or privileged. Note MTB_RAM SFR read access are not controlled by this bit and are always permitted.
Trace Stop Input Enable
If this field is 1 and the TSTOP signal is HIGH, then EN is set to 0. If a trace packet is being written to memory, the write is completed before tracing is stopped.
Trace Start Input Enable
If this field is 1 and the TSTART signal is HIGH, then EN is set to 1. Tracing continues until a stop condition occurs.
Mask
This value determines the maximum size of the trace buffer in RAM. It specifies the most-significant bit of the MTB_POSITION[POINTER] field that can be updated by automatic increment. If the trace tries to advance past this power of 2, the MTB_POSITION[WRAP] bit is set to 1, the MTB_POSITION[MASK+3:3]
== MTB_POSITION[POINTER[MASK:0]] bits are set to 0, and the MTB_POSITION[14:MASK+3] ==
MTB_POSITION[POINTER[11:MASK+1]] bits remain unchanged.
This field causes the trace packet information to be stored in a circular buffer of size 2^[MASK+4] bytes, that can be positioned in memory at multiples of this size. As detailed in the MTB_POSITION description, typical "upper limits" for the MTB size are RAM_Size/4 or RAM_Size/2. Values greater than the maximum have the same effect as the maximum.
19.31.3 MTB Flow Register (MTB_FLOW)
The MTB_FLOW register contains the watermark address and the autostop/autohalt control bits.
If tracing is stopped using the watermark autostop feature, it cannot be restarted until software clears the watermark autostop. This can be achieved in one of the following ways:
• Changing the MTB_POSITION[POINTER] field value to point to the beginning of the trace buffer, or
• Setting MTB_FLOW[AUTOSTOP] = 0.
A debug agent can use MTB_FLOW[AUTOSTOP] to fill the trace buffer once only without halting the processor.
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A debug agent can use MTB_FLOW[AUTOHALT] to fill the trace buffer once before causing the Cortex-M0+ processor to enter the Debug state. To enter Debug state, the
Cortex-M0+ processor might have to perform additional branch type operations.
Therefore, the MTB_FLOW[WATERMARK] field must be set below the final entry in the trace buffer region.
Address: F000_0000h base + 8h offset = F000_0008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset
Bit 15
R
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
Reset
* Notes:
• x = Undefined at reset.
0
Field
31–3
WATERMARK
2
Reserved
1
AUTOHALT
0
AUTOSTOP
MTB_FLOW field descriptions
Description
WATERMARK[28:0]
This field contains an address in the same format as the MTB_POSITION[POINTER] field. When
MTB_POSITION[POINTER] matches the WATERMARK field value, actions defined by the AUTOHALT and AUTOSTOP bits are performed.
This field is reserved.
This read-only field is reserved and always has the value 0.
If this field is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then
MTB_MASTER[HALTREQ] is automatically set to 1. If the DBGEN signal is HIGH, the MTB asserts this halt request to the Cortex-M0+ processor by asserting the EDBGRQ signal.
If this field is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then MTB_MASTER[EN] is automatically set to 0. This stops tracing.
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Chapter 19 Micro Trace Buffer (MTB)
19.31.4 MTB Base Register (MTB_BASE)
The read-only MTB_BASE Register indicates where the RAM is located in the system memory map. This register is provided to enable auto discovery of the MTB RAM location, by a debug agent and is defined by a hardware design parameter. For this device, the base address is defined by the expression: MTB_BASE[BASEADDR] =
0x2000_0000 - (RAM_Size/4)
Address: F000_0000h base + Ch offset = F000_000Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
Field
31–0
BASEADDR
MTB_BASE field descriptions
Description
This value is defined with a hardwired signal and the expression: 0x2000_0000 - (RAM_Size/4). For example, if the total RAM capacity is 16 KB, this field is 0x1FFF_F000.
19.31.5 Integration Mode Control Register (MTB_MODECTRL)
This register enables the device to switch from a functional mode, or default behavior, into integration mode. It is hardwired to specific values used during the auto-discovery process by an external debug agent.
Address: F000_0000h base + F00h offset = F000_0F00h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
MODECTRL
MTB_MODECTRL field descriptions
Description
Hardwired to 0x0000_0000
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19.31.6 Claim TAG Set Register (MTB_TAGSET)
The Claim Tag Set Register returns the number of bits that can be set on a read, and enables individual bits to be set on a write. It is hardwired to specific values used during the auto-discovery process by an external debug agent.
Address: F000_0000h base + FA0h offset = F000_0FA0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
TAGSET
MTB_TAGSET field descriptions
Description
Hardwired to 0x0000_0000
19.31.7 Claim TAG Clear Register (MTB_TAGCLEAR)
The read/write Claim Tag Clear Register is used to read the claim status on debug resources. A read indicates the claim tag status. Writing 1 to a specific bit clears the corresponding claim tag to 0. It is hardwired to specific values used during the autodiscovery process by an external debug agent.
Address: F000_0000h base + FA4h offset = F000_0FA4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
TAGCLEAR
MTB_TAGCLEAR field descriptions
Description
Hardwired to 0x0000_0000
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19.31.8 Lock Access Register (MTB_LOCKACCESS)
The Lock Access Register enables a write access to component registers. It is hardwired to specific values used during the auto-discovery process by an external debug agent.
Address: F000_0000h base + FB0h offset = F000_0FB0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
LOCKACCESS
MTB_LOCKACCESS field descriptions
Description
Hardwired to 0x0000_0000
19.31.9 Lock Status Register (MTB_LOCKSTAT)
The Lock Status Register indicates the status of the lock control mechanism. This register is used in conjunction with the Lock Access Register. It is hardwired to specific values used during the auto-discovery process by an external debug agent.
Address: F000_0000h base + FB4h offset = F000_0FB4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
LOCKSTAT
MTB_LOCKSTAT field descriptions
Description
Hardwired to 0x0000_0000
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19.31.10 Authentication Status Register (MTB_AUTHSTAT)
The Authentication Status Register reports the required security level and current status of the security enable bit pairs. Where functionality changes on a given security level, this change must be reported in this register. It is connected to specific signals used during the auto-discovery process by an external debug agent.
MTB_AUTHSTAT[3:2] indicates if nonsecure, noninvasive debug is enabled or disabled, while MTB_AUTHSTAT[1:0] indicates the enabled/disabled state of nonsecure, invasive debug. For both 2-bit fields, 0b10 indicates the functionality is disabled and 0b11 indicates it is enabled.
Address: F000_0000h base + FB8h offset = F000_0FB8h
Bit
R
31 30 29 28 27 26 25
W
Reset 0 0 0 0 0 0 0
15 14 13 12 11 10 9 Bit
R
W
Reset 0
Field
31–4
Reserved
3
Reserved
2
BIT2
1
Reserved
0
BIT0
Connected to NIDEN or DBGEN signal.
This read-only field is reserved and always has the value 1.
Connected to DBGEN.
24
0
8
23
0
7
22
0
6
21
0
5
0 0 0 0 0 0 0 0 0 0
MTB_AUTHSTAT field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
This read-only field is reserved and always has the value 1.
20
0
4
0
19
0
3
0
18
0
2
0
17
0
1
0
16
0
0
0
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19.31.11 Device Architecture Register (MTB_DEVICEARCH)
This register indicates the device architecture. It is hardwired to specific values used during the auto-discovery process by an external debug agent.
Address: F000_0000h base + FBCh offset = F000_0FBCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 1 0 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 1
Field
31–0
DEVICEARCH
MTB_DEVICEARCH field descriptions
Description
Hardwired to 0x4770_0A31.
19.31.12 Device Configuration Register (MTB_DEVICECFG)
This register indicates the device configuration. It is hardwired to specific values used during the auto-discovery process by an external debug agent.
Address: F000_0000h base + FC8h offset = F000_0FC8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
DEVICECFG
MTB_DEVICECFG field descriptions
Description
Hardwired to 0x0000_0000.
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19.31.13 Device Type Identifier Register (MTB_DEVICETYPID)
This register indicates the device type ID. It is hardwired to specific values used during the auto-discovery process by an external debug agent.
Address: F000_0000h base + FCCh offset = F000_0FCCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1
Field
31–0
DEVICETYPID
MTB_DEVICETYPID field descriptions
Description
Hardwired to 0x0000_0031.
19.31.14 Peripheral ID Register (MTB_PERIPHIDn)
These registers indicate the peripheral IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent.
Address: F000_0000h base + FD0h offset + (4d × i), where i=0d to 7d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• See field descriptions for the reset values.x = Undefined at reset.
Field
31–0
PERIPHID
MTB_PERIPHIDn field descriptions
Description
Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to 0x0000_00B9; ID2 to
0x0000_000B; and all the others to 0x0000_0000.
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19.31.15 Component ID Register (MTB_COMPIDn)
These registers indicate the component IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent.
Address: F000_0000h base + FF0h offset + (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• See field descriptions for the reset values.x = Undefined at reset.
Field
31–0
COMPID
MTB_COMPIDn field descriptions
Description
Component ID
Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0090; ID2 to 0x0000_0005; ID3 to
0x0000_00B1.
19.3.2 MTB_DWT Memory Map
The MTB_DWT programming model supports a very simplified subset of the v7M debug architecture and follows the standard ARM DWT definition.
MTBDWT memory map
Absolute address
(hex)
F000_1038
F000_1200
Register name
F000_1000 MTB DWT Control Register (MTBDWT_CTRL)
F000_1020 MTB_DWT Comparator Register (MTBDWT_COMP0)
F000_1024 MTB_DWT Comparator Mask Register (MTBDWT_MASK0)
F000_1028
MTB_DWT Comparator Function Register 0
(MTBDWT_FCT0)
F000_1030 MTB_DWT Comparator Register (MTBDWT_COMP1)
F000_1034 MTB_DWT Comparator Mask Register (MTBDWT_MASK1)
MTB_DWT Comparator Function Register 1
(MTBDWT_FCT1)
MTB_DWT Trace Buffer Control Register
(MTBDWT_TBCTRL)
F000_1FC8 Device Configuration Register (MTBDWT_DEVICECFG)
Width
(in bits)
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32
32
32
32
32
32
32
32
32
Access Reset value
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
2F00_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
2000_0000h
0000_0000h
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MTBDWT memory map (continued)
Absolute address
(hex)
Register name
F000_1FCC Device Type Identifier Register (MTBDWT_DEVICETYPID)
F000_1FD0 Peripheral ID Register (MTBDWT_PERIPHID4)
F000_1FD4 Peripheral ID Register (MTBDWT_PERIPHID5)
F000_1FD8 Peripheral ID Register (MTBDWT_PERIPHID6)
F000_1FDC Peripheral ID Register (MTBDWT_PERIPHID7)
F000_1FE0 Peripheral ID Register (MTBDWT_PERIPHID0)
F000_1FE4 Peripheral ID Register (MTBDWT_PERIPHID1)
F000_1FE8 Peripheral ID Register (MTBDWT_PERIPHID2)
F000_1FEC Peripheral ID Register (MTBDWT_PERIPHID3)
Width
(in bits)
Access Reset value
32
32
32
32
32
32
32
32
32
R
R
R
R
R
R
R
R
R
F000_1FF0 Component ID Register (MTBDWT_COMPID0)
F000_1FF4 Component ID Register (MTBDWT_COMPID1)
F000_1FF8 Component ID Register (MTBDWT_COMPID2)
F000_1FFC Component ID Register (MTBDWT_COMPID3)
32
32
32
32
R
R
R
R
Section/ page
0000_0004h
19.32.1 MTB DWT Control Register (MTBDWT_CTRL)
The MTBDWT_CTRL register provides read-only information on the watchpoint configuration for the MTB_DWT.
Address: F000_1000h base + 0h offset = F000_1000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–28
NUMCMP
MTBDWT_CTRL field descriptions
Number of comparators
Description
27–0
DWTCFGCTRL
The MTB_DWT implements two comparators.
DWT configuration controls
This field is hardwired to 0xF00_0000, disabling all the remaining DWT functionality. The specific fields and their state are:
MTBDWT_CTRL[27] = NOTRCPKT = 1, trace sample and exception trace is not supported
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Field
Chapter 19 Micro Trace Buffer (MTB)
MTBDWT_CTRL field descriptions (continued)
Description
MTBDWT_CTRL[26] = NOEXTTRIG = 1, external match signals are not supported
MTBDWT_CTRL[25] = NOCYCCNT = 1, cycle counter is not supported
MTBDWT_CTRL[24] = NOPRFCNT = 1, profiling counters are not supported
MTBDWT_CTRL[22] = CYCEBTENA = 0, no POSTCNT underflow packets generated
MTBDWT_CTRL[21] = FOLDEVTENA = 0, no folded instruction counter overflow events
MTBDWT_CTRL[20] = LSUEVTENA = 0, no LSU counter overflow events
MTBDWT_CTRL[19] = SLEEPEVTENA = 0, no sleep counter overflow events
MTBDWT_CTRL[18] = EXCEVTENA = 0, no exception overhead counter events
MTBDWT_CTRL[17] = CPIEVTENA = 0, no CPI counter overflow events
MTBDWT_CTRL[16] = EXCTRCENA = 0, generation of exception trace disabled
MTBDWT_CTRL[12] = PCSAMPLENA = 0, no periodic PC sample packets generated
MTBDWT_CTRL[11:10] = SYNCTAP = 0, no synchronization packets
MTBDWT_CTRL[9] = CYCTAP = 0, cycle counter is not supported
MTBDWT_CTRL[8:5] = POSTINIT = 0, cycle counter is not supported
MTBDWT_CTRL[4:1] = POSTPRESET = 0, cycle counter is not supported
MTBDWT_CTRL[0] = CYCCNTENA = 0, cycle counter is not supported
19.32.2 MTB_DWT Comparator Register (MTBDWT_COMPn)
The MTBDWT_COMPn registers provide the reference value for comparator n.
Address: F000_1000h base + 20h offset + (16d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
COMP
MTBDWT_COMPn field descriptions
Description
Reference value for comparison
If MTBDWT_COMP0 is used for a data value comparator and the access size is byte or halfword, the data value must be replicated across all appropriate byte lanes of this register. For example, if the data is a byte-sized "x" value, then COMP[31:24] = COMP[23:16] = COMP[15:8] = COMP[7:0] = "x". Likewise, if the data is a halfword-size "y" value, then COMP[31:16] = COMP[15:0] = "y".
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19.32.3 MTB_DWT Comparator Mask Register
(MTBDWT_MASKn)
The MTBDWT_MASKn registers define the size of the ignore mask applied to the reference address for address range matching by comparator n. Note the format of this mask field is different than the MTB_MASTER[MASK].
Address: F000_1000h base + 24h offset + (16d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–5
Reserved
4–0
MASK
MTBDWT_MASKn field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
MASK
The value of the ignore mask, 0-31 bits, is applied to address range matching. MASK = 0 is used to include all bits of the address in the comparison, except if MASK = 0 and the comparator is configured to watch instruction fetch addresses, address bit [0] is ignored by the hardware since all fetches must be at least halfword aligned. For MASK != 0 and regardless of watch type, address bits [x-1:0] are ignored in the address comparison.
Using a mask means the comparator matches on a range of addresses, defined by the unmasked most significant bits of the address, bits [31:x]. The maximum MASK value is 24, producing a 16 Mbyte mask.
An attempted write of a MASK value > 24 is limited by the MTBDWT hardware to 24.
If MTBDWT_COMP0 is used as a data value comparator, then MTBDWT_MASK0 should be programmed to zero.
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19.32.4 MTB_DWT Comparator Function Register 0
(MTBDWT_FCT0)
The MTBDWT_FCTn registers control the operation of comparator n.
Address: F000_1000h base + 28h offset = F000_1028h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
Reset 0
Field
31–25
Reserved
24
MATCHED
0 0 0 0 0 0 0 0 0 0
MTBDWT_FCT0 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Comparator match
0 0 0 0 0
If this read-only flag is asserted, it indicates the operation defined by the FUNCTION field occurred since the last read of the register. Reading the register clears this bit.
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MTBDWT_FCT0 field descriptions (continued)
Field
23–20
Reserved
19–16
Reserved
15–12
DATAVADDR0
11–10
DATAVSIZE
Description
0 No match.
1 Match occurred.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
Data Value Address 0
Since the MTB_DWT implements two comparators, the DATAVADDR0 field is restricted to values {0,1}.
When the DATAVMATCH bit is asserted, this field defines the comparator number to use for linked address comparison.
If MTBDWT_COMP0 is used as a data watchpoint and MTBDWT_COMP1 as an address watchpoint,
DATAVADDR0 must be set.
Data Value Size
For data value matching, this field defines the size of the required data comparison.
9
Reserved
8
DATAVMATCH
00 Byte.
01 Halfword.
10 Word.
11 Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.
This field is reserved.
This read-only field is reserved and always has the value 0.
Data Value Match
When this field is 1, it enables data value comparison. For this implementation, MTBDWT_COMP0 supports address or data value comparisons; MTBDWT_COMP1 only supports address comparisons.
7–4
Reserved
3–0
FUNCTION
0 Perform address comparison.
1 Perform data value comparison.
This field is reserved.
This read-only field is reserved and always has the value 0.
Function
Selects the action taken on a comparator match. If MTBDWT_COMP0 is used for a data value and
MTBDWT_COMP1 for an address value, then MTBDWT_FCT1[FUNCTION] must be set to zero. For this configuration, MTBDWT_MASK1 can be set to a non-zero value, so the combined comparators match on a range of addresses.
0000 Disabled.
0100 Instruction fetch.
0101 Data operand read.
0110 Data operand write.
0111 Data operand (read + write).
others Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.
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19.32.5 MTB_DWT Comparator Function Register 1
(MTBDWT_FCT1)
The MTBDWT_FCTn registers control the operation of comparator n. Since the
MTB_DWT only supports data value comparisons on comparator 0, there are several fields in the MTBDWT_FCT1 register that are RAZ/WI (bits 12, 11:10, 8).
Address: F000_1000h base + 38h offset = F000_1038h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
Reset 0
Field
31–25
Reserved
24
MATCHED
0 0 0 0 0 0 0 0 0 0
MTBDWT_FCT1 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Comparator match
0 0 0 0 0
If this read-only flag is asserted, it indicates the operation defined by the FUNCTION field occurred since the last read of the register. Reading the register clears this bit.
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MTBDWT_FCT1 field descriptions (continued)
Field
23–4
Reserved
3–0
FUNCTION
Description
0 No match.
1 Match occurred.
This field is reserved.
This read-only field is reserved and always has the value 0.
Function
Selects the action taken on a comparator match. If MTBDWT_COMP0 is used for a data value and
MTBDWT_COMP1 for an address value, then MTBDWT_FCT1[FUNCTION] must be set to zero. For this configuration, MTBDWT_MASK1 can be set to a non-zero value, so the combined comparators match on a range of addresses.
0000 Disabled.
0100 Instruction fetch.
0101 Data operand read.
0110 Data operand write.
0111 Data operand (read + write).
others Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.
19.32.6 MTB_DWT Trace Buffer Control Register
(MTBDWT_TBCTRL)
The MTBDWT_TBCTRL register defines how the watchpoint comparisons control the actual trace buffer operation.
Recall the MTB supports starting and stopping the program trace based on the watchpoint comparisons signaled via TSTART and TSTOP. The watchpoint comparison signals are enabled in the MTB's control logic by setting the appropriate enable bits,
MTB_MASTER[TSTARTEN, TSTOPEN]. In the event of simultaneous assertion of both TSTART and TSTOP, TSTART takes priority.
Address: F000_1000h base + 200h offset = F000_1200h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
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Bit 15 14 13 12 11 10 9
R
8 7 6 5
Chapter 19 Micro Trace Buffer (MTB)
4 3 2 1 0
W
Reset 0
Field
31–28
NUMCOMP
0 0 0 0 0 0 0 0 0 0
MTBDWT_TBCTRL field descriptions
Description
Number of Comparators
27–2
Reserved
1
ACOMP1
0 0 0 0 0
This read-only field specifies the number of comparators in the MTB_DWT. This implementation includes two registers.
This field is reserved.
This read-only field is reserved and always has the value 0.
Action based on Comparator 1 match
When the MTBDWT_FCT1[MATCHED] is set, it indicates MTBDWT_COMP1 address compare has triggered and the trace buffer's recording state is changed.
0
ACOMP0
0 Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED].
1 Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED].
Action based on Comparator 0 match
When the MTBDWT_FCT0[MATCHED] is set, it indicates MTBDWT_COMP0 address compare has triggered and the trace buffer's recording state is changed. The assertion of MTBDWT_FCT0[MATCHED] is caused by the following conditions:
• Address match in MTBDWT_COMP0 when MTBDWT_FCT0[DATAVMATCH] = 0
• Data match in MTBDWT_COMP0 when MTBDWT_FCT0[DATAVMATCH, DATAVADDR0] = {1,0}
• Data match in MTBDWT_COMP0 and address match in MTBDWT_COMP1 when
MTBDWT_FCT0[DATAVMATCH, DATAVADDR0] = {1,1}
0 Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED].
1 Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED].
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19.32.7 Device Configuration Register (MTBDWT_DEVICECFG)
This register indicates the device configuration. It is hardwired to specific values used during the auto-discovery process by an external debug agent.
Address: F000_1000h base + FC8h offset = F000_1FC8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
DEVICECFG
MTBDWT_DEVICECFG field descriptions
Description
Hardwired to 0x0000_0000.
19.32.8 Device Type Identifier Register (MTBDWT_DEVICETYPID)
This register indicates the device type ID. It is hardwired to specific values used during the auto-discovery process by an external debug agent.
Address: F000_1000h base + FCCh offset = F000_1FCCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Field
31–0
DEVICETYPID
MTBDWT_DEVICETYPID field descriptions
Description
Hardwired to 0x0000_0004.
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19.32.9 Peripheral ID Register (MTBDWT_PERIPHIDn)
These registers indicate the peripheral IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent.
Address: F000_1000h base + FD0h offset + (4d × i), where i=0d to 7d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• See field descriptions for the reset values. x = Undefined at reset.
Field
31–0
PERIPHID
MTBDWT_PERIPHIDn field descriptions
Description
Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the others to 0x0000_0000.
19.32.10 Component ID Register (MTBDWT_COMPIDn)
These registers indicate the component IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent.
Address: F000_1000h base + FF0h offset + (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• See field descriptions for the reset values.x = Undefined at reset.
Field
31–0
COMPID
MTBDWT_COMPIDn field descriptions
Description
Component ID
Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0090; ID2 to 0x0000_0005; ID3 to
0x0000_00B1.
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19.3.3 System ROM Memory Map
The System ROM Table registers are also mapped into a sparsely-populated 4 KB address space.
For core configurations like that supported by Cortex-M0+, ARM recommends that a debugger identifies and connects to the debug components using the CoreSight debug infrastructure.
ARM recommends that a debugger follows the flow as shown in the following figure to discover the components in the CoreSight debug infrastructure. In this case, a debugger reads the peripheral and component ID registers for each CoreSight component in the
CoreSight system.
Figure 19-56. CoreSight discovery process
ROM memory map
Absolute address
(hex)
F000_2000 Entry (ROM_ENTRY0)
F000_2004 Entry (ROM_ENTRY1)
F000_2008 Entry (ROM_ENTRY2)
Register name
F000_200C End of Table Marker Register (ROM_TABLEMARK)
F000_2FCC System Access Register (ROM_SYSACCESS)
F000_2FD0 Peripheral ID Register (ROM_PERIPHID4)
F000_2FD4 Peripheral ID Register (ROM_PERIPHID5)
F000_2FD8 Peripheral ID Register (ROM_PERIPHID6)
Width
(in bits)
Table continues on the next page...
32
32
32
32
32
32
32
32
Access Reset value
R
R
R
R
R
R
R
R
0000_0000h
0000_0001h
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Chapter 19 Micro Trace Buffer (MTB)
ROM memory map (continued)
Absolute address
(hex)
Register name
F000_2FDC Peripheral ID Register (ROM_PERIPHID7)
F000_2FE0 Peripheral ID Register (ROM_PERIPHID0)
F000_2FE4 Peripheral ID Register (ROM_PERIPHID1)
F000_2FE8 Peripheral ID Register (ROM_PERIPHID2)
F000_2FEC Peripheral ID Register (ROM_PERIPHID3)
F000_2FF0 Component ID Register (ROM_COMPID0)
F000_2FF4 Component ID Register (ROM_COMPID1)
F000_2FF8 Component ID Register (ROM_COMPID2)
F000_2FFC Component ID Register (ROM_COMPID3)
Width
(in bits)
Access Reset value
32
32
32
32
32
32
32
32
32
R
R
R
R
R
R
R
R
R
Section/ page
19.33.1 Entry (ROM_ENTRYn)
The System ROM Table begins with "n" relative 32-bit addresses, one for each debug component present in the device and terminating with an all-zero value signaling the end of the table at the "n+1"-th value.
It is hardwired to specific values used during the auto-discovery process by an external debug agent.
Address: F000_2000h base + 0h offset + (4d × i), where i=0d to 2d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• See field descriptions for reset values.x = Undefined at reset.
Field
31–0
ENTRY
ROM_ENTRYn field descriptions
Description
ENTRY
Entry 0 (MTB) is hardwired to 0xFFFF_E003; Entry 1 (MTBDWT) to 0xFFFF_F003; Entry 2 (CM0+ ROM
Table) to 0xF00F_D003.
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19.33.2 End of Table Marker Register (ROM_TABLEMARK)
This register indicates end of table marker. It is hardwired to specific values used during the auto-discovery process by an external debug agent.
Address: F000_2000h base + Ch offset = F000_200Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
MARK
ROM_TABLEMARK field descriptions
Description
Hardwired to 0x0000_0000
19.33.3 System Access Register (ROM_SYSACCESS)
This register indicates system access. It is hardwired to specific values used during the auto-discovery process by an external debug agent.
Address: F000_2000h base + FCCh offset = F000_2FCCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Field
31–0
SYSACCESS
ROM_SYSACCESS field descriptions
Description
Hardwired to 0x0000_0001
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19.33.4 Peripheral ID Register (ROM_PERIPHIDn)
These registers indicate the peripheral IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent.
Address: F000_2000h base + FD0h offset + (4d × i), where i=0d to 7d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• See field descriptions for reset values.x = Undefined at reset.
Field
31–0
PERIPHID
ROM_PERIPHIDn field descriptions
Description
Peripheral ID1 is hardwired to 0x0000_00E0; ID2 to 0x0000_0008; and all the others to 0x0000_0000.
19.33.5 Component ID Register (ROM_COMPIDn)
These registers indicate the component IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent.
Address: F000_2000h base + FF0h offset + (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• See field descriptions for reset values.x = Undefined at reset.
Field
31–0
COMPID
ROM_COMPIDn field descriptions
Description
Component ID
Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0010; ID2 to 0x0000_0005; ID3 to
0x0000_00B1.
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Chapter 20
Crossbar Switch Lite (AXBS-Lite)
This chapter provides information on the layout, configuration, and programming of the crossbar switch. The crossbar switch connects bus masters and bus slaves using a crossbar switch structure.
20.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
The information found here provides information on the layout, configuration, and programming of the crossbar switch.
The crossbar switch connects bus masters and bus slaves using a crossbar switch structure. This structure allows up to four bus masters to access different bus slaves simultaneously, while providing arbitration among the bus masters when they access the same slave.
20.1.1 Features
The crossbar switch includes these features:
• Symmetric crossbar bus switch implementation
• Allows concurrent accesses from different masters to different slaves
• 32-bit data bus
• Operation at a 1-to-1 clock frequency with the bus masters
• Programmable configuration for fixed-priority or round-robin slave port arbitration
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20.2 Memory Map / Register Definition
This crossbar switch is designed for minimal gate count. It, therefore, has no memorymapped configuration registers.
20.3 Functional Description
20.3.1 General operation
When a master accesses the crossbar switch, the access is immediately taken. If the targeted slave port of the access is available, then the access is immediately presented on the slave port. Single-clock or zero-wait-state accesses are possible through the crossbar.
If the targeted slave port of the access is busy or parked on a different master port, the requesting master simply sees wait states inserted until the targeted slave port can service the master's request. The latency in servicing the request depends on each master's priority level and the responding slave's access time.
Because the crossbar switch appears to be just another slave to the master device, the master device has no knowledge of whether it actually owns the slave port it is targeting.
While the master does not have control of the slave port it is targeting, it simply waits.
A master is given control of the targeted slave port only after a previous access to a different slave port completes, regardless of its priority on the newly targeted slave port.
This prevents deadlock from occurring when:
• A higher priority master has:
• An outstanding request to one slave port that has a long response time and
• A pending access to a different slave port, and
• A lower priority master is also making a request to the same slave port as the pending access of the higher priority master.
After the master has control of the slave port it is targeting, the master remains in control of the slave port until it relinquishes the slave port by running an IDLE cycle or by targeting a different slave port for its next access.
The master can also lose control of the slave port if another higher-priority master makes a request to the slave port.
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The crossbar terminates all master IDLE transfers, as opposed to allowing the termination to come from one of the slave buses. Additionally, when no master is requesting access to a slave port, the crossbar drives IDLE transfers onto the slave bus, even though a default master may be granted access to the slave port.
When a slave bus is being idled by the crossbar, it remains parked with the last master to use the slave port. This is done to save the initial clock of arbitration delay that otherwise would be seen if the master had to arbitrate to gain control of the slave port.
20.3.2 Arbitration
The crossbar switch supports two arbitration algorithms:
• Fixed priority
• Round-robin
The selection of the global slave port arbitration is controlled by MCM_PLACR[ARB].
For fixed priority, set MCM_PLACR[ARB] to 0. For round robin, set
MCM_PLACR[ARB] to 1. This arbitration setting applies to all slave ports.
20.3.2.1 Arbitration during undefined length bursts
All lengths of burst accesses lock out arbitration until the last beat of the burst.
20.3.2.2 Fixed-priority operation
When operating in fixed-priority mode, each master is assigned a unique priority level with the highest numbered master having the highest priority (master 1 has lower priority than master 3). If two masters request access to the same slave port, the master with the highest priority gains control over the slave port.
NOTE
In this arbitration mode, a higher-priority master can monopolize a slave port, preventing accesses from any lowerpriority master to the port.
When a master makes a request to a slave port, the slave port checks whether the new requesting master's priority level is higher than that of the master that currently has control over the slave port, unless the slave port is in a parked state. The slave port performs an arbitration check at every clock edge to ensure that the proper master, if any, has control of the slave port.
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The following table describes possible scenarios based on the requesting master port:
Table 20-1. How AXBS grants control of a slave port to a master
When Then AXBS grants control to the requesting master
Both of the following are true:
• The current master is not running a transfer.
• The new requesting master's priority level is higher than that of the current master.
The requesting master's priority level is lower than the current master.
At the next clock edge
At the conclusion of one of the following cycles:
• An IDLE cycle
• A non-IDLE cycle to a location other than the current slave port
20.3.2.3 Round-robin priority operation
When operating in round-robin mode, each master is assigned a relative priority based on the master port number. This relative priority is compared to the master port number (ID) of the last master to perform a transfer on the slave bus. The highest priority requesting master becomes owner of the slave bus at the next transfer boundary. Priority is based on how far ahead the ID of the requesting master is to the ID of the last master.
After granted access to a slave port, a master may perform as many transfers as desired to that port until another master makes a request to the same slave port. The next master in line is granted access to the slave port at the next transfer boundary, or possibly on the next clock cycle if the current master has no pending access request.
As an example of arbitration in round-robin mode, assume the crossbar is implemented with master ports 0, 1, 4, and 5. If the last master of the slave port was master 1, and master 0, 4, and 5 make simultaneous requests, they are serviced in the order: 4 then 5 then 0.
The round-robin arbitration mode generally provides a more fair allocation of the available slave-port bandwidth (compared to fixed priority) as the fixed master priority does not affect the master selection.
20.4 Initialization/application information
No initialization is required for the crossbar switch.
See the AXBS section of the configuration chapter for the reset state of the arbitration scheme.
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Chapter 21
Peripheral Bridge (AIPS-Lite)
The Peripheral Bridge (AIPS-Lite) converts the crossbar switch interface to an interface to access a majority of peripherals on the device. The peripheral bridge supports up to
128 peripherals, including separate clock enable inputs for each of the slots to accommodate slower peripherals.
21.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
The peripheral bridge converts the crossbar switch interface to an interface that can access most of the slave peripherals on this chip.
The peripheral bridge occupies 64 MB of the address space, which is divided into peripheral slots of 4 KB. (It might be possible that all the peripheral slots are not used.
See the memory map chapter for details on slot assignments.) The bridge includes separate clock enable inputs for each of the slots to accommodate slower peripherals.
21.1.1 Features
Key features of the peripheral bridge are:
• Supports peripheral slots with 8-, 16-, and 32-bit datapath width
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21.1.2 General operation
The slave devices connected to the peripheral bridge are modules which contain a programming model of control and status registers. The system masters read and write these registers through the peripheral bridge. The peripheral bridge performs a bus protocol conversion of the master transactions and generates the following as inputs to the peripherals:
• Module enables
• Module addresses
• Transfer attributes
• Byte enables
• Write data
The peripheral bridge selects and captures read data from the peripheral interface and returns it to the crossbar switch.
The register maps of the peripherals are located on 4-KB boundaries. Each peripheral is allocated one or more 4-KB block(s) of the memory map.
The AIPS-Lite module uses the data width of accessed peripheral to perform proper data byte lane routing; bus decomposition (bus sizing) is performed when the access size is larger than the peripheral's data width.
21.2 Functional description
The peripheral bridge functions as a bus protocol translator between the crossbar switch and the slave peripheral bus.
The peripheral bridge manages all transactions destined for the attached slave devices and generates select signals for modules on the peripheral bus by decoding accesses within the attached address space.
21.2.1 Access support
All combinations of access size and peripheral data port width are supported. An access that is larger than the target peripheral's data width will be decomposed to multiple, smaller accesses. Bus decomposition is terminated by a transfer error caused by an access to an empty register area.
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Chapter 22
Direct Memory Access Multiplexer (DMAMUX)
DMA MUX provides flexibility in the system's use of the available DMA channels. The
DMA MUX routes up to 63 DMA sources, which are called slots to be mapped to any of the 16 DMA channels. Functionally, the DMA MUX channels may be divided into two classes: Channels that implement the normal routing functionality plus periodic triggering capability, and channels that implement only the normal routing functionality.
22.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
22.1.1 Overview
The Direct Memory Access Multiplexer (DMAMUX) routes DMA sources, called slots, to any of the four DMA channels. This process is illustrated in the following figure.
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Source #1
Source #2
Source #3
DMAMUX
DMA channel #0
DMA channel #1
Source # x
Always #1
Always # y
Trigger #1
DMA channel #n
Trigger # z
Figure 22-1. DMAMUX block diagram
22.1.2 Features
The DMAMUX module provides these features:
• Up to 63 peripheral slots and up to four always-on slots can be routed to four channels.
• four independently selectable DMA channel routers.
• The first two channels additionally provide a trigger functionality.
• Each channel router can be assigned to one of the possible peripheral DMA slots or to one of the always-on slots.
22.1.3 Modes of operation
The following operating modes are available:
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• Disabled mode
In this mode, the DMA channel is disabled. Because disabling and enabling of DMA channels is done primarily via the DMA configuration registers, this mode is used mainly as the reset state for a DMA channel in the DMA channel MUX. It may also be used to temporarily suspend a DMA channel while reconfiguration of the system takes place, for example, changing the period of a DMA trigger.
• Normal mode
In this mode, a DMA source is routed directly to the specified DMA channel. The operation of the DMAMUX in this mode is completely transparent to the system.
• Periodic Trigger mode
In this mode, a DMA source may only request a DMA transfer, such as when a transmit buffer becomes empty or a receive buffer becomes full, periodically.
Configuration of the period is done in the registers of the periodic interrupt timer
(PIT). This mode is available only for channels 0–1.
22.2 External signal description
The DMAMUX has no external pins.
22.3 Memory map/register definition
This section provides a detailed description of all memory-mapped registers in the
DMAMUX.
DMAMUX memory map
Absolute address
(hex)
Register name
4002_1000 Channel Configuration register (DMAMUX0_CHCFG0)
4002_1001 Channel Configuration register (DMAMUX0_CHCFG1)
4002_1002 Channel Configuration register (DMAMUX0_CHCFG2)
4002_1003 Channel Configuration register (DMAMUX0_CHCFG3)
Width
(in bits)
Access Reset value
8
8
8
8
R/W
R/W
R/W
R/W
00h
00h
00h
00h
Section/ page
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22.3.1 Channel Configuration register (DMAMUXx_CHCFGn)
Each of the DMA channels can be independently enabled/disabled and associated with one of the DMA slots (peripheral slots or always-on slots) in the system.
NOTE
Setting multiple CHCFG registers with the same source value will result in unpredictable behavior.
Before changing the trigger or source settings, a DMA channel must be disabled via CHCFGn[ENBL].
Address: 4002_1000h base + 0h offset + (1d × i), where i=0d to 3d
Bit
Read
Write
Reset
7
0
6
0
5
0
4
0
Field
7
ENBL
DMAMUXx_CHCFGn field descriptions
Description
DMA Channel Enable
Enables the DMA channel.
3
0
2
0
6
TRIG
5–0
SOURCE
1
0
0
0
0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
1 DMA channel is enabled
DMA Channel Trigger Enable
Enables the periodic trigger capability for the triggered DMA channel.
0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
DMA Channel Source (Slot)
Specifies which DMA source, if any, is routed to a particular DMA channel. See your device's chip configuration details for information about the peripherals and their slot numbers.
22.4 Functional description
The primary purpose of the DMAMUX is to provide flexibility in the system's use of the available DMA channels.
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As such, configuration of the DMAMUX is intended to be a static procedure done during
is followed, the configuration of the DMAMUX may be changed during the normal operation of the system.
Functionally, the DMAMUX channels may be divided into two classes:
• Channels that implement the normal routing functionality plus periodic triggering capability
• Channels that implement only the normal routing functionality
22.4.1 DMA channels with periodic triggering capability
Besides the normal routing functionality, the first 2 channels of the DMAMUX provide a special periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes, frames, or packets at fixed intervals without the need for processor intervention. The trigger is generated by the periodic interrupt timer (PIT); as such, the configuration of the periodic triggering interval is done via configuration registers in the
PIT. See the section on periodic interrupt timer for more information on this topic.
Note
Because of the dynamic nature of the system (due to DMA channel priorities, bus arbitration, interrupt service routine lengths, etc.), the number of clock cycles between a trigger and the actual DMA transfer cannot be guaranteed.
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Source #1
Source #2
Source #3
Trigger #1
DMA channel #0
Source # x
Always #1
Trigger #m
DMA channel #m-1
Always # y
Figure 22-12. DMAMUX triggered channels
The DMA channel triggering capability allows the system to schedule regular DMA transfers, usually on the transmit side of certain peripherals, without the intervention of the processor. This trigger works by gating the request from the peripheral to the DMA until a trigger event has been seen. This is illustrated in the following figure.
Peripheral request
Trigger
DMA request
Figure 22-13. DMAMUX channel triggering: normal operation
After the DMA request has been serviced, the peripheral will negate its request, effectively resetting the gating mechanism until the peripheral reasserts its request and the next trigger event is seen. This means that if a trigger is seen, but the peripheral is not requesting a transfer, then that trigger will be ignored. This situation is illustrated in the following figure.
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Peripheral request
Trigger
DMA request
Figure 22-14. DMAMUX channel triggering: ignored trigger
This triggering capability may be used with any peripheral that supports DMA transfers, and is most useful for two types of situations:
• Periodically polling external devices on a particular bus
As an example, the transmit side of an SPI is assigned to a DMA channel with a trigger, as described above. After it has been set up, the SPI will request DMA transfers, presumably from memory, as long as its transmit buffer is empty. By using a trigger on this channel, the SPI transfers can be automatically performed every 5 μ s
(as an example). On the receive side of the SPI, the SPI and DMA can be configured to transfer receive data into memory, effectively implementing a method to periodically read data from external devices and transfer the results into memory without processor intervention.
• Using the GPIO ports to drive or sample waveforms
By configuring the DMA to transfer data to one or more GPIO ports, it is possible to create complex waveforms using tabular data stored in on-chip memory. Conversely, using the DMA to periodically transfer data from one or more GPIO ports, it is possible to sample complex waveforms and store the results in tabular form in onchip memory.
A more detailed description of the capability of each trigger, including resolution, range of values, and so on, may be found in the periodic interrupt timer section.
22.4.2 DMA channels with no triggering capability
The other channels of the DMAMUX provide the normal routing functionality as
described in Modes of operation .
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22.4.3 Always-enabled DMA sources
In addition to the peripherals that can be used as DMA sources, there are four additional
DMA sources that are always enabled. Unlike the peripheral DMA sources, where the peripheral controls the flow of data during DMA transfers, the sources that are always enabled provide no such "throttling" of the data transfers. These sources are most useful in the following cases:
• Performing DMA transfers to/from GPIO—Moving data from/to one or more GPIO pins, either unthrottled (that is, as fast as possible), or periodically (using the DMA triggering capability).
• Performing DMA transfers from memory to memory—Moving data from memory to memory, typically as fast as possible, sometimes with software activation.
• Performing DMA transfers from memory to the external bus, or vice-versa—Similar to memory to memory transfers, this is typically done as quickly as possible.
• Any DMA transfer that requires software activation—Any DMA transfer that should be explicitly started by software.
In cases where software should initiate the start of a DMA transfer, an always-enabled
DMA source can be used to provide maximum flexibility. When activating a DMA channel via software, subsequent executions of the minor loop require that a new start event be sent. This can either be a new software activation, or a transfer request from the
DMA channel MUX. The options for doing this are:
• Transfer all data in a single minor loop.
By configuring the DMA to transfer all of the data in a single minor loop (that is, major loop counter = 1), no reactivation of the channel is necessary. The disadvantage to this option is the reduced granularity in determining the load that the
DMA transfer will impose on the system. For this option, the DMA channel must be disabled in the DMA channel MUX.
• Use explicit software reactivation.
In this option, the DMA is configured to transfer the data using both minor and major loops, but the processor is required to reactivate the channel by writing to the DMA registers after every minor loop. For this option, the DMA channel must be disabled in the DMA channel MUX.
• Use an always-enabled DMA source.
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In this option, the DMA is configured to transfer the data using both minor and major loops, and the DMA channel MUX does the channel reactivation. For this option, the
DMA channel should be enabled and pointing to an "always enabled" source. Note that the reactivation of the channel can be continuous (DMA triggering is disabled) or can use the DMA triggering capability. In this manner, it is possible to execute periodic transfers of packets of data from one source to another, without processor intervention.
22.5 Initialization/application information
This section provides instructions for initializing the DMA channel MUX.
22.5.1 Reset
The reset state of each individual bit is shown in
Memory map/register definition
. In summary, after reset, all channels are disabled and must be explicitly enabled before use.
22.5.2 Enabling and configuring sources
To enable a source with periodic triggering:
1. Determine with which DMA channel the source will be associated. Note that only the first 2 DMA channels have periodic triggering capability.
2. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel.
3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point.
4. Configure the corresponding timer.
5. Select the source to be routed to the DMA channel. Write to the corresponding
CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are set.
NOTE
The following is an example. See the chip configuration details for the number of this device's DMA channels that have triggering capability.
To configure source #5 transmit for use with DMA channel 1, with periodic triggering capability:
1. Write 0x00 to CHCFG1 (base address + 0x01).
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2. Configure channel 1 in the DMA, including enabling the channel.
3. Configure a timer for the desired trigger interval.
4. Write 0xC5 to CHCFG1 (base address + 0x01).
The following code example illustrates steps 1 and 4 above:
In File registers.h:
#define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! */
/* Following example assumes char is 8-bits */ volatile unsigned char *CHCFG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000); volatile unsigned char *CHCFG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001); volatile unsigned char *CHCFG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002); volatile unsigned char *CHCFG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0003); volatile unsigned char *CHCFG4 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0004); volatile unsigned char *CHCFG5 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0005); volatile unsigned char *CHCFG6 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0006); volatile unsigned char *CHCFG7 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0007); volatile unsigned char *CHCFG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008); volatile unsigned char *CHCFG9 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0009); volatile unsigned char *CHCFG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A); volatile unsigned char *CHCFG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B); volatile unsigned char *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F);
:
:
In File main.c:
#include "registers.h"
*CHCFG1 = 0x00;
*CHCFG1 = 0xC5;
To enable a source without periodic triggering:
1. Determine with which DMA channel the source will be associated. Note that only the first 2 DMA channels have periodic triggering capability.
2. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel.
3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point.
4. Select the source to be routed to the DMA channel. Write to the corresponding
CHCFG register, ensuring that CHCFG[ENBL] is set while CHCFG[TRIG] is cleared.
NOTE
The following is an example. See the chip configuration details for the number of this device's DMA channels that have triggering capability.
To configure source #5 transmit for use with DMA channel 1, with no periodic triggering capability:
1. Write 0x00 to CHCFG1 (base address + 0x01).
2. Configure channel 1 in the DMA, including enabling the channel.
3. Write 0x85 to CHCFG1 (base address + 0x01).
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The following code example illustrates steps 1 and 3 above:
In File registers.h:
#define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! */
/* Following example assumes char is 8-bits */ volatile unsigned char *CHCFG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000); volatile unsigned char *CHCFG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001); volatile unsigned char *CHCFG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002); volatile unsigned char *CHCFG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0003); volatile unsigned char *CHCFG4 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0004); volatile unsigned char *CHCFG5 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0005); volatile unsigned char *CHCFG6 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0006); volatile unsigned char *CHCFG7 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0007); volatile unsigned char *CHCFG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008); volatile unsigned char *CHCFG9 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0009); volatile unsigned char *CHCFG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A); volatile unsigned char *CHCFG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B); volatile unsigned char *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F);
:
:
In File main.c:
#include "registers.h"
*CHCFG1 = 0x00;
*CHCFG1 = 0x85;
To disable a source:
A particular DMA source may be disabled by not writing the corresponding source value into any of the CHCFG registers. Additionally, some module-specific configuration may be necessary. See the appropriate section for more details.
To switch the source of a DMA channel:
1. Disable the DMA channel in the DMA and reconfigure the channel for the new source.
2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel.
3. Select the source to be routed to the DMA channel. Write to the corresponding
CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are set.
To switch DMA channel 8 from source #5 transmit to source #7 transmit:
1. In the DMA configuration registers, disable DMA channel 8 and reconfigure it to handle the transfers to peripheral slot 7. This example assumes channel 8 doesn't have triggering capability.
2. Write 0x00 to CHCFG8 (base address + 0x08).
3. Write 0x87 to CHCFG8 (base address + 0x08). (In this example, setting
CHCFG[TRIG] would have no effect due to the assumption that channel 8 does not support the periodic triggering functionality).
The following code example illustrates steps 2 and 3 above:
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In File registers.h:
#define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! */
/* Following example assumes char is 8-bits */ volatile unsigned char *CHCFG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000); volatile unsigned char *CHCFG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001); volatile unsigned char *CHCFG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002); volatile unsigned char *CHCFG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0003); volatile unsigned char *CHCFG4 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0004); volatile unsigned char *CHCFG5 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0005); volatile unsigned char *CHCFG6 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0006); volatile unsigned char *CHCFG7 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0007); volatile unsigned char *CHCFG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008); volatile unsigned char *CHCFG9 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0009); volatile unsigned char *CHCFG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A); volatile unsigned char *CHCFG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B); volatile unsigned char *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F);
:
:
In File main.c:
#include "registers.h"
*CHCFG8 = 0x00;
*CHCFG8 = 0x87;
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Chapter 23
DMA Controller Module
DMA Controller Module describes in detail its signals and programming model. It also explains operations, features, and supported data transfer modes.
23.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
Information found here describes the direct memory access (DMA) controller module. It provides an overview of the module and describes in detail its signals and programming model.
The latter sections of this chapter describe operations, features, and supported data transfer modes in detail.
An example of using several features of the DMA module is described in AN4631: Using the Asynchronous DMA features of the Kinetis L Series .
Note
The designation n is used throughout this section to refer to registers or signals associated with one of the four identical
DMA channels: DMA0, DMA1, DMA2, or DMA3.
23.1.1 Overview
The DMA controller module enables fast transfers of data, providing an efficient way to move blocks of data with minimal processor interaction. The DMA module, shown in the following figure, has four channels that allow 8-bit, 16-bit, or 32-bit data transfers. Each
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Introduction channel has a dedicated Source Address register (SARn), Destination Address register
(DARn), Status register (DSRn), Byte Count register (BCRn), and Control register
(DCRn). Collectively, the combined program-visible registers associated with each channel define a transfer control descriptor (TCD). All transfers are dual address, moving data from a source memory location to a destination memory location with the module operating as a 32-bit bus master connected to the system bus. The programming model is accessed through a 32-bit connection with the slave peripheral bus. DMA data transfers may be explicitly initiated by software or by peripheral hardware requests.
The following figure is a simplified block diagram of the 4-channel DMA controller.
DREQ0
DACK0
DREQ1
DACK1
DREQ2
DACK2
DREQ3
DACK3
Slave
Peripheral Bus
Channel
Requests
Channel 0 Channel 1 Channel 2 Channel 3
SAR0
DAR0
DSR0
BCR0
DCR0
SAR1
DAR1
DSR1
BCR1
DCR1
SAR2
DAR2
DSR2
BCR2
DCR2
SAR3
DAR3
DSR3
BCR3
DCR3
Interrupts
Channel
Enables
MUX
Control
Channel
Attributes
MUX
System Bus Address
System Bus Size
Current Master Attributes
SysBus Interface
Data Path
Read Data Bus Write Data Bus
Data Path
Control
Arbitraton/
Control
SysBus Interface
Addr + Attr
Registered Addr
Phase Bus Signals
Figure 23-1. 4-Channel DMA Block Diagram
The terms peripheral request and DREQ refer to a DMA request from one of the on-chip peripherals or package pins. The DMA provides hardware handshake signals: either a
DMA acknowledge (DACK) or a done indicator back to the peripheral.
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Chapter 23 DMA Controller Module
23.1.2 Features
The DMA controller module features:
• Four independently programmable DMA controller channels
• Dual-address transfers via 32-bit master connection to the system bus
• Data transfers in 8-, 16-, or 32-bit blocks
• Continuous-mode or cycle-steal transfers from software or peripheral initiation
• Automatic hardware acknowledge/done indicator from each channel
• Independent source and destination address registers
• Optional modulo addressing and automatic updates of source and destination addresses
• Independent transfer sizes for source and destination
• Optional auto-alignment feature for source or destination accesses
• Optional automatic single or double channel linking
• Programming model accessed via 32-bit slave peripheral bus
• Channel arbitration on transfer boundaries using fixed priority scheme
23.2 DMA Transfer Overview
The DMA module can move data within system memory (including memory and peripheral devices) with minimal processor intervention, greatly improving overall system performance.
The DMA module consists of four independent, functionally equivalent channels, so references to DMA in this chapter apply to any of the channels. It is not possible to address all four channels at once.
As soon as a channel has been initialized, it may be started by setting DCRn[START] or a properly-selected peripheral DMA request, depending on the status of DCRn[ERQ].
The DMA controller supports dual-address transfers using its bus master connection to the system bus. The DMA channels support transfers up to 32 data bits in size and have the same memory map addressibility as the processor.
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Memory Map/Register Definition
• Dual-address transfers—A dual-address transfer consists of a read followed by a write and is initiated by a request using the DCRn[START] bit or by a peripheral
DMA request. The read data is temporarily held in the DMA channel hardware until the write operation. Two types of single transfers occur: a read from a source address followed by a write to a destination address. See the following figure.
Control and Data
Read
Memory/
Peripheral
DMA
Control and Data
Write
Memory/
Peripheral
Figure 23-2. Dual-Address Transfer
Any operation involving a DMA channel follows the same three steps:
1. Channel initialization—The transfer control descriptor, contained in the channel registers, is loaded with address pointers, a byte-transfer count, and control information using accesses from the slave peripheral bus.
2. Data transfer—The DMA accepts requests for data transfers. Upon receipt of a request, it provides address and bus control for the transfers via its master connection to the system bus and temporary storage for the read data. The channel performs one or more source read and destination write data transfers.
3. Channel termination—Occurs after the operation is finished successfully or due to an error. The channel indicates the operation status in the channel's DSR, described in the definitions of the DMA Status Registers (DSRn) and Byte Count Registers
(BCRn).
23.3 Memory Map/Register Definition
Information about the registers related to the DMA controller module can be found here.
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Descriptions of each register and its bit assignments follow. Modifying DMA control registers during a transfer can result in undefined operation. The following table shows the mapping of DMA controller registers. The DMA programming model is accessed via the slave peripheral bus. The concatenation of the source and destination address registers, the status and byte count register, and the control register create a 128-bit transfer control descriptor (TCD) that defines the operation of each DMA channel.
DMA memory map
Absolute address
(hex)
Register name
4000_8100 Source Address Register (DMA_SAR0)
4000_8104 Destination Address Register (DMA_DAR0)
4000_8108
DMA Status Register / Byte Count Register
(DMA_DSR_BCR0)
4000_810C DMA Control Register (DMA_DCR0)
4000_8110 Source Address Register (DMA_SAR1)
4000_8114 Destination Address Register (DMA_DAR1)
4000_8118
DMA Status Register / Byte Count Register
(DMA_DSR_BCR1)
4000_811C DMA Control Register (DMA_DCR1)
4000_8120 Source Address Register (DMA_SAR2)
4000_8124 Destination Address Register (DMA_DAR2)
4000_8128
DMA Status Register / Byte Count Register
(DMA_DSR_BCR2)
4000_812C DMA Control Register (DMA_DCR2)
4000_8130 Source Address Register (DMA_SAR3)
4000_8134 Destination Address Register (DMA_DAR3)
4000_8138
DMA Status Register / Byte Count Register
(DMA_DSR_BCR3)
4000_813C DMA Control Register (DMA_DCR3)
Width
(in bits)
Access Reset value
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Section/ page
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
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Memory Map/Register Definition
23.3.1 Source Address Register (DMA_SARn)
Restriction
For this register:
• Only 32-bit writes are allowed. 16-bit and 8-bit writes result in a bus error.
• Only four values are allowed to be written to bits 31-20 of this register. A write of any other value to these bits causes a configuration error when the channel starts to execute.
For more information about the configuration error, see the
field of DSR.
Address: 4000_8000h base + 100h offset + (16d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
SAR
DMA_SARn field descriptions
Description
Each SAR contains the byte address used by the DMA controller to read data. The SARn is typically aligned on a 0-modulo-ssize boundary—that is, on the natural alignment of the source data.
Restriction: Bits 31-20 of this register must be written with one of only four allowed values. Each of these four allowed values corresponds to a valid region of the device's memory map. The allowed values are:
• 0x000x_xxxx
• 0x1FFx_xxxx
• 0x200x_xxxx
• 0x400x_xxxx
After being written with one of the allowed values, bits 31-20 read back as the written value.
After being written with any other value, bits 31-20 read back as an indeterminate value.
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23.3.2 Destination Address Register (DMA_DARn)
Restriction
For this register:
• Only 32-bit writes are allowed. 16-bit and 8-bit writes result in a bus error.
• Only four values are allowed to be written to bits 31-20 of this register. A write of any other value to these bits causes a configuration error when the channel starts to execute.
For more information about the configuration error, see the
field of DSR.
Address: 4000_8000h base + 104h offset + (16d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
DAR
DMA_DARn field descriptions
Description
Each DAR contains the byte address used by the DMA controller to write data. The DARn is typically aligned on a 0-modulo-dsize boundary—that is, on the natural alignment of the destination data.
Restriction: Bits 31-20 of this register must be written with one of only four allowed values. Each of these four allowed values corresponds to a valid region of the device's memory map. The allowed values are:
• 0x000x_xxxx
• 0x1FFx_xxxx
• 0x200x_xxxx
• 0x400x_xxxx
After being written with one of the allowed values, bits 31-20 read back as the written value.
After being written with any other value, bits 31-20 read back as an indeterminate value.
23.3.3 DMA Status Register / Byte Count Register
(DMA_DSR_BCRn)
DSR and BCR are two logical registers that occupy one 32-bit address. DSRn occupies bits 31–24, and BCRn occupies bits 23–0. DSRn contains flags indicating the channel status, and BCRn contains the number of bytes yet to be transferred for a given block.
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Memory Map/Register Definition
On the successful completion of the write transfer, BCRn decrements by 1, 2, or 4 for 8bit, 16-bit, or 32-bit accesses, respectively. BCRn is cleared if a 1 is written to
DSR[DONE].
In response to an event, the DMA controller writes to the appropriate DSRn bit. Only a write to DSRn[DONE] results in action. DSRn[DONE] is set when the block transfer is complete.
When a transfer sequence is initiated and BCRn[BCR] is not a multiple of 4 or 2 when the DMA is configured for 32-bit or 16-bit transfers, respectively, DSRn[CE] is set and no transfer occurs.
Address: 4000_8000h base + 108h offset + (16d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset
Bit
0
15
R
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
W
Reset 0
Field
31
Reserved
30
CE
0 0 0 0 0 0 0 0 0 0
DMA_DSR_BCRn field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Configuration Error
0 0 0 0
Any of the following conditions causes a configuration error:
• BCR, SAR, or DAR does not match the requested transfer size.
• A value greater than 0F_FFFFh is written to BCR.
• Bits 31-20 of SAR or DAR are written with a value other than one of the allowed values. See
• SSIZE or DSIZE is set to an unsupported value.
• BCR equals 0 when the DMA receives a start condition.
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0
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Field
29
BES
28
BED
27
Reserved
26
REQ
25
BSY
24
DONE
23–0
BCR
Chapter 23 DMA Controller Module
DMA_DSR_BCRn field descriptions (continued)
Description
CE is cleared at hardware reset or by writing a 1 to DONE.
0 No configuration error exists.
1 A configuration error has occurred.
Bus Error on Source
BES is cleared at hardware reset or by writing a 1 to DONE.
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the read portion of a transfer.
Bus Error on Destination
BED is cleared at hardware reset or by writing a 1 to DONE.
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the write portion of a transfer.
This field is reserved.
This read-only field is reserved and always has the value 0.
Request
0 No request is pending or the channel is currently active. Cleared when the channel is selected.
1 The DMA channel has a transfer remaining and the channel is not selected.
Busy
0 DMA channel is inactive. Cleared when the DMA has finished the last transaction.
1 BSY is set the first time the channel is enabled after a transfer is initiated.
Transactions Done
Set when all DMA controller transactions complete as determined by transfer count, or based on error conditions. When BCR reaches 0, DONE is set when the final transfer completes successfully. DONE can also be used to abort a transfer by resetting the status bits. When a transfer completes, software must clear DONE before reprogramming the DMA.
0 DMA transfer is not yet complete. Writing a 0 has no effect.
1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
This field contains the number of bytes yet to be transferred for a given block.
Restriction: BCR must be written with a value equal to or less than 0F_FFFFh. After being written with a value in this range, bits 23-20 of BCR read back as 0000b. A write to BCR of a value greater than 0F_FFFFh causes a configuration error when the channel starts to execute.
After being written with a value in this range, bits 23-20 of BCR read back as 0001b.
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Memory Map/Register Definition
23.3.4 DMA Control Register (DMA_DCRn)
Address: 4000_8000h base + 10Ch offset + (16d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
R
0
7
0
6
W
0
5
0
4
0
3
0
2
0
1
0
0
Reset 0
378
Field
31
EINT
30
ERQ
29
CS
28
AA
0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_DCRn field descriptions
Description
Enable Interrupt on Completion of Transfer
Determines whether an interrupt is generated by completing a transfer or by the occurrence of an error condition.
0
0 No interrupt is generated.
1 Interrupt signal is enabled.
Enable Peripheral Request
CAUTION: Be careful: a collision can occur between START and D_REQ when ERQ is 1.
0 Peripheral request is ignored.
1 Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.
Cycle Steal
0 DMA continuously makes read/write transfers until the BCR decrements to 0.
1 Forces a single read/write transfer per request.
Auto-align
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Field
27–25
Reserved
24
Reserved
23
EADREQ
22
SINC
21–20
SSIZE
19
DINC
18–17
DSIZE
16
START
Chapter 23 DMA Controller Module
DMA_DCRn field descriptions (continued)
Description
AA and SIZE bits determine whether the source or destination is auto-aligned; that is, transfers are optimized based on the address and size.
0 Auto-align disabled
1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of
DINC or SINC.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
CAUTION: Must be written as zero; otherwise, undefined behavior results.
Enable asynchronous DMA requests
Enables the channel to support asynchronous DREQs while the MCU is in Stop mode.
0 Disabled
1 Enabled
Source Increment
Controls whether the source address increments after each successful transfer.
0 No change to SAR after a successful transfer.
1 The SAR increments by 1, 2, 4 as determined by the transfer size.
Source Size
Determines the data size of the source bus cycle for the DMA controller.
00 32-bit
01 8-bit
10 16-bit
11 Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
Destination Increment
Controls whether the destination address increments after each successful transfer.
0 No change to the DAR after a successful transfer.
1 The DAR increments by 1, 2, 4 depending upon the size of the transfer.
Destination Size
Determines the data size of the destination bus cycle for the DMA controller.
00 32-bit
01 8-bit
10 16-bit
11 Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
Start Transfer
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Memory Map/Register Definition
DMA_DCRn field descriptions (continued)
Field
15–12
SMOD
Description
0 DMA inactive
1 The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
Source Address Modulo
Defines the size of the source data circular buffer used by the DMA Controller. If enabled (SMOD is nonzero), the buffer base address is located on a boundary of the buffer size. The value of this boundary is based upon the initial source address (SAR). The base address should be aligned to a 0-modulo-(circular buffer size) boundary. Misaligned buffers are not possible. The boundary is forced to the value determined by the upper address bits in the field selection.
11–8
DMOD
0000 Buffer disabled
0001 Circular buffer size is 16 bytes.
0010 Circular buffer size is 32 bytes.
0011 Circular buffer size is 64 bytes.
0100 Circular buffer size is 128 bytes.
0101 Circular buffer size is 256 bytes.
0110 Circular buffer size is 512 bytes.
0111 Circular buffer size is 1 KB.
1000 Circular buffer size is 2 KB.
1001 Circular buffer size is 4 KB.
1010 Circular buffer size is 8 KB.
1011 Circular buffer size is 16 KB.
1100 Circular buffer size is 32 KB.
1101 Circular buffer size is 64 KB.
1110 Circular buffer size is 128 KB.
1111 Circular buffer size is 256 KB.
Destination Address Modulo
Defines the size of the destination data circular buffer used by the DMA Controller. If enabled (DMOD value is non-zero), the buffer base address is located on a boundary of the buffer size. The value of this boundary depends on the initial destination address (DAR). The base address should be aligned to a 0modulo-(circular buffer size) boundary. Misaligned buffers are not possible. The boundary is forced to the value determined by the upper address bits in the field selection.
0000 Buffer disabled
0001 Circular buffer size is 16 bytes
0010 Circular buffer size is 32 bytes
0011 Circular buffer size is 64 bytes
0100 Circular buffer size is 128 bytes
0101 Circular buffer size is 256 bytes
0110 Circular buffer size is 512 bytes
0111 Circular buffer size is 1 KB
1000 Circular buffer size is 2 KB
1001 Circular buffer size is 4 KB
1010 Circular buffer size is 8 KB
1011 Circular buffer size is 16 KB
1100 Circular buffer size is 32 KB
1101 Circular buffer size is 64 KB
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Field
7
D_REQ
6
Reserved
5–4
LINKCC
3–2
LCH1
1–0
LCH2
Chapter 23 DMA Controller Module
DMA_DCRn field descriptions (continued)
Description
1110 Circular buffer size is 128 KB
1111 Circular buffer size is 256 KB
Disable Request
DMA hardware automatically clears the corresponding DCRn[ERQ] bit when the byte count register reaches 0.
0 ERQ bit is not affected.
1 ERQ bit is cleared when the BCR is exhausted.
This field is reserved.
This read-only field is reserved and always has the value 0.
Link Channel Control
Allows DMA channels to have their transfers linked. The current DMA channel triggers a DMA request to the linked channels (LCH1 or LCH2) depending on the condition described by the LINKCC bits.
If not in cycle steal mode (DCRn[CS]=0) and LINKCC equals 01 or 10, no link to LCH1 occurs.
If LINKCC equals 01, a link to LCH1 is created after each cycle-steal transfer performed by the current
DMA channel is completed. As the last cycle-steal is performed and the BCR reaches zero, then the link to
LCH1 is closed and a link to LCH2 is created.
00 No channel-to-channel linking
01 Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the
BCR decrements to 0.
10 Perform a link to channel LCH1 after each cycle-steal transfer
11 Perform a link to channel LCH1 after the BCR decrements to 0.
Link Channel 1
Indicates the DMA channel assigned as link channel 1. The link channel number cannot be the same as the currently executing channel, and generates a configuration error if this is attempted (DSRn[CE] is set).
00 DMA Channel 0
01 DMA Channel 1
10 DMA Channel 2
11 DMA Channel 3
Link Channel 2
Indicates the DMA channel assigned as link channel 2. The link channel number cannot be the same as the currently executing channel, and generates a configuration error if this is attempted (DSRn[CE] is set).
00 DMA Channel 0
01 DMA Channel 1
10 DMA Channel 2
11 DMA Channel 3
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Functional Description
23.4 Functional Description
In the following discussion, the term DMA request implies that DCRn[START] is set, or
DCRn[ERQ] is set and then followed by assertion of the properly selected DMA peripheral request. DCRn[START] is cleared when the channel is activated.
Before initiating a dual-address access, the DMA module verifies that DCRn[SSIZE] and
DCRn[DSIZE] are consistent with the source and destination addresses. If they are not consistent, the configuration error bit, DSRn[CE], is set. If misalignment is detected, no transfer occurs, DSRn[CE] is set, and, depending on the DCR configuration, an interrupt event may be issued. If the auto-align bit, DCRn[AA], is set, error checking is performed on the appropriate registers.
A read/write transfer sequence reads data from the source address and writes it to the destination address. The number of bytes transferred is the largest of the sizes specified by DCRn[SSIZE] and DCRn[DSIZE] in the DMA Control Registers (DCRn).
Source and destination address registers (SARn and DARn) can be programmed in the
DCRn to increment at the completion of a successful transfer.
23.4.1 Transfer requests (Cycle-Steal and Continuous modes)
The DMA channel supports software-initiated or peripheral-initiated requests. A request is issued by setting DCRn[START] or when the selected peripheral request asserts and
DCRn[ERQ] is set. Setting DCRn[ERQ] enables recognition of the peripheral DMA requests. Selecting between cycle-steal and continuous modes minimizes bus usage for either type of request.
• Cycle-steal mode (DCRn[CS] = 1)—Only one complete transfer from source to destination occurs for each request. If DCRn[ERQ] is set, the request is peripheral initiated. A software-initiated request is enabled by setting DCRn[START].
• Continuous mode (DCRn[CS] = 0)—After a software-initiated or peripheral request, the DMA continuously transfers data until BCRn reaches 0. The DMA performs the specified number of transfers, then retires the channel.
In either mode, the crossbar switch performs independent arbitration on each slave port after each transaction.
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23.4.2 Channel initialization and startup
Before a data transfer starts, the channel's transfer control descriptor must be initialized with information describing configuration, request-generation method, and pointers to the data to be moved.
23.4.2.1 Channel prioritization
The four DMA channels are prioritized based on number, with channel 0 having highest priority and channel 3 having the lowest, that is, channel 0 > channel 1 > channel 2 > channel 3.
Simultaneous peripheral requests activate the channels based on this priority order. Once activated, a channel runs to completion as defined by DCRn[CS] and BCRn.
23.4.2.2 Programming the DMA Controller Module
CAUTION
During a channel's execution, writes to programming model registers can corrupt the data transfer. The DMA module itself does not have a mechanism to prevent writes to registers during a channel's execution.
General guidelines for programming the DMA are:
• TCDn is initialized.
• SARn is loaded with the source (read) address. If the transfer is from a peripheral device to memory or to another peripheral, the source address is the location of the peripheral data register. If the transfer is from memory to a peripheral device or to memory, the source address is the starting address of the data block. This can be any appropriately aligned address.
• DARn is initialized with the destination (write) address. If the transfer is from a peripheral device to memory, or from memory to memory, DARn is loaded with the starting address of the data block to be written. If the transfer is from memory to a peripheral device, or from a peripheral device to a peripheral device, DARn is loaded with the address of the peripheral data register. This address can be any appropriately aligned address.
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Functional Description
• SARn and DARn change after each data transfer depending on DCRn[SSIZE,
DSIZE, SINC, DINC, SMOD, DMOD] and the starting addresses. Increment values can be 1, 2, or 4 for 8-bit, 16-bit, or 32-bit transfers, respectively. If the address register is programmed to remain unchanged, the register is not incremented after the data transfer.
• BCRn[BCR] must be loaded with the total number of bytes to be transferred. It is decremented by 1, 2, or 4 at the end of each transfer, depending on the transfer size. DSRn[DONE] must be cleared for channel startup.
• After the channel has been initialized, it may be started by setting DCRn[START] or a properly selected peripheral DMA request, depending on the status of
DCRn[ERQ]. For a software-initiated transfer, the channel can be started by setting
DCRn[START] as part of a single 32-bit write to the last 32 bits of the TCDn; that is, it is not required to write the DCRn with START cleared and then perform a second write to explicitly set START.
• Programming the channel for a software-initiated request causes the channel to request the system bus and start transferring data immediately. If the channel is programmed for peripheral-initiated request, a properly selected peripheral DMA request must be asserted before the channel begins the system bus transfers.
• The hardware can automatically clear DCRn[ERQ], disabling the peripheral request, when BCRn reaches zero by setting DCRn[D_REQ].
• Changes to DCRn are effective immediately while the channel is active. To avoid problems with changing a DMA channel setup, write a one to DSRn[DONE] to stop the DMA channel.
23.4.3 Dual-Address Data Transfer Mode
Each channel supports dual-address transfers. Dual-address transfers consist of a source data read and a destination data write. The DMA controller module begins a dual-address transfer sequence after a DMA request. If no error condition exists, DSRn[REQ] is set.
• Dual-address read—The DMA controller drives the SARn value onto the system address bus. If DCRn[SINC] is set, the SARn increments by the appropriate number of bytes upon a successful read cycle. When the appropriate number of read cycles complete (multiple reads if the destination size is larger than the source), the DMA initiates the write portion of the transfer.
If a termination error occurs, DSRn[BES, DONE] are set and DMA transactions stop.
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Chapter 23 DMA Controller Module
• Dual-address write—The DMA controller drives the DARn value onto the system address bus. When the appropriate number of write cycles complete (multiple writes if the source size is larger than the destination), DARn increments by the appropriate number of bytes if DCRn[DINC] is set. BCRn decrements by the appropriate number of bytes. DSRn[DONE] is set when BCRn reaches zero. If the BCRn is greater than zero, another read/write transfer is initiated if continuous mode is enabled
(DCRn[CS] = 0).
If a termination error occurs, DSRn[BED, DONE] are set and DMA transactions stop.
23.4.4 Advanced Data Transfer Controls: Auto-Alignment
Typically, auto-alignment for DMA transfers applies for transfers of large blocks of data.
As a result, it does not apply for peripheral-initiated cycle-steal transfers.
Auto-alignment allows block transfers to occur at the optimal size based on the address, byte count, and programmed size. To use this feature, DCRn[AA] must be set. The source is auto-aligned if DCRn[SSIZE] indicates a transfer size larger than
DCRn[DSIZE]. Source alignment takes precedence over the destination when the source and destination sizes are equal. Otherwise, the destination is auto-aligned. The address register chosen for alignment increments regardless of the increment value. Configuration error checking is performed on registers not chosen for alignment.
If BCRn is greater than 16, the address determines transfer size. Transfers of 8 bits, 16 bits, or 32 bits are transferred until the address is aligned to the programmed size boundary, at which time accesses begin using the programmed size. If BCRn is less than
16 at the start of a transfer, the number of bytes remaining dictates transfer size.
Consider this example:
• AA equals 1.
• SARn equals 0x2000_0001.
• BCRn equals 0x00_00F0.
• SSIZE equals 00 (32 bits).
• DSIZE equals 01 (8 bits).
Because SSIZE > DSIZE, the source is auto-aligned. Error checking is performed on destination registers. The access sequence is as follows:
1. Read 1 byte from 0x2000_0001, increment SARn, write 1 byte (using DARn).
2. Read 2 bytes from 0x2000_0002, increment SARn, write 2 bytes.
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Functional Description
3. Read 4 bytes from 0x2000_0004, increment SARn, write 4 bytes.
4. Repeat 4-byte operations until SARn equals 0x2000_00F0.
5. Read byte from 0x2000_00F0, increment SARn, write byte.
If DSIZE is another size, data writes are optimized to write the largest size allowed based on the address, but not exceeding the configured size.
23.4.5 Termination
An unsuccessful transfer can terminate for one of the following reasons:
• Error conditions—When the DMA encounters a read or write cycle that terminates with an error condition, DSRn[BES] is set for a read and DSRn[BED] is set for a write before the transfer is halted. If the error occurred in a write cycle, data in the internal holding registers is lost.
• Interrupts—If DCRn[EINT] is set, the DMA drives the appropriate interrupt request signal. The processor can read DSRn to determine whether the transfer terminated successfully or with an error. DSRn[DONE] is then written with a 1 to clear the interrupt, DSRn[DONE], and error status bits.
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Chapter 24
Multipurpose Clock Generator (MCG)
The Multipurpose Clock Generator (MCG) module provides several clock source choices for the MCU. The MCG operates in conjuction with a crystal oscillator, which allows an external crystal, ceramic resonator, or another external clock source to produce the external reference clock.
24.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
The multipurpose clock generator (MCG) module provides several clock source choices for the MCU.
The module contains a frequency-locked loop (FLL) and a phase-locked loop (PLL). The
FLL is controllable by either an internal or an external reference clock. The PLL is controllable by the external reference clock. The module can select either of the FLL or
PLL output clocks, or either of the internal or external reference clocks as a source for the
MCU system clock. The MCG operates in conjuction with a crystal oscillator, which allows an external crystal, ceramic resonator, or another external clock source to produce the external reference clock.
24.1.1 Features
Key features of the MCG module are:
• Frequency-locked loop (FLL):
• Digitally-controlled oscillator (DCO)
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Introduction
• DCO frequency range is programmable for up to four different frequency ranges.
• Option to program and maximize DCO output frequency for a low frequency external reference clock source.
• Option to prevent FLL from resetting its current locked frequency when switching clock modes if FLL reference frequency is not changed.
• Internal or external reference clock can be used as the FLL source.
• Can be used as a clock source for other on-chip peripherals.
• Phase-locked loop (PLL):
• Voltage-controlled oscillator (VCO)
• External reference clock is used as the PLL source.
• Modulo VCO frequency divider
• Phase/Frequency detector
• Integrated loop filter
• Can be used as a clock source for other on-chip peripherals.
• Internal reference clock generator:
• Slow clock with nine trim bits for accuracy
• Fast clock with four trim bits
• Can be used as source clock for the FLL. In FEI mode, only the slow Internal
Reference Clock (IRC) can be used as the FLL source.
• Either the slow or the fast clock can be selected as the clock source for the MCU.
• Can be used as a clock source for other on-chip peripherals.
• Control signals for the MCG external reference low power oscillator clock generators are provided:
• HGO0, RANGE0, EREFS0
HGO1, RANGE1, EREFS1
• External clock from the Crystal Oscillator (OSC0):
• Can be used as a source for the FLL and/or the PLL.
• Can be selected as the clock source for the MCU.
• External clock from the Real Time Counter (RTC):
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Chapter 24 Multipurpose Clock Generator (MCG)
• Can only be used as a source for the FLL.
• Can be selected as the clock source for the MCU.
• External clock from the Crystal Oscillator (OSC1)
• Can only be used as a source for the PLL.
• External clock monitor with reset and interrupt request capability to check for external clock failure when running in FBE, PEE, BLPE, or FEE modes
• Lock detector with interrupt request capability for use with the PLL
• Internal Reference Clocks Auto Trim Machine (ATM) capability using an external clock as a reference
• Reference dividers for both the FLL and the PLL are provided
• Reference dividers for the Fast Internal Reference Clock are provided
• MCG PLL Clock (MCGPLLCLK) is provided as a clock source for other on-chip peripherals
• MCG FLL Clock (MCGFLLCLK) is provided as a clock source for other on-chip peripherals
• MCG Fixed Frequency Clock (MCGFFCLK) is provided as a clock source for other on-chip peripherals
• MCG Internal Reference Clock (MCGIRCLK) is provided as a clock source for other on-chip peripherals
This figure presents the block diagram of the MCG module.
Figure 24-1. Multipurpose Clock Generator (MCG) block diagram
NOTE
Refer to the chip configuration chapter to identify the oscillator used in this MCU.
24.1.2 Modes of Operation
The MCG has the following modes of operation: FEI, FEE, FBI, FBE, PBE, PEE, BLPI,
BLPE, and Stop. For details, see MCG modes of operation
.
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24.2 External Signal Description
There are no MCG signals that connect off chip.
24.3 Memory Map/Register Definition
This section includes the memory map and register definition.
The MCG registers can only be written when in supervisor mode. Write accesses when in user mode will result in a bus error. Read accesses may be performed in both supervisor and user mode.
MCG memory map
Absolute address
(hex)
Register name
4006_4000 MCG Control 1 Register (MCG_C1)
4006_4001 MCG Control 2 Register (MCG_C2)
4006_4002 MCG Control 3 Register (MCG_C3)
4006_4003 MCG Control 4 Register (MCG_C4)
4006_4004 MCG Control 5 Register (MCG_C5)
4006_4005 MCG Control 6 Register (MCG_C6)
4006_4006 MCG Status Register (MCG_S)
4006_4008 MCG Status and Control Register (MCG_SC)
4006_400A
MCG Auto Trim Compare Value High Register
(MCG_ATCVH)
4006_400B
MCG Auto Trim Compare Value Low Register
(MCG_ATCVL)
4006_400C MCG Control 7 Register (MCG_C7)
4006_400D MCG Control 8 Register (MCG_C8)
4006_400E MCG Control 9 Register (MCG_C9)
4006_400F MCG Control 10 Register (MCG_C10)
Width
(in bits)
Access Reset value
8
8
8
8
8
8
8
8
8
8
8
8
8
8
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
04h
Undefined
Undefined
00h
00h
10h
02h
00h
00h
00h
80h
00h
00h
Section/ page
24.3.1 MCG Control 1 Register (MCG_C1)
Address: 4006_4000h base + 0h offset = 4006_4000h
7 6 5 Bit
Read
Write
Reset 0
0 0
4
0
3
0
2
1
1 0
0 0
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Field
7–6
CLKS
5–3
FRDIV
2
IREFS
1
IRCLKEN
0
IREFSTEN
Chapter 24 Multipurpose Clock Generator (MCG)
MCG_C1 field descriptions
Description
Clock Source Select
Selects the clock source for MCGOUTCLK .
00 Encoding 0 — Output of FLL or PLL is selected (depends on PLLS control bit).
01 Encoding 1 — Internal reference clock is selected.
10 Encoding 2 — External reference clock is selected.
11 Encoding 3 — Reserved.
FLL External Reference Divider
Selects the amount to divide down the external reference clock for the FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is required when FLL/DCO is the clock source for
MCGOUTCLK . In FBE mode, it is not required to meet this range, but it is recommended in the cases when trying to enter a FLL mode from FBE).
000 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE 0 values, Divide Factor is
32.
001 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE 0 values, Divide Factor is
64.
010 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE 0 values, Divide Factor is
128.
011 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE 0 values, Divide Factor is
256.
100 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE 0 values, Divide Factor is
512.
101 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE 0 values, Divide Factor is
1024.
110 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE 0 values, Divide Factor is
1280 .
111 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE 0 values, Divide Factor is
1536 .
Internal Reference Select
Selects the reference clock source for the FLL.
0 External reference clock is selected.
1 The slow internal reference clock is selected.
Internal Reference Clock Enable
Enables the internal reference clock for use as MCGIRCLK.
0 MCGIRCLK inactive.
1 MCGIRCLK active.
Internal Reference Stop Enable
Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode.
0 Internal reference clock is disabled in Stop mode.
1 Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
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24.3.2 MCG Control 2 Register (MCG_C2)
Address: 4006_4000h base + 1h offset = 4006_4001h
Bit
Read
Write
Reset
Field
7
LOCRE0
7
1
6
1
5
0
4
0
3
0
MCG_C2 field descriptions
Description
Loss of Clock Reset Enable
2
0
1
0
0
0
Determines whether an interrupt or a reset request is made following a loss of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is set.
6
FCFTRIM
5–4
RANGE0
3
HGO0
2
EREFS0
1
LP
0 Interrupt request is generated on a loss of OSC0 external reference clock.
1 Generate a reset request on a loss of OSC0 external reference clock.
Fast Internal Reference Clock Fine Trim
FCFTRIM controls the smallest adjustment of the fast internal reference clock frequency. Setting
FCFTRIM increases the period and clearing FCFTRIM decreases the period by the smallest amount possible. If an FCFTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this bit.
Frequency Range Select
Selects the frequency range for the crystal oscillator or external clock source. See the Oscillator (OSC) chapter for more details and the device data sheet for the frequency ranges used.
00 Encoding 0 — Low frequency range selected for the crystal oscillator .
01 Encoding 1 — High frequency range selected for the crystal oscillator .
1X Encoding 2 — Very high frequency range selected for the crystal oscillator .
High Gain Oscillator Select
Controls the crystal oscillator mode of operation. See the Oscillator (OSC) chapter for more details.
0 Configure crystal oscillator for low-power operation.
1 Configure crystal oscillator for high-gain operation.
External Reference Select
Selects the source for the external reference clock. See the Oscillator (OSC) chapter for more details.
0 External reference clock requested.
1 Oscillator requested.
Low Power Select
Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any other MCG mode, LP bit has no affect.
0 FLL or PLL is not disabled in bypass modes.
1 FLL or PLL is disabled in bypass modes (lower power)
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Field
0
IRCS
Chapter 24 Multipurpose Clock Generator (MCG)
MCG_C2 field descriptions (continued)
Description
Internal Reference Clock Select
Selects between the fast or slow internal reference clock source.
0 Slow internal reference clock selected.
1 Fast internal reference clock selected.
24.3.3 MCG Control 3 Register (MCG_C3)
Address: 4006_4000h base + 2h offset = 4006_4002h
6 5 Bit
Read
Write
Reset
7
* Notes:
• x = Undefined at reset.
4
3
2
1
0
Field
7–0
SCTRIM
MCG_C3 field descriptions
Description
Slow Internal Reference Clock Trim Setting
clock period. The SCTRIM bits are binary weighted, that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value increases the period, and decreasing the value decreases the period.
An additional fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset, this value is loaded with a factory trim value.
If an SCTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this register.
1. A value for SCTRIM is loaded during reset from a factory programmed location.
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24.3.4 MCG Control 4 Register (MCG_C4)
NOTE
Reset values for DRST and DMX32 bits are 0.
Address: 4006_4000h base + 3h offset = 4006_4003h
Bit
Read
Write
Reset
7
0
6
5
0 0
4 3
2 1
•
•
* Notes: x = Undefined at reset.
A value for FCTRIM is loaded during reset from a factory programmed location. x = Undefined at reset.
Field
7
DMX32
0
MCG_C4 field descriptions
Description
DCO Maximum Frequency with 32.768 kHz Reference
The DMX32 bit controls whether the DCO frequency range is narrowed to its maximum frequency with a
32.768 kHz reference.
The following table identifies settings for the DCO frequency range.
NOTE: The system clocks derived from this source should not exceed their specified maximums.
DRST_DRS
00
01
10
11
DMX32
0
1
0
1
0
1
0
1
Reference Range
31.25–39.0625 kHz
32.768 kHz
31.25–39.0625 kHz
32.768 kHz
31.25–39.0625 kHz
32.768 kHz
31.25–39.0625 kHz
32.768 kHz
FLL Factor
640
732
1280
1464
1920
2197
2560
2929
DCO Range
20–25 MHz
24 MHz
40–50 MHz
48 MHz
60–75 MHz
72 MHz
80–100 MHz
96 MHz
6–5
DRST_DRS
0 DCO has a default range of 25%.
1 DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
DCO Range Select
The DRS bits select the frequency range for the FLL output, DCOOUT. When the LP bit is set, writes to the DRS bits are ignored. The DRST read field indicates the current frequency range for DCOOUT. The
DRST field does not update immediately after a write to the DRS field due to internal synchronization between clock domains. See the DCO Frequency Range table for more details.
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Field
4–1
FCTRIM
0
SCFTRIM
Chapter 24 Multipurpose Clock Generator (MCG)
MCG_C4 field descriptions (continued)
Description
00 Encoding 0 — Low range (reset default).
01 Encoding 1 — Mid range.
10 Encoding 2 — Mid-high range.
11 Encoding 3 — High range.
Fast Internal Reference Clock Trim Setting
FCTRIM
controls the fast internal reference clock frequency by controlling the fast internal reference clock period. The FCTRIM bits are binary weighted, that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value increases the period, and decreasing the value decreases the period.
If an FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this register.
Slow Internal Reference Clock Fine Trim
SCFTRIM
controls the smallest adjustment of the slow internal reference clock frequency. Setting
SCFTRIM increases the period and clearing SCFTRIM decreases the period by the smallest amount possible.
If an SCFTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this bit.
1. A value for FCTRIM is loaded during reset from a factory programmed location.
2. A value for SCFTRIM is loaded during reset from a factory programmed location .
24.3.5 MCG Control 5 Register (MCG_C5)
Address: 4006_4000h base + 4h offset = 4006_4004h
Bit
Read
Write
Reset
7
0
6 5
0 0
Field
7
Reserved
6
PLLCLKEN0
5
PLLSTEN0
4 3 2
0
1 0
0 0 0 0
MCG_C5 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
PLL Clock Enable
Enables the PLL independent of PLLS and enables the PLL clock for use as MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a PLL reference clock in the range of 2 - 4 MHz range prior to setting the PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit, and the external oscillator is being used as the reference clock, the OSCINIT 0 bit should be checked to make sure it is set.
0 MCGPLLCLK is inactive.
1
MCGPLLCLK is active.
PLL Stop Enable
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Field
MCG_C5 field descriptions (continued)
Description
Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL clock gets disabled even if
PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit has no affect and does not enable the PLL Clock to run if it is written to 1.
4–0
PRDIV0
0 MCGPLLCLK is disabled in any of the Stop modes.
1
MCGPLLCLK is enabled if system is in Normal Stop mode.
PLL External Reference Divider
Selects the amount to divide down the external reference clock for the PLL. The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the
PRDIV 0 value must not be changed when LOCK0 is zero.
PRDIV
0
00000 1
Divide
Factor
00001 2
00010 3
00011 4
00100 5
00101 6
00110 7
00111 8
Table 24-7. PLL External Reference Divide Factor
PRDIV
0
01000 9
Divide
Factor
01001 10
PRDIV
0
Divide
Factor
10000 17
10001 18
01010 11
01011 12
01100 13
01101 14
01110 15
01111 16
10010 19
10011 20
10100 21
10101 22
10110 23
10111 24
PRDIV
0
Divide
Factor
11000 25
11001 Reserve d
11010 Reserve d
11011 Reserve d
11100 Reserve d
11101 Reserve d
11110 Reserve d
11111 Reserve d
24.3.6 MCG Control 6 Register (MCG_C6)
Address: 4006_4000h base + 5h offset = 4006_4005h
Bit
Read
Write
Reset
Field
7
LOLIE0
7
0
6
0
5
0
4
0
3
0
MCG_C6 field descriptions
Description
Loss of Lock Interrrupt Enable
396
2
0
1
0
0
0
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Field
6
PLLS
5
CME0
4–0
VDIV0
Chapter 24 Multipurpose Clock Generator (MCG)
MCG_C6 field descriptions (continued)
Description
Determines if an interrupt request is made following a loss of lock indication. This bit only has an effect when LOLS 0 is set.
0 No interrupt request is generated on loss of lock.
1 Generate an interrupt request on loss of lock.
PLL Select
Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is disabled in all modes. If the PLLS is set, the FLL is disabled in all modes.
0 FLL is selected.
1
PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 2–4 MHz prior to setting the PLLS bit).
Clock Monitor Enable
Enables the loss of clock monitoring circuit for the OSC0 external reference mux select. The LOCRE0 bit will determine if a interrupt or a reset request is generated following a loss of OSC0 indication. The CME0 bit must only be set to a logic 1 when the MCG is in an operational mode that uses the external clock
(FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1, the value of the RANGE0 bits in the C2 register should not be changed. CME0 bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a reset request may occur while in Stop mode. CME0 should also be set to a logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
0 External clock monitor is disabled for OSC0.
1 External clock monitor is enabled for OSC0.
VCO 0 Divider
Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits establish the multiplication factor
(M) applied to the reference clock frequency. After the PLL is enabled (by setting either PLLCLKEN 0 or
PLLS), the VDIV 0 value must not be changed when LOCK 0 is zero.
VDIV 0 Multiply
Factor
00000 24
00001 25
00010 26
00011 27
00100 28
00101 29
00110 30
00111 31
Table 24-9. PLL VCO Divide Factor
VDIV 0 Multiply
Factor
01000 32
01001 33
01010 34
01011 35
01100 36
01101 37
01110 38
01111 39
VDIV 0 Multiply
Factor
10000 40
10001 41
10010 42
10011 43
10100 44
10101 45
10110 46
10111 47
VDIV 0 Multiply
Factor
11000 48
11001 49
11010 50
11011 51
11100 52
11101 53
11110 54
11111 55
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24.3.7 MCG Status Register (MCG_S)
Address: 4006_4000h base + 6h offset = 4006_4006h
Bit
Read
Write
Reset
7
0
6
0
5
4
3
0 1 0
MCG_S field descriptions
Description
Field
7
LOLS0
Loss of Lock Status
2
0
1
0
0
0
This bit is a sticky bit indicating the lock status for the PLL. LOLS is set if after acquiring lock, the PLL output frequency has fallen outside the lock exit frequency tolerance, D unl
. LOLIE determines whether an interrupt request is made when LOLS is set. LOLRE determines whether a reset request is made when
LOLS is set. This bit is cleared by reset or by writing a logic 1 to it when set. Writing a logic 0 to this bit has no effect.
6
LOCK0
5
PLLST
0 PLL has not lost lock since LOLS 0 was last cleared.
1 PLL has lost lock since LOLS 0 was last cleared.
Lock Status
This bit indicates whether the PLL has acquired lock. Lock detection is only enabled when the PLL is enabled (either through clock mode selection or PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted. If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in the C5 register or the
VDIV0[4:0] bits in the C6 register causes the lock status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL reference clock will also cause the LOCK0 bit to clear until the PLL has reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes the lock status bit to clear and stay cleared until the Stop mode is exited and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted again.
0 PLL is currently unlocked.
1 PLL is currently locked.
PLL Select Status
This bit indicates the clock source selected by PLLS . The PLLST bit does not update immediately after a write to the PLLS bit due to internal synchronization between clock domains.
4
IREFST
0 Source of PLLS clock is FLL clock.
1 Source of PLLS clock is PLL output clock.
Internal Reference Status
This bit indicates the current source for the FLL reference clock. The IREFST bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock domains.
0 Source of FLL reference clock is the external reference clock.
1 Source of FLL reference clock is the internal reference clock.
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Field
3–2
CLKST
1
OSCINIT0
0
IRCST
Chapter 24 Multipurpose Clock Generator (MCG)
MCG_S field descriptions (continued)
Description
Clock Mode Status
These bits indicate the current clock mode. The CLKST bits do not update immediately after a write to the
CLKS bits due to internal synchronization between clock domains.
00 Encoding 0 — Output of the FLL is selected (reset default).
01 Encoding 1 — Internal reference clock is selected.
10 Encoding 2 — External reference clock is selected.
11 Encoding 3 — Output of the PLL is selected.
OSC Initialization
This bit, which resets to 0, is set to 1 after the initialization cycles of the crystal oscillator clock have completed. After being set, the bit is cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed description for more information.
Internal Reference Clock Status
The IRCST bit indicates the current source for the internal reference clock select clock (IRCSCLK). The
IRCST bit does not update immediately after a write to the IRCS bit due to internal synchronization between clock domains. The IRCST bit will only be updated if the internal reference clock is enabled, either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN] bit .
0 Source of internal reference clock is the slow clock (32 kHz IRC).
1 Source of internal reference clock is the fast clock (4 MHz IRC).
24.3.8 MCG Status and Control Register (MCG_SC)
Address: 4006_4000h base + 8h offset = 4006_4008h
Bit
Read
Write
Reset
7
0
6
0
5
0
Field
7
ATME
4
3 2
1 0
0 0
MCG_SC field descriptions
Description
Automatic Trim Machine Enable
0 1 0
Enables the Auto Trim Machine to start automatically trimming the selected Internal Reference Clock.
NOTE: ATME deasserts after the Auto Trim Machine has completed trimming all trim bits of the IRCS clock selected by the ATMS bit.
Writing to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim operation and clears this bit.
0 Auto Trim Machine disabled.
1 Auto Trim Machine enabled.
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Memory Map/Register Definition
Field
6
ATMS
MCG_SC field descriptions (continued)
Description
Automatic Trim Machine Select
Selects the IRCS clock for Auto Trim Test.
5
ATMF
0 32 kHz Internal Reference Clock selected.
1 4 MHz Internal Reference Clock selected.
Automatic Trim Machine Fail Flag
4
FLTPRSRV
3–1
FCRDIV
Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC registers is detected or the MCG enters into any
Stop mode. A write to ATMF clears the flag.
0 Automatic Trim Machine completed normally.
1 Automatic Trim Machine failed.
FLL Filter Preserve Enable
This bit will prevent the FLL filter values from resetting allowing the FLL output frequency to remain the same during clock mode changes where the FLL/DCO output is still valid. (Note: This requires that the
FLL reference frequency to remain the same as what it was prior to the new clock mode switch. Otherwise
FLL filter and frequency values will change.)
0 FLL filter and FLL frequency will reset on changes to currect clock mode.
1 Fll filter and FLL frequency retain their previous values during new clock mode change.
Fast Clock Internal Reference Divider
Selects the amount to divide down the fast internal reference clock. The resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the divider when the Fast IRC is enabled is not supported).
0
LOCS0
000 Divide Factor is 1
001 Divide Factor is 2.
010 Divide Factor is 4.
011 Divide Factor is 8.
100 Divide Factor is 16
101 Divide Factor is 32
110 Divide Factor is 64
111 Divide Factor is 128.
OSC0 Loss of Clock Status
The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a logic 1 to it when set.
0 Loss of OSC0 has not occurred.
1 Loss of OSC0 has occurred.
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24.3.9 MCG Auto Trim Compare Value High Register
(MCG_ATCVH)
Address: 4006_4000h base + Ah offset = 4006_400Ah
7 6 5 Bit
Read
Write
Reset 0 0 0
Field
7–0
ATCVH
4
3 2 1 0
0 0
MCG_ATCVH field descriptions
Description
ATM Compare Value High
0 0 0
Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM
SAR conversion.
24.3.10 MCG Auto Trim Compare Value Low Register
(MCG_ATCVL)
Address: 4006_4000h base + Bh offset = 4006_400Bh
7 6 5 Bit
Read
Write
Reset 0 0 0
Field
7–0
ATCVL
4
3 2 1 0
0 0
MCG_ATCVL field descriptions
Description
ATM Compare Value Low
0 0 0
Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM
SAR conversion.
24.3.11 MCG Control 7 Register (MCG_C7)
Address: 4006_4000h base + Ch offset = 4006_400Ch
7 6 5 Bit
Read
Write
Reset 0
0 0
4
0
3
0
2
0
1
0
0
0
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Memory Map/Register Definition
Field
7–6
Reserved
5–2
Reserved
MCG_C7 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Reserved
1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Reserved
0
OSCSEL
This field is reserved.
This read-only field is reserved and always has the value 0.
MCG OSC Clock Select
Selects the MCG FLL external reference clock
0 Selects Oscillator (OSCCLK).
1 Selects 32 kHz RTC Oscillator.
24.3.12 MCG Control 8 Register (MCG_C8)
Address: 4006_4000h base + Dh offset = 4006_400Dh
Bit
Read
Write
Reset
Field
7
Reserved
6
LOLRE
7
6
0
5
4 3
1 0 0 0
MCG_C8 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
PLL Loss of Lock Reset Enable
2
0
Determines if an interrupt or a reset request is made following a PLL loss of lock.
5
Reserved
4–1
Reserved
0
Reserved
1
0
0
0
0 Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request.
1 Generate a reset request on a PLL loss of lock indication.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
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24.3.13 MCG Control 9 Register (MCG_C9)
Address: 4006_4000h base + Eh offset = 4006_400Eh
7 6 5 Bit
Read
Write
Reset
Field
7–6
Reserved
5–4
Reserved
4 3
0 0 0 0 0
MCG_C9 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Reserved
3–1
Reserved
0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
2
0
1
0
0
0
24.3.14 MCG Control 10 Register (MCG_C10)
Address: 4006_4000h base + Fh offset = 4006_400Fh
7 6 5 Bit
Read
Write
Reset 0 0
0
Field
7–4
Reserved
3–0
Reserved
4 3
0 0
MCG_C10 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
0
2
0
1 0
0
24.4 Functional description
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Functional description
24.4.1 MCG mode state diagram
The nine states of the MCG are shown in the following figure and are described in
24-18 . The arrows indicate the permitted MCG mode transitions.
Reset FEI FEE
BLPI
FBI FBE
PBE
BLPE
PEE
Entered from any state when the MCU enters Stop mode Stop
Returns to the state that was active before the MCU entered Stop mode, unless a reset occurs while in Stop mode.
Figure 24-16. MCG mode state diagram
NOTE
• During exits from LLS or VLPS when the MCG is in PEE mode, the MCG will reset to PBE clock mode and the
C1[CLKS] and S[CLKST] will automatically be set to
2’b10.
• If entering Normal Stop mode when the MCG is in PEE mode with PLLSTEN=0, the MCG will reset to PBE clock mode and C1[CLKS] and S[CLKST] will automatically be set to 2’b10.
24.4.1.1 MCG modes of operation
The MCG operates in one of the following modes.
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Note
The MCG restricts transitions between modes. For the permitted transitions, see
Mode
FLL Engaged Internal
(FEI)
Table 24-18. MCG modes of operation
Description
FLL engaged internal (FEI) is the default mode of operation and is entered when all the following condtions occur:
• 00 is written to C1[CLKS].
• 1 is written to C1[IREFS].
• 0 is written to C6[PLLS].
FLL Engaged External
(FEE)
In FEI mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the 32 kHz Internal Reference Clock (IRC). The FLL loop will lock the DCO frequency to the FLL factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency. See the
C4[DMX32] bit description for more details. In FEI mode, the PLL is disabled in a low-power state unless C5[PLLCLKEN] is set .
FLL engaged external (FEE) mode is entered when all the following conditions occur:
• 00 is written to C1[CLKS].
• 0 is written to C1[IREFS].
• C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25
kHz to 39.0625 kHz
• 0 is written to C6[PLLS].
FLL Bypassed Internal
(FBI)
In FEE mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the external reference clock. The FLL loop will lock the DCO frequency to the FLL factor, as selected by
C4[DRST_DRS] and C4[DMX32] bits, times the external reference frequency, as specified by
C1[FRDIV] and C2[RANGE0]. See the C4[DMX32] bit description for more details. In FEE mode, the PLL is disabled in a low-power state unless C5[PLLCLKEN] is set .
FLL bypassed internal (FBI) mode is entered when all the following conditions occur:
• 01 is written to C1[CLKS].
• 1 is written to C1[IREFS].
• 0 is written to C6[PLLS]
• 0 is written to C2[LP].
In FBI mode, the MCGOUTCLK is derived either from the slow (32 kHz IRC) or fast (4 MHz IRC) internal reference clock, as selected by the C2[IRCS] bit. The FLL is operational but its output is not used. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUTCLK is driven from the C2[IRCS] selected internal reference clock. The FLL clock (DCOCLK) is controlled by the slow internal reference clock, and the DCO clock frequency locks to a multiplication factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency. See the
C4[DMX32] bit description for more details. In FBI mode, the PLL is disabled in a low-power state unless C5[PLLCLKEN] is set .
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Functional description
Table 24-18. MCG modes of operation (continued)
Mode
FLL Bypassed External
(FBE)
Description
FLL bypassed external (FBE) mode is entered when all the following conditions occur:
• 10 is written to C1[CLKS].
• 0 is written to C1[IREFS].
• C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25
kHz to 39.0625 kHz.
• 0 is written to C6[PLLS].
• 0 is written to C2[LP].
PLL Engaged External
(PEE)
In FBE mode, the MCGOUTCLK is derived from the OSCSEL external reference clock. The FLL is operational but its output is not used. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUTCLK is driven from the external reference clock. The FLL clock
(DCOCLK) is controlled by the external reference clock, and the DCO clock frequency locks to a multiplication factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the divided external reference frequency. See the C4[DMX32] bit description for more details. In FBI mode, the PLL is disabled in a low-power state unless C5[PLLCLKEN] is set .
PLL Engaged External (PEE) mode is entered when all the following conditions occur:
• 00 is written to C1[CLKS].
• 0 is written to C1[IREFS].
• 1 is written to C6[PLLS].
PLL Bypassed External
(PBE)
In PEE mode, the MCGOUTCLK is derived from the output of PLL which is controlled by a external reference clock. The PLL clock frequency locks to a multiplication factor, as specified by its corresponding VDIV, times the selected PLL reference frequency, as specified by its corresponding
PRDIV. The PLL's programmable reference divider must be configured to produce a valid PLL reference clock. The FLL is disabled in a low-power state.
PLL Bypassed External (PBE) mode is entered when all the following conditions occur:
• 10 is written to C1[CLKS].
• 0 is written to C1[IREFS].
• 1 is written to C6[PLLS].
• 0 is written to C2[LP].
In PBE mode, MCGOUTCLK is derived from the OSCSEL external reference clock; the PLL is operational, but its output clock is not used. This mode is useful to allow the PLL to acquire its target frequency while MCGOUTCLK is driven from the external reference clock. The PLL clock frequency locks to a multiplication factor, as specified by its [VDIV], times the PLL reference frequency, as specified by its [PRDIV]. In preparation for transition to PEE, the PLL's programmable reference divider must be configured to produce a valid PLL reference clock. The FLL is disabled in a lowpower state.
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Mode
Bypassed Low Power
Chapter 24 Multipurpose Clock Generator (MCG)
Table 24-18. MCG modes of operation (continued)
Description
Bypassed Low Power Internal (BLPI) mode is entered when all the following conditions occur:
• 01 is written to C1[CLKS].
• 1 is written to C1[IREFS].
• 0 is written to C6[PLLS].
• 1 is written to C2[LP].
Bypassed Low Power
External (BLPE)
In BLPI mode, MCGOUTCLK is derived from the internal reference clock. The FLL is disabled and
PLL is disabled even if C5[PLLCLKEN] is set to 1.
Bypassed Low Power External (BLPE) mode is entered when all the following conditions occur:
• 10 is written to C1[CLKS].
• 0 is written to C1[IREFS].
• 1 is written to C2[LP].
Stop
In BLPE mode, MCGOUTCLK is derived from the OSCSEL external reference clock. The FLL is disabled and PLL is disabled even if the C5[PLLCLKEN] is set to 1.
Entered whenever the MCU enters a Stop state. The power modes are chip specific. For power mode assignments, see the chapter that describes how modules are configured and MCG behavior during Stop recovery. Entering Stop mode, the FLL is disabled, and all MCG clock signals are static except in the following case:
MCGPLLCLK is active in Normal Stop mode when PLLSTEN=1
MCGPLL1CLK is active in Normal Stop mode when PLLSTEN1=1
MCGIRCLK is active in Normal Stop mode when all the following conditions become true:
• C1[IRCLKEN] = 1
• C1[IREFSTEN] = 1
NOTE:
NOTE:
• In VLPS Stop Mode, the MCGIRCLK can be programmed to stay enabled and continue running if C1[IRCLKEN] = 1, C1[IREFSTEN]=1, and Fast IRC clock is selected (C2[IRCS] = 1)
• When entering Low Power Stop modes (LLS or VLPS) from PEE mode, on exit the
MCG clock mode is forced to PBE clock mode. C1[CLKS] and S[CLKST] will be configured to 2’b10if entering from PEE mode or to 2’b01 if entering from PEI mode,
C5[PLLSTEN0] will be force to 1'b0 and S[LOCK] bit will be cleared without setting
S[LOLS].
• When entering Normal Stop mode from PEE mode and if C5[PLLSTEN]=0, on exit the MCG clock mode is forced to PBE mode, the C1[CLKS] and S[CLKST] will be configured to 2’b10 and S[LOCK] bit will clear without setting S[LOLS]. If
C5[PLLSTEN]=1, the S[LOCK] bit will not get cleared and on exit the MCG will continue to run in PEE mode.
1. If entering VLPR mode, MCG has to be configured and enter BLPE mode or BLPI mode with the Fast IRC clock selected
(C2[IRCS]=1). After it enters VLPR mode, writes to any of the MCG control registers that can cause an MCG clock mode switch to a non low power clock mode must be avoided.
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Functional description
NOTE
For the chip-specific modes of operation, see the power management chapter of this MCU.
24.4.1.2 MCG mode switching
C1[IREFS] can be changed at any time, but the actual switch to the newly selected reference clocks is shown by S[IREFST]. When switching between engaged internal and engaged external modes, the FLL will begin locking again after the switch is completed.
C1[CLKS] can also be changed at any time, but the actual switch to the newly selected clock is shown by S[CLKST]. If the newly selected clock is not available, the previous clock will remain selected.
The C4[DRST_DRS] write bits can be changed at any time except when C2[LP] bit is 1.
If C4[DRST_DRS] write bits are changed while in FLL engaged internal (FEI) or FLL engaged external (FEE), the MCGOUTCLK will switch to the new selected DCO range within three clocks of the selected DCO clock. After switching to the new DCO, the FLL remains unlocked for several reference cycles. DCO startup time is equal to the FLL acquisition time. After the selected DCO startup time is over, the FLL is locked. The completion of the switch is shown by the C4[DRST_DRS] read bits.
24.4.2 Low-power bit usage
C2[LP] is provided to allow the FLL or PLL to be disabled and thus conserve power when these systems are not being used. C4[DRST_DRS] can not be written while C2[LP] is 1. However, in some applications, it may be desirable to enable the FLL or PLL and allow it to lock for maximum accuracy before switching to an engaged mode. Do this by writing 0 to C2[LP].
24.4.3 MCG Internal Reference Clocks
This module supports two internal reference clocks with nominal frequencies of 32 kHz
(slow IRC) and 4 MHz (fast IRC). The fast IRC frequency can be divided down by programming of the FCRDIV to produce a frequency range of 32 kHz to 4 MHz.
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24.4.3.1 MCG Internal Reference Clock
The MCG Internal Reference Clock (MCGIRCLK) provides a clock source for other onchip peripherals and is enabled when C1[IRCLKEN]=1. When enabled, MCGIRCLK is driven by either the fast internal reference clock (4 MHz IRC which can be divided down by the FRDIV factors) or the slow internal reference clock (32 kHz IRC). The IRCS clock frequency can be re-targeted by trimming the period of its IRCS selected internal reference clock. This can be done by writing a new trim value to the
C3[SCTRIM]:C4[SCFTRIM] bits when the slow IRC clock is selected or by writing a new trim value to C4[FCTRIM]:C2[FCFTRIM] when the fast IRC clock is selected. The internal reference clock period is proportional to the trim value written.
C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) and C4[FCTRIM]:C2[FCFTRIM] (if
C2[IRCS]=1) bits affect the MCGOUTCLK frequency if the MCG is in FBI or BLPI modes. C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) bits also affect the
MCGOUTCLK frequency if the MCG is in FEI mode.
Additionally, this clock can be enabled in Stop mode by setting C1[IRCLKEN] and
C1[IREFSTEN], otherwise this clock is disabled in Stop mode.
24.4.4 External Reference Clock
The MCG module can support an external reference clock in all modes. See the device datasheet for external reference frequency range. When C1[IREFS] is set, the external reference clock will not be used by the FLL or PLL. In these modes, the frequency can be equal to the maximum frequency the chip-level timing specifications will support.
If any of the CME bits are asserted the slow internal reference clock is enabled along with the enabled external clock monitor. For the case when C6[CME0]=1, a loss of clock f is detected if the OSC0 external reference falls below a minimum frequency (f loc_high loc_low
depending on C2[RANGE0]).
or
NOTE
All clock monitors must be disabled before entering these lowpower modes: Stop, VLPS, VLPR, VLPW, LLS, and VLLSx.
On detecting a loss-of-clock event, the MCU generates a system reset if the respective
LOCRE bit is set. Otherwise the MCG sets the respective LOCS bit and the MCG generates a LOCS interrupt request. In the case where a OSC loss of clock is detected, the
PLL LOCK status bit is cleared.
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24.4.5 MCG Fixed Frequency Clock
The MCG Fixed Frequency Clock (MCGFFCLK) provides a fixed frequency clock source for other on-chip peripherals; see the block diagram. This clock is driven by either the slow clock from the internal reference clock generator or the external reference clock from the Crystal Oscillator, divided by the FLL reference clock divider. The source of
MCGFFCLK is selected by C1[IREFS].
This clock is synchronized to the peripheral bus clock and is valid only when its frequency is not more than 1/8 of the MCGOUTCLK frequency. When it is not valid, it is disabled and held high. The MCGFFCLK is not available when the MCG is in BLPI mode. This clock is also disabled in Stop mode. The FLL reference clock must be set within the valid frequency range for the MCGFFCLK.
24.4.6 MCG PLL clock
The MCG PLL Clock (MCGPLLCLK) is available depending on the device's configuration of the MCG module. For more details, see the clock distribution chapter of this MCU. The MCGPLLCLK is prevented from coming out of the MCG until it is enabled and S[LOCK0] is set.
24.4.7 MCG Auto TRIM (ATM)
The MCG Auto Trim (ATM) is a MCG feature that when enabled, it configures the MCG hardware to automatically trim the MCG Internal Reference Clocks using an external clock as a reference. The selection between which MCG IRC clock gets tested and enabled is controlled by the ATC[ATMS] control bit (ATC[ATMS]=0 selects the 32 kHz
IRC and ATC[ATMS]=1 selects the 4 MHz IRC). If 4 MHz IRC is selected for the ATM, a divide by 128 is enabled to divide down the 4 MHz IRC to a range of 31.250 kHz.
When MCG ATM is enabled by writing ATC[ATME] bit to 1, The ATM machine will start auto trimming the selected IRC clock. During the autotrim process, ATC[ATME] will remain asserted and will deassert after ATM is completed or an abort occurs. The
MCG ATM is aborted if a write to any of the following control registers is detected : C1,
C3, C4, or ATC or if Stop mode is entered. If an abort occurs, ATC[ATMF] fail flag is asserted.
The ATM machine uses the bus clock as the external reference clock to perform the IRC auto-trim. Therefore, it is required that the MCG is configured in a clock mode where the reference clock used to generate the system clock is the external reference clock such as
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FBE clock mode. The MCG must not be configured in a clock mode where selected IRC
ATM clock is used to generate the system clock. The bus clock is also required to be running with in the range of 8–16 MHz.
To perform the ATM on the selected IRC, the ATM machine uses the successive approximation technique to adjust the IRC trim bits to generate the desired IRC trimmed frequency. The ATM SARs each of the ATM IRC trim bits starting with the MSB. For each trim bit test, the ATM uses a pulse that is generated by the ATM selected IRC clock to enable a counter that counts number of ATM external clocks. At end of each trim bit, the ATM external counter value is compared to the ATCV[15:0] register value. Based on the comparison result, the ATM trim bit under test will get cleared or stay asserted. This is done until all trim bits have been tested by ATM SAR machine.
Before the ATM can be enabled, the ATM expected count needs to be derived and stored into the ATCV register. The ATCV expected count is derived based on the required target Internal Reference Clock (IRC) frequency, and the frequency of the external reference clock using the following formula:
ATCV
• Fr = Target Internal Reference Clock (IRC) Trimmed Frequency
• Fe = External Clock Frequency
If the auto trim is being performed on the 4 MHz IRC, the calculated expected count value must be multiplied by 128 before storing it in the ATCV register. Therefore, the
ATCV Expected Count Value for trimming the 4 MHz IRC is calculated using the following formula.
(128)
24.5 Initialization / Application information
This section describes how to initialize and configure the MCG module in an application.
The following sections include examples on how to initialize the MCG and properly switch between the various available modes.
24.5.1 MCG module initialization sequence
The MCG comes out of reset configured for FEI mode.
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The internal reference will stabilize in t irefsts
microseconds before the FLL can acquire lock. As soon as the internal reference is stable, the FLL will acquire lock in t fll_acquire milliseconds.
24.5.1.1 Initializing the MCG
Because the MCG comes out of reset in FEI mode, the only MCG modes that can be
directly switched to upon reset are FEE, FBE, and FBI modes (see Figure 24-16 ).
Reaching any of the other modes requires first configuring the MCG for one of these three intermediate modes. Care must be taken to check relevant status bits in the MCG status register reflecting all configuration changes within each mode.
To change from FEI mode to FEE or FBE modes, follow this procedure:
1. Enable the external clock source by setting the appropriate bits in C2 register.
2. Write to C1 register to select the clock mode.
• If entering FEE mode, set C1[FRDIV] appropriately, clear C1[IREFS] bit to switch to the external reference, and leave C1[CLKS] at 2'b00 so that the output of the FLL is selected as the system clock source.
• If entering FBE, clear C1[IREFS] to switch to the external reference and change
C1[CLKS] to 2'b10 so that the external reference clock is selected as the system clock source. The C1[FRDIV] bits should also be set appropriately here according to the external reference frequency to keep the FLL reference clock in the range of 31.25 kHz to 39.0625 kHz. Although the FLL is bypassed, it is still on in FBE mode.
• The internal reference can optionally be kept running by setting C1[IRCLKEN].
This is useful if the application will switch back and forth between internal and external modes. For minimum power consumption, leave the internal reference disabled while in an external clock mode.
3. Once the proper configuration bits have been set, wait for the affected bits in the
MCG status register to be changed appropriately, reflecting that the MCG has moved into the proper mode.
• If the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and C2[EREFS0] was also set in step 1, wait here for S[OSCINIT0] bit to become set indicating that the external clock source has finished its initialization cycles and stabilized.
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• If in FEE mode, check to make sure S[IREFST] is cleared before moving on.
• If in FBE mode, check to make sure S[IREFST] is cleared and S[CLKST] bits have changed to 2'b10 indicating the external reference clock has been appropriately selected. Although the FLL is bypassed, it is still on in FBE mode.
4. Write to the C4 register to determine the DCO output (MCGFLLCLK) frequency range.
• By default, with C4[DMX32] cleared to 0, the FLL multiplier for the DCO output is 640. For greater flexibility, if a mid-low-range FLL multiplier of 1280 is desired instead, set C4[DRST_DRS] bits to 2'b01 for a DCO output frequency of 40 MHz. If a mid high-range FLL multiplier of 1920 is desired instead, set the
C4[DRST_DRS] bits to 2'b10 for a DCO output frequency of 60 MHz. If a highrange FLL multiplier of 2560 is desired instead, set the C4[DRST_DRS] bits to
2'b11 for a DCO output frequency of 80 MHz.
• When using a 32.768 kHz external reference, if the maximum low-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set
C4[DRST_DRS] bits to 2'b00 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 732 will be 24
MHz.
• When using a 32.768 kHz external reference, if the maximum mid-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set
C4[DRST_DRS] bits to 2'b01 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 1464 will be 48
MHz.
• When using a 32.768 kHz external reference, if the maximum mid high-range
DCO frequency that can be achieved with a 32.768 kHz reference is desired, set
C4[DRST_DRS] bits to 2'b10 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 2197 will be 72
MHz.
• When using a 32.768 kHz external reference, if the maximum high-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set
C4[DRST_DRS] bits to 2'b11 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 2929 will be 96
MHz.
5. Wait for the FLL lock time to guarantee FLL is running at new C4[DRST_DRS] and
C4[DMX32] programmed frequency.
To change from FEI clock mode to FBI clock mode, follow this procedure:
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1. Change C1[CLKS] bits in C1 register to 2'b01 so that the internal reference clock is selected as the system clock source.
2. Wait for S[CLKST] bits in the MCG status register to change to 2'b01, indicating that the internal reference clock has been appropriately selected.
3. Write to the C2 register to determine the IRCS output (IRCSCLK) frequency range.
• By default, with C2[IRCS] cleared to 0, the IRCS selected output clock is the slow internal reference clock (32 kHz IRC). If the faster IRC is desired, set
C2[IRCS] to 1 for a IRCS clock derived from the 4 MHz IRC source.
24.5.2 Using a 32.768 kHz reference
In FEE and FBE modes, if using a 32.768 kHz external reference, at the default FLL multiplication factor of 640, the DCO output (MCGFLLCLK) frequency is 20.97 MHz at low-range.
If C4[DRST_DRS] bits are set to 2'b01, the multiplication factor is doubled to 1280, and the resulting DCO output frequency is 41.94 MHz at mid-low-range. If C4[DRST_DRS] bits are set to 2'b10, the multiplication factor is set to 1920, and the resulting DCO output frequency is 62.91 MHz at mid high-range. If C4[DRST_DRS] bits are set to 2'b11, the multiplication factor is set to 2560, and the resulting DCO output frequency is 83.89
MHz at high-range.
In FBI and FEI modes, setting C4[DMX32] bit is not recommended. If the internal reference is trimmed to a frequency above 32.768 kHz, the greater FLL multiplication factor could potentially push the microcontroller system clock out of specification and damage the part.
24.5.3 MCG mode switching
When switching between operational modes of the MCG, certain configuration bits must be changed in order to properly move from one mode to another.
Each time any of these bits are changed (C6[PLLS], C1[IREFS], C1[CLKS], C2[IRCS], or C2[EREFS0]), the corresponding bits in the MCG status register (PLLST, IREFST,
CLKST, IRCST, or OSCINIT) must be checked before moving on in the application software.
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Additionally, care must be taken to ensure that the reference clock divider (C1[FRDIV] and C5[PRDIV0]) is set properly for the mode being switched to. For instance, in PEE mode, if using a 4 MHz crystal, C5[PRDIV0] must be set to 5'b000 (divide-by-1) or
5'b001 (divide-by-2) to divide the external reference down to the required frequency between 2 and 4 MHz.
In FBE, FEE, FBI, and FEI modes, at any time, the application can switch the FLL multiplication factor between 640, 1280, 1920, and 2560 with C4[DRST_DRS] bits.
Writes to C4[DRST_DRS] bits will be ignored if C2[LP]=1.
The table below shows MCGOUTCLK frequency calculations using C1[FRDIV],
C5[PRDIV0], and C6[VDIV0] settings for each clock mode.
Table 24-19. MCGOUTCLK Frequency Calculation Options
Clock Mode
FEI (FLL engaged internal)
FEE (FLL engaged external)
FBE (FLL bypassed external)
FBI (FLL bypassed internal)
PEE (PLL engaged external)
PBE (PLL bypassed external)
BLPI (Bypassed low power internal) f
MCGOUTCLK
(f int
* F)
(f ext
/ FLL_R) *F
OSCCLK
MCGIRCLK
(OSCCLK / PLL_R) * M
OSCCLK
MCGIRCLK
Note
Typical f
MCGOUTCLK
= 21 MHz immediately after reset.
f ext
/ FLL_R must be in the range of
31.25 kHz to 39.0625 kHz
OSCCLK / FLL_R must be in the range of 31.25 kHz to 39.0625 kHz
Selectable between slow and fast
IRC
OSCCLK / PLL_R must be in the range of 2 – 4 MHz
OSCCLK / PLL_R must be in the range of 2 – 4 MHz
Selectable between slow and fast
IRC
BLPE (Bypassed low power external) OSCCLK
1. FLL_R is the reference divider selected by the C1[FRDIV] bits, PLL_R is the reference divider selected by C5[PRDIV0] bits, F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32] bits, and M is the multiplier selected by C6[VDIV0] bits.
This section will include three mode switching examples using an 4 MHz external crystal. If using an external clock source less than 2 MHz, the MCG must not be configured for any of the PLL modes (PEE and PBE).
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Initialization / Application information
24.5.3.1 Example 1: Moving from FEI to PEE mode: External Crystal =
4 MHz, MCGOUTCLK frequency = 48 MHz
In this example, the MCG will move through the proper operational modes from FEI to
PEE to achieve 48 MHz MCGOUTCLK frequency from 4 MHz external crystal reference. First, the code sequence will be described. Then there is a flowchart that illustrates the sequence.
1. First, FEI must transition to FBE mode: a. C2 = 0x2C
• C2[RANGE0] set to 2'b01 because the frequency of 4 MHz is within the high frequency range.
• C2[HGO0] set to 1 to configure the crystal oscillator for high gain operation.
• C2[EREFS0] set to 1, because a crystal is being used.
b. C1 = 0x90
• C1[CLKS] set to 2'b10 to select external reference clock as system clock source
• C1[FRDIV] set to 3'b010, or divide-by-128 because 4 MHz / 128 = 31.25
kHz which is in the 31.25 kHz to 39.0625 kHz range required by the FLL
• C1[IREFS] cleared to 0, selecting the external reference clock and enabling the external oscillator.
c. Loop until S[OSCINIT0] is 1, indicating the crystal selected by C2[EREFS0] has been initialized.
d. Loop until S[IREFST] is 0, indicating the external reference is the current source for the reference clock.
e. Loop until S[CLKST] is 2'b10, indicating that the external reference clock is selected to feed MCGOUTCLK.
2. Then configure C5[PRDIV0] to generate correct PLL reference frequency.
a. C5 = 0x01
• C5[PRDIV] set to 5'b00001, or divide-by-2 resulting in a pll reference frequency of 4MHz/2 = 2 MHz.
3. Then, FBE must transition either directly to PBE mode or first through BLPE mode and then to PBE mode:
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Chapter 24 Multipurpose Clock Generator (MCG) a. BLPE: If a transition through BLPE mode is desired, first set C2[LP] to 1.
b. BLPE/PBE: C6 = 0x40
• C6[PLLS] set to 1, selects the PLL. At this time, with a C1[PRDIV] value of
2'b001, the PLL reference divider is 2 (see PLL External Reference Divide
Factor table), resulting in a reference frequency of 4 MHz/ 2 = 2 MHz. In
BLPE mode, changing the C6[PLLS] bit only prepares the MCG for PLL usage in PBE mode.
• C6[VDIV] set to 5'b00000, or multiply-by-24 because 2 MHz reference * 24
= 48 MHz. In BLPE mode, the configuration of the VDIV bits does not matter because the PLL is disabled. Changing them only sets up the multiply value for PLL usage in PBE mode.
c. BLPE: If transitioning through BLPE mode, clear C2[LP] to 0 here to switch to
PBE mode.
d. PBE: Loop until S[PLLST] is set, indicating that the current source for the PLLS clock is the PLL.
e. PBE: Then loop until S[LOCK0] is set, indicating that the PLL has acquired lock.
4. Lastly, PBE mode transitions into PEE mode: a. C1 = 0x10
• C1[CLKS] set to 2'b00 to select the output of the PLL as the system clock source.
b. Loop until S[CLKST] are 2'b11, indicating that the PLL output is selected to feed MCGOUTCLK in the current clock mode.
• Now, with PRDIV of divide-by-2, and C6[VDIV] of multiply-by-24,
MCGOUTCLK = [(4 MHz / 2) * 24] = 48 MHz.
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Initialization / Application information
START
IN FEI MODE
C2 = 0x1C
C1 = 0x90
CHECK
S[OSCINIT] = 1?
NO
YES
CHECK
S[IREFST] = 0?
NO
YES
CHECK
S[CLKST] = %10?
NO
YES
C5 = 0x01
(C5[VDIV] = 1)
ENTER
BLPE MODE ?
NO
YES
C2 = 0x1E
(C2[LP] = 1)
C6 = 0x40
IN
BLPE MODE ?
(S[LP]=1)
NO
YES
C2 = 0x1C
(S[LP]=0)
CHECK
S[PLLST] = 1?
NO
YES
CHECK
S[LOCK] = 1?
NO
YES
C1 = 0x10
CHECK
S[CLKST] = %11?
NO
YES
CONTINUE
IN PEE MODE
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Figure 24-17. Flowchart of FEI to PEE mode transition using an 4 MHz crystal
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Chapter 24 Multipurpose Clock Generator (MCG)
24.5.3.2 Example 2: Moving from PEE to BLPI mode: MCGOUTCLK frequency =32 kHz
In this example, the MCG will move through the proper operational modes from PEE mode with a 4 MHz crystal configured for a 48 MHz MCGOUTCLK frequency (see previous example) to BLPI mode with a 32 kHz MCGOUTCLK frequency. First, the code sequence will be described. Then there is a flowchart that illustrates the sequence.
1. First, PEE must transition to PBE mode: a. C1 = 0x90
• C1[CLKS] set to 2'b10 to switch the system clock source to the external reference clock.
b. Loop until S[CLKST] are 2'b10, indicating that the external reference clock is selected to feed MCGOUTCLK.
2. Then, PBE must transition either directly to FBE mode or first through BLPE mode and then to FBE mode: a. BLPE: If a transition through BLPE mode is desired, first set C2[LP] to 1.
b. BLPE/FBE: C6 = 0x00
• C6[PLLS] clear to 0 to select the FLL. At this time, with C1[FRDIV] value of 3'b010, the FLL divider is set to 128, resulting in a reference frequency of
4 MHz / 128 = 31.25 kHz. If C1[FRDIV] was not previously set to 3'b010
(necessary to achieve required 31.25–39.06 kHz FLL reference frequency with an 4 MHz external source frequency), it must be changed prior to clearing C6[PLLS] bit. In BLPE mode,changing this bit only prepares the
MCG for FLL usage in FBE mode. With C6[PLLS] = 0, the C6[VDIV] value does not matter.
c. BLPE: If transitioning through BLPE mode, clear C2[LP] to 0 here to switch to
FBE mode.
d. FBE: Loop until S[PLLST] is cleared, indicating that the current source for the
PLLS clock is the FLL.
3. Next, FBE mode transitions into FBI mode: a. C1 = 0x54
• C1[CLKS] set to 2'b01 to switch the system clock to the internal reference clock.
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Initialization / Application information
• C1[IREFS] set to 1 to select the internal reference clock as the reference clock source.
• C1[FRDIV] remain unchanged because the reference divider does not affect the internal reference.
b. Loop until S[IREFST] is 1, indicating the internal reference clock has been selected as the reference clock source.
c. Loop until S[CLKST] are 2'b01, indicating that the internal reference clock is selected to feed MCGOUTCLK.
4. Lastly, FBI transitions into BLPI mode.
a. C2 = 0x02
• C2[LP] is 1
• C2[RANGE0], C2[HGO0], C2[EREFS0], C1[IRCLKEN], and
C1[IREFSTEN] bits are ignored when the C1[IREFS] bit is set. They can remain set, or be cleared at this point.
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START
IN PEE MODE
C1 = 0x90
CHECK
S[CLKST] = %10 ?
NO
YES
ENTER
BLPE MODE ?
NO
YES
C2 = 0x1E
(C2[LP] = 1)
C6 = 0x00
CHECK
S[PLLST] = 0?
NO
YES
C1 = 0x54
CHECK
S[IREFST] = 0?
NO
YES
CHECK
S[CLKST] = %01?
NO
YES
C2 = 0x02
IN
BLPE MODE ?
(C2[LP]=1)
NO
YES
C2 = 0x1C
(C2[LP] = 0)
CONTINUE
IN BLPI MODE
Figure 24-18. Flowchart of PEE to BLPI mode transition using an 4 MHz crystal
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Initialization / Application information
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Chapter 25
Oscillator (OSC)
The OSC module is a crystal oscillator. The module, in conjunction with an external crystal or resonator, generates a reference clock for the MCU.
25.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
The OSC module is a crystal oscillator. The module, in conjunction with an external crystal or resonator, generates a reference clock for the MCU.
25.2 Features and Modes
Key features of the module are listed here.
• Supports 32 kHz crystals (Low Range mode)
• Supports 3–8 MHz, 8–32 MHz crystals and resonators (High Range mode)
• Automatic Gain Control (AGC) to optimize power consumption in high frequency ranges 3–8 MHz, 8–32 MHz using low-power mode
• High gain option in frequency ranges: 32 kHz, 3–8 MHz, and 8–32 MHz
• Voltage and frequency filtering to guarantee clock frequency and stability
• Optionally external input bypass clock from EXTAL signal directly
• One clock for MCU clock system
• Two clocks for on-chip peripherals that can work in Stop modes
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Block Diagram
describes the module's operation in more detail.
25.3 Block Diagram
The OSC module uses a crystal or resonator to generate three filtered oscillator clock signals.Three clocks are output from OSC module: OSCCLK for MCU system,
OSCERCLK for on-chip peripherals, and OSC32KCLK. The OSCCLK can only work in run mode. OSCERCLK and OSC32KCLK can work in low power modes. For the clock source assignments, refer to the clock distribution information of this MCU.
Refer to the chip configuration chapter for the external reference clock source in this
MCU.
The figure found here shows the block diagram of the OSC module.
EXTAL XTAL
OSC Clock Enable
XTL_CLK
Mux
OSC_CLK_OUT
OSCERCLK
ERCLKEN
Range selections
Low Power config
Oscillator Circuits E N
OSC32KCLK
ERCLKEN EREFSTEN OSC_EN
4096
Counter
CNT_DONE_4096
OSC clock selection
Control and Decoding logic
OSCCLK
STOP
Figure 25-1. OSC Module Block Diagram
25.4 OSC Signal Descriptions
The table found here shows the user-accessible signals available for the OSC module.
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Chapter 25 Oscillator (OSC)
Refer to signal multiplexing information for this MCU for more details.
Table 25-1. OSC Signal Descriptions
Signal
EXTAL
XTAL
Description
External clock/Oscillator input
Oscillator output
I/O
I
O
25.5 External Crystal / Resonator Connections
The connections for a crystal/resonator frequency reference are shown in the figures found here.
When using low-frequency, low-power mode, the only external component is the crystal or ceramic resonator itself. In the other oscillator modes, load capacitors (C x feedback resistor (R
F
, C y
) and
) are required. The following table shows all possible connections.
Table 25-2. External Caystal/Resonator Connections
Oscillator Mode
Low-frequency (32 kHz), low-power
Low-frequency (32 kHz), high-gain
High-frequency (3~32 MHz), low-power
High-frequency (3~32 MHz), high-gain
Connections
Connection 1
Connection 3
Connection 3
1. With the low-power mode, the oscillator has the internal feedback resistor R
F externally with the Connection 3.
2. When the load capacitors (Cx, Cy) are greater than 30 pF, use Connection 3.
. Therefore, the feedback resistor must not be
XTAL
OSC
V
SS
EXTAL
Crystal or Resonator
Figure 25-2. Crystal/Ceramic Resonator Connections - Connection 1
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External Clock Connections
XTAL
OSC
V
SS
R
F
EXTAL
Crystal or Resonator
Figure 25-3. Crystal/Ceramic Resonator Connections - Connection 2
NOTE
Connection 1 and Connection 2 should use internal capacitors as the load of the oscillator by configuring the CR[SCxP] bits.
XTAL
OSC
V
SS
EXTAL
C x
C y
R
F
Crystal or Resonator
Figure 25-4. Crystal/Ceramic Resonator Connections - Connection 3
25.6 External Clock Connections
In external clock mode, the pins can be connected as shown in the figure found here.
NOTE
XTAL can be used as a GPIO when the GPIO alternate function is configured for it.
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XTAL
OSC
V
SS
EXTAL
I/O Clock Input
Figure 25-5. External Clock Connections
Chapter 25 Oscillator (OSC)
25.7 Memory Map/Register Definitions
Some oscillator module register bits are typically incorporated into other peripherals such as MCG or SIM.
25.7.1
OSC Memory Map/Register Definition
OSC memory map
Absolute address
(hex)
Register name
4006_5000 OSC Control Register (OSC0_CR)
Width
(in bits)
Access Reset value
8 R/W 00h
Section/ page
25.71.1 OSC Control Register (OSCx_CR)
NOTE
After OSC is enabled and starts generating the clocks, the configurations such as low power and frequency range, must not be changed.
Address: 4006_5000h base + 0h offset = 4006_5000h
Bit
Read
Write
Reset
7
0
6
0
5
0
4
0
3
0
2
0
OSCx_CR field descriptions
Field
7
ERCLKEN
External Reference Enable
Description
Enables external reference clock (OSCERCLK).
Table continues on the next page...
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0
0
0
427
Functional Description
Field
6
Reserved
5
EREFSTEN
OSCx_CR field descriptions (continued)
Description
0 External reference clock is inactive.
1 External reference clock is enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
External Reference Stop Enable
Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters
Stop mode.
4
Reserved
3
SC2P
0 External reference clock is disabled in Stop mode.
1 External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.
This field is reserved.
This read-only field is reserved and always has the value 0.
Oscillator 2 pF Capacitor Load Configure
Configures the oscillator load.
2
SC4P
1
SC8P
0
SC16P
0 Disable the selection.
1 Add 2 pF capacitor to the oscillator load.
Oscillator 4 pF Capacitor Load Configure
Configures the oscillator load.
0 Disable the selection.
1 Add 4 pF capacitor to the oscillator load.
Oscillator 8 pF Capacitor Load Configure
Configures the oscillator load.
0 Disable the selection.
1 Add 8 pF capacitor to the oscillator load.
Oscillator 16 pF Capacitor Load Configure
Configures the oscillator load.
0 Disable the selection.
1 Add 16 pF capacitor to the oscillator load.
25.8 Functional Description
Functional details of the module can be found here.
25.8.1 OSC module states
The states of the OSC module are shown in the following figure. The states and their transitions between each other are described in this section.
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Chapter 25 Oscillator (OSC)
OSCCLK
not requested
Off
Oscillator OFF
OSC_CLK_OUT = Static
OSCCLK requested
&&
Select OSC internal clock
OSCCLK requested
&&
Select clock from EXTAL signal
Start-Up
Oscillator ON, not yet stable
OSC_CLK_OUT = Static
External Clock Mode
Oscillator ON
OSC_CLK_OUT = EXTAL
CNT_DONE_4096
Stable
Oscillator ON, Stable
OSC_CLK_OUT = XTL_CLK
Figure 25-8. OSC Module state diagram
NOTE
XTL_CLK is the clock generated internally from OSC circuits.
25.8.1.1 Off
The OSC enters the Off state when the system does not require OSC clocks. Upon entering this state, XTL_CLK is static unless OSC is configured to select the clock from the EXTAL pad by clearing the external reference clock selection bit. For details regarding the external reference clock source in this MCU, refer to the chip configuration chapter. The EXTAL and XTAL pins are also decoupled from all other oscillator circuitry in this state. The OSC module circuitry is configured to draw minimal current.
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Functional Description
25.8.1.2 Oscillator startup
The OSC enters startup state when it is configured to generate clocks (internally the
OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit. In this state, the OSC module is enabled and oscillations are starting up, but have not yet stabilized. When the oscillation amplitude becomes large enough to pass through the input buffer, XTL_CLK begins clocking the counter. When the counter reaches 4096 cycles of XTL_CLK, the oscillator is considered stable and
XTL_CLK is passed to the output clock OSC_CLK_OUT.
25.8.1.3 Oscillator Stable
The OSC enters stable state when it is configured to generate clocks (internally the
OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit and the counter reaches 4096 cycles of XTL_CLK (when
CNT_DONE_4096 is high). In this state, the OSC module is producing a stable output clock on OSC_CLK_OUT. Its frequency is determined by the external components being used.
25.8.1.4 External Clock mode
The OSC enters external clock state when it is enabled and external reference clock selection bit is cleared. For details regarding external reference clock source in this MCU, see the chip configuration chapter. In this state, the OSC module is set to buffer (with hysteresis) a clock from EXTAL onto the OSC_CLK_OUT. Its frequency is determined by the external clock being supplied.
25.8.2 OSC module modes
The OSC is a pierce-type oscillator that supports external crystals or resonators operating
over the frequency ranges shown in Table 25-7 . These modes assume the following
conditions: OSC is enabled to generate clocks (OSC_EN=1), configured to generate clocks internally (MCG_C2[EREFS] = 1), and some or one of the other peripherals
(MCG, Timer, and so on) is configured to use the oscillator output clock
(OSC_CLK_OUT).
Table 25-7. Oscillator modes
Mode
Low-frequency, high-gain
Frequency Range f osc_lo
(1 kHz) up to f osc_lo
(32.768 kHz)
Table continues on the next page...
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Chapter 25 Oscillator (OSC)
Table 25-7. Oscillator modes (continued)
Mode
High-frequency mode1, high-gain
High-frequency mode1, low-power
High-frequency mode2, high-gain
High-frequency mode2, low-power
Frequency Range f osc_hi_1
(3 MHz) up to f osc_hi_1
(8 MHz) f osc_hi_2
(8 MHz) up to f osc_hi_2
(32 MHz)
NOTE
For information about low power modes of operation used in this chip and their alignment with some OSC modes, see the chip's Power Management details.
25.8.2.1 Low-Frequency, High-Gain Mode
In Low-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier.
The gain is set to achieve rail-to-rail oscillation amplitudes.
The oscillator input buffer in this mode is single-ended. It provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels.
In this mode, the internal capacitors could be used.
25.8.2.2 Low-Frequency, Low-Power Mode
In low-frequency, low-power mode, the oscillator uses a gain control loop to minimize power consumption. As the oscillation amplitude increases, the amplifier current is reduced. This continues until a desired amplitude is achieved at steady-state. This mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. In this mode, the internal capacitors could be used, the internal feedback resistor is connected, and no external resistor should be used.
In this mode, the amplifier inputs, gain-control input, and input buffer input are all capacitively coupled for leakage tolerance (not sensitive to the DC level of EXTAL).
Also in this mode, all external components except for the resonator itself are integrated, which includes the load capacitors and feeback resistor that biases EXTAL.
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Reset
25.8.2.3 High-Frequency, High-Gain Mode
In high-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier.
The gain is set to achieve rail-to-rail oscillation amplitudes. This mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels.
25.8.2.4 High-Frequency, Low-Power Mode
In high-frequency, low-power mode, the oscillator uses a gain control loop to minimize power consumption. As the oscillation amplitude increases, the amplifier current is reduced. This continues until a desired amplitude is achieved at steady-state. In this mode, no external resistor should be used.
The oscillator input buffer in this mode is differential. It provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels.
25.8.3 Counter
The oscillator output clock (OSC_CLK_OUT) is gated off until the counter has detected
4096 cycles of its input clock (XTL_CLK). After 4096 cycles are completed, the counter passes XTL_CLK onto OSC_CLK_OUT. This counting timeout is used to guarantee output clock stability.
25.8.4 Reference clock pin requirements
The OSC module requires use of both the EXTAL and XTAL pins to generate an output clock in Oscillator mode, but requires only the EXTAL pin in External clock mode. The
EXTAL and XTAL pins are available for I/O. For the implementation of these pins on this device, refer to the Signal Multiplexing chapter.
25.9 Reset
There is no reset state associated with the OSC module. The counter logic is reset when the OSC is not configured to generate clocks.
There are no sources of reset requests for the OSC module.
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25.10 Low power modes operation
When the MCU enters Stop modes, the OSC is functional depending on CR[ERCLKEN] and CR[EREFSETN] bit settings. If both these bits are set, the OSC is in operation.
In Low Leakage Stop (LLS) modes, the OSC holds all register settings. If
CR[ERCLKEN] and CR[EREFSTEN] are set before entry to Low Leakage Stop modes, the OSC is still functional in these modes. After waking up from Very Low Leakage Stop
(VLLSx) modes, all OSC register bits are reset and initialization is required through software.
25.11 Interrupts
The OSC module does not generate any interrupts.
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Interrupts
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Chapter 26
Flash Memory Controller (FMC)
26.1 Introduction
The Flash Memory Controller (FMC) is a memory acceleration unit. A list of features provided by the FMC can be found here.
• an interface between bus masters and the 32-bit program flash memory.
• a buffer and a cache that can accelerate program flash memory data transfers.
26.1.1 Overview
The Flash Memory Controller manages the interface between bus masters and the 32-bit program flash memory. The FMC receives status information detailing the configuration of the flash memory and uses this information to ensure a proper interface. The FMC supports 8-bit, 16-bit, and 32-bit read operations from the program flash memory. A write operation to program flash memory results in a bus error.
In addition, the FMC provides two separate mechanisms for accelerating the interface between bus masters and program flash memory. A 32-bit speculation buffer can prefetch the next 32-bit flash memory location, and a 4-way, 4-set program flash memory cache can store previously accessed program flash memory data for quick access times.
26.1.2 Features
The features of FMC module include:
• Interface between bus masters and the 32-bit program flash memory:
• 8-bit, 16-bit, and 32-bit read operations to nonvolatile flash memory.
• Acceleration of data transfer from the program flash memory to the device:
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Modes of operation
• 32-bit prefetch speculation buffer for program flash accesses with controls for instruction/data access
• 4-way, 4-set, 32-bit line size program flash memory cache for a total of sixteen
32-bit entries with invalidation control
26.2 Modes of operation
The FMC operates only when a bus master accesses the program flash memory.
In terms of chip power modes:
• The FMC operates only in Run and Wait modes, including VLPR and VLPW modes.
• For any power mode where the program flash memory cannot be accessed, the FMC is disabled.
26.3 External signal description
The FMC has no external (off-chip) signals.
26.4 Memory map and register descriptions
The MCM's programming model provides control and configuration of the FMC's features.
For details, see the description of the MCM's Platform Control Register (PLACR).
26.5 Functional description
The FMC is a flash acceleration unit with flexible buffers for user configuration.
Besides managing the interface between bus masters and the program flash memory, the
FMC can be used to customize the program flash memory cache and buffer to provide single-cycle system clock data access times. Whenever a hit occurs for the prefetch speculation buffer or the cache (when enabled), the requested data is transferred within a single system clock.
Upon system reset, the FMC is configured as follows:
• Flash cache is enabled.
• Instruction speculation and caching are enabled.
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• Data speculation is disabled.
• Data caching is enabled.
Though the default configuration provides flash acceleration, advanced users may desire to customize the FMC buffer configurations to maximize throughput for their use cases.
For example, the user may adjust the controls to enable buffering per access type (data or instruction).
NOTE
When reconfiguring the FMC, do not program the control and configuration inputs to the FMC while the program flash memory is being accessed. Instead, change them with a routine executing from RAM in supervisor mode.
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Functional description
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Chapter 27
Flash Memory Module (FTFA)
27.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
The flash memory module includes the following accessible memory regions:
• Program flash memory for vector space and code store
Flash memory is ideal for single-supply applications, permitting in-the-field erase and reprogramming operations without the need for any external high voltage power sources.
The flash memory module includes a memory controller that executes commands to modify flash memory contents. An erased bit reads '1' and a programmed bit reads '0'.
The programming operation is unidirectional; it can only move bits from the '1' state
(erased) to the '0' state (programmed). Only the erase operation restores bits from '0' to
'1'; bits cannot be programmed from a '0' to a '1'.
CAUTION
A flash memory location must be in the erased state before being programmed. Cumulative programming of bits (back-toback program operations without an intervening erase) within a flash memory location is not allowed. Re-programming of existing 0s to 0 is not allowed as this overstresses the device.
The standard shipping condition for flash memory is erased with security disabled. Data loss over time may occur due to degradation of the erased ('1') states and/or programmed ('0') states. Therefore, it is recommended that each flash block or sector be re-erased immediately prior to factory programming to ensure that the full data retention capability is achieved.
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Introduction
27.1.1 Features
The flash memory module includes the following features.
NOTE
See the device's Chip Configuration details for the exact amount of flash memory available on your device.
27.1.1.1 Program Flash Memory Features
• Sector size of 1 KB
• Program flash protection scheme prevents accidental program or erase of stored data
• Automated, built-in, program and erase algorithms with verify
27.1.1.2 Other Flash Memory Module Features
• Internal high-voltage supply generator for flash memory program and erase operations
• Optional interrupt generation upon flash command completion
• Supports MCU security mechanisms which prevent unauthorized access to the flash memory contents
27.1.2 Block Diagram
The block diagram of the flash memory module is shown in the following figure.
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Interrupt
Register access
Status registers
Control registers
Memory controller
Program flash
0
To MCU's flash controller
Figure 27-1. Flash Block Diagram
27.1.3 Glossary
Command write sequence — A series of MCU writes to the flash FCCOB register group that initiates and controls the execution of flash algorithms that are built into the flash memory module.
Endurance — The number of times that a flash memory location can be erased and reprogrammed.
FCCOB (Flash Common Command Object) — A group of flash registers that are used to pass command, address, data, and any associated parameters to the memory controller in the flash memory module.
Flash block — A macro within the flash memory module which provides the nonvolatile memory storage.
Flash Memory Module — All flash blocks plus a flash management unit providing high-level control and an interface to MCU buses.
IFR — Nonvolatile information register found in each flash block, separate from the main memory array.
Longword — 32 bits of data with an aligned longword having byte-address[1:0] = 00.
NVM — Nonvolatile memory. A memory technology that maintains stored data during power-off. The flash array is an NVM using NOR-type flash memory technology.
NVM Normal Mode — An NVM mode that provides basic user access to flash memory module resources. The CPU or other bus masters initiate flash program and erase operations (or other flash commands) using writes to the FCCOB register group in the flash memory module.
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External Signal Description
NVM Special Mode — An NVM mode enabling external, off-chip access to the memory resources in the flash memory module. A reduced flash command set is available when the MCU is secured. See the Chip Configuration details for information on when this mode is used.
Program flash — The program flash memory provides nonvolatile storage for vectors and code store.
Program flash Sector — The smallest portion of the program flash memory
(consecutive addresses) that can be erased.
Retention — The length of time that data can be kept in the NVM without experiencing errors upon readout. Since erased (1) states are subject to degradation just like programmed (0) states, the data retention limit may be reached from the last erase operation (not from the programming time).
RWW— Read-While-Write. The ability to simultaneously read from one memory resource while commanded operations are active in another memory resource.
Secure — An MCU state conveyed to the flash memory module as described in the Chip
Configuration details for this device. In the secure state, reading and changing NVM contents is restricted.
Word — 16 bits of data with an aligned word having byte-address[0] = 0.
27.2 External Signal Description
The flash memory module contains no signals that connect off-chip.
27.3 Memory Map and Registers
This section describes the memory map and registers for the flash memory module.
Data read from unimplemented memory space in the flash memory module is undefined.
Writes to unimplemented or reserved memory space (registers) in the flash memory module are ignored.
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27.3.1 Flash Configuration Field Description
The program flash memory contains a 16-byte flash configuration field that stores default protection settings (loaded on reset) and security information that allows the MCU to restrict access to the flash memory module.
Flash Configuration Field Byte
Address
0x0_0400–0x0_0407 8
Size (Bytes) Field Description
0x0_0408–0x0_040B
0x0_040F
0x0_040E
0x0_040D
0x0_040C
4
1
1
1
1
Backdoor Comparison Key. Refer to
Verify Backdoor Access Key Command
and
Program flash protection bytes. Refer to the description of the Program Flash
Protection Registers (FPROT0-3).
Reserved
Reserved
Flash nonvolatile option byte. Refer to the description of the Flash Option
Register (FOPT).
Flash security byte. Refer to the description of the Flash Security
Register (FSEC).
27.3.2 Program Flash IFR Map
The program flash IFR is nonvolatile information memory that can be read freely, but the user has no erase and limited program capabilities (see the Read Once, Program Once,
and Read Resource commands in Read Once Command ,
).
The contents of the program flash IFR are summarized in the table found here and further described in the subsequent paragraphs.
The program flash IFR is located within the program flash 0 memory block.
Address Range
0x00 – 0xBF
0xC0 – 0xFF
Size (Bytes)
192
64
Field Description
Reserved
Program Once Field
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27.3.2.1 Program Once Field
The Program Once Field in the program flash IFR provides 64 bytes of user data storage separate from the program flash main array. The user can program the Program Once
Field one time only as there is no program flash IFR erase mechanism available to the user. The Program Once Field can be read any number of times. This section of the program flash IFR is accessed in 4-byte records using the Read Once and Program Once
commands (see Read Once Command and
).
27.3.3 Register Descriptions
The flash memory module contains a set of memory-mapped control and status registers.
NOTE
While a command is running (FSTAT[CCIF]=0), register writes are not accepted to any register except FCNFG and
FSTAT. The no-write rule is relaxed during the start-up reset sequence, prior to the initial rise of CCIF. During this initialization period the user may write any register. All register writes are also disabled (except for registers FCNFG and
FSTAT) whenever an erase suspend request is active
(FCNFG[ERSSUSP]=1).
FTFA memory map
Absolute address
(hex)
Register name
4002_0000 Flash Status Register (FTFA_FSTAT)
4002_0001 Flash Configuration Register (FTFA_FCNFG)
4002_0002 Flash Security Register (FTFA_FSEC)
4002_0003 Flash Option Register (FTFA_FOPT)
4002_0004
4002_0005
Flash Common Command Object Registers
(FTFA_FCCOB3)
Flash Common Command Object Registers
(FTFA_FCCOB2)
4002_0006
4002_0007
4002_0008
4002_0009
Flash Common Command Object Registers
(FTFA_FCCOB1)
Flash Common Command Object Registers
(FTFA_FCCOB0)
Flash Common Command Object Registers
(FTFA_FCCOB7)
Flash Common Command Object Registers
(FTFA_FCCOB6)
Width
(in bits)
Table continues on the next page...
8
8
8
8
8
8
8
8
8
8
Access Reset value
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
00h
00h
Section/ page
Undefined
Undefined
00h
00h
00h
00h
00h
00h
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FTFA memory map (continued)
Absolute address
(hex)
Register name
4002_000A
4002_000B
4002_000C
Flash Common Command Object Registers
(FTFA_FCCOB5)
Flash Common Command Object Registers
(FTFA_FCCOB4)
Flash Common Command Object Registers
(FTFA_FCCOBB)
4002_000D
4002_000E
Flash Common Command Object Registers
(FTFA_FCCOBA)
Flash Common Command Object Registers
(FTFA_FCCOB9)
4002_000F
Flash Common Command Object Registers
(FTFA_FCCOB8)
4002_0010 Program Flash Protection Registers (FTFA_FPROT3)
4002_0011 Program Flash Protection Registers (FTFA_FPROT2)
4002_0012 Program Flash Protection Registers (FTFA_FPROT1)
4002_0013 Program Flash Protection Registers (FTFA_FPROT0)
Width
(in bits)
Access Reset value
8
8
8
8
8
8
8
8
8
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00h
00h
00h
00h
00h
00h
Section/ page
Undefined
Undefined
Undefined
Undefined
27.33.1 Flash Status Register (FTFA_FSTAT)
The FSTAT register reports the operational status of the flash memory module.
The CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The
MGSTAT0 bit is read only. The unassigned bits read 0 and are not writable.
NOTE
When set, the Access Error (ACCERR) and Flash Protection
Violation (FPVIOL) bits in this register prevent the launch of any more commands until the flag is cleared (by writing a one to it).
Address: 4002_0000h base + 0h offset = 4002_0000h
Bit
Read
Write
Reset
7
0
6
0
5
0
Field
7
CCIF
4
0
3
0
FTFA_FSTAT field descriptions
Description
Command Complete Interrupt Flag
Table continues on the next page...
2
0
1
0
0
0
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Field
FTFA_FSTAT field descriptions (continued)
Description
Indicates that a flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command, and CCIF stays low until command completion or command violation.
CCIF is reset to 0 but is set to 1 by the memory controller at the end of the reset initialization sequence.
Depending on how quickly the read occurs after reset release, the user may or may not see the 0 hardware reset value.
6
RDCOLERR
5
ACCERR
0 Flash command in progress
1 Flash command has completed
Flash Read Collision Error Flag
Indicates that the MCU attempted a read from a flash memory resource that was being manipulated by a flash command (CCIF=0). Any simultaneous access is detected as a collision error by the block arbitration logic. The read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by writing a 1 to it.
Writing a 0 to RDCOLERR has no effect.
0 No collision error detected
1 Collision error detected
Flash Access Error Flag
Indicates an illegal access has occurred to a flash memory resource caused by a violation of the command write sequence or issuing an illegal flash command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the
ACCERR bit has no effect.
4
FPVIOL
3–1
Reserved
0
MGSTAT0
0 No access error detected
1 Access error detected
Flash Protection Violation Flag
Indicates an attempt was made to program or erase an address in a protected area of program flash memory during a command write sequence . While FPVIOL is set, the CCIF flag cannot be cleared to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a 0 to the FPVIOL bit has no effect.
0 No protection violation detected
1 Protection violation detected
This field is reserved.
This read-only field is reserved and always has the value 0.
Memory Controller Command Completion Status Flag
The MGSTAT0 status flag is set if an error is detected during execution of a flash command or during the flash reset sequence. As a status flag, this field cannot (and need not) be cleared by the user like the other error flags in this register.
The value of the MGSTAT0 bit for "command-N" is valid only at the end of the "command-N" execution when CCIF=1 and before the next command has been launched. At some point during the execution of
"command-N+1," the previous result is discarded and any previous error is cleared.
27.33.2 Flash Configuration Register (FTFA_FCNFG)
This register provides information on the current functional state of the flash memory module.
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The erase control bits (ERSAREQ and ERSSUSP) have write restrictions. The unassigned bits read as noted and are not writable.
Address: 4002_0000h base + 1h offset = 4002_0001h
Bit
Read
Write
Reset
7
6
5
Field
7
CCIE
4
3
0 0 0 0 0
FTFA_FCNFG field descriptions
Description
Command Complete Interrupt Enable
Controls interrupt generation when a flash command completes.
6
RDCOLLIE
5
ERSAREQ
4
ERSSUSP
2
0
1
0
0
0
0 Command complete interrupt disabled
1 Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
Read Collision Error Interrupt Enable
Controls interrupt generation when a flash memory read collision error occurs.
0 Read collision error interrupt disabled
1 Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]).
Erase All Request
Issues a request to the memory controller to execute the Erase All Blocks command and release security.
ERSAREQ is not directly writable but is under indirect user control. Refer to the device's Chip
Configuration details on how to request this command.
ERSAREQ sets when an erase all request is triggered external to the flash memory module and CCIF is set (no command is currently being executed). ERSAREQ is cleared by the flash memory module when the operation completes.
0 No request or request complete
1 Request to:
1. run the Erase All Blocks command,
2. verify the erased state,
3. program the security byte in the Flash Configuration Field to the unsecure state, and
4. release MCU security by setting the FSEC[SEC] field to the unsecure state.
Erase Suspend
Allows the user to suspend (interrupt) the Erase Flash Sector command while it is executing.
3
Reserved
2
Reserved
1
Reserved
0 No suspend requested
1 Suspend the current Erase Flash Sector command execution.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
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Field
0
Reserved
FTFA_FCNFG field descriptions (continued)
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
27.33.3 Flash Security Register (FTFA_FSEC)
This read-only register holds all bits associated with the security of the MCU and flash memory module.
During the reset sequence, the register is loaded with the contents of the flash security byte in the Flash Configuration Field located in program flash memory. The flash basis for the values is signified by X in the reset value.
Address: 4002_0000h base + 2h offset = 4002_0002h
5 Bit
Read
Write
Reset
7
* Notes:
• x = Undefined at reset.
6
4
3
2
1
0
Field
7–6
KEYEN
5–4
MEEN
3–2
FSLACC
FTFA_FSEC field descriptions
Description
Backdoor Key Security Enable
Enables or disables backdoor key access to the flash memory module.
00 Backdoor key access disabled
01 Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
10 Backdoor key access enabled
11 Backdoor key access disabled
Mass Erase Enable Bits
Enables and disables mass erase capability of the flash memory module. The state of this field is relevant only when SEC is set to secure outside of NVM Normal Mode. When SEC is set to unsecure, the MEEN setting does not matter.
00 Mass erase is enabled
01 Mass erase is enabled
10 Mass erase is disabled
11 Mass erase is enabled
Freescale Failure Analysis Access Code
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Field
1–0
SEC
Chapter 27 Flash Memory Module (FTFA)
FTFA_FSEC field descriptions (continued)
Description
Enables or disables access to the flash memory contents during returned part failure analysis at
Freescale. When SEC is secure and FSLACC is denied, access to the program flash contents is denied and any failure analysis performed by Freescale factory test must begin with a full erase to unsecure the part.
When access is granted (SEC is unsecure, or SEC is secure and FSLACC is granted), Freescale factory testing has visibility of the current flash contents. The state of the FSLACC bits is only relevant when SEC is set to secure. When SEC is set to unsecure, the FSLACC setting does not matter.
00 Freescale factory access granted
01 Freescale factory access denied
10 Freescale factory access denied
11 Freescale factory access granted
Flash Security
Defines the security state of the MCU. In the secure state, the MCU limits access to flash memory module resources. The limitations are defined per device and are detailed in the Chip Configuration details. If the flash memory module is unsecured using backdoor key access, SEC is forced to 10b.
00 MCU security status is secure.
01 MCU security status is secure.
10 MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)
11 MCU security status is secure.
27.33.4 Flash Option Register (FTFA_FOPT)
The flash option register allows the MCU to customize its operations by examining the state of these read-only bits, which are loaded from NVM at reset. The function of the bits is defined in the device's Chip Configuration details.
All bits in the register are read-only .
During the reset sequence, the register is loaded from the flash nonvolatile option byte in the Flash Configuration Field located in program flash memory. The flash basis for the values is signified by X in the reset value.
Address: 4002_0000h base + 3h offset = 4002_0003h
6 5 Bit
Read
Write
Reset
7
* Notes:
• x = Undefined at reset.
4
3
2
1
0
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Field
7–0
OPT
FTFA_FOPT field descriptions
Description
Nonvolatile Option
These bits are loaded from flash to this register at reset. Refer to the device's Chip Configuration details for the definition and use of these bits.
27.33.5 Flash Common Command Object Registers
(FTFA_FCCOBn)
The FCCOB register group provides 12 bytes for command codes and parameters. The individual bytes within the set append a 0-B hex identifier to the FCCOB register name:
FCCOB0, FCCOB1, ..., FCCOBB.
Address: 4002_0000h base + 4h offset + (1d × i), where i=0d to 11d
Bit
Read
Write
Reset
Field
7–0
CCOBn
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
FTFA_FCCOBn field descriptions
Description
The FCCOB register provides a command code and relevant parameters to the memory controller. The individual registers that compose the FCCOB data set can be written in any order, but you must provide all needed values, which vary from command to command. First, set up all required FCCOB fields and then initiate the command’s execution by writing a 1 to the FSTAT[CCIF] bit. This clears the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed by the user until the command completes
(CCIF returns to 1). No command buffering or queueing is provided; the next command can be loaded only after the current command completes.
Some commands return information to the FCCOB registers. Any values returned to FCCOB are available for reading after the FSTAT[CCIF] flag returns to 1 by the memory controller.
The following table shows a generic flash command format. The first FCCOB register, FCCOB0, always contains the command code. This 8-bit value defines the command to be executed. The command code is followed by the parameters required for this specific flash command, typically an address and/or data values.
NOTE: The command parameter table is written in terms of FCCOB Number (which is equivalent to the byte number). This number is a reference to the FCCOB register name and is not the register address.
0
1
2
3
FCCOB Number Typical Command Parameter Contents [7:0]
FCMD (a code that defines the flash command)
Flash address [23:16]
Flash address [15:8]
Flash address [7:0]
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Field
8
9
6
7
4
5
A
B
Chapter 27 Flash Memory Module (FTFA)
FTFA_FCCOBn field descriptions (continued)
FCCOB Number
Description
Typical Command Parameter Contents [7:0]
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
FCCOB Endianness and Multi-Byte Access :
The FCCOB register group uses a big endian addressing convention. For all command parameter fields larger than 1 byte, the most significant data resides in the lowest FCCOB register number. The FCCOB register group may be read and written as individual bytes, aligned words (2 bytes) or aligned longwords
(4 bytes).
27.33.6 Program Flash Protection Registers (FTFA_FPROTn)
The FPROT registers define which logical program flash regions are protected from program and erase operations. Protected flash regions cannot have their content changed; that is, these regions cannot be programmed and cannot be erased by any flash command.
Unprotected regions can be changed by program and erase operations.
The four FPROT registers allow up to 32 protectable regions. Each bit protects a 1/32 region of the program flash memory except for memory configurations with less than 32
KB of program flash where each assigned bit protects 1 KB . For configurations with 24
KB of program flash memory or less, FPROT0 is not used. For configurations with 16
KB of program flash memory or less, FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is not used. The bitfields are defined in each register as follows:
Program flash protection register
FPROT0
FPROT1
FPROT2
FPROT3
Program flash protection bits
PROT[31:24]
PROT[23:16]
PROT[15:8]
PROT[7:0]
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Memory Map and Registers
During the reset sequence, the FPROT registers are loaded with the contents of the program flash protection bytes in the Flash Configuration Field as indicated in the following table.
Program flash protection register
FPROT0
FPROT1
FPROT2
FPROT3
Flash Configuration Field offset address
0x000B
0x000A
0x0009
0x0008
To change the program flash protection that is loaded during the reset sequence, unprotect the sector of program flash memory that contains the Flash Configuration
Field. Then, reprogram the program flash protection byte.
Address: 4002_0000h base + 10h offset + (1d × i), where i=0d to 3d
Bit
Read
Write
Reset
7
6
5
4
* Notes:
• x = Undefined at reset.
3
2
1
0
Field
7–0
PROT
FTFA_FPROTn field descriptions
Description
Program Flash Region Protect
Each program flash region can be protected from program and erase operations by setting the associated
PROT bit.
In NVM Normal mode: The protection can only be increased, meaning that currently unprotected memory can be protected, but currently protected memory cannot be unprotected. Since unprotected regions are marked with a 1 and protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are ignored.
In NVM Special mode: All bits of FPROT are writable without restriction. Unprotected areas can be protected and protected areas can be unprotected.
Restriction: The user must never write to any FPROT register while a command is running (CCIF=0).
Trying to alter data in any protected area in the program flash memory results in a protection violation error and sets the FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible if it contains any protected region.
Each bit in the 32-bit protection register represents 1/32 of the total program flash except for configurations where program flash memory is less than 32 KB. For configurations with less than 32 KB of program flash memory, each assigned bit represents 1 KB.
0 Program flash region is protected.
1 Program flash region is not protected
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Chapter 27 Flash Memory Module (FTFA)
27.4 Functional Description
The information found here describes functional details of the flash memory module.
27.4.1 Flash Protection
Individual regions within the flash memory can be protected from program and erase operations.
Protection is controlled by the following registers:
• FPROTn —
• For 2 n program flash sizes, four registers typically protect 32 regions of the program flash memory as shown in the following figure
Program flash
0x0_0000
Program flash size / 32 FPROT3[PROT0]
Program flash size / 32
Program flash size / 32
Program flash size / 32
FPROT3[PROT1]
FPROT3[PROT2]
FPROT3[PROT3]
Program flash size / 32
Program flash size / 32
FPROT0[PROT29]
FPROT0[PROT30]
Program flash size / 32 FPROT0[PROT31]
Last program flash address
Figure 27-24. Program flash protection
NOTE
Flash protection features are discussed further in AN4507:
Using the Kinetis Security and Flash Protection Features . Not all features described in the application note are available on this device.
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Functional Description
27.4.2 Interrupts
The flash memory module can generate interrupt requests to the MCU upon the occurrence of various flash events.
These interrupt events and their associated status and control bits are shown in the following table.
Table 27-24. Flash Interrupt Sources
Flash Event
Flash Command Complete
Readable
Status Bit
FSTAT[CCIF]
Interrupt
Enable Bit
FCNFG[CCIE]
Flash Read Collision Error FSTAT[RDCOLERR] FCNFG[RDCOLLIE]
Note
Vector addresses and their relative interrupt priority are determined at the MCU level.
Some devices also generate a bus error response as a result of a Read Collision Error event. See the chip configuration information to determine if a bus error response is also supported.
27.4.3 Flash Operation in Low-Power Modes
27.4.3.1 Wait Mode
When the MCU enters wait mode, the flash memory module is not affected. The flash memory module can recover the MCU from wait via the command complete interrupt
27.4.3.2 Stop Mode
When the MCU requests stop mode, if a flash command is active (CCIF = 0) the command execution completes before the MCU is allowed to enter stop mode.
CAUTION
The MCU should never enter stop mode while any flash command is running (CCIF = 0).
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Chapter 27 Flash Memory Module (FTFA)
NOTE
While the MCU is in very-low-power modes (VLPR, VLPW,
VLPS), the flash memory module does not accept flash commands.
27.4.4 Functional Modes of Operation
The flash memory module has two operating modes: NVM Normal and NVM Special.
The operating mode affects the command set availability (see
). Refer to the
Chip Configuration details of this device for how to activate each mode.
27.4.5 Flash Reads and Ignored Writes
The flash memory module requires only the flash address to execute a flash memory read.
The MCU must not read from the flash memory while commands are running (as evidenced by CCIF=0) on that block. Read data cannot be guaranteed from a flash block while any command is processing within that block. The block arbitration logic detects any simultaneous access and reports this as a read collision error (see the
FSTAT[RDCOLERR] bit).
27.4.6 Read While Write (RWW)
The following simultaneous accesses are not allowed:
• Reading from program flash memory space while a flash command is active
(CCIF=0).
27.4.7 Flash Program and Erase
All flash functions except read require the user to setup and launch a flash command through a series of peripheral bus writes.
The user cannot initiate any further flash commands until notified that the current command has completed. The flash command structure and operation are detailed in
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Functional Description
27.4.8 Flash Command Operations
Flash command operations are typically used to modify flash memory contents.
The next sections describe:
• The command write sequence used to set flash command parameters and launch execution
• A description of all flash commands available
27.4.8.1 Command Write Sequence
Flash commands are specified using a command write sequence illustrated in
27-25 . The flash memory module performs various checks on the command (FCCOB)
content and continues with command execution if all requirements are fulfilled.
Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be zero and the CCIF flag must read 1 to verify that any previous command has completed. If CCIF is zero, the previous command execution is still active, a new command write sequence cannot be started, and all writes to the FCCOB registers are ignored.
Attempts to launch a flash command in VLP mode will be ignored.
27.4.8.1.1 Load the FCCOB Registers
The user must load the FCCOB registers with all parameters required by the desired flash command. The individual registers that make up the FCCOB data set can be written in any order.
27.4.8.1.2 Launch the Command by Clearing CCIF
Once all relevant command parameters have been loaded, the user launches the command by clearing FSTAT[CCIF] by writing a '1' to it. FSTAT[CCIF] remains 0 until the flash command completes.
The FSTAT register contains a blocking mechanism that prevents a new command from launching (can't clear FSTAT[CCIF]) if the previous command resulted in an access error
(FSTAT[ACCERR]=1) or a protection violation (FSTAT[FPVIOL]=1). In error scenarios, two writes to FSTAT are required to initiate the next command: the first write clears the error flags, the second write clears CCIF.
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Chapter 27 Flash Memory Module (FTFA)
27.4.8.1.3 Command Execution and Error Reporting
The command processing has several steps:
1. The flash memory module reads the command code and performs a series of parameter checks and protection checks, if applicable, which are unique to each command.
If the parameter check fails, the FSTAT[ACCERR] (access error) flag is set.
FSTAT[ACCERR] reports invalid instruction codes and out-of bounds addresses.
Usually, access errors suggest that the command was not set-up with valid parameters in the FCCOB register group.
Program and erase commands also check the address to determine if the operation is requested to execute on protected areas. If the protection check fails,
FSTAT[FPVIOL] (protection error) flag is set.
Command processing never proceeds to execution when the parameter or protection step fails. Instead, command processing is terminated after setting FSTAT[CCIF].
2. If the parameter and protection checks pass, the command proceeds to execution.
Run-time errors, such as failure to erase verify, may occur during the execution phase. Run-time errors are reported in FSTAT[MGSTAT0]. A command may have access errors, protection errors, and run-time errors, but the run-time errors are not seen until all access and protection errors have been corrected.
3. Command execution results, if applicable, are reported back to the user via the
FCCOB and FSTAT registers.
4. The flash memory module sets FSTAT[CCIF] signifying that the command has completed.
The flow for a generic command write sequence is illustrated in the following figure.
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Functional Description
START
Read: FSTAT register
FCCOB
Availability Check no
CCIF
= ‘1’?
Previous command complete?
yes
Results from previous command
Access Error and
Protection Violation
Check
ACCERR/
FPVIOL
Set?
no yes
Write to the FCCOB registers to load the required command parameter.
Clear the old errors
Write 0x30 to FSTAT register
More
Parameters?
no
Clear the CCIF to launch the command
Write 0x80 to FSTAT register yes
EXIT
Figure 27-25. Generic flash command write sequence flowchart
27.4.8.2 Flash Commands
The following table summarizes the function of all flash commands.
FCMD
0x01
0x02
0x03
0x06
Command
Read 1s Section
Program Check
Read Resource
Program Longword
×
Program flash
×
IFR, ID
×
Function
Verify that a given number of program flash locations from a starting address are erased.
Tests previously-programmed locations at margin read levels.
Read 4 bytes from program flash IFR or version ID.
Program 4 bytes in a program flash block.
Table continues on the next page...
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FCMD
0x09
0x40
0x41
0x43
0x44
0x45
Command
Erase Flash Sector
Read 1s All Blocks
Read Once
Program Once
Erase All Blocks
×
Program flash
×
IFR
IFR
×
Verify Backdoor Access Key ×
Chapter 27 Flash Memory Module (FTFA)
Function
Erase all bytes in a program flash sector.
Verify that the program flash block is erased then release
MCU security.
Read 4 bytes of a dedicated
64 byte field in the program flash 0 IFR.
One-time program of 4 bytes of a dedicated 64-byte field in the program flash 0 IFR.
Erase the program flash block, verify-erase and release MCU security.
NOTE: An erase is only possible when all memory locations are unprotected.
Release MCU security after comparing a set of usersupplied security keys to those stored in the program flash.
27.4.8.3 Flash Commands by Mode
The following table shows the flash commands that can be executed in each flash operating mode.
Table 27-25. Flash Commands by Mode
FCMD Command
0x01 Read 1s Section
0x02 Program Check
0x03 Read Resource
0x06 Program Longword
0x09 Erase Flash Sector
0x40 Read 1s All Blocks
0x41 Read Once
0x43 Program Once
0x44 Erase All Blocks
0x45
Verify Backdoor Access
Key
Unsecure
×
×
×
×
×
×
×
×
×
×
NVM Normal
Secure
×
×
×
×
×
×
×
×
×
×
MEEN=10
×
×
×
×
×
×
×
×
×
×
Unsecure
×
×
×
×
×
×
×
×
×
×
NVM Special
Secure
—
×
—
—
—
—
—
—
×
—
MEEN=10
—
—
—
—
—
—
—
—
—
—
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Functional Description
27.4.9 Margin Read Commands
The Read-1s commands (Read 1s All Blocks and Read 1s Section) and the Program
Check command have a margin choice parameter that allows the user to apply nonstandard read reference levels to the program flash array reads performed by these commands. Using the preset 'user' and 'factory' margin levels, these commands perform their associated read operations at tighter tolerances than a 'normal' read. These nonstandard read levels are applied only during the command execution. All simple
(uncommanded) flash array reads to the MCU always use the standard, un-margined, read reference level.
Only the 'normal' read level should be employed during normal flash usage. The nonstandard, 'user' and 'factory' margin levels should be employed only in special cases.
They can be used during special diagnostic routines to gain confidence that the device is not suffering from the end-of-life data loss customary of flash memory devices.
Erased ('1') and programmed ('0') bit states can degrade due to elapsed time and data cycling (number of times a bit is erased and re-programmed). The lifetime of the erased states is relative to the last erase operation. The lifetime of the programmed states is measured from the last program time.
The 'user' and 'factory' levels become, in effect, a minimum safety margin; i.e. if the reads pass at the tighter tolerances of the 'user' and 'factory' margins, then the 'normal' reads have at least this much safety margin before they experience data loss.
The 'user' margin is a small delta to the normal read reference level. 'User' margin levels can be employed to check that flash memory contents have adequate margin for normal level read operations. If unexpected read results are encountered when checking flash memory contents at the 'user' margin levels, loss of information might soon occur during
'normal' readout.
The 'factory' margin is a bigger deviation from the norm, a more stringent read criteria that should only be attempted immediately (or very soon) after completion of an erase or program command, early in the cycling life. 'Factory' margin levels can be used to check that flash memory contents have adequate margin for long-term data retention at the normal level setting. If unexpected results are encountered when checking flash memory contents at 'factory' margin levels, the flash memory contents should be erased and reprogrammed.
CAUTION
Factory margin levels must only be used during verify of the initial factory programming.
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Chapter 27 Flash Memory Module (FTFA)
27.4.10 Flash Command Description
This section describes all flash commands that can be launched by a command write sequence.
The flash memory module sets the FSTAT[ACCERR] bit and aborts the command execution if any of the following illegal conditions occur:
• There is an unrecognized command code in the FCCOB FCMD field.
• There is an error in a FCCOB field for the specific commands. Refer to the error handling table provided for each command.
Ensure that FSTAT[ACCERR] and FSTAT[FPVIOL] are cleared prior to starting the command write sequence. As described in
Launch the Command by Clearing CCIF
, a new command cannot be launched while these error flags are set.
Do not attempt to read a flash block while the flash memory module is running a command (FSTAT[CCIF] = 0) on that same block. The flash memory module may return invalid data to the MCU with the collision error flag (FSTAT[RDCOLERR]) set.
CAUTION
Flash data must be in the erased state before being programmed. Cumulative programming of bits (adding more zeros) is not allowed.
27.4.10.1 Read 1s Section Command
The Read 1s Section command checks if a section of program flash memory is erased to the specified read margin level. The Read 1s Section command defines the starting address and the number of longwords to be verified.
Table 27-26. Read 1s Section Command FCCOB Requirements
FCCOB Number
5
6
3
4
0
1
2
FCCOB Contents [7:0]
0x01 (RD1SEC)
Flash address [23:16] of the first longword to be verified
Flash address [15:8] of the first longword to be verified
Flash address [7:0]
1 of the first longword to be verified
Number of longwords to be verified [15:8]
Number of longwords to be verified [7:0]
Read-1 Margin Choice
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1. Must be longword aligned (Flash address [1:0] = 00).
Upon clearing CCIF to launch the Read 1s Section command, the flash memory module
sets the read margin for 1s according to Table 27-27
and then reads all locations within the specified section of flash memory. If the flash memory module fails to read all 1s
(that is, the flash section is not erased), FSTAT[MGSTAT0] is set. FSTAT[CCIF] sets after the Read 1s Section operation completes.
Read Margin Choice
0x00
0x01
0x02
Table 27-27. Margin Level Choices for Read 1s Section
Margin Level Description
Use the 'normal' read level for 1s
Apply the 'User' margin to the normal read-1 level
Apply the 'Factory' margin to the normal read-1 level
Table 27-28. Read 1s Section Command Error Handling
Error condition
Command not available in current mode/security
An invalid margin code is supplied.
An invalid flash address is supplied.
Flash address is not longword aligned.
The requested section crosses a Flash block boundary.
The requested number of longwords is 0.
Read-1s fails.
Error bit
FSTAT[ACCERR]
FSTAT[ACCERR]
FSTAT[ACCERR]
FSTAT[ACCERR]
FSTAT[ACCERR]
FSTAT[ACCERR]
FSTAT[MGSTAT0]
27.4.10.2 Program Check Command
The Program Check command tests a previously programmed program flash longword to see if it reads correctly at the specified margin level.
FCCOB Number
0
1
2
8
9
3
4
A
B
Table 27-29. Program Check Command FCCOB Requirements
FCCOB Contents [7:0]
0x02 (PGMCHK)
Flash address [23:16]
Flash address [15:8]
Margin Choice
Byte 0 expected data
Byte 1 expected data
Byte 2 expected data
Byte 3 expected data
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1. Must be longword aligned (Flash address [1:0] = 00).
Upon clearing CCIF to launch the Program Check command, the flash memory module
sets the read margin for 1s according to Table 27-30
, reads the specified longword, and compares the actual read data to the expected data provided by the FCCOB. If the comparison at margin-1 fails, FSTAT[MGSTAT0] is set.
The flash memory module then sets the read margin for 0s, re-reads, and compares again.
If the comparison at margin-0 fails, FSTAT[MGSTAT0] is set. FSTAT[CCIF] is set after the Program Check operation completes.
The supplied address must be longword aligned (the lowest two bits of the byte address must be 00):
• Byte 3 data is written to the supplied byte address ('start'),
• Byte 2 data is programmed to byte address start+0b01,
• Byte 1 data is programmed to byte address start+0b10,
• Byte 0 data is programmed to byte address start+0b11.
NOTE
See the description of margin reads, Margin Read Commands
Table 27-30. Margin Level Choices for Program Check
Read Margin Choice
0x01
0x02
Margin Level Description
Read at 'User' margin-1 and 'User' margin-0
Read at 'Factory' margin-1 and 'Factory' margin-0
Table 27-31. Program Check Command Error Handling
Error Condition
Command not available in current mode/security
An invalid flash address is supplied
Flash address is not longword aligned
An invalid margin choice is supplied
Either of the margin reads does not match the expected data
Error Bit
FSTAT[ACCERR]
FSTAT[ACCERR]
FSTAT[ACCERR]
FSTAT[ACCERR]
FSTAT[MGSTAT0]
27.4.10.3 Read Resource Command
The Read Resource command allows the user to read data from special-purpose memory resources located within the flash memory module. The special-purpose memory resources available include program flash IFR space and the Version ID field. Each
resource is assigned a select code as shown in Table 27-33
.
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Functional Description
Table 27-32. Read Resource Command FCCOB Requirements
FCCOB Number
0
1
2
3
4
5
6
7
8
FCCOB Contents [7:0]
0x03 (RDRSRC)
Flash address [23:16]
Flash address [15:8]
Returned Values
Read Data [31:24]
Read Data [23:16]
Read Data [15:8]
Read Data [7:0]
User-provided values
Resource Select Code (see
1. Must be longword aligned (Flash address [1:0] = 00).
Table 27-33. Read Resource Select Codes
Resource
Select Code
0x00
0x01
Description
Program Flash 0 IFR
Version ID
Resource Size
256 Bytes
8 Bytes
Local Address Range
0x00_0000–0x00_00FF
0x00_0000–0x00_0007
1. Located in program flash 0 reserved space.
After clearing CCIF to launch the Read Resource command, four consecutive bytes are read from the selected resource at the provided relative address and stored in the FCCOB register. The CCIF flag sets after the Read Resource operation completes. The Read
Resource command exits with an access error if an invalid resource code is provided or if the address for the applicable area is out-of-range.
Table 27-34. Read Resource Command Error Handling
Error Condition
Command not available in current mode/security
An invalid resource code is entered
Flash address is out-of-range for the targeted resource.
Flash address is not longword aligned
Error Bit
FSTAT[ACCERR]
FSTAT[ACCERR]
FSTAT[ACCERR]
FSTAT[ACCERR]
27.4.10.4 Program Longword Command
The Program Longword command programs four previously-erased bytes in the program flash memory using an embedded algorithm.
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CAUTION
FCCOB Number
0
5
6
7
3
4
1
2
A flash memory location must be in the erased state before being programmed. Cumulative programming of bits (back-toback program operations without an intervening erase) within a flash memory location is not allowed. Re-programming of existing 0s to 0 is not allowed as this overstresses the device.
Table 27-35. Program Longword Command FCCOB Requirements
FCCOB Contents [7:0]
0x06 (PGM4)
Flash address [23:16]
Flash address [15:8]
Byte 0 program value
Byte 1 program value
Byte 2 program value
Byte 3 program value
1. Must be longword aligned (Flash address [1:0] = 00).
Upon clearing CCIF to launch the Program Longword command, the flash memory module programs the data bytes into the flash using the supplied address. The targeted flash locations must be currently unprotected (see the description of the FPROT registers) to permit execution of the Program Longword operation.
The programming operation is unidirectional. It can only move NVM bits from the erased state ('1') to the programmed state ('0'). Erased bits that fail to program to the '0' state are flagged as errors in FSTAT[MGSTAT0]. The CCIF flag is set after the Program
Longword operation completes.
The supplied address must be longword aligned (flash address [1:0] = 00):
• Byte 3 data is written to the supplied byte address ('start'),
• Byte 2 data is programmed to byte address start+0b01,
• Byte 1 data is programmed to byte address start+0b10, and
• Byte 0 data is programmed to byte address start+0b11.
Table 27-36. Program Longword Command Error Handling
Error Condition
Command not available in current mode/security
An invalid flash address is supplied
Flash address is not longword aligned
Flash address points to a protected area
Table continues on the next page...
Error Bit
FSTAT[ACCERR]
FSTAT[ACCERR]
FSTAT[ACCERR]
FSTAT[FPVIOL]
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Table 27-36. Program Longword Command Error Handling (continued)
Error Condition
Any errors have been encountered during the verify operation
Error Bit
FSTAT[MGSTAT0]
27.4.10.5 Erase Flash Sector Command
The Erase Flash Sector operation erases all addresses in a flash sector.
FCCOB Number
0
1
2
3
Table 27-37. Erase Flash Sector Command FCCOB Requirements
FCCOB Contents [7:0]
0x09 (ERSSCR)
Flash address [23:16] in the flash sector to be erased
Flash address [15:8] in the flash sector to be erased
Flash address [7:0] 1 in the flash sector to be erased
1. Must be longword aligned (flash address [1:0] = 00).
After clearing CCIF to launch the Erase Flash Sector command, the flash memory module erases the selected program flash sector and then verifies that it is erased. The
Erase Flash Sector command aborts if the selected sector is protected (see the description of the FPROT registers). If the erase-verify fails the FSTAT[MGSTAT0] bit is set. The
CCIF flag is set after the Erase Flash Sector operation completes. The Erase Flash Sector command is suspendable (see the FCNFG[ERSSUSP] bit and
Table 27-38. Erase Flash Sector Command Error Handling
Error Condition
Command not available in current mode/security
An invalid Flash address is supplied
Flash address is not longword aligned
The selected program flash sector is protected
Any errors have been encountered during the verify operation 1
Error Bit
FSTAT[ACCERR]
FSTAT[ACCERR]
FSTAT[ACCERR]
FSTAT[FPVIOL]
FSTAT[MGSTAT0]
1. User margin read may be run using the Read 1s Section command to verify all bits are erased.
27.4.10.5.1 Suspending an Erase Flash Sector Operation
To suspend an Erase Flash Sector operation set the FCNFG[ERSSUSP] bit (see Flash
Configuration Field Description
) when CCIF is clear and the CCOB command field holds the code for the Erase Flash Sector command. During the Erase Flash Sector operation
(see Erase Flash Sector Command
), the flash memory module samples the state of the
ERSSUSP bit at convenient points. If the flash memory module detects that the
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Chapter 27 Flash Memory Module (FTFA)
ERSSUSP bit is set, the Erase Flash Sector operation is suspended and the flash memory module sets CCIF. While ERSSUSP is set, all writes to flash registers are ignored except for writes to the FSTAT and FCNFG registers.
If an Erase Flash Sector operation effectively completes before the flash memory module detects that a suspend request has been made, the flash memory module clears the
ERSSUSP bit prior to setting CCIF. When an Erase Flash Sector operation has been successfully suspended, the flash memory module sets CCIF and leaves the ERSSUSP bit set. While CCIF is set, the ERSSUSP bit can only be cleared to prevent the withdrawal of a suspend request before the flash memory module has acknowledged it.
27.4.10.5.2 Resuming a Suspended Erase Flash Sector Operation
If the ERSSUSP bit is still set when CCIF is cleared to launch the next command, the previous Erase Flash Sector operation resumes. The flash memory module acknowledges the request to resume a suspended operation by clearing the ERSSUSP bit. A new suspend request can then be made by setting ERSSUSP. A single Erase Flash Sector operation can be suspended and resumed multiple times.
There is a minimum elapsed time limit between the request to resume the Erase Flash
Sector operation (CCIF is cleared) and the request to suspend the operation again
(ERSSUSP is set). This minimum time period is required to ensure that the Erase Flash
Sector operation will eventually complete. If the minimum period is continually violated, i.e. the suspend requests come repeatedly and too quickly, no forward progress is made by the Erase Flash Sector algorithm. The resume/suspend sequence runs indefinitely without completing the erase.
27.4.10.5.3 Aborting a Suspended Erase Flash Sector Operation
The user may choose to abort a suspended Erase Flash Sector operation by clearing the
ERSSUSP bit prior to clearing CCIF for the next command launch. When a suspended operation is aborted, the flash memory module starts the new command using the new
FCCOB contents.
Note
Aborting the erase leaves the bitcells in an indeterminate, partially-erased state. Data in this sector is not reliable until a new erase command fully completes.
The following figure shows how to suspend and resume the Erase Flash Sector operation.
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Functional Description
Command Initiation
Next Command
(Write FCCOB)
Yes
No
Enter with CCIF = 1
ERSSCR Command
(Write FCCOB)
Launch/Resume Command
(Clear CCIF)
CCIF = 1?
No
Interrupt?
Memory Controller
Command Processing
SUSPACK=1
No
Start
New
Resume
ERSSCR
Yes
Restore Erase Algo
Clear SUSPACK = 0
Execute
Yes
Request Suspend
(Set ERSSUSP)
DONE?
No
Yes
ERSSUSP=1?
No
No
CCIF = 1?
Yes
Save Erase Algo Clear ERSSUSP
Yes
Service Interrupt
(Read Flash)
ERSSCR
Completed
Yes
ERSSUSP=0?
ERSSCR Suspended No
Set SUSPACK = 1
ERSSCR Suspended
ERSSUSP=1
Set CCIF
ERSSCR Completed
ERSSUSP=0
Yes
Resume Erase?
No, Abort
Clear ERSSUSP
ERSSUSP: Bit in FCNFG register
SUSPACK: Internal Suspend Acknowledge
User Cmd Interrupt/Suspend
Figure 27-26. Suspend and Resume of Erase Flash Sector Operation
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Chapter 27 Flash Memory Module (FTFA)
27.4.10.6 Read 1s All Blocks Command
The Read 1s All Blocks command checks if the program flash blocks have been erased to the specified read margin level, if applicable, and releases security if the readout passes, i.e. all data reads as '1'.
Table 27-39. Read 1s All Blocks Command FCCOB Requirements
FCCOB Number
0
1
FCCOB Contents [7:0]
0x40 (RD1ALL)
Read-1 Margin Choice
After clearing CCIF to launch the Read 1s All Blocks command, the flash memory module :
• sets the read margin for 1s according to Table 27-40
,
• checks the contents of the program flash are in the erased state.
If the flash memory module confirms that these memory resources are erased, security is released by setting the FSEC[SEC] field to the unsecure state. The security byte in the
flash configuration field (see Flash Configuration Field Description ) remains unaffected
by the Read 1s All Blocks command. If the read fails, i.e. all memory resources are not in the fully erased state, the FSTAT[MGSTAT0] bit is set.
The CCIF flag sets after the Read 1s All Blocks operation has completed.
Table 27-40. Margin Level Choices for Read 1s All Blocks
Read Margin Choice
0x00
0x01
0x02
Margin Level Description
Use the 'normal' read level for 1s
Apply the 'User' margin to the normal read-1 level
Apply the 'Factory' margin to the normal read-1 level
Table 27-41. Read 1s All Blocks Command Error Handling
Error Condition
An invalid margin choice is specified
Read-1s fails
Error Bit
FSTAT[ACCERR]
FSTAT[MGSTAT0]
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Functional Description
27.4.10.7 Read Once Command
The Read Once command provides read access to a reserved 64-byte field located in the
program flash 0 IFR (see Program Flash IFR Map and Program Once Field
). Access to the Program Once field is via 16 records, each 4 bytes long. The Program Once field is programmed using the Program Once command described in
.
Table 27-42. Read Once Command FCCOB Requirements
FCCOB Number
0
1
2
3
6
7
4
5
FCCOB Contents [7:0]
0x41 (RDONCE)
Program Once record index (0x00 - 0x0F)
Not used
Returned Values
Not used
Program Once byte 0 value
Program Once byte 1 value
Program Once byte 2 value
Program Once byte 3 value
After clearing CCIF to launch the Read Once command, a 4-byte Program Once record is read from the program flash IFR and stored in the FCCOB register. The CCIF flag is set after the Read Once operation completes. Valid record index values for the Read Once command range from 0x00 to 0x0F. During execution of the Read Once command, any attempt to read addresses within the program flash block containing this 64-byte field returns invalid data. The Read Once command can be executed any number of times.
Table 27-43. Read Once Command Error Handling
Error Condition
Command not available in current mode/security
An invalid record index is supplied
Error Bit
FSTAT[ACCERR]
FSTAT[ACCERR]
27.4.10.8 Program Once Command
The Program Once command enables programming to a reserved 64-byte field in the
program flash 0 IFR (see Program Flash IFR Map and Program Once Field
). Access to the Program Once field is via 16 records, each 4 bytes long. The Program Once field can
be read using the Read Once command (see Read Once Command ) or using the Read
Resource command (see
Read Resource Command ). Each Program Once record can be
programmed only once since the program flash 0 IFR cannot be erased.
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FCCOB Number
0
1
4
5
2
3
6
7
Chapter 27 Flash Memory Module (FTFA)
Table 27-44. Program Once Command FCCOB Requirements
FCCOB Contents [7:0]
0x43 (PGMONCE)
Program Once record index (0x00 - 0x0F)
Not Used
Not Used
Program Once byte 0 value
Program Once byte 1 value
Program Once byte 2 value
Program Once byte 3 value
After clearing CCIF to launch the Program Once command, the flash memory module first verifies that the selected record is erased. If erased, then the selected record is programmed using the values provided. The Program Once command also verifies that the programmed values read back correctly. The CCIF flag is set after the Program Once operation has completed.
The reserved program flash 0 IFR location accessed by the Program Once command cannot be erased and any attempt to program one of these records when the existing value is not Fs (erased) is not allowed. Valid record index values for the Program Once command range from 0x00 to 0x0F. During execution of the Program Once command, any attempt to read addresses within the program flash block containing this 64-byte field returns invalid data.
Table 27-45. Program Once Command Error Handling
Error Condition
Command not available in current mode/security
An invalid record index is supplied
The requested record has already been programmed to a non-FFFF value 1
Any errors have been encountered during the verify operation
Error Bit
FSTAT[ACCERR]
FSTAT[ACCERR]
FSTAT[ACCERR]
FSTAT[MGSTAT0]
1. If a Program Once record is initially programmed to 0xFFFF_FFFF, the Program Once command is allowed to execute again on that same record.
27.4.10.9 Erase All Blocks Command
The Erase All Blocks operation erases all flash memory, verifies all memory contents, and releases MCU security.
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Functional Description
Table 27-46. Erase All Blocks Command FCCOB Requirements
FCCOB Number
0
FCCOB Contents [7:0]
0x44 (ERSALL)
After clearing CCIF to launch the Erase All Blocks command, the flash memory module erases all program flash memory, then verifies that all are erased.
If the flash memory module verifies that all flash memories were properly erased, security is released by setting the FSEC[SEC] field to the unsecure state. The Erase All
Blocks command aborts if any flash region is protected. The security byte and all other
contents of the flash configuration field (see Flash Configuration Field Description
) are erased by the Erase All Blocks command. If the erase-verify fails, the
FSTAT[MGSTAT0] bit is set. The CCIF flag is set after the Erase All Blocks operation completes.
Table 27-47. Erase All Blocks Command Error Handling
Error Condition
Command not available in current mode/security
Any region of the program flash memory is protected
Any errors have been encountered during the verify operation 1
Error Bit
FSTAT[ACCERR]
FSTAT[FPVIOL]
FSTAT[MGSTAT0]
1. User margin read may be run using the Read 1s All Blocks command to verify all bits are erased.
27.4.10.9.1 Triggering an Erase All External to the Flash Memory Module
The functionality of the Erase All BlocksErase All Blocks Unsecure command is also available in an uncommanded fashion outside of the flash memory. Refer to the device's
Chip Configuration details for information on this functionality.
Before invoking the external erase all function, the FSTAT[ACCERR and PVIOL] flags must be cleared and the FCCOB0 register must not contain 0x44. When invoked, the erase-all function erases all program flash memory regardless of the protection settings. If the post-erase verify passes, the routine then releases security by setting the FSEC[SEC] field register to the unsecure state. The security byte in the Flash Configuration Field is also programmed to the unsecure state. The status of the erase-all request is reflected in the FCNFG[ERSAREQ] bit. The FCNFG[ERSAREQ] bit is cleared once the operation completes and the normal FSTAT error reporting is available as described in
.
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Chapter 27 Flash Memory Module (FTFA)
27.4.10.10 Verify Backdoor Access Key Command
The Verify Backdoor Access Key command only executes if the mode and security conditions are satisfied (see
Flash Commands by Mode ). Execution of the Verify
Backdoor Access Key command is further qualified by the FSEC[KEYEN] bits. The
Verify Backdoor Access Key command releases security if user-supplied keys in the
FCCOB match those stored in the Backdoor Comparison Key bytes of the Flash
Configuration Field (see
Flash Configuration Field Description ). The column labelled
Flash Configuration Field offset address shows the location of the matching byte in the
Flash Configuration Field.
Table 27-48. Verify Backdoor Access Key Command FCCOB Requirements
FCCOB Number
0
9
A
7
8
1-3
4
5
6
B
FCCOB Contents [7:0]
0x45 (VFYKEY)
Not Used
Key Byte 0
Key Byte 1
Key Byte 2
Key Byte 3
Key Byte 4
Key Byte 5
Key Byte 6
Key Byte 7
Flash Configuration Field Offset Address
0x0_0000
0x0_0001
0x0_0002
0x0_0003
0x0_0004
0x0_0005
0x0_0006
0x0_0007
After clearing CCIF to launch the Verify Backdoor Access Key command, the flash memory module checks the FSEC[KEYEN] bits to verify that this command is enabled.
If not enabled, the flash memory module sets the FSTAT[ACCERR] bit and terminates.
If the command is enabled, the flash memory module compares the key provided in
FCCOB to the backdoor comparison key in the Flash Configuration Field. If the backdoor keys match, the FSEC[SEC] field is changed to the unsecure state and security is released. If the backdoor keys do not match, security is not released and all future attempts to execute the Verify Backdoor Access Key command are immediately aborted and the FSTAT[ACCERR] bit is (again) set to 1 until a reset of the flash memory module module occurs. If the entire 8-byte key is all zeros or all ones, the Verify Backdoor
Access Key command fails with an access error. The CCIF flag is set after the Verify
Backdoor Access Key operation completes.
Table 27-49. Verify Backdoor Access Key Command Error Handling
Error Condition
The supplied key is all-0s or all-Fs
An incorrect backdoor key is supplied
Error Bit
FSTAT[ACCERR]
FSTAT[ACCERR]
Table continues on the next page...
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Functional Description
Table 27-49. Verify Backdoor Access Key Command Error Handling (continued)
Error Condition
Backdoor key access has not been enabled (see the description of the FSEC register)
This command is launched and the backdoor key has mismatched since the last power down reset
Error Bit
FSTAT[ACCERR]
FSTAT[ACCERR]
27.4.11 Security
The flash memory module provides security information to the MCU based on contents of the FSEC security register.
The MCU then limits access to flash memory resources as defined in the device's Chip
Configuration details. During reset, the flash memory module initializes the FSEC register using data read from the security byte of the Flash Configuration Field (see
Configuration Field Description
).
The following fields are available in the FSEC register. The settings are described in the
Flash Security Register (FTFA_FSEC)
details.
Flash security features are discussed further in AN4507: Using the Kinetis Security and
Flash Protection Features . Note that not all features described in the application note are available on this device.
FSEC field
KEYEN
MEEN
FSLACC
SEC
Table 27-50. FSEC register fields
Description
Backdoor Key Access
Mass Erase Capability
Freescale Factory Access
MCU security
27.4.11.1 Flash Memory Access by Mode and Security
The following table summarizes how access to the flash memory module is affected by security and operating mode.
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Operating Mode
NVM Normal
NVM Special
Chapter 27 Flash Memory Module (FTFA)
Table 27-51. Flash Memory Access Summary
Unsecure
Full command set
Chip Security State
Secure
Full command set
Only the Erase All BlocksErase All Blocks
Unsecure and Read 1s All Blocks commands.
27.4.11.2 Changing the Security State
The security state out of reset can be permanently changed by programming the security byte of the flash configuration field. This assumes that you are starting from a mode where the necessary program flash erase and program commands are available and that the region of the program flash containing the flash configuration field is unprotected. If the flash security byte is successfully programmed, its new value takes affect after the next chip reset.
27.4.11.2.1 Unsecuring the Chip Using Backdoor Key Access
The chip can be unsecured by using the backdoor key access feature, which requires knowledge of the contents of the 8-byte backdoor key value stored in the Flash
Configuration Field (see
Flash Configuration Field Description ). If the FSEC[KEYEN]
bits are in the enabled state, the Verify Backdoor Access Key command (see
) can be run; it allows the user to present prospective keys for comparison to the stored keys. If the keys match, the FSEC[SEC] bits are changed to unsecure the chip. The entire 8-byte key cannot be all 0s or all 1s; that is,
0000_0000_0000_0000h and FFFF_FFFF_FFFF_FFFFh are not accepted by the Verify
Backdoor Access Key command as valid comparison values. While the Verify Backdoor
Access Key command is active, program flash memory is not available for read access and returns invalid data.
The user code stored in the program flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports.
If the KEYEN bits are in the enabled state, the chip can be unsecured by the following backdoor key access sequence:
1. Follow the command sequence for the Verify Backdoor Access Key command as
explained in Verify Backdoor Access Key Command
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Functional Description
2. If the Verify Backdoor Access Key command is successful, the chip is unsecured and the FSEC[SEC] bits are forced to the unsecure state
An illegal key provided to the Verify Backdoor Access Key command prohibits further use of the Verify Backdoor Access Key command. A reset of the chip is the only method to re-enable the Verify Backdoor Access Key command when a comparison fails.
After the backdoor keys have been correctly matched, the chip is unsecured by changing the FSEC[SEC] bits. A successful execution of the Verify Backdoor Access Key command changes the security in the FSEC register only. It does not alter the security
byte or the keys stored in the Flash Configuration Field ( Flash Configuration Field
Description ). After the next reset of the chip, the security state of the flash memory
module reverts back to the flash security byte in the Flash Configuration Field. The
Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the program flash protection registers.
If the backdoor keys successfully match, the unsecured chip has full control of the contents of the Flash Configuration Field. The chip may erase the sector containing the
Flash Configuration Field and reprogram the flash security byte to the unsecure state and change the backdoor keys to any desired value.
27.4.12 Reset Sequence
On each system reset the flash memory module executes a sequence which establishes initial values for the flash block configuration parameters, FPROT, FOPT, and FSEC registers.
FSTAT[CCIF] is cleared throughout the reset sequence. The flash memory module holds off CPU access during the reset sequence. Flash reads are possible when the hold is removed. Completion of the reset sequence is marked by setting CCIF which enables flash user commands.
If a reset occurs while any flash command is in progress, that command is immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. Commands and operations do not automatically resume after exiting reset.
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Chapter 28
Analog-to-digital converter (ADC)
The 16-bit analog-to-digital converter (ADC) is a linear successive approximation ADC designed for operation within an integrated microcontroller system-on-chip.
28.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
The 16-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip.
NOTE
For the chip specific modes of operation, see the power management information of the device.
28.1.1 Features
Following are the features of the ADC module.
• Linear successive approximation algorithm with up to 16-bit resolution
• Up to four pairs of differential and 24 single-ended external analog inputs
• Output modes:
• differential 16-bit, 13-bit, 11-bit, and 9-bit modes
• single-ended 16-bit, 12-bit, 10-bit, and 8-bit modes
• Output format in 2's complement 16-bit sign extended for differential modes
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Introduction
• Output in right-justified unsigned format for single-ended
• Single or continuous conversion, that is, automatic return to idle after single conversion
• Configurable sample time and conversion speed/power
• Conversion complete/hardware average complete flag and interrupt
• Input clock selectable from up to four sources
• Operation in low-power modes for lower noise
• Asynchronous clock source for lower noise operation with option to output the clock
• Selectable hardware conversion trigger with hardware channel select
• Automatic compare with interrupt for less-than, greater-than or equal-to, within range, or out-of-range, programmable value
• Temperature sensor
• Hardware average function
• Selectable voltage reference: external or alternate
• Self-Calibration mode
28.1.2 Block diagram
The following figure is the ADC module block diagram.
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ADHWTSA
ADHWTSn
ADHWT
C o m p a re tru e 1
Interrupt
MCU STOP
DADP0
DADP3
AD4
AD23
TempP
DADM0
DADM3
TempM
V REFH
V
ALTH
V
REFL
V
ALTL
Conversion trigger control
Chapter 28 Analog-to-digital converter (ADC)
SC1A
SC1n
A D T R G
Control Registers (SC2, CFG1, CFG2)
A D A C K E N
Async
Clock Gen
Control sequencer
A D C K Clock divide
2
ADACK
Bus clock
ALTCLK
A D V IN P
A D V IN M
SAR converter
PG, MG
CLPx
C L M x
PG, MG
CLPx
CLMx
Offset subtractor
Averager
ADCOFS
AVGE, AVGS
OFS
Calibration
CAL
SC3
CALF
REFSH
Formatting
D tra n s fe r
M O D E
RA
REFSL
Compare logic
C V1
CV1:CV2
C V 2
A C F E
ACFGT, ACREN
Compare true
1
Figure 28-1. ADC block diagram
Rn
CFG1,2
SC2
28.2 ADC signal descriptions
The ADC module supports up to 4 pairs of differential inputs and up to 24 single-ended inputs.
Each differential pair requires two inputs, DADPx and DADMx. The ADC also requires four supply/reference/ground connections.
NOTE
Refer to ADC configuration section in chip configuration chapter for the number of channels supported on this device.
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ADC signal descriptions
Signal
DADP3–DADP0
DADM3–DADM0
AD n
V
REFSH
V
REFSL
V
DDA
V
SSA
Table 28-1. ADC signal descriptions
Description
Differential Analog Channel Inputs
Differential Analog Channel Inputs
Single-Ended Analog Channel Inputs
Voltage Reference Select High
Voltage Reference Select Low
Analog Power Supply
Analog Ground
I
I
I
I
I
I/O
I
I
28.2.1 Analog Power (V
DDA
)
The ADC analog portion uses V
DDA voltage potential as V
DD good results.
as its power connection. In some packages, V connected internally to V
DD
. If externally available, connect the V
DDA
DDA
is
pin to the same
. External filtering may be necessary to ensure clean V
DDA
for
28.2.2 Analog Ground (V
SSA
)
The ADC analog portion uses V
SSA
as its ground connection. In some packages, V connected internally to V voltage potential as V
SS
.
SS
. If externally available, connect the V
SSA
SSA
is
pin to the same
28.2.3 Voltage Reference Select
V
REFSH
and V
REFSL
are the high and low reference voltages for the ADC module.
The ADC can be configured to accept one of two voltage reference pairs for V
REFSH
V
REFSL
and
. Each pair contains a positive reference that must be between the minimum Ref
Voltage High and V
DDA
, and a ground reference that must be at the same potential as
V
SSA
. The two pairs are external (V
REFH
and V
REFL
) and alternate (V
ALTH
).
These voltage references are selected using SC2[REFSEL]. The alternate V
ALTH
V
ALTL
and V
ALTL
and
voltage reference pair may select additional external pins or internal sources depending on MCU configuration. See the chip configuration information on the Voltage
References specific to this MCU.
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Chapter 28 Analog-to-digital converter (ADC)
In some packages, V
REFH
is connected in the package to V
DDA
and V
REFL
to V
SSA
. If externally available, the positive reference(s) may be connected to the same potential as
V
DDA
or may be driven by an external source to a level between the minimum Ref
Voltage High and the V
DDA
potential. V
REFH
must never exceed V ground references to the same voltage potential as V
SSA
.
DDA
. Connect the
28.2.4 Analog Channel Inputs (ADx)
The ADC module supports up to 24 single-ended analog inputs. A single-ended input is selected for conversion through the SC1[ADCH] channel select bits when SC1n[DIFF] is low.
28.2.5 Differential Analog Channel Inputs (DADx)
The ADC module supports up to four differential analog channel inputs. Each differential analog input is a pair of external pins, DADPx and DADMx, referenced to each other to provide the most accurate analog to digital readings. A differential input is selected for conversion through SC1[ADCH] when SC1n[DIFF] is high. All DADPx inputs may be used as single-ended inputs if SC1n[DIFF] is low. In certain MCU configurations, some
DADMx inputs may also be used as single-ended inputs if SC1n[DIFF] is low. See the chip configuration chapter for ADC connections specific to this MCU.
28.3 Memory map and register definitions
This section describes the ADC registers.
ADC memory map
Absolute address
(hex)
Register name
4003_B000 ADC Status and Control Registers 1 (ADC0_SC1A)
4003_B004 ADC Status and Control Registers 1 (ADC0_SC1B)
4003_B008 ADC Configuration Register 1 (ADC0_CFG1)
4003_B00C ADC Configuration Register 2 (ADC0_CFG2)
4003_B010 ADC Data Result Register (ADC0_RA)
4003_B014 ADC Data Result Register (ADC0_RB)
4003_B018 Compare Value Registers (ADC0_CV1)
4003_B01C Compare Value Registers (ADC0_CV2)
Width
(in bits)
Table continues on the next page...
32
32
32
32
32
32
32
32
Access Reset value
R/W
R/W
R/W
R/W
R
R
R/W
R/W
0000_001Fh
0000_001Fh
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
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Memory map and register definitions
ADC memory map (continued)
Absolute address
(hex)
Register name
4003_B020 Status and Control Register 2 (ADC0_SC2)
4003_B024 Status and Control Register 3 (ADC0_SC3)
4003_B028 ADC Offset Correction Register (ADC0_OFS)
4003_B02C ADC Plus-Side Gain Register (ADC0_PG)
4003_B030 ADC Minus-Side Gain Register (ADC0_MG)
4003_B034
4003_B038
4003_B03C
4003_B040
ADC Plus-Side General Calibration Value Register
(ADC0_CLPD)
ADC Plus-Side General Calibration Value Register
(ADC0_CLPS)
ADC Plus-Side General Calibration Value Register
(ADC0_CLP4)
ADC Plus-Side General Calibration Value Register
(ADC0_CLP3)
4003_B044
4003_B048
4003_B04C
4003_B054
4003_B058
4003_B05C
4003_B060
4003_B064
4003_B068
4003_B06C
ADC Plus-Side General Calibration Value Register
(ADC0_CLP2)
ADC Plus-Side General Calibration Value Register
(ADC0_CLP1)
ADC Plus-Side General Calibration Value Register
(ADC0_CLP0)
ADC Minus-Side General Calibration Value Register
(ADC0_CLMD)
ADC Minus-Side General Calibration Value Register
(ADC0_CLMS)
ADC Minus-Side General Calibration Value Register
(ADC0_CLM4)
ADC Minus-Side General Calibration Value Register
(ADC0_CLM3)
ADC Minus-Side General Calibration Value Register
(ADC0_CLM2)
ADC Minus-Side General Calibration Value Register
(ADC0_CLM1)
ADC Minus-Side General Calibration Value Register
(ADC0_CLM0)
Width
(in bits)
Access Reset value
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
R/W
R/W
R/W
R/W
R/W
Section/ page
0000_0000h
0000_0000h
0000_0004h
0000_8200h
0000_8200h
R/W 0000_000Ah
R/W
R/W
R/W
R/W
R/W
R/W
0000_0020h
0000_0200h
0000_0100h
0000_0080h
0000_0040h
0000_0020h
R/W 0000_000Ah
R/W
R/W
R/W
R/W
R/W
R/W
0000_0020h
0000_0200h
0000_0100h
0000_0080h
0000_0040h
0000_0020h
28.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)
SC1A is used for both software and hardware trigger modes of operation.
To allow sequential conversions of the ADC to be triggered by internal peripherals, the
ADC can have more than one status and control register: one for each conversion. The
SC1B–SC1n registers indicate potentially multiple SC1 registers for use only in hardware
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Chapter 28 Analog-to-digital converter (ADC) trigger mode. See the chip configuration information about the number of SC1n registers specific to this device. The SC1n registers have identical fields, and are used in a "pingpong" approach to control ADC operation.
At any one point in time, only one of the SC1n registers is actively controlling ADC conversions. Updating SC1A while SC1n is actively controlling a conversion is allowed, and vice-versa for any of the SC1n registers specific to this MCU.
Writing SC1A while SC1A is actively controlling a conversion aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0, writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a value other than all 1s.
Writing any of the SC1n registers while that specific SC1n register is actively controlling a conversion aborts the current conversion. None of the SC1B-SC1n registers are used for software trigger operation and therefore writes to the SC1B–SC1n registers do not initiate a new conversion.
Address: 4003_B000h base + 0h offset + (4d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
Reset 0
Field
31–8
Reserved
7
COCO
0 0 0 0 0 0 0 0 0
ADCx_SC1n field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Conversion Complete Flag
0
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ADCx_SC1n field descriptions (continued)
Field Description
This is a read-only field that is set each time a conversion is completed when the compare function is disabled, or SC2[ACFE]=0 and the hardware average function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare result is true. When the hardware average function is enabled, or SC3[AVGE]=1, COCO is set upon completion of the selected number of conversions (determined by AVGS). COCO in SC1A is also set at the completion of a calibration sequence. COCO is cleared when the respective SC1n register is written or when the respective Rn register is read.
6
AIEN
5
DIFF
0 Conversion is not completed.
1 Conversion is completed.
Interrupt Enable
Enables conversion complete interrupts. When COCO becomes set while the respective AIEN is high, an interrupt is asserted.
0 Conversion complete interrupt is disabled.
1 Conversion complete interrupt is enabled.
Differential Mode Enable
4–0
ADCH
Configures the ADC to operate in differential mode. When enabled, this mode automatically selects from the differential channels, and changes the conversion algorithm and the number of cycles to complete a conversion.
0 Single-ended conversions and input channels are selected.
1 Differential conversions and input channels are selected.
Input channel select
Selects one of the input channels. The input channel decode depends on the value of DIFF. DAD0-DAD3 are associated with the input pin pairs DADPx and DADMx.
NOTE: Some of the input channel options in the bitfield-setting descriptions might not be available for your device. For the actual ADC channel assignments for your device, see the Chip Configuration details.
The successive approximation converter subsystem is turned off when the channel select bits are all set, that is, ADCH = 11111. This feature allows explicit disabling of the ADC and isolation of the input channel from all sources. Terminating continuous conversions this way prevents an additional single conversion from being performed. It is not necessary to set ADCH to all 1s to place the ADC in a low-power state when continuous conversions are not enabled because the module automatically enters a low-power state when a conversion completes.
00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
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Field
Chapter 28 Analog-to-digital converter (ADC)
ADCx_SC1n field descriptions (continued)
Description
01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
11000 Reserved.
11001 Reserved.
11010 When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor
(differential) is selected as input.
11011 When DIFF=0,Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.
11100 Reserved.
11101 When DIFF=0,V
REFSH
is selected as input; when DIFF=1, -V
REFSH input. Voltage reference selected is determined by SC2[REFSEL].
(differential) is selected as
11110 When DIFF=0,V
REFSL
is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
11111 Module is disabled.
28.3.2 ADC Configuration Register 1 (ADCx_CFG1)
The configuration Register 1 (CFG1) selects the mode of operation, clock source, clock divide, and configuration for low power or long sample time.
Address: 4003_B000h base + 8h offset = 4003_B008h
Bit 31 30 29 28 27 26 25
R
24
23 22 21 20 19 18 17 16
W
Reset
Bit
R
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Field
31–8
Reserved
7
ADLPC
ADCx_CFG1 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Low-Power Configuration
Controls the power configuration of the successive approximation converter. This optimizes power consumption when higher sample rates are not required.
6–5
ADIV
0 Normal power configuration.
1 Low-power configuration. The power is reduced at the expense of maximum clock speed.
Clock Divide Select
4
ADLSMP
3–2
MODE
Selects the divide ratio used by the ADC to generate the internal clock ADCK.
00 The divide ratio is 1 and the clock rate is input clock.
01 The divide ratio is 2 and the clock rate is (input clock)/2.
10 The divide ratio is 4 and the clock rate is (input clock)/4.
11 The divide ratio is 8 and the clock rate is (input clock)/8.
Sample Time Configuration
Selects between different sample times based on the conversion mode selected. This field adjusts the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs. Longer sample times can also be used to lower overall power consumption if continuous conversions are enabled and high conversion rates are not required. When
ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the extent of the long sample time.
0 Short sample time.
1 Long sample time.
Conversion mode selection
1–0
ADICLK
Selects the ADC resolution mode.
00 When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with
2's complement output.
01 When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output.
10 When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output
11 When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output
Input Clock Select
Selects the input clock source to generate the internal clock, ADCK. Note that when the ADACK clock source is selected, it is not required to be active prior to conversion start. When it is selected and it is not active prior to a conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at the start of a conversion and deactivated when conversions are terminated. In this case, there is an associated clock startup delay each time the clock source is re-activated.
00 Bus clock
01 Alternate clock 2 (ALTCLK2)
10 Alternate clock (ALTCLK)
11 Asynchronous clock (ADACK)
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Chapter 28 Analog-to-digital converter (ADC)
28.3.3 ADC Configuration Register 2 (ADCx_CFG2)
Configuration Register 2 (CFG2) selects the special high-speed configuration for very high speed conversions and selects the long sample time duration during long sample mode.
Address: 4003_B000h base + Ch offset = 4003_B00Ch
Bit 31 30 29 28 27 26 25
R
24
23 22 21 20 19 18 17 16
W
Reset
Bit
R
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
W
Reset 0
Field
31–8
Reserved
7–5
Reserved
4
MUXSEL
3
ADACKEN
2
ADHSC
0 0 0 0 0 0 0 0 0
ADCx_CFG2 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
ADC Mux Select
0 0 0 0 0 0
Changes the ADC mux setting to select between alternate sets of ADC channels.
0 ADxxa channels are selected.
1 ADxxb channels are selected.
Asynchronous Clock Output Enable
Enables the asynchronous clock source and the clock source output regardless of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the asynchronous clock may be used by other modules. See chip configuration information. Setting this field allows the clock to be used even while the
ADC is idle or operating from a different clock source. Also, latency of initiating a single or first-continuous conversion with the asynchronous clock selected is reduced because the ADACK clock is already operational.
0 Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.
1 Asynchronous clock and clock output is enabled regardless of the state of the ADC.
High-Speed Configuration
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ADCx_CFG2 field descriptions (continued)
Field Description
Configures the ADC for very high-speed operation. The conversion sequence is altered with 2 ADCK cycles added to the conversion time to allow higher speed conversion clocks.
1–0
ADLSTS
0 Normal conversion sequence selected.
1 High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
Long Sample Time Select
Selects between the extended sample times when long sample time is selected, that is, when
CFG1[ADLSMP]=1. This allows higher impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs. Longer sample times can also be used to lower overall power consumption when continuous conversions are enabled if high conversion rates are not required.
00 Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
01 12 extra ADCK cycles; 16 ADCK cycles total sample time.
10 6 extra ADCK cycles; 10 ADCK cycles total sample time.
11 2 extra ADCK cycles; 6 ADCK cycles total sample time.
28.3.4 ADC Data Result Register (ADCx_Rn)
The data result registers (Rn) contain the result of an ADC conversion of the channel selected by the corresponding status and channel control register (SC1A:SC1n). For every status and channel control register, there is a corresponding data result register.
Unused bits in R n are cleared in unsigned right-aligned modes and carry the sign bit
(MSB) in sign-extended 2's complement modes. For example, when configured for 10-bit single-ended mode, D[15:10] are cleared. When configured for 11-bit differential mode,
D[15:10] carry the sign bit, that is, bit 10 extended through bit 15.
The following table describes the behavior of the data result registers in the different modes of operation.
Table 28-43. Data result register description
Conversion mode
16-bit differential S
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D D D D D
16-bit singleended
13-bit differential S
12-bit singleended
D
0
11-bit differential S
D
S
0
S
D
S
0
S
D
S
0
S
D
D
D
S
D
D
D
S
Format
D D D D D D D D D D Signed 2's complement
D D D D D D D D D D Unsigned right justified
D D D D D D D D D D Sign-extended
2's complement
D D D D D D D D D D Unsigned rightjustified
D D D D D D D D D D Sign-extended
2's complement
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Chapter 28 Analog-to-digital converter (ADC)
Table 28-43. Data result register description (continued)
Conversion mode
8-bit singleended
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
10-bit singleended
0
9-bit differential S
0
0
S
0
0
S
0
0
S
0
0
S
0
0
S
0
D
S
D
S
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Format
Unsigned rightjustified
Sign-extended
2's complement
0 0 D D D D D D D D Unsigned rightjustified
NOTE
S: Sign bit or sign bit extension;
D: Data, which is 2's complement data if indicated
Address: 4003_B000h base + 10h offset + (4d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–16
Reserved
15–0
D
ADCx_Rn field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Data result
28.3.5 Compare Value Registers (ADCx_CVn)
The Compare Value Registers (CV1 and CV2) contain a compare value used to compare the conversion result when the compare function is enabled, that is, SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in different modes of operation for both bit position definition and value format using unsigned or sign-extended 2's complement. Therefore, the compare function uses only the CVn fields that are related to the ADC mode of operation.
The compare value 2 register (CV2) is used only when the compare range function is enabled, that is, SC2[ACREN]=1.
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Address: 4003_B000h base + 18h offset + (4d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–16
Reserved
15–0
CV
ADCx_CVn field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Compare Value.
28.3.6 Status and Control Register 2 (ADCx_SC2)
The status and control register 2 (SC2) contains the conversion active, hardware/software trigger select, compare function, and voltage reference select of the ADC module.
Address: 4003_B000h base + 20h offset = 4003_B020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Field
31–8
Reserved
7
ADACT
6
ADTRG
5
ACFE
4
ACFGT
3
ACREN
2
DMAEN
1–0
REFSEL
Chapter 28 Analog-to-digital converter (ADC)
ADCx_SC2 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Conversion Active
Indicates that a conversion or hardware averaging is in progress. ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted.
0 Conversion not in progress.
1 Conversion in progress.
Conversion Trigger Select
Selects the type of trigger used for initiating a conversion. Two types of trigger are selectable:
• Software trigger: When software trigger is selected, a conversion is initiated following a write to
SC1A.
• Hardware trigger: When hardware trigger is selected, a conversion is initiated following the assertion of the ADHWT input after a pulse of the ADHWTSn input.
0 Software trigger selected.
1 Hardware trigger selected.
Compare Function Enable
Enables the compare function.
0 Compare function disabled.
1 Compare function enabled.
Compare Function Greater Than Enable
Configures the compare function to check the conversion result relative to the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to have any effect.
0 Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.
1 Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.
Compare Function Range Enable
Configures the compare function to check if the conversion result of the input being monitored is either between or outside the range formed by CV1 and CV2 determined by the value of ACFGT. ACFE must be set for ACFGT to have any effect.
0 Range function disabled. Only CV1 is compared.
1 Range function enabled. Both CV1 and CV2 are compared.
DMA Enable
0 DMA is disabled.
1 DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.
Voltage Reference Selection
Selects the voltage reference source used for conversions.
00 Default voltage reference pin pair, that is, external pins V
REFH
and V
REFL
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ADCx_SC2 field descriptions (continued)
Field Description
01 Alternate reference pair, that is, V
ALTL
. This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU
ALTH
and V
10 Reserved
11 Reserved
28.3.7 Status and Control Register 3 (ADCx_SC3)
The Status and Control Register 3 (SC3) controls the calibration, continuous convert, and hardware averaging functions of the ADC module.
Address: 4003_B000h base + 24h offset = 4003_B024h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
Reset 0
Field
31–8
Reserved
0 0 0 0 0 0 0 0 0
ADCx_SC3 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
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0
492
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Field
7
CAL
6
CALF
5–4
Reserved
3
ADCO
2
AVGE
1–0
AVGS
Chapter 28 Analog-to-digital converter (ADC)
ADCx_SC3 field descriptions (continued)
Description
Calibration
Begins the calibration sequence when set. This field stays set while the calibration is in progress and is cleared when the calibration sequence is completed. CALF must be checked to determine the result of the calibration sequence. Once started, the calibration routine cannot be interrupted by writes to the ADC registers or the results will be invalid and CALF will set. Setting CAL will abort any current conversion.
Calibration Failed Flag
Displays the result of the calibration sequence. The calibration sequence will fail if SC2[ADTRG] = 1, any
ADC register is written, or any stop mode is entered before the calibration sequence completes. Writing 1 to CALF clears it.
0 Calibration completed normally.
1 Calibration failed. ADC accuracy specifications are not guaranteed.
This field is reserved.
This read-only field is reserved and always has the value 0.
Continuous Conversion Enable
Enables continuous conversions.
0 One conversion or one set of conversions if the hardware average function is enabled, that is,
AVGE=1, after initiating a conversion.
1 Continuous conversions or sets of conversions if the hardware average function is enabled, that is,
AVGE=1, after initiating a conversion.
Hardware Average Enable
Enables the hardware average function of the ADC.
0 Hardware average function disabled.
1 Hardware average function enabled.
Hardware Average Select
Determines how many ADC conversions will be averaged to create the ADC average result.
00 4 samples averaged.
01 8 samples averaged.
10 16 samples averaged.
11 32 samples averaged.
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28.3.8 ADC Offset Correction Register (ADCx_OFS)
The ADC Offset Correction Register (OFS) contains the user-selected or calibrationgenerated offset error correction value. This register is a 2’s complement, left-justified,
16-bit value . The value in OFS is subtracted from the conversion and the result is transferred into the result registers, Rn. If the result is greater than the maximum or less than the minimum result value, it is forced to the appropriate limit for the current mode of operation.
Address: 4003_B000h base + 28h offset = 4003_B028h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Field
31–16
Reserved
15–0
OFS
ADCx_OFS field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Offset Error Correction Value
28.3.9 ADC Plus-Side Gain Register (ADCx_PG)
The Plus-Side Gain Register (PG) contains the gain error correction for the plus-side input in differential mode or the overall conversion in single-ended mode. PG, a 16-bit real number in binary format, is the gain adjustment factor, with the radix point fixed between ADPG15 and ADPG14. This register must be written by the user with the value described in the calibration procedure. Otherwise, the gain error specifications may not be met.
Address: 4003_B000h base + 2Ch offset = 4003_B02Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
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Field
31–16
Reserved
15–0
PG
Chapter 28 Analog-to-digital converter (ADC)
ADCx_PG field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Plus-Side Gain
28.3.10 ADC Minus-Side Gain Register (ADCx_MG)
The Minus-Side Gain Register (MG) contains the gain error correction for the minus-side input in differential mode. This register is ignored in single-ended mode. MG, a 16-bit real number in binary format, is the gain adjustment factor, with the radix point fixed between ADMG15 and ADMG14. This register must be written by the user with the value described in the calibration procedure. Otherwise, the gain error specifications may not be met.
Address: 4003_B000h base + 30h offset = 4003_B030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Field
31–16
Reserved
15–0
MG
ADCx_MG field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Minus-Side Gain
28.3.11 ADC Plus-Side General Calibration Value Register
(ADCx_CLPD)
The Plus-Side General Calibration Value Registers (CLPx) contain calibration information that is generated by the calibration function. These registers contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0], CLP2[7:0], CLP3[8:0],
CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set when the selfcalibration sequence is done, that is, CAL is cleared. If these registers are written by the user after calibration, the linearity error specifications may not be met.
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Address: 4003_B000h base + 34h offset = 4003_B034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
Field
31–6
Reserved
5–0
CLPD
ADCx_CLPD field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Calibration Value
28.3.12 ADC Plus-Side General Calibration Value Register
(ADCx_CLPS)
For more information, see CLPD register description.
Address: 4003_B000h base + 38h offset = 4003_B038h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
Field
31–6
Reserved
5–0
CLPS
ADCx_CLPS field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Calibration Value
28.3.13 ADC Plus-Side General Calibration Value Register
(ADCx_CLP4)
For more information, see CLPD register description.
Address: 4003_B000h base + 3Ch offset = 4003_B03Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
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Field
31–10
Reserved
9–0
CLP4
Chapter 28 Analog-to-digital converter (ADC)
ADCx_CLP4 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Calibration Value
28.3.14 ADC Plus-Side General Calibration Value Register
(ADCx_CLP3)
For more information, see CLPD register description.
Address: 4003_B000h base + 40h offset = 4003_B040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Field
31–9
Reserved
8–0
CLP3
ADCx_CLP3 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Calibration Value
28.3.15 ADC Plus-Side General Calibration Value Register
(ADCx_CLP2)
For more information, see CLPD register description.
Address: 4003_B000h base + 44h offset = 4003_B044h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Field
31–8
Reserved
7–0
CLP2
ADCx_CLP2 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Calibration Value
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28.3.16 ADC Plus-Side General Calibration Value Register
(ADCx_CLP1)
For more information, see CLPD register description.
Address: 4003_B000h base + 48h offset = 4003_B048h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Field
31–7
Reserved
6–0
CLP1
ADCx_CLP1 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Calibration Value
28.3.17 ADC Plus-Side General Calibration Value Register
(ADCx_CLP0)
For more information, see CLPD register description.
Address: 4003_B000h base + 4Ch offset = 4003_B04Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
Field
31–6
Reserved
5–0
CLP0
ADCx_CLP0 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Calibration Value
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28.3.18 ADC Minus-Side General Calibration Value Register
(ADCx_CLMD)
The Minus-Side General Calibration Value (CLMx) registers contain calibration information that is generated by the calibration function. These registers contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0], CLM2[7:0], CLM3[8:0],
CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically set when the selfcalibration sequence is done, that is, CAL is cleared. If these registers are written by the user after calibration, the linearity error specifications may not be met.
Address: 4003_B000h base + 54h offset = 4003_B054h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
Field
31–6
Reserved
5–0
CLMD
ADCx_CLMD field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Calibration Value
28.3.19 ADC Minus-Side General Calibration Value Register
(ADCx_CLMS)
For more information, see CLMD register description.
Address: 4003_B000h base + 58h offset = 4003_B058h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
Field
31–6
Reserved
5–0
CLMS
ADCx_CLMS field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Calibration Value
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28.3.20 ADC Minus-Side General Calibration Value Register
(ADCx_CLM4)
For more information, see CLMD register description.
Address: 4003_B000h base + 5Ch offset = 4003_B05Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Field
31–10
Reserved
9–0
CLM4
ADCx_CLM4 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Calibration Value
28.3.21 ADC Minus-Side General Calibration Value Register
(ADCx_CLM3)
For more information, see CLMD register description.
Address: 4003_B000h base + 60h offset = 4003_B060h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Field
31–9
Reserved
8–0
CLM3
ADCx_CLM3 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Calibration Value
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28.3.22 ADC Minus-Side General Calibration Value Register
(ADCx_CLM2)
For more information, see CLMD register description.
Address: 4003_B000h base + 64h offset = 4003_B064h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Field
31–8
Reserved
7–0
CLM2
ADCx_CLM2 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Calibration Value
28.3.23 ADC Minus-Side General Calibration Value Register
(ADCx_CLM1)
For more information, see CLMD register description.
Address: 4003_B000h base + 68h offset = 4003_B068h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Field
31–7
Reserved
6–0
CLM1
ADCx_CLM1 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Calibration Value
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Functional description
28.3.24 ADC Minus-Side General Calibration Value Register
(ADCx_CLM0)
For more information, see CLMD register description.
Address: 4003_B000h base + 6Ch offset = 4003_B06Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
Field
31–6
Reserved
5–0
CLM0
ADCx_CLM0 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Calibration Value
28.4 Functional description
The ADC module is disabled during reset, in Low-Power Stop mode, or when
SC1n[ADCH] are all high; see the power management information for details. The module is idle when a conversion has completed and another conversion has not been initiated. When it is idle and the asynchronous clock output enable is disabled, or
CFG2[ADACKEN]= 0, the module is in its lowest power state. The ADC can perform an analog-to-digital conversion on any of the software selectable channels. All modes perform conversion by a successive approximation algorithm.
To meet accuracy specifications, the ADC module must be calibrated using the on-chip calibration function.
See
for details on how to perform calibration.
When the conversion is completed, the result is placed in the Rn data registers. The respective SC1n[COCO] is then set and an interrupt is generated if the respective conversion complete interrupt has been enabled, or, when SC1n[AIEN]=1.
The ADC module has the capability of automatically comparing the result of a conversion with the contents of the CV1 and CV2 registers. The compare function is enabled by setting SC2[ACFE] and operates in any of the conversion modes and configurations.
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The ADC module has the capability of automatically averaging the result of multiple conversions. The hardware average function is enabled by setting SC3[AVGE] and operates in any of the conversion modes and configurations.
NOTE
For the chip specific modes of operation, see the power management information of this MCU.
28.4.1 Clock select and divide control
One of four clock sources can be selected as the clock source for the ADC module.
This clock source is then divided by a configurable value to generate the input clock
ADCK, to the module. The clock is selected from one of the following sources by means of CFG1[ADICLK].
• Bus clock. This is the default selection following reset.
• Bus clock divided by two. For higher bus clock rates, this allows a maximum divideby-16 of the bus clock using CFG1[ADIV].
• ALTCLK: As defined for this MCU. See the chip configuration information.
Conversions are possible using ALTCLK as the input clock source while the MCU is in Normal Stop mode.
• Asynchronous clock (ADACK): This clock is generated from a clock source within the ADC module. When the ADACK clock source is selected, it is not required to be active prior to conversion start. When it is selected and it is not active prior to a conversion start CFG2[ADACKEN]=0, ADACK is activated at the start of a conversion and deactivated when conversions are terminated. In this case, there is an associated clock startup delay each time the clock source is re-activated. To avoid the conversion time variability and latency associated with the ADACK clock startup, set
CFG2[ADACKEN]=1 and wait the worst-case startup time of 5 µs prior to initiating any conversions using the ADACK clock source. Conversions are possible using
ADACK as the input clock source while the MCU is in Normal Stop mode. See
for more information.
Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the available clocks are too slow, the ADC may not perform according to specifications. If the available clocks are too fast, the clock must be divided to the appropriate frequency. This divider is specified by CFG1[ADIV] and can be divide-by 1,
2, 4, or 8.
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Functional description
28.4.2 Voltage reference selection
The ADC can be configured to accept one of the two voltage reference pairs as the reference voltage (V
REFSH
and V
REFSL
) used for conversions.
Each pair contains a positive reference that must be between the minimum Ref Voltage
High and V
DDA
, and a ground reference that must be at the same potential as V
SSA two pairs are external (V
REFH
and V
REFL
) and alternate (V
ALTH
and V voltage references are selected using SC2[REFSEL]. The alternate (V
ALTL
ALTH
). These
. The
and V
ALTL
) voltage reference pair may select additional external pins or internal sources depending on MCU configuration. See the chip configuration information on the voltage references specific to this MCU.
28.4.3 Hardware trigger and channel selects
The ADC module has a selectable asynchronous hardware conversion trigger, ADHWT, that is enabled when SC2[ADTRG] is set and a hardware trigger select event,
ADHWTSn, has occurred.
This source is not available on all MCUs. See the Chip Configuration chapter for information on the ADHWT source and the ADHWTSn configurations specific to this
MCU.
When an ADHWT source is available and hardware trigger is enabled, that is
SC2[ADTRG]=1, a conversion is initiated on the rising-edge of ADHWT after a hardware trigger select event, that is, ADHWTSn, has occurred. If a conversion is in progress when a rising-edge of a trigger occurs, the rising-edge is ignored. In continuous convert configuration, only the initial rising-edge to launch continuous conversions is observed, and until conversion is aborted, the ADC continues to do conversions on the same SCn register that initiated the conversion. The hardware trigger function operates in conjunction with any of the conversion modes and configurations.
The hardware trigger select event, ADHWTSn, must be set prior to the receipt of the
ADHWT signal. If these conditions are not met, the converter may ignore the trigger or use the incorrect configuration. If a hardware trigger select event is asserted during a conversion, it must stay asserted until the end of current conversion and remain set until the receipt of the ADHWT signal to trigger a new conversion. The channel and status fields selected for the conversion depend on the active trigger select signal:
• ADHWTSA active selects SC1A.
• ADHWTSn active selects SC1n.
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Note
Asserting more than one hardware trigger select signal
(ADHWTSn) at the same time results in unknown results. To avoid this, select only one hardware trigger select signal
(ADHWTSn) prior to the next intended conversion.
When the conversion is completed, the result is placed in the Rn registers associated with the ADHWTSn received. For example:
• ADHWTSA active selects RA register
• ADHWTSn active selects Rn register
The conversion complete flag associated with the ADHWTSn received, that is,
SC1n[COCO], is then set and an interrupt is generated if the respective conversion complete interrupt has been enabled, that is, SC1[AIEN]=1.
28.4.4 Conversion control
Conversions can be performed as determined by CFG1[MODE] and SC1n[DIFF] as shown in the description of CFG1[MODE].
Conversions can be initiated by a software or hardware trigger.
In addition, the ADC module can be configured for:
• Low-power operation
• Long sample time
• Continuous conversion
• Hardware average
• Automatic compare of the conversion result to a software determined compare value
28.4.4.1 Initiating conversions
A conversion is initiated:
• Following a write to SC1A, with SC1n[ADCH] not all 1's, if software triggered operation is selected, that is, when SC2[ADTRG]=0.
• Following a hardware trigger, or ADHWT event, if hardware triggered operation is selected, that is, SC2[ADTRG]=1, and a hardware trigger select event, ADHWTSn, has occurred. The channel and status fields selected depend on the active trigger select signal:
• ADHWTSA active selects SC1A.
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• ADHWTSn active selects SC1n.
• if neither is active, the off condition is selected
Note
Selecting more than one ADHWTSn prior to a conversion completion will result in unknown results. To avoid this, select only one ADHWTSn prior to a conversion completion.
• Following the transfer of the result to the data registers when continuous conversion is enabled, that is, when SC3[ADCO] = 1.
If continuous conversions are enabled, a new conversion is automatically initiated after the completion of the current conversion. In software triggered operation, that is, when
SC2[ADTRG] = 0, continuous conversions begin after SC1A is written and continue until aborted. In hardware triggered operation, that is, when SC2[ADTRG] = 1 and one
ADHWTSn event has occurred, continuous conversions begin after a hardware trigger event and continue until aborted.
If hardware averaging is enabled, a new conversion is automatically initiated after the completion of the current conversion until the correct number of conversions are completed. In software triggered operation, conversions begin after SC1A is written. In hardware triggered operation, conversions begin after a hardware trigger. If continuous conversions are also enabled, a new set of conversions to be averaged are initiated following the last of the selected number of conversions.
28.4.4.2 Completing conversions
A conversion is completed when the result of the conversion is transferred into the data result registers, Rn. If the compare functions are disabled, this is indicated by setting of
SC1n[COCO]. If hardware averaging is enabled, the respective SC1n[COCO] sets only if the last of the selected number of conversions is completed. If the compare function is enabled, the respective SC1n[COCO] sets and conversion result data is transferred only if the compare condition is true. If both hardware averaging and compare functions are enabled, then the respective SC1n[COCO] sets only if the last of the selected number of conversions is completed and the compare condition is true. An interrupt is generated if the respective SC1n[AIEN] is high at the time that the respective SC1n[COCO] is set.
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28.4.4.3 Aborting conversions
Any conversion in progress is aborted when:
• Writing to SC1A while it is actively controlling a conversion, aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0, a write to SC1A initiates a new conversion if SC1A[ADCH] is equal to a value other than all 1s.
Writing to any of the SC1B–SC1n registers while that specific SC1B–SC1n register is actively controlling a conversion aborts the current conversion. The SC1(B-n) registers are not used for software trigger operation and therefore writes to the
SC1(B-n) registers do not initiate a new conversion.
• A write to any ADC register besides the SC1A-SC1n registers occurs. This indicates that a change in mode of operation has occurred and the current conversion is therefore invalid.
• The MCU is reset or enters Low-Power Stop modes.
• The MCU enters Normal Stop mode with ADACK not enabled.
When a conversion is aborted, the contents of the data registers, Rn, are not altered. The data registers continue to be the values transferred after the completion of the last successful conversion. If the conversion was aborted by a reset or Low-Power Stop modes, RA and Rn return to their reset states.
28.4.4.4 Power control
The ADC module remains in its idle state until a conversion is initiated. If ADACK is selected as the conversion clock source, but the asynchronous clock output is disabled, that is CFG2[ADACKEN]=0, the ADACK clock generator also remains in its idle state
(disabled) until a conversion is initiated. If the asynchronous clock output is enabled, that is, CFG2[ADACKEN]=1, it remains active regardless of the state of the ADC or the
MCU power mode.
Power consumption when the ADC is active can be reduced by setting CFG1[ADLPC].
This results in a lower maximum value for f
ADCK
.
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Functional description
28.4.4.5 Sample time and total conversion time
For short sample, that is, when CFG1[ADLSMP]=0, there is a 2-cycle adder for first conversion over the base sample time of four ADCK cycles. For high-speed conversions, that is, when CFG2[ADHSC]=1, there is an additional 2-cycle adder on any conversion.
The table below summarizes sample times for the possible ADC configurations.
CFG1[ADLSMP]
0
1
1
0
1
1
1
1
1
1
ADC configuration
CFG2[ADLSTS]
X
00
01
10
11
X
00
01
10
11
CFG2[ADHSC]
0
0
0
1
1
0
0
1
1
1
Sample time (ADCK cycles)
First or Single
6
Subsequent
4
24
16
10
6
8 6
26
18
12
8
The total conversion time depends upon:
• The sample time as determined by CFG1[ADLSMP] and CFG2[ADLSTS]
• The MCU bus frequency
• The conversion mode, as determined by CFG1[MODE] and SC1n[DIFF]
• The high-speed configuration, that is, CFG2[ADHSC]
• The frequency of the conversion clock, that is, f
ADCK
.
CFG2[ADHSC] is used to configure a higher clock input frequency. This will allow faster overall conversion times. To meet internal ADC timing requirements,
CFG2[ADHSC] adds additional ADCK cycles. Conversions with CFG2[ADHSC]=1 take two more ADCK cycles. CFG2[ADHSC] must be used when the ADCLK exceeds the limit for CFG2[ADHSC]=0.
After the module becomes active, sampling of the input begins.
1. CFG1[ADLSMP] and CFG2[ADLSTS] select between sample times based on the conversion mode that is selected.
2. When sampling is completed, the converter is isolated from the input channel and a successive approximation algorithm is applied to determine the digital value of the analog signal.
3. The result of the conversion is transferred to Rn upon completion of the conversion algorithm.
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If the bus frequency is less than f
ADCK
, precise sample time for continuous conversions cannot be guaranteed when short sample is enabled, that is, when CFG1[ADLSMP]=0.
The maximum total conversion time is determined by the clock source chosen and the divide ratio selected. The clock source is selectable by CFG1[ADICLK], and the divide ratio is specified by CFG1[ADIV].
The maximum total conversion time for all configurations is summarized in the equation below. See the following tables for the variables referenced in the equation.
CFG1[AD
LSMP]
1
0
1
1
0
0
Figure 28-62. Conversion time equation
Table 28-70. Single or first continuous time adder (SFCAdder)
CFG2[AD
ACKEN]
0 x x
1
1
0
CFG1[ADICLK]
0x, 10
11
11
0x, 10
11
11
Single or first continuous time adder (SFCAdder)
3 ADCK cycles + 5 bus clock cycles
3 ADCK cycles + 5 bus clock cycles 1
5 μs + 3 ADCK cycles + 5 bus clock cycles
5 ADCK cycles + 5 bus clock cycles
5 ADCK cycles + 5 bus clock cycles 1
5 μs + 5 ADCK cycles + 5 bus clock cycles
1. To achieve this time, CFG2[ADACKEN] must be 1 for at least 5 μs prior to the conversion is initiated.
SC3[AVGE]
0
1
1
1
1
Table 28-71. Average number factor (AverageNum)
SC3[AVGS] xx
00
01
10
11
Average number factor (AverageNum)
1
4
8
16
32
Mode
8b single-ended
9b differential
10b single-ended
11b differential
12b single-ended
13b differential
Table 28-72. Base conversion time (BCT)
Base conversion time (BCT)
17 ADCK cycles
27 ADCK cycles
20 ADCK cycles
30 ADCK cycles
20 ADCK cycles
30 ADCK cycles
Table continues on the next page...
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Functional description
Table 28-72. Base conversion time (BCT) (continued)
Mode
16b single-ended
16b differential
Base conversion time (BCT)
25 ADCK cycles
34 ADCK cycles
CFG1[ADLSMP]
1
1
0
1
1
Table 28-73. Long sample time adder (LSTAdder)
CFG2[ADLSTS] xx
00
01
10
11
Long sample time adder
(LSTAdder)
0 ADCK cycles
20 ADCK cycles
12 ADCK cycles
6 ADCK cycles
2 ADCK cycles
Table 28-74. High-speed conversion time adder (HSCAdder)
CFG2[ADHSC]
0
1
High-speed conversion time adder (HSCAdder)
0 ADCK cycles
2 ADCK cycles
Note f
The ADCK frequency must be between f
ADCK
ADCK
maximum to meet ADC specifications.
minimum and
28.4.4.6 Conversion time examples
The following examples use the
Figure 28-62 , and the information provided in Table
28.4.4.6.1 Typical conversion time configuration
A typical configuration for ADC conversion is:
• 10-bit mode, with the bus clock selected as the input clock source
• The input clock divide-by-1 ratio selected
• Bus frequency of 8 MHz
• Long sample time disabled
• High-speed conversion disabled
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The conversion time for a single conversion is calculated by using the
the information provided in
Table 28-74 . The table below lists the
variables of
Table 28-75. Typical conversion time
Variable
SFCAdder
AverageNum
BCT
LSTAdder
HSCAdder
Time
5 ADCK cycles + 5 bus clock cycles
1
20 ADCK cycles
0
0
The resulting conversion time is generated using the parameters listed in the preceding table. Therefore, for a bus clock and an ADCK frequency equal to 8 MHz, the resulting conversion time is 3.75 µs.
28.4.4.6.2 Long conversion time configuration
A configuration for long ADC conversion is:
• 16-bit differential mode with the bus clock selected as the input clock source
• The input clock divide-by-8 ratio selected
• Bus frequency of 8 MHz
• Long sample time enabled
• Configured for longest adder
• High-speed conversion disabled
• Average enabled for 32 conversions
The conversion time for this conversion is calculated by using the Figure 28-62
, and the information provided in
Table 28-74 . The following table lists the
variables of the
Table 28-76. Typical conversion time
Variable
SFCAdder
AverageNum
BCT
LSTAdder
HSCAdder
Time
3 ADCK cycles + 5 bus clock cycles
32
34 ADCK cycles
20 ADCK cycles
0
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Functional description
The resulting conversion time is generated using the parameters listed in the preceding table. Therefore, for bus clock equal to 8 MHz and ADCK equal to 1 MHz, the resulting conversion time is 57.625 µs, that is, AverageNum. This results in a total conversion time of 1.844 ms.
28.4.4.6.3 Short conversion time configuration
A configuration for short ADC conversion is:
• 8-bit Single-Ended mode with the bus clock selected as the input clock source
• The input clock divide-by-1 ratio selected
• Bus frequency of 20 MHz
• Long sample time disabled
• High-speed conversion enabled
The conversion time for this conversion is calculated by using the Figure 28-62
, and the information provided in
Table 28-74 . The table below lists the
variables of
Table 28-77. Typical conversion time
Variable
SFCAdder
AverageNum
BCT
LSTAdder
HSCAdder
Time
5 ADCK cycles + 5 bus clock cycles
1
17 ADCK cycles
0 ADCK cycles
2
The resulting conversion time is generated using the parameters listed in in the preceding table. Therefore, for bus clock and ADCK frequency equal to 20 MHz, the resulting conversion time is 1.45 µs.
28.4.4.7 Hardware average function
The hardware average function can be enabled by setting SC3[AVGE]=1 to perform a hardware average of multiple conversions. The number of conversions is determined by the AVGS[1:0] bits, which can select 4, 8, 16, or 32 conversions to be averaged. While the hardware average function is in progress, SC2[ADACT] will be set.
After the selected input is sampled and converted, the result is placed in an accumulator from which an average is calculated once the selected number of conversions have been completed. When hardware averaging is selected, the completion of a single conversion will not set SC1n[COCO].
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If the compare function is either disabled or evaluates true, after the selected number of conversions are completed, the average conversion result is transferred into the data result registers, Rn, and SC1n[COCO] is set. An ADC interrupt is generated upon the setting of SC1n[COCO] if the respective ADC interrupt is enabled, that is,
SC1n[AIEN]=1.
Note
The hardware average function can perform conversions on a channel while the MCU is in Wait or Normal Stop modes. The
ADC interrupt wakes the MCU when the hardware average is completed if SC1n[AIEN] is set.
28.4.5 Automatic compare function
The compare function can be configured to check whether the result is less than or greater-than-or-equal-to a single compare value, or, if the result falls within or outside a range determined by two compare values.
The compare mode is determined by SC2[ACFGT], SC2[ACREN], and the values in the compare value registers, CV1 and CV2. After the input is sampled and converted, the compare values in CV1 and CV2 are used as described in the following table. There are six Compare modes as shown in the following table.
Table 28-78. Compare modes
SC2[AC
FGT]
0
SC2[AC
REN]
0
ADCCV1 relative to
ADCCV2
—
Function
Less than threshold
Compare mode description
1
0
0
1
1
0
1
1
1
1
—
Less than or equal
Outside range, not inclusive
Greater than Inside range, not inclusive
Less than or equal
Greater than or equal to threshold
Inside range, inclusive
Greater than Outside range, inclusive
Compare true if the result is less than the
CV1 registers.
Compare true if the result is greater than or equal to CV1 registers.
Compare true if the result is less than CV1
Or the result is greater than CV2.
Compare true if the result is less than CV1
And the result is greater than CV2.
Compare true if the result is greater than or equal to CV1 And the result is less than or equal to CV2.
Compare true if the result is greater than or equal to CV1 Or the result is less than or equal to CV2.
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Functional description
With SC2[ACREN] =1, and if the value of CV1 is less than or equal to the value of CV2, then setting SC2[ACFGT] will select a trigger-if-inside-compare-range inclusive-ofendpoints function. Clearing SC2[ACFGT] will select a trigger-if-outside-comparerange, not-inclusive-of-endpoints function.
If CV1 is greater than CV2, setting SC2[ACFGT] will select a trigger-if-outsidecompare-range, inclusive-of-endpoints function. Clearing SC2[ACFGT] will select a trigger-if-inside-compare-range, not-inclusive-of-endpoints function.
If the condition selected evaluates true, SC1n[COCO] is set.
Upon completion of a conversion while the compare function is enabled, if the compare condition is not true, SC1n[COCO] is not set and the conversion result data will not be transferred to the result register, Rn. If the hardware averaging function is enabled, the compare function compares the averaged result to the compare values. The same compare function definitions apply. An ADC interrupt is generated when SC1n[COCO] is set and the respective ADC interrupt is enabled, that is, SC1n[AIEN]=1.
Note
The compare function can monitor the voltage on a channel while the MCU is in Wait or Normal Stop modes. The ADC interrupt wakes the MCU when the compare condition is met.
28.4.6 Calibration function
>The ADC contains a self-calibration function that is required to achieve the specified accuracy.
Calibration must be run, or valid calibration values written, after any reset and before a conversion is initiated. The calibration function sets the offset calibration value, the minus-side calibration values, and the plus-side calibration values. The offset calibration value is automatically stored in the ADC offset correction register (OFS), and the plusside and minus-side calibration values are automatically stored in the ADC plus-side and minus-side calibration registers, CLPx and CLMx. The user must configure the ADC correctly prior to calibration, and must generate the plus-side and minus-side gain calibration results and store them in the ADC plus-side gain register (PG) after the calibration function completes.
Prior to calibration, the user must configure the ADC's clock source and frequency, low power configuration, voltage reference selection, sample time, and high speed configuration according to the application's clock source availability and needs. If the
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Chapter 28 Analog-to-digital converter (ADC) application uses the ADC in a wide variety of configurations, the configuration for which the highest accuracy is required should be selected, or multiple calibrations can be done for the different configurations. For best calibration results:
• Set hardware averaging to maximum, that is, SC3[AVGE]=1 and SC3[AVGS]=11 for an average of 32
• Set ADC clock frequency f
ADCK
less than or equal to 4 MHz
• V
REFH
=V
DDA
• Calibrate at nominal voltage and temperature
The input channel, conversion mode continuous function, compare function, resolution mode, and differential/single-ended mode are all ignored during the calibration function.
To initiate calibration, the user sets SC3[CAL] and the calibration will automatically begin if the SC2[ADTRG] is 0. If SC2[ADTRG] is 1, SC3[CAL] will not get set and
SC3[CALF] will be set. While calibration is active, no ADC register can be written and no stop mode may be entered, or the calibration routine will be aborted causing
SC3[CAL] to clear and SC3[CALF] to set. At the end of a calibration sequence,
SC1n[COCO] will be set. SC1n[AIEN] can be used to allow an interrupt to occur at the end of a calibration sequence. At the end of the calibration routine, if SC3[CALF] is not set, the automatic calibration routine is completed successfully.
To complete calibration, the user must generate the gain calibration values using the following procedure:
1. Initialize or clear a 16-bit variable in RAM.
2. Add the plus-side calibration results CLP0, CLP1, CLP2, CLP3, CLP4, and CLPS to the variable.
3. Divide the variable by two.
4. Set the MSB of the variable.
5. The previous two steps can be achieved by setting the carry bit, rotating to the right through the carry bit on the high byte and again on the low byte.
6. Store the value in the plus-side gain calibration register PG.
7. Repeat the procedure for the minus-side gain calibration value.
When calibration is complete, the user may reconfigure and use the ADC as desired. A second calibration may also be performed, if desired, by clearing and again setting
SC3[CAL].
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Overall, the calibration routine may take as many as 14k ADCK cycles and 100 bus cycles, depending on the results and the clock source chosen. For an 8 MHz clock source, this length amounts to about 1.7 ms. To reduce this latency, the calibration values, which are offset, plus-side and minus-side gain, and plus-side and minus-side calibration values, may be stored in flash memory after an initial calibration and recovered prior to the first
ADC conversion. This method can reduce the calibration latency to 20 register store operations on all subsequent power, reset, or Low-Power Stop mode recoveries.
Further information on the calibration procedure can be found in the Calibration section of AN3949: ADC16 Calibration Procedure and Programmable Delay Block
Synchronization .
28.4.7 User-defined offset function
OFS contains the user-selected or calibration-generated offset error correction value.
This register is a 2’s complement, left-justified. The value in OFS is subtracted from the conversion and the result is transferred into the result registers, Rn. If the result is greater than the maximum or less than the minimum result value, it is forced to the appropriate limit for the current mode of operation.
The formatting of the OFS is different from the data result register, Rn, to preserve the resolution of the calibration value regardless of the conversion mode selected. Lower order bits are ignored in lower resolution modes. For example, in 8-bit single-ended mode, OFS[14:7] are subtracted from D[7:0]; OFS[15] indicates the sign (negative numbers are effectively added to the result) and OFS[6:0] are ignored. The same bits are used in 9-bit differential mode because OFS[15] indicates the sign bit, which maps to
D[8]. For 16-bit differential mode, OFS[15:0] are directly subtracted from the conversion result data D[15:0]. In 16-bit single-ended mode, there is no field in the OFS corresponding to the least significant result D[0], so odd values, such as -1 or +1, cannot be subtracted from the result.
OFS is automatically set according to calibration requirements once the self-calibration sequence is done, that is, SC3[CAL] is cleared. The user may write to OFS to override the calibration result if desired. If the OFS is written by the user to a value that is different from the calibration value, the ADC error specifications may not be met. Storing the value generated by the calibration function in memory before overwriting with a userspecified value is recommended.
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Note
There is an effective limit to the values of offset that can be set by the user. If the magnitude of the offset is too high, the results of the conversions will cap off at the limits.
The offset calibration function may be employed by the user to remove application offsets or DC bias values. OFS may be written with a number in 2's complement format and this offset will be subtracted from the result, or hardware averaged value. To add an offset, store the negative offset in 2's complement format and the effect will be an addition. An offset correction that results in an out-of-range value will be forced to the minimum or maximum value. The minimum value for single-ended conversions is
0x0000; for a differential conversion it is 0x8000.
To preserve accuracy, the calibrated offset value initially stored in OFS must be added to the user-defined offset. For applications that may change the offset repeatedly during operation, store the initial offset calibration value in flash so it can be recovered and added to any user offset adjustment value and the sum stored in OFS.
28.4.8 Temperature sensor
The ADC module includes a temperature sensor whose output is connected to one of the
ADC analog channel inputs.
The following equation provides an approximate transfer function of the temperature sensor.
m
Figure 28-63. Approximate transfer function of the temperature sensor where:
• V
TEMP
is the voltage of the temperature sensor channel at the ambient temperature.
• V
TEMP25
is the voltage of the temperature sensor channel at 25 °C.
• m is referred as temperature sensor slope in the device data sheet. It is the hot or cold voltage versus temperature slope in V/°C.
For temperature calculations, use the V
TEMP25 the ADC Electricals table.
and temperature sensor slope values from
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Functional description
In application code, the user reads the temperature sensor channel, calculates V
TEMP compares to V
TEMP25
. If V
TEMP
is greater than V the preceding equation. If V
TEMP
is less than V
TEMP25
TEMP25
, and
the cold slope value is applied in
, the hot slope value is applied in the preceding equation. ADC Electricals table may only specify one temperature sensor slope value. In that case, the user could use the same slope for the calculation across the operational temperature range.
For more information on using the temperature sensor, see the application note titled
Temperature Sensor for the HCS08 Microcontroller Family (document AN3031).
28.4.9 MCU wait mode operation
>Wait mode is a lower-power consumption Standby mode from which recovery is fast because the clock sources remain active.
If a conversion is in progress when the MCU enters Wait mode, it continues until completion. Conversions can be initiated while the MCU is in Wait mode by means of the hardware trigger or if continuous conversions are enabled.
The bus clock, bus clock divided by two, and ADACK are available as conversion clock sources while in Wait mode. The use of ALTCLK as the conversion clock source in Wait is dependent on the definition of ALTCLK for this MCU. See the Chip Configuration information on ALTCLK specific to this MCU.
If the compare and hardware averaging functions are disabled, a conversion complete event sets SC1n[COCO] and generates an ADC interrupt to wake the MCU from Wait mode if the respective ADC interrupt is enabled, that is, when SC1n[AIEN]=1. If the hardware averaging function is enabled, SC1n[COCO] will set, and generate an interrupt if enabled, when the selected number of conversions are completed. If the compare function is enabled, SC1n[COCO] will set, and generate an interrupt if enabled, only if the compare conditions are met. If a single conversion is selected and the compare trigger is not met, the ADC will return to its idle state and cannot wake the MCU from Wait mode unless a new conversion is initiated by the hardware trigger.
28.4.10 MCU Normal Stop mode operation
Stop mode is a low-power consumption Standby mode during which most or all clock sources on the MCU are disabled.
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28.4.10.1 Normal Stop mode with ADACK disabled
If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a stop instruction aborts the current conversion and places the ADC in its Idle state. The contents of the ADC registers, including Rn, are unaffected by Normal Stop mode. After exiting from Normal Stop mode, a software or hardware trigger is required to resume conversions.
28.4.10.2 Normal Stop mode with ADACK enabled
If ADACK is selected as the conversion clock, the ADC continues operation during
Normal Stop mode. See the chip configuration chapter for configuration information for this MCU.
If a conversion is in progress when the MCU enters Normal Stop mode, it continues until completion. Conversions can be initiated while the MCU is in Normal Stop mode by means of the hardware trigger or if continuous conversions are enabled.
If the compare and hardware averaging functions are disabled, a conversion complete event sets SC1n[COCO] and generates an ADC interrupt to wake the MCU from Normal
Stop mode if the respective ADC interrupt is enabled, that is, when SC1n[AIEN]=1. The result register, Rn, will contain the data from the first completed conversion that occurred during Normal Stop mode. If the hardware averaging function is enabled, SC1n[COCO] will set, and generate an interrupt if enabled, when the selected number of conversions are completed. If the compare function is enabled, SC1n[COCO] will set, and generate an interrupt if enabled, only if the compare conditions are met. If a single conversion is selected and the compare is not true, the ADC will return to its Idle state and cannot wake the MCU from Normal Stop mode unless a new conversion is initiated by another hardware trigger.
28.4.11 MCU Low-Power Stop mode operation
The ADC module is automatically disabled when the MCU enters Low-Power Stop mode.
All module registers contain their reset values following exit from Low-Power Stop mode. Therefore, the module must be re-enabled and re-configured following exit from
Low-Power Stop mode.
NOTE
For the chip specific modes of operation, see the power management information for the device.
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Initialization information
28.5 Initialization information
This section gives an example that provides some basic direction on how to initialize and configure the ADC module.
The user can configure the module for 16-bit, 12-bit, 10-bit, or 8-bit single-ended resolution or 16-bit, 13-bit, 11-bit, or 9-bit differential resolution, single or continuous conversion, and a polled or interrupt approach, among many other options. For
information used in this example, refer to Table 28-73 , Table 28-74
.
Note
Hexadecimal values are designated by a preceding 0x, binary values designated by a preceding %, and decimal values have no preceding character.
28.5.1 ADC module initialization example
28.5.1.1 Initialization sequence
Before the ADC module can be used to complete conversions, an initialization procedure must be performed. A typical sequence is:
1. Calibrate the ADC by following the calibration instructions in
.
2. Update CFG to select the input clock source and the divide ratio used to generate
ADCK. This register is also used for selecting sample time and low-power configuration.
3. Update SC2 to select the conversion trigger, hardware or software, and compare function options, if enabled.
4. Update SC3 to select whether conversions will be continuous or completed only once
(ADCO) and whether to perform hardware averaging.
5. Update SC1:SC1n registers to select whether conversions will be single-ended or differential and to enable or disable conversion complete interrupts. Also, select the input channel which can be used to perform conversions.
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28.5.1.2 Pseudo-code example
In this example, the ADC module is set up with interrupts enabled to perform a single 10bit conversion at low-power with a long sample time on input channel 1, where ADCK is derived from the bus clock divided by 1.
CFG1 = 0x98 (%10011000)
Bit 7 ADLPC 1 Configures for low power, lowers maximum clock speed.
Bit 6:5 ADIV 00 Sets the ADCK to the input clock ÷ 1.
Bit 4 ADLSMP 1 Configures for long sample time.
Bit 3:2 MODE 10 Selects the single-ended 10-bit conversion, differential 11bit conversion.
Bit 1:0 ADICLK 00 Selects the bus clock.
SC2 = 0x00 (%00000000)
Bit 7 ADACT 0 Flag indicates if a conversion is in progress.
Bit 6 ADTRG 0 Software trigger selected.
Bit 5 ACFE 0 Compare function disabled.
Bit 4 ACFGT 0 Not used in this example.
Bit 3 ACREN 0 Compare range disabled.
Bit 2 DMAEN 0 DMA request disabled.
Bit 1:0 REFSEL 00 Selects default voltage reference pin pair (External pins V
REFH and V
REFL
).
SC1A = 0x41 (%01000001)
Bit 7 COCO 0 Read-only flag which is set when a conversion completes.
Bit 6 AIEN 1 Conversion complete interrupt enabled.
Bit 5 DIFF 0 Single-ended conversion selected.
Bit 4:0 ADCH 00001 Input channel 1 selected as ADC input channel.
RA = 0xxx
Holds results of conversion.
CV = 0xxx
Holds compare value when compare function enabled.
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Application information
Reset
Initialize ADC
CFG1 = 0x98
SC2 = 0x00
SC1n = 0x41
Check
SC1n[COCO]=1?
No
Yes
Read Rn to clear
SC1n[COCO]
Continue
Figure 28-64. Initialization flowchart example
28.6 Application information
The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an ADC.
For guidance on selecting optimum external component values and converter parameters see AN4373: Cookbook for SAR ADC Measurements .
28.6.1 External pins and routing
28.6.1.1 Analog supply pins
Depending on the device, the analog power and ground supplies, V
DDA
ADC module are available as:
and V
SSA
, of the
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Chapter 28 Analog-to-digital converter (ADC)
• V
DDA
and V
SSA
V
DDA
and V
SSA
available as separate pins—When available on a separate pin, both
must be connected to the same voltage potential as their corresponding MCU digital supply, V
DD
and V
SS
, and must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package.
• V
SSA
• V
SSA
is shared on the same pin as the MCU digital V
SS
and V
DDA
.
are shared with the MCU digital supply pins—In these cases, there are separate pads for the analog supplies bonded to the same pin as the corresponding digital supply so that some degree of isolation between the supplies is maintained.
If separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the V
SSA between these supplies, if possible. V
SSA
pin. This must be the only ground connection
makes a good single point ground location.
28.6.1.2 Analog voltage reference pins
In addition to the analog supplies, the ADC module has connections for two reference voltage inputs used by the converter:
• V
REFSH
• V
REFSL
is the high reference voltage for the converter.
is the low reference voltage for the converter.
The ADC can be configured to accept one of two voltage reference pairs for V
REFSH
V
REFSL
. Each pair contains a positive reference and a ground reference. The two pairs are external, V
REFH
and V
REFL
and alternate, V
ALTH
and V
ALTL selected using SC2[REFSEL]. The alternate voltage reference pair, V
ALTH
and
. These voltage references are
and V
ALTL
, may select additional external pins or internal sources based on MCU configuration. See the chip configuration information on the voltage references specific to this MCU.
In some packages, the external or alternate pairs are connected in the package to V
DDA and V
SSA as V
DDA as V
SSA
, respectively. One of these positive references may be shared on the same pin
on some devices. One of these ground references may be shared on the same pin
on some devices.
If externally available, the positive reference may be connected to the same potential as
V
DDA
or may be driven by an external source to a level between the minimum Ref
Voltage High and the V
DDA
potential. The positive reference must never exceed V externally available, the ground reference must be connected to the same voltage
DDA
. If potential as V
SSA
. The voltage reference pairs must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package.
AC current in the form of current spikes required to supply charge to the capacitor array at each successive approximation step is drawn through the V
REFH
and V
REFL
loop. The best external component to meet this current demand is a 0.1 μ F capacitor with good
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Application information high-frequency characteristics. This capacitor is connected between V
REFH
and V
REFL and must be placed as near as possible to the package pins. Resistance in the path is not recommended because the current causes a voltage drop that could result in conversion errors. Inductance in this path must be minimum, that is, parasitic only.
28.6.1.3 Analog input pins
The external analog inputs are typically shared with digital I/O pins on MCU devices.
Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise or when the source impedance is high. Use of 0.01 μ F capacitors with good high-frequency characteristics is sufficient. These capacitors are not necessary in all cases, but when used, they must be placed as near as possible to the package pins and be referenced to V
SSA
.
For proper conversion, the input voltage must fall between V
REFH is equal to or exceeds V
REFH
and V
REFL
. If the input
, the converter circuit converts the signal to 0xFFF, which is full scale 12-bit representation, 0x3FF, which is full scale 10-bit representation, or 0xFF, which is full scale 8-bit representation. If the input is equal to or less than V
REFL converter circuit converts it to 0x000. Input voltages between V
REFH
and V
REFL straight-line linear conversions. There is a brief current associated with V sampling capacitor is charging.
REFL
, the
are
when the
For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins must not be transitioning during conversions.
28.6.2 Sources of error
28.6.2.1 Sampling error
For proper conversions, the input must be sampled long enough to achieve the proper accuracy.
RAS + RADIN =SC / (FMAX * NUMTAU * CADIN)
Figure 28-65. Sampling equation
Where:
RAS = External analog source resistance
SC = Number of ADCK cycles used during sample window
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CADIN = Internal ADC input capacitance
NUMTAU = -ln(LSBERR / 2 N )
LSBERR = value of acceptable sampling error in LSBs
Chapter 28 Analog-to-digital converter (ADC)
N = 8 in 8-bit mode, 10 in 10-bit mode, 12 in 12-bit mode or 16 in 16-bit mode
Higher source resistances or higher-accuracy sampling is possible by setting
CFG1[ADLSMP] and changing CFG2[ADLSTS] to increase the sample window, or decreasing ADCK frequency to increase sample time.
28.6.2.2 Pin leakage error
Leakage on the I/O pins can cause conversion error if the external analog source resistance, R
AS
, is high. If this error cannot be tolerated by the application, keep R lower than V
REFH
/ (4 × I
LEAK
× 2 N
AS
) for less than 1/4 LSB leakage error, where N = 8 in
8-bit mode, 10 in 10-bit mode, 12 in 12-bit mode, or 16 in 16-bit mode.
28.6.2.3 Noise-induced errors
System noise that occurs during the sample or conversion process can affect the accuracy of the conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are met:
• There is a 0.1 μ F low-ESR capacitor from V
REFH
to V
REFL
.
• There is a 0.1 μ F low-ESR capacitor from V
DDA
to V
SSA
.
• If inductive isolation is used from the primary supply, an additional 1 μ F capacitor is placed from V
DDA
to V
SSA
.
• V
SSA plane.
, and V
REFL
, if connected, is connected to V
SS
at a quiet point in the ground
• Operate the MCU in Wait or Normal Stop mode before initiating (hardware-triggered conversions) or immediately after initiating (hardware- or software-triggered conversions) the ADC conversion.
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• For software triggered conversions, immediately follow the write to SC1 with a
Wait instruction or Stop instruction.
• For Normal Stop mode operation, select ADACK as the clock source. Operation in Normal Stop reduces V
DD stop recovery.
noise but increases effective conversion time due to
• There is no I/O switching, input or output, on the MCU during the conversion.
There are some situations where external system activity causes radiated or conducted noise emissions or excessive V
DD
noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in Wait or Normal Stop mode, or I/O activity cannot be halted, the following actions may reduce the effect of noise on the accuracy:
• Place a 0.01 μ F capacitor (C
AS
) on the selected input channel to V
REFL
or V
SSA
. This improves noise issues, but affects the sample rate based on the external analog source resistance.
• Average the result by converting the analog input many times in succession and dividing the sum of the results. Four samples are required to eliminate the effect of a
1 LSB, one-time error.
• Reduce the effect of synchronous noise by operating off the asynchronous clock, that is, ADACK, and averaging. Noise that is synchronous to ADCK cannot be averaged out.
28.6.2.4 Code width and quantization error
The ADC quantizes the ideal straight-line transfer function into 65536 steps in the 16-bit mode). Each step ideally has the same height, that is, 1 code, and width. The width is defined as the delta between the transition points to one code and the next. The ideal code width for an N-bit converter, where N can be 16, 12, 10, or 8, defined as 1 LSB, is:
LSB
Figure 28-66. Ideal code width for an N-bit converter
There is an inherent quantization error due to the digitization of the result. For 8-bit, 10bit, or 12-bit conversions, the code transitions when the voltage is at the midpoint between the points where the straight line transfer function is exactly represented by the actual transfer function. Therefore, the quantization error will be ± 1/2 LSB in 8-bit, 10bit, or 12-bit modes. As a consequence, however, the code width of the first (0x000) conversion is only 1/2 LSB and the code width of the last (0xFF or 0x3FF) is 1.5 LSB.
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Chapter 28 Analog-to-digital converter (ADC)
For 16-bit conversions, the code transitions only after the full code width is present, so the quantization error is -1 LSB to 0 LSB and the code width of each step is 1 LSB.
28.6.2.5 Linearity errors
The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these errors, but the system designers must be aware of these errors because they affect overall accuracy:
• Zero-scale error (E
ZS
), sometimes called offset: This error is defined as the difference between the actual code width of the first conversion and the ideal code width. This is 1/2 LSB in 8-bit, 10-bit, or 12-bit modes and 1 LSB in 16-bit mode. If the first conversion is 0x001, the difference between the actual 0x001 code width and its ideal
(1 LSB) is used.
• Full-scale error (E
FS
): This error is defined as the difference between the actual code width of the last conversion and the ideal code width. This is 1.5 LSB in 8-bit, 10-bit, or 12-bit modes and 1 LSB in 16-bit mode. If the last conversion is 0x3FE, the difference between the actual 0x3FE code width and its ideal (1 LSB) is used.
• Differential non-linearity (DNL): This error is defined as the worst-case difference between the actual code width and the ideal code width for all conversions.
• Integral non-linearity (INL): This error is defined as the highest-value or absolute value that the running sum of DNL achieves. More simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes.
• Total unadjusted error (TUE): This error is defined as the difference between the actual transfer function and the ideal straight-line transfer function and includes all forms of error.
28.6.2.6 Code jitter, non-monotonicity, and missing codes
Analog-to-digital converters are susceptible to three special forms of error:
• Code jitter: Code jitter is when, at certain points, a given input voltage converts to one of the two values when sampled repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the converter yields the lower code, and vice-versa. However, even small amounts of system noise can cause the converter to be indeterminate, between two codes, for a range of input voltages around the transition voltage.
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Application information
This error may be reduced by repeatedly sampling the input and averaging the result.
Additionally, the techniques discussed in
Noise-induced errors reduces this error.
• Non-monotonicity: Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage.
• Missing codes: Missing codes are those values never converted for any input value.
In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes.
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Chapter 29
Comparator (CMP)
The Comparator module (CMP) provides a circuit for comparing two analog input voltages. The comparator circuit is designed to operate across the full supply voltage range (rail-to-rail operation) and supports programmable hysteresis control. The output of the comparator can be samples, windowed, or digitally filtered.
29.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
The comparator (CMP) module provides a circuit for comparing two analog input voltages. The comparator circuit is designed to operate across the full range of the supply voltage, known as rail-to-rail operation.
The Analog MUX (ANMUX) provides a circuit for selecting an analog input signal from eight channels. One signal is provided by the 6-bit digital-to-analog converter (DAC).
The mux circuit is designed to operate across the full range of the supply voltage.
The 6-bit DAC is 64-tap resistor ladder network which provides a selectable voltage reference for applications where voltage reference is needed. The 64-tap resistor ladder network divides the supply reference V in
into 64 voltage levels. A 6-bit digital signal input selects the output voltage level, which varies from V in from two voltage sources, V in1
and V in2
to V in
/64. V as an on-chip internal signal only and is not available externally to a pin.
in
can be selected
. The 6-bit DAC from a comparator is available
29.1.1 CMP features
The CMP has the following features:
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Introduction
• Operational over the entire supply range
• Inputs may range from rail to rail
• Programmable hysteresis control
• Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of the comparator output
• Selectable inversion on comparator output
• Capability to produce a wide range of outputs such as:
• Sampled
• Windowed, which is ideal for certain PWM zero-crossing-detection applications
• Digitally filtered:
• Filter can be bypassed
• Can be clocked via external SAMPLE signal or scaled bus clock
• External hysteresis can be used at the same time that the output filter is used for internal functions
• Two software selectable performance levels:
• Shorter propagation delay at the expense of higher power
• Low power, with longer propagation delay
• DMA transfer support
• A comparison event can be selected to trigger a DMA transfer
• Functional in all modes of operation
• The window and filter functions are not available in the following modes:
• Stop
• VLPS
• LLS
• VLLSx
29.1.2 6-bit DAC key features
• 6-bit resolution
• Selectable supply reference source
• Power Down mode to conserve power when not in use
• Option to route the output to internal comparator input
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Chapter 29 Comparator (CMP)
29.1.3 ANMUX key features
• Two 8-to-1 channel mux
• Operational over the entire supply range
29.1.4 CMP, DAC and ANMUX diagram
The following figure shows the block diagram for the High-Speed Comparator, DAC, and ANMUX modules.
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VRSEL
V in1
V in2
MUX
VOSEL[5:0]
DACEN
DAC output
DAC
Reference Input 0
Reference Input 1
Reference Input 2
Reference Input 3
Reference Input 4
Reference Input 5
Reference Input 6
PSEL[2:0]
ANMUX
INP
INM
CMP
CMP
Sample input
Window and filter control
IRQ
CMPO
MSEL[2:0]
Figure 29-1. CMP, DAC and ANMUX block diagram
29.1.5 CMP block diagram
The following figure shows the block diagram for the CMP module.
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Chapter 29 Comparator (CMP)
EN,PMODE,HYSCTRL[1:0]
FILT_PER
COS INV
Internal bus
WE FILTER_CNT SE
OPE
COUT IER/F CFR/F
INP
+
-
CMPO
Polarity select
Window control
Filter block
Interrupt control
IRQ
INM
WINDOW/SAMPLE 1
COUT
To other SOC functions
0 bus clock
FILT_PER
Clock prescaler divided bus clock
0
CGMUX
SE
COUTA
1 CMPO to
PAD
COS
Figure 29-2. Comparator module block diagram
In the CMP block diagram:
• The Window Control block is bypassed when CR1[WE] = 0
• If CR1[WE] = 1, the comparator output will be sampled on every bus clock when
WINDOW=1 to generate COUTA. Sampling does NOT occur when WINDOW = 0.
• The Filter block is bypassed when not in use.
• The Filter block acts as a simple sampler if the filter is bypassed and
CR0[FILTER_CNT] is set to 0x01.
• The Filter block filters based on multiple samples when the filter is bypassed and
CR0[FILTER_CNT] is set greater than 0x01.
• If CR1[SE] = 1, the external SAMPLE input is used as sampling clock
• IF CR1[SE] = 0, the divided bus clock is used as sampling clock
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• If enabled, the Filter block will incur up to one bus clock additional latency penalty on COUT due to the fact that COUT, which is crossing clock domain boundaries, must be resynchronized to the bus clock.
• CR1[WE] and CR1[SE] are mutually exclusive.
29.2 Memory map/register definitions
CMP memory map
Absolute address
(hex)
Register name
4007_3000 CMP Control Register 0 (CMP0_CR0)
4007_3001 CMP Control Register 1 (CMP0_CR1)
4007_3002 CMP Filter Period Register (CMP0_FPR)
4007_3003 CMP Status and Control Register (CMP0_SCR)
4007_3004 DAC Control Register (CMP0_DACCR)
4007_3005 MUX Control Register (CMP0_MUXCR)
Width
(in bits)
Access Reset value
8
8
8
8
8
8
R/W
R/W
R/W
R/W
R/W
R/W
00h
00h
00h
00h
00h
00h
Section/ page
29.2.1 CMP Control Register 0 (CMPx_CR0)
Address: 4007_3000h base + 0h offset = 4007_3000h
Bit
Read
Write
Reset
7
0
6
0
5
0
Field
7
Reserved
6–4
FILTER_CNT
4 3
0 0
CMPx_CR0 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Filter Sample Count
2
0
1
0
0
0
Represents the number of consecutive samples that must agree prior to the comparator ouput filter accepting a new output state. For information regarding filter programming and latency, see the
.
000 Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
001 One sample must agree. The comparator output is simply sampled.
010 2 consecutive samples must agree.
011 3 consecutive samples must agree.
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Field
3
Reserved
2
Reserved
1–0
HYSTCTR
Chapter 29 Comparator (CMP)
CMPx_CR0 field descriptions (continued)
Description
100 4 consecutive samples must agree.
101 5 consecutive samples must agree.
110 6 consecutive samples must agree.
111 7 consecutive samples must agree.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
Comparator hard block hysteresis control
Defines the programmable hysteresis level. The hysteresis values associated with each level are devicespecific. See the Data Sheet of the device for the exact values.
00 Level 0
01 Level 1
10 Level 2
11 Level 3
29.2.2 CMP Control Register 1 (CMPx_CR1)
Address: 4007_3000h base + 1h offset = 4007_3001h
Bit
Read
Write
Reset
7
0
6
0
5
0
4
0
3
0
CMPx_CR1 field descriptions
Description Field
7
SE
Sample Enable
2
0
1
0
0
0
At any given time, either SE or WE can be set. It is mandatory request to not set SE and WE both at a given time.
6
WE
0 Sampling mode is not selected.
1 Sampling mode is selected.
Windowing Enable
At any given time, either SE or WE can be set. It is mandatory request to not set SE and WE both at a given time.
5
TRIGM
0 Windowing mode is not selected.
1 Windowing mode is selected.
Trigger Mode Enable
CMP and DAC are configured to CMP Trigger mode when CMP_CR1[TRIGM] is set to 1. In addition, the
CMP should be enabled. If the DAC is to be used as a reference to the CMP, it should also be enabled.
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Memory map/register definitions
CMPx_CR1 field descriptions (continued)
Field Description
CMP Trigger mode depends on an external timer resource to periodically enable the CMP and 6-bit DAC in order to generate a triggered compare.
Upon setting TRIGM, the CMP and DAC are placed in a standby state until an external timer resource trigger is received.
See the chip configuration chapter for details about the external timer resource.
4
PMODE
0 Trigger mode is disabled.
1 Trigger mode is enabled.
Power Mode Select
See the electrical specifications table in the device Data Sheet for details.
3
INV
2
COS
1
OPE
0
EN
0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
Comparator INVERT
Allows selection of the polarity of the analog comparator function. It is also driven to the COUT output, on both the device pin and as SCR[COUT], when OPE=0.
0 Does not invert the comparator output.
1 Inverts the comparator output.
Comparator Output Select
0 Set the filtered comparator output (CMPO) to equal COUT.
1 Set the unfiltered comparator output (CMPO) to equal COUTA.
Comparator Output Pin Enable
0 CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
1
CMPO is available on the associated CMPO output pin.
The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.
Comparator Module Enable
Enables the Analog Comparator module. When the module is not enabled, it remains in the off state, and consumes no power. When the user selects the same input from analog mux to the positive and negative port, the comparator is disabled automatically.
0 Analog Comparator is disabled.
1 Analog Comparator is enabled.
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Chapter 29 Comparator (CMP)
29.2.3 CMP Filter Period Register (CMPx_FPR)
Address: 4007_3000h base + 2h offset = 4007_3002h
Bit
Read
Write
Reset
Field
7–0
FILT_PER
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
CMPx_FPR field descriptions
Description
Filter Sample Period
Specifies the sampling period, in bus clock cycles, of the comparator output filter, when CR1[SE]=0.
Setting FILT_PER to 0x0 disables the filter. Filter programming and latency details appear in the
.
This field has no effect when CR1[SE]=1. In that case, the external SAMPLE signal is used to determine the sampling period.
29.2.4 CMP Status and Control Register (CMPx_SCR)
Address: 4007_3000h base + 3h offset = 4007_3003h
Bit
Read
Write
Reset
7
6
5
Field
7
Reserved
6
DMAEN
4
3
0 0 0 0 0
CMPx_SCR field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
DMA Enable Control
2
0
1
0
0
Enables the DMA transfer triggered from the CMP module. When this field is set, a DMA request is asserted when CFR or CFF is set.
0
5
Reserved
4
IER
0 DMA is disabled.
1 DMA is enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
Comparator Interrupt Enable Rising
Enables the CFR interrupt from the CMP. When this field is set, an interrupt will be asserted when CFR is set.
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CMPx_SCR field descriptions (continued)
Field Description
3
IEF
0 Interrupt is disabled.
1 Interrupt is enabled.
Comparator Interrupt Enable Falling
Enables the CFF interrupt from the CMP. When this field is set, an interrupt will be asserted when CFF is set.
2
CFR
1
CFF
0
COUT
0 Interrupt is disabled.
1 Interrupt is enabled.
Analog Comparator Flag Rising
Detects a rising-edge on COUT, when set, during normal operation. CFR is cleared by writing 1 to it.
During Stop modes, CFR is level sensitive .
0 Rising-edge on COUT has not been detected.
1 Rising-edge on COUT has occurred.
Analog Comparator Flag Falling
Detects a falling-edge on COUT, when set, during normal operation. CFF is cleared by writing 1 to it.
During Stop modes, CFF is level sensitive .
0 Falling-edge on COUT has not been detected.
1 Falling-edge on COUT has occurred.
Analog Comparator Output
Returns the current value of the Analog Comparator output, when read. The field is reset to 0 and will read as CR1[INV] when the Analog Comparator module is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
29.2.5 DAC Control Register (CMPx_DACCR)
Address: 4007_3000h base + 4h offset = 4007_3004h
5 Bit
Read
Write
Reset
7
0
6
0 0
Field
7
DACEN
4
0
3
0
2
0
CMPx_DACCR field descriptions
Description
DAC Enable
Enables the DAC. When the DAC is disabled, it is powered down to conserve power.
1
0
6
VRSEL
0 DAC is disabled.
1 DAC is enabled.
Supply Voltage Reference Source Select
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Field
5–0
VOSEL
CMPx_DACCR field descriptions (continued)
Chapter 29 Comparator (CMP)
Description
0 V is selected as resistor ladder network supply reference V. in1in
1 V is selected as resistor ladder network supply reference V. in2in
DAC Output Voltage Select
Selects an output voltage from one of 64 distinct levels.
DACO = (V in
/64) * (VOSEL[5:0] + 1) , so the DACO range is from V in
/64 to V in
.
29.2.6 MUX Control Register (CMPx_MUXCR)
Address: 4007_3000h base + 5h offset = 4007_3005h
Bit
Read
Write
Reset
7
0
6
0
5
0
Field
7
PSTM
4
0
3 2 1
0
0
0 0 0
CMPx_MUXCR field descriptions
Description
Pass Through Mode Enable
This bit is used to enable to MUX pass through mode. Pass through mode is always available but for some devices this feature must be always disabled due to the lack of package pins.
6
Reserved
5–3
PSEL
2–0
MSEL
0 Pass Through Mode is disabled.
1 Pass Through Mode is enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
Plus Input Mux Control
Determines which input is selected for the plus input of the comparator. For INx inputs, see CMP, DAC, and ANMUX block diagrams.
NOTE: When an inappropriate operation selects the same input for both muxes, the comparator automatically shuts down to prevent itself from becoming a noise generator.
000 IN0
001 IN1
010 IN2
011 IN3
100 IN4
101 IN5
110 IN6
111 IN7
Minus Input Mux Control
Determines which input is selected for the minus input of the comparator. For INx inputs, see CMP, DAC, and ANMUX block diagrams.
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Functional description
Field
CMPx_MUXCR field descriptions (continued)
Description
NOTE: When an inappropriate operation selects the same input for both muxes, the comparator automatically shuts down to prevent itself from becoming a noise generator.
000 IN0
001 IN1
010 IN2
011 IN3
100 IN4
101 IN5
110 IN6
111 IN7
29.3 Functional description
The CMP module can be used to compare two analog input voltages applied to INP and
INM.
CMPO is high when the non-inverting input is greater than the inverting input, and is low when the non-inverting input is less than the inverting input. This signal can be selectively inverted by setting CR1[INV] = 1.
SCR[IER] and SCR[IEF] are used to select the condition which will cause the CMP module to assert an interrupt to the processor. SCR[CFF] is set on a falling-edge and
SCR[CFR] is set on rising-edge of the comparator output. The optionally filtered CMPO can be read directly through SCR[COUT].
29.3.1 CMP functional modes
There are three main sub-blocks to the CMP module:
• The comparator itself
• The window function
• The filter function
The filter, CR0[FILTER_CNT], can be clocked from an internal or external clock source.
The filter is programmable with respect to the number of samples that must agree before a change in the output is registered. In the simplest case, only one sample must agree. In this case, the filter acts as a simple sampler.
The external sample input is enabled using CR1[SE]. When set, the output of the comparator is sampled only on rising edges of the sample input.
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The "windowing mode" is enabled by setting CR1[WE]. When set, the comparator output is sampled only when WINDOW=1. This feature can be used to ignore the comparator output during time periods in which the input voltages are not valid. This is especially useful when implementing zero-crossing-detection for certain PWM applications.
The comparator filter and sampling features can be combined as shown in the following table. Individual modes are discussed below.
Table 29-15. Comparator sample/filter controls
Mode #
1
2A
2B
3A
3B
4A
4B
5A
5B
6
7
CR1[EN] CR1[WE] CR1[SE]
CR0[FILTER_C
NT]
X
FPR[FILT_PER] Operation
0
1
1
1
1
1
1
1
1
X
0
0
0
0
0
0
1
1
X
0
0
1
0
1
0
0
0
0x00
X
0x01
0x01
> 0x01
> 0x01
0x00
X
X
X
0x00
X
> 0x00
X
> 0x00
X
0x00
Disabled
Continuous Mode
See the Continuous mode (#s 2A &
.
Sampled, Non-Filtered mode
See the Sampled, Non-Filtered mode (#s 3A & 3B) .
Sampled, Filtered mode
See the
Windowed mode
Comparator output is sampled on every rising bus clock edge when
SAMPLE=1 to generate COUTA.
1 1 0 0x01 0x01–0xFF
See the
.
Windowed/Resampled mode
Comparator output is sampled on every rising bus clock edge when
SAMPLE=1 to generate COUTA, which is then resampled on an interval determined by FILT_PER to generate COUT.
See the Windowed/Resampled mode (# 6)
.
Windowed/Filtered mode 1 1 0 > 0x01 0x01–0xFF
Comparator output is sampled on every rising bus clock edge when
SAMPLE=1 to generate COUTA, which is then resampled and filtered to generate COUT.
See the Windowed/Filtered mode
All other combinations of CR1[EN], CR1[WE], CR1[SE], CR0[FILTER_CNT], and FPR[FILT_PER] are illegal.
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Functional description
For cases where a comparator is used to drive a fault input, for example, for a motorcontrol module such as FTM, it must be configured to operate in Continuous mode so that an external fault can immediately pass through the comparator to the target fault circuitry.
Note
Filtering and sampling settings must be changed only after setting CR1[SE]=0 and CR0[FILTER_CNT]=0x00. This resets the filter to a known state.
29.3.1.1 Disabled mode (# 1)
In Disabled mode, the analog comparator is non-functional and consumes no power.
CMPO is 0 in this mode.
29.3.1.2 Continuous mode (#s 2A & 2B)
Internal bus
EN,PMODE,HYSTCTR[1:0]
FILT_PER
COS INV WE FILTER_CNT SE
OPE
COUT IER/F CFR/F
INP
INM
0
+
-
CMPO
Polarity select
Window contro l
Filter block
Interrupt control
IRQ
COUT
To other system functions
WINDOW/SAMPLE 1
0 bus clock
FILT_PER
Clock prescaler divided bus clock
0
CGMUX
COUTA
1
SE
COS
Figure 29-15. Comparator operation in Continuous mode
CMPO to
PAD
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Chapter 29 Comparator (CMP)
NOTE
See the chip configuration section for the source of sample/ window input.
The analog comparator block is powered and active. CMPO may be optionally inverted, but is not subject to external sampling or filtering. Both window control and filter blocks are completely bypassed. SCR[COUT] is updated continuously. The path from comparator input pins to output pin is operating in combinational unclocked mode.
COUT and COUTA are identical.
For control configurations which result in disabling the filter block, see the Filter Block
29.3.1.3 Sampled, Non-Filtered mode (#s 3A & 3B)
Internal bus
EN,PMODE,HYSTCTR[1:0]
FILT_PER
COS INV WE FILTER_CNT SE
OPE
COUT IER/F CFR/F
0 0x01 1
INP
+
CMPO
Polarity select
Window control
Filter block
Interrupt control
IRQ
INM
COUT
To other SOC functions
WINDOW/SAMPLE 1
0 bus clock
FILT_PER
Clock prescaler divided bus clock
0
CGMUX
COUTA
1 CMPO to
PAD
SE=1
COS
Figure 29-16. Sampled, Non-Filtered (# 3A): sampling point externally driven
In Sampled, Non-Filtered mode, the analog comparator block is powered and active. The path from analog inputs to COUTA is combinational unclocked. Windowing control is completely bypassed. COUTA is sampled whenever a rising-edge is detected on the filter block clock input.
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Functional description
The only difference in operation between Sampled, Non-Filtered (# 3A) and Sampled,
Non-Filtered (# 3B) is in how the clock to the filter block is derived. In #3A, the clock to filter block is externally derived while in #3B, the clock to filter block is internally derived.
The comparator filter has no other function than sample/hold of the comparator output in this mode (# 3B).
Internal bus
EN,PMODE,HYSTCTR[1:0]
FILT_PER
COS INV WE FILTER_CNT SE
OPE
COUT IER/F CFR/F
0 0x01 0
INP
+
-
CMPO
Polarity select
Window control
Filter block
Interrupt control
IRQ
INM
COUT
To other SOC functions
WINDOW/SAMPLE 1
0 bus clock
FILT_PER
Clock prescaler divided bus clock
0
CGMUX
COUTA
1 CMPO to
PAD
SE=0
COS
Figure 29-17. Sampled, Non-Filtered (# 3B): sampling interval internally derived
29.3.1.4 Sampled, Filtered mode (#s 4A & 4B)
In Sampled, Filtered mode, the analog comparator block is powered and active. The path from analog inputs to COUTA is combinational unclocked. Windowing control is completely bypassed. COUTA is sampled whenever a rising edge is detected on the filter block clock input.
The only difference in operation between Sampled, Non-Filtered (# 3A) and Sampled,
Filtered (# 4A) is that, now, CR0[FILTER_CNT]>1, which activates filter operation.
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EN, PMODE, HYSTCTR[1:0]
FILT_PER
COS INV
Internal bus
WE FILTER_CNT SE
OPE
COUT IER/F CFR/F
INP
INM
0 > 0x01 1
+
CMPO
Polarity select
Window control
Filter block
Interrupt control
IRQ
COUT
To other SOC functions
WINDOW/SAMPLE 1
0 bus clock
FILT_PER
Clock prescaler divided bus clock
0
CGMUX
COUTA
1 CMPO to
PAD
SE=1
COS
Figure 29-18. Sampled, Filtered (# 4A): sampling point externally driven
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Functional description
EN, PMODE, HYSTCTR[1:0 ]
FILT_PER
COS INV
Internal bus
WE FILTER_CNT SE
OPE
COUT IER/F CFR/F
0
>
0x01
0
INP
+
CMPO
Polarity select
Window control
Filter block
Interrupt control
IRQ
INM
COUT
To other SOC functions
WINDOW/SAMPLE 1
0 bus clock
FILT_PER
Clock prescaler divided bus clock
0
CGMUX
COUTA
1 CMPO to
PAD
SE=0
COS
Figure 29-19. Sampled, Filtered (# 4B): sampling point internally derived
The only difference in operation between Sampled, Non-Filtered (# 3B) and Sampled,
Filtered (# 4B) is that now, CR0[FILTER_CNT]>1, which activates filter operation.
29.3.1.5 Windowed mode (#s 5A & 5B)
The following figure illustrates comparator operation in the Windowed mode, ignoring latency of the analog comparator, polarity select, and window control block. It also assumes that the polarity select is set to non-inverting state.
NOTE
The analog comparator output is passed to COUTA only when the WINDOW signal is high.
In actual operation, COUTA may lag the analog inputs by up to one bus clock cycle plus the combinational path delay through the comparator and polarity select logic.
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Chapter 29 Comparator (CMP)
WINDOW
Plus input
Minus input
CMPO
COUTA
Figure 29-20. Windowed mode operation
Internal bus
EN, PMODE,HYSCTR[1:0]
FILT_PER
COS INV WE FILTER_CNT SE
OPE
COUT IER/F CFR/F
0x01 0
INP
+
CMPO
Polarity select
Window control
Filter block
Interrupt control
IRQ
INM
WINDOW/SAMPLE 1
COUT
To other SOC functions
0 bus clock
FILT_PER
Clock prescaler divided bus clock
0
CGMUX
SE=0
COUTA
1 CMPO to
PAD
COS
Figure 29-21. Windowed mode
For control configurations which result in disabling the filter block, see Filter Block
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Functional description
When any windowed mode is active, COUTA is clocked by the bus clock whenever
WINDOW = 1. The last latched value is held when WINDOW = 0.
29.3.1.6 Windowed/Resampled mode (# 6)
The following figure uses the same input stimulus shown in Figure 29-20 , and adds
resampling of COUTA to generate COUT. Samples are taken at the time points indicated by the arrows in the figure. Again, prop delays and latency are ignored for the sake of clarity.
This example was generated solely to demonstrate operation of the comparator in windowed/resampled mode, and does not reflect any specific application. Depending upon the sampling rate and window placement, COUT may not see zero-crossing events detected by the analog comparator. Sampling period and/or window placement must be carefully considered for a given application.
WINDOW
Plus input
Minus input
CMPO
COUTA
COUT
Figure 29-22. Windowed/resampled mode operation
This mode of operation results in an unfiltered string of comparator samples where the interval between the samples is determined by FPR[FILT_PER] and the bus clock rate.
Configuration for this mode is virtually identical to that for the Windowed/Filtered Mode shown in the next section. The only difference is that the value of CR0[FILTER_CNT] must be 1.
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Chapter 29 Comparator (CMP)
29.3.1.7 Windowed/Filtered mode (#7)
This is the most complex mode of operation for the comparator block, as it uses both windowing and filtering features. It also has the highest latency of any of the modes. This can be approximated: up to 1 bus clock synchronization in the window function +
((CR0[FILTER_CNT] * FPR[FILT_PER]) + 1) * bus clock for the filter function.
When any windowed mode is active, COUTA is clocked by the bus clock whenever
WINDOW = 1. The last latched value is held when WINDOW = 0.
Internal bus
EN, PMODE,HYSCTR[1:0]
FILT_PER
COS INV WE FILTER_CNT SE
OPE
COUT IER/F CFR/F
INP
INM bus clock
FILT_PER
1 > 0x01 0
+
CMPO
Polarity select
Window control
Filter block
Interrupt control
IRQ
WINDOW/SAMPLE
Clock prescaler divided bus clock
1
0
CGMUX
SE=0
Figure 29-23. Windowed/Filtered mode
COUT
To other SOC functions
0
COUTA
1 CMPO to
PAD
COS
29.3.2 Power modes
29.3.2.1 Wait mode operation
During Wait and VLPW modes, the CMP, if enabled, continues to operate normally and a CMP interrupt can wake the MCU.
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Functional description
29.3.2.2 Stop mode operation
Depending on clock restrictions related to the MCU core or core peripherals, the MCU is brought out of stop when a compare event occurs and the corresponding interrupt is enabled. Similarly, if CR1[OPE] is enabled, the comparator output operates as in the normal operating mode and comparator output is placed onto the external pin. In Stop modes, the comparator can be operational in both:
• High-Speed (HS) Comparison mode when CR1[PMODE] = 1
• Low-Speed (LS) Comparison mode when CR1[PMODE] = 0
It is recommended to use the LS mode to minimize power consumption.
If stop is exited with a reset, all comparator registers are put into their reset state.
29.3.2.3 Low-Leakage mode operation
When the chip is in Low-Leakage modes:
• The CMP module is partially functional and is limited to Low-Speed mode, regardless of CR1[PMODE] setting
• Windowed, Sampled, and Filtered modes are not supported
• The CMP output pin is latched and does not reflect the compare output state.
The positive- and negative-input voltage can be supplied from external pins or the DAC output. The MCU can be brought out of the Low-Leakage mode if a compare event occurs and the CMP interrupt is enabled. After wakeup from low-leakage modes, the
CMP module is in the reset state except for SCR[CFF] and SCR[CFR].
29.3.2.4 Background Debug Mode Operation
When the microcontroller is in active background debug mode, the CMP continues to operate normally.
29.3.3 Startup and operation
A typical startup sequence is listed here.
• The time required to stabilize COUT will be the power-on delay of the comparators plus the largest propagation delay from a selected analog source through the analog
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Chapter 29 Comparator (CMP) comparator, windowing function and filter. See the Data Sheets for power-on delays of the comparators. The windowing function has a maximum of one bus clock period delay. The filter delay is specified in the
.
• During operation, the propagation delay of the selected data paths must always be considered. It may take many bus clock cycles for COUT and SCR[CFR]/SCR[CFF] to reflect an input change or a configuration change to one of the components involved in the data path.
• When programmed for filtering modes, COUT will initially be equal to 0, until sufficient clock cycles have elapsed to fill all stages of the filter. This occurs even if
COUTA is at a logic 1.
29.3.4 Low-pass filter
The low-pass filter operates on the unfiltered and unsynchronized and optionally inverted comparator output COUTA and generates the filtered and synchronized output COUT.
Both COUTA and COUT can be configured as module outputs and are used for different purposes within the system.
Synchronization and edge detection are always used to determine status register bit values. They also apply to COUT for all sampling and windowed modes. Filtering can be performed using an internal timebase defined by FPR[FILT_PER], or using an external
SAMPLE input to determine sample time.
The need for digital filtering and the amount of filtering is dependent on user requirements. Filtering can become more useful in the absence of an external hysteresis circuit. Without external hysteresis, high-frequency oscillations can be generated at
COUTA when the selected INM and INP input voltages differ by less than the offset voltage of the differential comparator.
29.3.4.1 Enabling filter modes
Filter modes can be enabled by:
• Setting CR0[FILTER_CNT] > 0x01 and
• Setting FPR[FILT_PER] to a nonzero value or setting CR1[SE]=1
If using the divided bus clock to drive the filter, it will take samples of COUTA every
FPR[FILT_PER] bus clock cycles.
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Functional description
The filter output will be at logic 0 when first initalized, and will subsequently change when all the consecutive CR0[FILTER_CNT] samples agree that the output value has changed. In other words, SCR[COUT] will be 0 for some initial period, even when
COUTA is at logic 1.
Setting both CR1[SE] and FPR[FILT_PER] to 0 disables the filter and eliminates switching current associated with the filtering process.
Note
Always switch to this setting prior to making any changes in filter parameters. This resets the filter to a known state.
Switching CR0[FILTER_CNT] on the fly without this intermediate step can result in unexpected behavior.
If CR1[SE]=1, the filter takes samples of COUTA on each positive transition of the sample input. The output state of the filter changes when all the consecutive
CR0[FILTER_CNT] samples agree that the output value has changed.
29.3.4.2 Latency issues
The value of FPR[FILT_PER] or SAMPLE period must be set such that the sampling period is just longer than the period of the expected noise. This way a noise spike will corrupt only one sample. The value of CR0[FILTER_CNT] must be chosen to reduce the probability of noisy samples causing an incorrect transition to be recognized. The probability of an incorrect transition is defined as the probability of an incorrect sample raised to the power of CR0[FILTER_CNT].
The values of FPR[FILT_PER] or SAMPLE period and CR0[FILTER_CNT] must also be traded off against the desire for minimal latency in recognizing actual comparator output transitions. The probability of detecting an actual output change within the nominal latency is the probability of a correct sample raised to the power of
CR0[FILTER_CNT].
The following table summarizes maximum latency values for the various modes of operation in the absence of noise. Filtering latency is restarted each time an actual output transition is masked by noise.
Mode #
1
CR1[
EN]
0
Table 29-16. Comparator sample/filter maximum latencies
CR1[
WE]
X
CR1[
SE]
X
CR0[FILTER
_CNT]
X
FPR[FILT_P
ER]
X
Operation
Disabled
Table continues on the next page...
Maximum latency
N/A
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Mode #
5A
5B
6
2A
2B
3A
3B
4A
4B
7
1
1
1
Chapter 29 Comparator (CMP)
Table 29-16. Comparator sample/filter maximum latencies (continued)
CR1[
EN]
1
1
1
1
1
1
1
CR1[
WE]
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
CR1[
SE]
1
0
0
0
0
CR0[FILTER
_CNT]
0x00
X
0x01
0x01
> 0x01
> 0x01
0x00
X
0x01
> 0x01
FPR[FILT_P
ER]
Operation Maximum latency
X
0x00
Continuous Mode T
PD
X
> 0x00
X
> 0x00
Sampled, Non-Filtered mode
Sampled, Filtered mode
T
PD
+ T
SAMPLE
+ T per
T
PD
+ (FPR[FILT_PER] *
T per
) + T per
T
PD
+ (CR0[FILTER_CNT] *
T
SAMPLE
) + T per
T
PD
+ (CR0[FILTER_CNT] *
FPR[FILT_PER] x T per
) + T per
X
0x00
Windowed mode T
PD
+ T per
T
PD
+ T per
0x01 - 0xFF Windowed / Resampled mode
T
PD
+ (FPR[FILT_PER] *
T per
) + 2T per
0x01 - 0xFF Windowed / Filtered mode T
PD
+ (CR0[FILTER_CNT] *
FPR[FILT_PER] x T per
) +
2T per
1. T
PD
represents the intrinsic delay of the analog component plus the polarity select logic. T
SAMPLE external sample clock. T per
is the period of the bus clock.
is the clock period of the
29.4 CMP interrupts
The CMP module is capable of generating an interrupt on either the rising- or fallingedge of the comparator output, or both.
The following table gives the conditions in which the interrupt request is asserted and deasserted.
When
SCR[IER] and SCR[CFR] are set
SCR[IEF] and SCR[CFF] are set
SCR[IER] and SCR[CFR] are cleared for a rising-edge interrupt
SCR[IEF] and SCR[CFF] are cleared for a falling-edge interrupt
Then
The interrupt request is asserted
The interrupt request is asserted
The interrupt request is deasserted
The interrupt request is deasserted
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CMP Asyncrhonous DMA support
29.5 DMA support
Normally, the CMP generates a CPU interrupt if there is a change on the COUT. When
DMA support is enabled by setting SCR[DMAEN] and the interrupt is enabled by setting
SCR[IER], SCR[IEF], or both, the corresponding change on COUT forces a DMA transfer request rather than a CPU interrupt instead. When the DMA has completed the transfer, it sends a transfer completing indicator that deasserts the DMA transfer request and clears the flag to allow a subsequent change on comparator output to occur and force another DMA request.
The comparator can remain functional in STOP modes.
When DMA support is enabled by setting SCR[DMAEN] and the interrupt is enabled by setting SCR[IER], SCR[IEF], or both, the corresponding change on COUT forces a DMA transfer request to wake up the system from STOP modes. After the data transfer has finished, system will go back to STOP modes. Refer to DMA chapters in the device reference manual for the asynchronous DMA function for details.
29.6 CMP Asyncrhonous DMA support
The comparator can remain functional in STOP modes.
When DMA support is enabled by setting SCR[DMAEN] and the interrupt is enabled by setting SCR[IER], SCR[IEF], or both, the corresponding change on COUT forces a DMA transfer request to wake up the system from STOP modes. After the data transfer has finished, system will go back to STOP modes. Refer to DMA chapters in the device reference manual for the asynchronous DMA function for details.
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Chapter 29 Comparator (CMP)
29.7 Digital-to-analog converter
The figure found here shows the block diagram of the DAC module.
It contains a 64-tap resistor ladder network and a 64-to-1 multiplexer, which selects an output voltage from one of 64 distinct levels that outputs from DACO. It is controlled through the DAC Control Register (DACCR). Its supply reference source can be selected from two sources V in1
and V in2
. The module can be powered down or disabled when not in use. When in Disabled mode, DACO is connected to the analog ground.
V in1
V in2
VRSEL MUX
Vin
VOSEL[5:0] DACEN
DACO
Figure 29-24. 6-bit DAC block diagram
29.8 DAC functional description
This section provides DAC functional description information.
29.8.1 Voltage reference source select
• V in1
connects to the primary voltage source as supply reference of 64 tap resistor ladder
• V in2
connects to an alternate voltage source
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DAC clocks
29.9 DAC resets
This module has a single reset input, corresponding to the chip-wide peripheral reset.
29.10 DAC clocks
This module has a single clock input, the bus clock.
29.11 DAC interrupts
This module has no interrupts.
29.12 CMP Trigger Mode
CMP and DAC are configured to CMP Trigger mode when CMP_CR1[TRIGM] is set to
1.
In addition, the CMP must be enabled. If the DAC is to be used as a reference to the
CMP, it must also be enabled.
CMP Trigger mode depends on an external timer resource to periodically enable the
CMP and 6-bit DAC in order to generate a triggered compare.
Upon setting TRIGM, the CMP and DAC are placed in a standby state until an external timer resource trigger is received.
See the chip configuration chapter for details about the external timer resource.
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Chapter 30
12-bit digital-to-analog converter (DAC)
The 12-bit digital-to-analog converter (DAC) is a low-power general purpose DAC whose output can be placed on an external pin, or set as one of the inputs to the analog comparator, OPAMPs, ADC, or other peripherals.
30.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
The 12-bit digital-to-analog converter (DAC) is a low-power, general-purpose DAC. The output of the DAC can be placed on an external pin or set as one of the inputs to the analog comparator, op-amps, or ADC.
30.2 Features
The features of the DAC module include:
• On-chip programmable reference generator output. The voltage output range is from
1⁄4096 V in
to V in
, and the step is 1⁄4096 V in
, where V in
is the input voltage.
• V in
can be selected from two reference sources
• Static operation in Normal Stop mode
• 2-word data buffer supported with multiple operation modes
• DMA support
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Memory map/register definition
30.3 Block diagram
The block diagram of the DAC module is as follows:
DACREF_2
MUX
V in
DACREF_1
DACEN
LPEN
V o
AMP buffer
+
-
V
DD
V out
DACDAT[11:0]
12
Hardware trigger
DACSWTRG
DACBFWM
DACBFEN
DACBFUP
DACBFRP
DACBFMD
DACTRGSE
DACBFWMF
Data
Buffer
DACBWIEN
DACBFRPTF
DACBTIEN
DACBFRPBF
DACBBIEN
&
&
&
Figure 30-1. DAC block diagram
OR dac_interrupt
30.4 Memory map/register definition
The DAC has registers to control analog comparator and programmable voltage divider to perform the digital-to-analog functions.
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Chapter 30 12-bit digital-to-analog converter (DAC)
DAC memory map
Absolute address
(hex)
Register name
4003_F000 DAC Data Low Register (DAC0_DAT0L)
4003_F001 DAC Data High Register (DAC0_DAT0H)
4003_F002 DAC Data Low Register (DAC0_DAT1L)
4003_F003 DAC Data High Register (DAC0_DAT1H)
4003_F020 DAC Status Register (DAC0_SR)
4003_F021 DAC Control Register (DAC0_C0)
4003_F022 DAC Control Register 1 (DAC0_C1)
4003_F023 DAC Control Register 2 (DAC0_C2)
Width
(in bits)
Access Reset value
8
8
8
8
8
8
8
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00h
00h
00h
00h
02h
00h
00h
01h
Section/ page
30.4.1 DAC Data Low Register (DACx_DATnL)
Address: 4003_F000h base + 0h offset + (2d × i), where i=0d to 1d
Bit
Read
Write
Reset
7
0
6
0
5
0
4
0
Field
7–0
DATA0
3
0
2
0
1
0
DACx_DATnL field descriptions
Description
When the DAC buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula: V out
= V in
* (1 + DACDAT0[11:0])/4096
When the DAC buffer is enabled, DATA is mapped to the 16-word buffer.
0
0
30.4.2 DAC Data High Register (DACx_DATnH)
Address: 4003_F000h base + 1h offset + (2d × i), where i=0d to 1d
Bit
Read
Write
Reset
7
0
6
0
5
0
4
0
Field
7–4
Reserved
3–0
DATA1
3
0
2
0
1
0
DACx_DATnH field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula. V out
= V in
* (1 + DACDAT0[11:0])/4096
When the DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
0
0
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Memory map/register definition
30.4.3 DAC Status Register (DACx_SR)
If DMA is enabled, the flags can be cleared automatically by DMA when the DMA request is done. Writing 0 to a field clears it whereas writing 1 has no effect. After reset,
DACBFRPTF is set and can be cleared by software, if needed. The flags are set only when the data buffer status is changed.
NOTE
Do not use 32/16-bit accesses to this register.
Address: 4003_F000h base + 20h offset = 4003_F020h
7 6 5 Bit
Read
Write
Reset
Field
7–2
Reserved
1
DACBFRPTF
4 3
0 0 0 0 0
DACx_SR field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
DAC Buffer Read Pointer Top Position Flag
0
DACBFRPBF
0 The DAC buffer read pointer is not zero.
1 The DAC buffer read pointer is zero.
DAC Buffer Read Pointer Bottom Position Flag
0 The DAC buffer read pointer is not equal to C2[DACBFUP].
1 The DAC buffer read pointer is equal to C2[DACBFUP].
2
0
1
1
0
0
30.4.4 DAC Control Register (DACx_C0)
NOTE
Do not use 32- or 16-bit accesses to this register.
Address: 4003_F000h base + 21h offset = 4003_F021h
7 6 Bit
Read
Write
Reset
0
0
5 4
0
0
0
3
0
2
0
1 0
0 0
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Field
7
DACEN
6
DACRFS
5
DACTRGSEL
4
DACSWTRG
3
LPEN
Chapter 30 12-bit digital-to-analog converter (DAC)
DACx_C0 field descriptions
Description
DAC Enable
Starts the Programmable Reference Generator operation.
0 The DAC system is disabled.
1 The DAC system is enabled.
DAC Reference Select
0 The DAC selects DACREF_1 as the reference voltage.
1 The DAC selects DACREF_2 as the reference voltage.
DAC Trigger Select
0 The DAC hardware trigger is selected.
1 The DAC software trigger is selected.
DAC Software Trigger
Active high. This is a write-only field, which always reads 0. If DAC software trigger is selected and buffer is enabled, writing 1 to this field will advance the buffer read pointer once.
0 The DAC soft trigger is not valid.
1 The DAC soft trigger is valid.
DAC Low Power Control
2
Reserved
1
DACBTIEN
0
DACBBIEN
NOTE: See the 12-bit DAC electrical characteristics of the device data sheet for details on the impact of the modes below.
0 High-Power mode
1 Low-Power mode
This field is reserved.
This read-only field is reserved and always has the value 0.
DAC Buffer Read Pointer Top Flag Interrupt Enable
0 The DAC buffer read pointer top flag interrupt is disabled.
1 The DAC buffer read pointer top flag interrupt is enabled.
DAC Buffer Read Pointer Bottom Flag Interrupt Enable
0 The DAC buffer read pointer bottom flag interrupt is disabled.
1 The DAC buffer read pointer bottom flag interrupt is enabled.
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Memory map/register definition
30.4.5 DAC Control Register 1 (DACx_C1)
NOTE
Do not use 32- or 16-bit accesses to this register.
Address: 4003_F000h base + 22h offset = 4003_F022h
6 5 Bit
Read
Write
Reset
7
0 0
4 3
0 0 0
DACx_C1 field descriptions
Description Field
7
DMAEN
DMA Enable Select
6–3
Reserved
2
DACBFMD
1
0
0 DMA is disabled.
1 DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.
This field is reserved.
This read-only field is reserved and always has the value 0.
DAC Buffer Work Mode Select
1
Reserved
0
DACBFEN
0 Normal mode
1 One-Time Scan mode
This field is reserved.
This read-only field is reserved and always has the value 0.
DAC Buffer Enable
2
0
0
0
0 Buffer read pointer is disabled. The converted data is always the first word of the buffer.
1 Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer.
30.4.6 DAC Control Register 2 (DACx_C2)
Address: 4003_F000h base + 23h offset = 4003_F023h
Bit
Read
Write
Reset
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
1
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Field
7–5
Reserved
4
DACBFRP
3–1
Reserved
0
DACBFUP
Chapter 30 12-bit digital-to-analog converter (DAC)
DACx_C2 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
DAC Buffer Read Pointer
Keeps the current value of the buffer read pointer.
This field is reserved.
This read-only field is reserved and always has the value 0.
DAC Buffer Upper Limit
Selects the upper limit of the DAC buffer. The buffer read pointer cannot exceed it.
30.5 Functional description
The 12-bit DAC module can select one of the two reference inputs—DACREF_1 and
DACREF_2 as the DAC reference voltage, V in
by C0[DACRFS]. See the module introduction for information on the source for DACREF_1 and DACREF_2.
When the DAC is enabled, it converts the data in DACDAT0[11:0] or the data from the
DAC data buffer to a stepped analog output voltage. The output voltage range is from V in to V in
∕4096, and the step is V in
∕4096.
30.5.1 DAC data buffer operation
When the DAC is enabled and the buffer is not enabled, the DAC module always converts the data in DAT0 to analog output voltage.
When both the DAC and the buffer are enabled, the DAC converts the data in the data buffer to analog output voltage. The data buffer read pointer advances to the next word whenever any hardware or software trigger event occurs. Refer to
hardware trigger connection.
The data buffer can be configured to operate in Normal mode, Swing mode, One-Time
Scan mode or FIFO mode. When the buffer operation is switched from one mode to another, the read pointer does not change. The read pointer can be set to any value between 0 and C2[DACBFUP] by writing C2[DACBFRP].
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Functional description
30.5.1.1 DAC data buffer interrupts
There are several interrupts and associated flags that can be configured for the DAC buffer. SR[DACBFRPBF] is set when the DAC buffer read pointer reaches the DAC buffer upper limit, that is, C2[DACBFRP] = C2[DACBFUP]. SR[DACBFRPTF] is set when the DAC read pointer is equal to the start position, 0.
30.5.1.2 Modes of DAC data buffer operation
The following table describes the different modes of data buffer operation for the DAC module.
Table 30-23. Modes of DAC data buffer operation
Modes
Buffer Normal mode
Buffer One-time Scan mode
Description
This is the default mode. The buffer works as a circular buffer.
The read pointer increases by one, every time the trigger occurs. When the read pointer reaches the upper limit, it goes to 0 directly in the next trigger event.
The read pointer increases by 1 every time the trigger occurs.
When it reaches the upper limit, it stops there. If read pointer is reset to the address other than the upper limit, it will increase to the upper address and stop there again.
NOTE: If the software set the read pointer to the upper limit, the read pointer will not advance in this mode.
30.5.2 DMA operation
When DMA is enabled, DMA requests are generated instead of interrupt requests. The
DMA Done signal clears the DMA request.
The status register flags are still set and are cleared automatically when the DMA completes.
30.5.3 Resets
During reset, the DAC is configured in the default mode and is disabled.
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Chapter 30 12-bit digital-to-analog converter (DAC)
30.5.4 Low-Power mode operation
The following table shows the wait mode and the stop mode operation of the DAC module.
Table 30-24. Modes of operation
Modes of operation
Wait mode
Stop mode
Description
The DAC will operate normally, if enabled.
If enabled, the DAC module continues to operate in Normal Stop mode and the output voltage will hold the value before stop.
In low-power stop modes, the DAC is fully shut down.
NOTE
The assignment of module modes to core modes is chipspecific. For module-to-core mode assignments, see the chapter that describes how modules are configured.
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Chapter 31
Timer/PWM Module (TPM)
31.1 Introduction
The TPM (Timer/PWM Module) is a 2- to 8-channel timer which supports input capture, output compare, and the generation of PWM signals to control electric motor and power management applications.
The counter, compare and capture registers are clocked by an asynchronous clock that can remain enabled in low power modes. An example of using the TPM with the asynchronous DMA is described in AN4631:Using the Asynchronous DMA features of the Kinetis L Series .
31.1.1 TPM Philosophy
The TPM is built upon a very simple timer (HCS08 Timer PWM Module – TPM) used for many years on Freescale's 8-bit microcontrollers. The TPM extends the functionality to support operation in low power modes by clocking the counter, compare and capture registers from an asynchronous clock that can remain functional in low power modes.
31.1.2 Features
The TPM features include:
• TPM clock mode is selectable
• Can increment on every edge of the asynchronous counter clock
• Can increment on rising edge of an external clock input synchronized to the asynchronous counter clock
• Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128
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Introduction
• TPM includes a 16-bit counter
• It can be a free-running counter or modulo counter
• The counting can be up or up-down
• Includes 6 channels that can be configured for input capture, output compare, or edge-aligned PWM mode
• In input capture mode the capture can occur on rising edges, falling edges or both edges
• In output compare mode the output signal can be set, cleared, pulsed, or toggled on match
• All channels can be configured for center-aligned PWM mode
• Support the generation of an interrupt and/or DMA request per channel
• Support the generation of an interrupt and/or DMA request when the counter overflows
• Support selectable trigger input to optionally reset or cause the counter to start incrementing.
• The counter can also optionally stop incrementing on counter overflow
• Support the generation of hardware triggers when the counter overflows and per channel
31.1.3 Modes of operation
During debug mode, the TPM can can be configured to temporarily pause all counting until the core returns to normal user operating mode or to operate normally. When the counter is paused, trigger inputs and input capture events are ignored.
During doze mode, the TPM can be configured to operate normally or to pause all counting for the duration of doze mode. When the counter is paused, trigger inputs and input capture events are ignored.
During stop mode, the TPM counter clock can remain functional and the TPM can generate an asynchronous interrupt to exit the MCU from stop mode.
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Chapter 31 Timer/PWM Module (TPM)
31.1.4 Block diagram
The TPM uses one input/output (I/O) pin per channel, CHn (TPM channel (n)) where n is the channel number.
The following figure shows the TPM structure. The central component of the TPM is the
16-bit counter with programmable final value and its counting can be up or up-down.
CMOD no clock selected
(counter disable) module clock external clock synchronizer
PS prescaler
3
(1, 2, 4, 8, 16, 32, 64 or 128)
CPWMS
MS0B:MS0A
ELS0B:ELS0A channel 0 input input capture mode logic
Module counter
MOD
Channel 0
CH0IE
CH0F
C0V
TOIE
TOF channel 0 interrupt output modes logic
(generation of channel 0 outputs signals in output compare, EPWM and CPWM modes) timer overflow interrupt channel 0 output signal
MSNB:MSNA
ELSNB:ELSNA channel N input input capture mode logic CNV
Channel N
CHNIE
CHNF channel N interrupt output modes logic
(generation of channel N outputs signals in output compare, EPWM and CPWM modes)
Figure 31-1. TPM block diagram channel N output signal
31.2 TPM Signal Descriptions
Table 31-1 shows the user-accessible signals for the TPM.
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Table 31-1. TPM signal descriptions
Signal
TPM_EXTCLK
TPM_CHn
Description
External clock. TPM external clock can be selected to increment the TPM counter on every rising edge synchronized to the counter clock.
TPM channel (n = 5 to 0)
I/O
I
I/O
31.2.1 TPM_EXTCLK — TPM External Clock
The rising edge of the external input signal is used to increment the TPM counter if selected by CMOD[1:0] bits in the SC register. This input signal must be less than half of the TPM counter clock frequency. The TPM counter prescaler selection and settings are also used when an external input is selected.
31.2.2 TPM_CHn — TPM Channel (n) I/O Pin
Each TPM channel can be configured to operate either as input or output. The direction associated with each channel, input or output, is selected according to the mode assigned for that channel.
31.3 Memory Map and Register Definition
This section provides a detailed description of all TPM registers.
Attempting to access a reserved register location in the TPM memory map will generate a bus error.
TPM memory map
Absolute address
(hex)
4003_8000 Status and Control (TPM0_SC)
4003_8004 Counter (TPM0_CNT)
4003_8008 Modulo (TPM0_MOD)
Register name
4003_800C Channel (n) Status and Control (TPM0_C0SC)
4003_8010 Channel (n) Value (TPM0_C0V)
4003_8014 Channel (n) Status and Control (TPM0_C1SC)
4003_8018 Channel (n) Value (TPM0_C1V)
4003_801C Channel (n) Status and Control (TPM0_C2SC)
Width
(in bits)
Table continues on the next page...
32
32
32
32
32
32
32
32
Access Reset value
R/W
R/W
Section/ page
R/W 0000_FFFFh
R/W
R/W
R/W
R/W
R/W
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
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Chapter 31 Timer/PWM Module (TPM)
TPM memory map (continued)
Absolute address
(hex)
Register name
4003_8020 Channel (n) Value (TPM0_C2V)
4003_8024 Channel (n) Status and Control (TPM0_C3SC)
4003_8028 Channel (n) Value (TPM0_C3V)
4003_802C Channel (n) Status and Control (TPM0_C4SC)
4003_8030 Channel (n) Value (TPM0_C4V)
4003_8034 Channel (n) Status and Control (TPM0_C5SC)
4003_8038 Channel (n) Value (TPM0_C5V)
4003_8050 Capture and Compare Status (TPM0_STATUS)
4003_8084 Configuration (TPM0_CONF)
4003_9000 Status and Control (TPM1_SC)
4003_9004 Counter (TPM1_CNT)
4003_9008 Modulo (TPM1_MOD)
4003_900C Channel (n) Status and Control (TPM1_C0SC)
4003_9010 Channel (n) Value (TPM1_C0V)
4003_9014 Channel (n) Status and Control (TPM1_C1SC)
4003_9018 Channel (n) Value (TPM1_C1V)
4003_901C Channel (n) Status and Control (TPM1_C2SC)
4003_9020 Channel (n) Value (TPM1_C2V)
4003_9024 Channel (n) Status and Control (TPM1_C3SC)
4003_9028 Channel (n) Value (TPM1_C3V)
4003_902C Channel (n) Status and Control (TPM1_C4SC)
4003_9030 Channel (n) Value (TPM1_C4V)
4003_9034 Channel (n) Status and Control (TPM1_C5SC)
4003_9038 Channel (n) Value (TPM1_C5V)
4003_9050 Capture and Compare Status (TPM1_STATUS)
4003_9084 Configuration (TPM1_CONF)
4003_A000 Status and Control (TPM2_SC)
4003_A004 Counter (TPM2_CNT)
4003_A008 Modulo (TPM2_MOD)
4003_A00C Channel (n) Status and Control (TPM2_C0SC)
4003_A010 Channel (n) Value (TPM2_C0V)
4003_A014 Channel (n) Status and Control (TPM2_C1SC)
4003_A018 Channel (n) Value (TPM2_C1V)
4003_A01C Channel (n) Status and Control (TPM2_C2SC)
4003_A020 Channel (n) Value (TPM2_C2V)
4003_A024 Channel (n) Status and Control (TPM2_C3SC)
4003_A028 Channel (n) Value (TPM2_C3V)
4003_A02C Channel (n) Status and Control (TPM2_C4SC)
Width
(in bits)
Table continues on the next page...
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access Reset value
Section/ page
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
R/W
R/W
R/W
R/W
0000_0000h
0000_0000h
0000_0000h
0000_0000h
R/W 0000_0000h
R/W 0000_FFFFh
R/W
R/W
0000_0000h
0000_0000h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
R/W
R/W
R/W
R/W
0000_0000h
0000_0000h
0000_0000h
0000_0000h
R/W
R/W
0000_0000h
0000_0000h
R/W 0000_FFFFh
R/W 0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
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Memory Map and Register Definition
TPM memory map (continued)
Absolute address
(hex)
Register name
4003_A030 Channel (n) Value (TPM2_C4V)
4003_A034 Channel (n) Status and Control (TPM2_C5SC)
4003_A038 Channel (n) Value (TPM2_C5V)
4003_A050 Capture and Compare Status (TPM2_STATUS)
4003_A084 Configuration (TPM2_CONF)
Width
(in bits)
Access Reset value
32
32
32
32
32
R/W
R/W
R/W
R/W
R/W
Section/ page
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
31.3.1 Status and Control (TPMx_SC)
SC contains the overflow status flag and control bits used to configure the interrupt enable, module configuration and prescaler factor. These controls relate to all channels within this module.
Address: Base address + 0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W
Reset 0
Field
31–9
Reserved
0 0 0 0 0 0 0 0 0
TPMx_SC field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
0 0
0 0
0 0
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Field
8
DMA
7
TOF
6
TOIE
5
CPWMS
4–3
CMOD
2–0
PS
Chapter 31 Timer/PWM Module (TPM)
TPMx_SC field descriptions (continued)
Description
DMA Enable
Enables DMA transfers for the overflow flag.
0 Disables DMA transfers.
1 Enables DMA transfers.
Timer Overflow Flag
Set by hardware when the TPM counter equals the value in the MOD register and increments. Writing a 1 to TOF clears it. Writing a 0 to TOF has no effect.
If another LPTPM overflow occurs between the flag setting and the flag clearing, the write operation has no effect; therefore, TOF remains set indicating another overflow has occurred. In this case a TOF interrupt request is not lost due to a delay in clearing the previous TOF.
0 TPM counter has not overflowed.
1 TPM counter has overflowed.
Timer Overflow Interrupt Enable
Enables TPM overflow interrupts.
0 Disable TOF interrupts. Use software polling or DMA request.
1 Enable TOF interrupts. An interrupt is generated when TOF equals one.
Center-Aligned PWM Select
Selects CPWM mode. This mode configures the TPM to operate in up-down counting mode.
This field is write protected. It can be written only when the counter is disabled.
0 TPM counter operates in up counting mode.
1 TPM counter operates in up-down counting mode.
Clock Mode Selection
Selects the TPM counter clock modes. When disabling the counter, this field remain set until acknolwedged in the TPM clock domain.
00 TPM counter is disabled
01 TPM counter increments on every TPM counter clock
10 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock
11 Reserved
Prescale Factor Selection
Selects one of 8 division factors for the clock mode selected by CMOD.
This field is write protected. It can be written only when the counter is disabled.
000 Divide by 1
001 Divide by 2
010 Divide by 4
011 Divide by 8
100 Divide by 16
101 Divide by 32
110 Divide by 64
111 Divide by 128
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31.3.2 Counter (TPMx_CNT)
The CNT register contains the TPM counter value.
Reset clears the CNT register. Writing any value to COUNT also clears the counter.
When debug is active, the TPM counter does not increment unless configured otherwise.
Reading the CNT register adds two wait states to the register access due to synchronization delays.
Address: Base address + 4h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–16
Reserved
15–0
COUNT
TPMx_CNT field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Counter value
31.3.3 Modulo (TPMx_MOD)
The Modulo register contains the modulo value for the TPM counter. When the TPM counter reaches the modulo value and increments, the overflow flag (TOF) is set and the next value of TPM counter depends on the selected counting method (see
).
Writing to the MOD register latches the value into a buffer. The MOD register is updated with the value of its write buffer according to
MOD Register Update . Additional writes
to the MOD write buffer are ignored until the register has been updated.
It is recommended to initialize the TPM counter (write to CNT) before writing to the
MOD register to avoid confusion about when the first counter overflow will occur.
Address: Base address + 8h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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Field
31–16
Reserved
15–0
MOD
TPMx_MOD field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Modulo value
When writing this field, all bytes must be written at the same time.
Chapter 31 Timer/PWM Module (TPM)
31.3.4 Channel (n) Status and Control (TPMx_CnSC)
CnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function. When switching from one channel mode to a different channel mode, the channel must first be disabled and this must be acknowledged in the TPM counter clock domain.
CPWMS
X
X
0
Table 31-34. Mode, Edge, and Level Selection
MSnB:MSnA
00
01
00
ELSnB:ELSnA
00
00
01
Mode
None
Software compare
Input capture
01
10
11
10
11
01
10
11
10
X1
10
01
Output compare
Edge-aligned PWM
Output compare
Configuration
Channel disabled
Pin not used for TPM
Capture on Rising Edge
Only
Capture on Falling
Edge Only
Capture on Rising or
Falling Edge
Toggle Output on match
Clear Output on match
Set Output on match
High-true pulses (clear
Output on match, set
Output on reload)
Low-true pulses (set
Output on match, clear
Output on reload)
Pulse Output low on match
Pulse Output high on match
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Memory Map and Register Definition
Table 31-34. Mode, Edge, and Level Selection (continued)
CPWMS
1
MSnB:MSnA
10
ELSnB:ELSnA
10
01
Mode Configuration
Center-aligned PWM High-true pulses (clear
Output on match-up, set Output on matchdown)
Low-true pulses (set
Output on match-up, clear Output on matchdown)
Address: Base address + Ch offset + (8d × i), where i=0d to 5d
Bit
R
31 30 29 28 27 26 25 24
W
Reset 0 0 0 0 0 0 0 0
23
0
Bit
R
W
Reset
15
0
Field
31–8
Reserved
7
CHF
6
CHIE
5
MSB
4
MSA
14
0
13 12
11 10
22
0
21
0
20
0
19
0
18
0
17
0
16
0
0 0 0 0 0 0 0 0
TPMx_CnSC field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Channel Flag
Set by hardware when an event occurs on the channel. CHF is cleared by writing a 1 to the CHF bit.
Writing a 0 to CHF has no effect.
If another event occurs between the CHF sets and the write operation, the write operation has no effect; therefore, CHF remains set indicating another event has occurred. In this case a CHF interrupt request is not lost due to the delay in clearing the previous CHF.
0 No channel event has occurred.
1 A channel event has occurred.
Channel Interrupt Enable
9 8 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Enables channel interrupts.
0 Disable channel interrupts.
1 Enable channel interrupts.
Channel Mode Select
Used for further selections in the channel logic. Its functionality is dependent on the channel mode. When a channel is disabled, this field will not change state until acknowledged in the TPM counter clock domain.
Channel Mode Select
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Field
3
ELSB
2
ELSA
1
Reserved
0
DMA
Chapter 31 Timer/PWM Module (TPM)
TPMx_CnSC field descriptions (continued)
Description
Used for further selections in the channel logic. Its functionality is dependent on the channel mode. When a channel is disabled, this field will not change state until acknowledged in the TPM counter clock domain.
Edge or Level Select
The functionality of ELSB and ELSA depends on the channel mode. When a channel is disabled, this field will not change state until acknowledged in the TPM counter clock domain.
Edge or Level Select
The functionality of ELSB and ELSA depends on the channel mode. When a channel is disabled, this field will not change state until acknowledged in the TPM counter clock domain.
This field is reserved.
This read-only field is reserved and always has the value 0.
DMA Enable
Enables DMA transfers for the channel.
0 Disable DMA transfers.
1 Enable DMA transfers.
31.3.5 Channel (n) Value (TPMx_CnV)
These registers contain the captured TPM counter value for the input modes or the match value for the output modes.
In input capture mode, any write to a CnV register is ignored.
In compare modes, writing to a CnV register latches the value into a buffer. A CnV register is updated with the value of its write buffer according to
Additional writes to the CnV write buffer are ignored until the register has been updated.
Address: Base address + 10h offset + (8d × i), where i=0d to 5d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–16
Reserved
15–0
VAL
TPMx_CnV field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Channel Value
Captured TPM counter value of the input modes or the match value for the output modes. When writing this field, all bytes must be written at the same time.
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31.3.6 Capture and Compare Status (TPMx_STATUS)
The STATUS register contains a copy of the status flag, CnSC[CHnF] for each TPM channel, as well as SC[TOF], for software convenience.
Each CHnF bit in STATUS is a mirror of CHnF bit in CnSC. All CHnF bits can be checked using only one read of STATUS. All CHnF bits can be cleared by writing all ones to STATUS.
Hardware sets the individual channel flags when an event occurs on the channel. Writing a 1 to CHF clears it. Writing a 0 to CHF has no effect.
If another event occurs between the flag setting and the write operation, the write operation has no effect; therefore, CHF remains set indicating another event has occurred.
In this case a CHF interrupt request is not lost due to the clearing sequence for a previous
CHF.
Address: Base address + 50h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset
Bit
0
15
0
14
R
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
W
0 0 0 0 0 Reset 0
Field
31–9
Reserved
8
TOF
0 0 0 0 0 0 0 0 0 0
TPMx_STATUS field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Timer Overflow Flag
See register description
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Field
7–6
Reserved
5
CH5F
4
CH4F
3
CH3F
2
CH2F
1
CH1F
0
CH0F
Chapter 31 Timer/PWM Module (TPM)
TPMx_STATUS field descriptions (continued)
Description
0 TPM counter has not overflowed.
1 TPM counter has overflowed.
This field is reserved.
This read-only field is reserved and always has the value 0.
Channel 5 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
Channel 4 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
Channel 3 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
Channel 2 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
Channel 1 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
Channel 0 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
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31.3.7 Configuration (TPMx_CONF)
This register selects the behavior in debug and wait modes and the use of an external global time base.
Address: Base address + 84h offset
Bit 31 30 29 28
R
27 26 25 24 23 22 21
20 19 18 17
W
16
Reset
Bit
R
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
W
Reset 0
Field
31–28
Reserved
27–24
TRGSEL
23–19
Reserved
18
CROT
17
CSOO
0 0 0 0 0 0 0 0 0
TPMx_CONF field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Trigger Select
0 0 0 0 0 0
Selects the input trigger to use for starting the counter and/or reloading the counter. This field should only be changed when the TPM counter is disabled. See Chip configuration section for available options.
This field is reserved.
This read-only field is reserved and always has the value 0.
Counter Reload On Trigger
When set, the TPM counter will reload with 0 (and initialize PWM outputs to their default value) when a rising edge is detected on the selected trigger input.
The trigger input is ignored if the TPM counter is paused during debug mode or doze mode. This field should only be changed when the TPM counter is disabled.
0 Counter is not reloaded due to a rising edge on the selected input trigger
1 Counter is reloaded when a rising edge is detected on the selected input trigger
Counter Stop On Overflow
When set, the TPM counter will stop incrementing once the counter equals the MOD value and incremented (this also sets the TOF). Reloading the counter with 0 due to writing to the counter register or due to a trigger input does not cause the counter to stop incrementing. Once the counter has stopped incrementing, the counter will not start incrementing unless it is disabled and then enabled again, or a rising edge on the selected trigger input is detected when CSOT set.
Table continues on the next page...
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Field
16
CSOT
15–10
Reserved
9
GTBEEN
8
Reserved
7–6
DBGMODE
5
DOZEEN
4–0
Reserved
Chapter 31 Timer/PWM Module (TPM)
TPMx_CONF field descriptions (continued)
Description
This field should only be changed when the TPM counter is disabled.
0 TPM counter continues incrementing or decrementing after overflow
1 TPM counter stops incrementing or decrementing after overflow.
Counter Start on Trigger
When set, the TPM counter will not start incrementing after it is enabled until a rising edge on the selected trigger input is detected. If the TPM counter is stopped due to an overflow, a rising edge on the selected trigger input will also cause the TPM counter to start incrementing again.
The trigger input is ignored if the TPM counter is paused during debug mode or doze mode. This field should only be changed when the TPM counter is disabled.
0 TPM counter starts to increment immediately, once it is enabled.
1 TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.
This field is reserved.
This read-only field is reserved and always has the value 0.
Global time base enable
Configures the TPM to use an externally generated global time base counter. When an externally generated timebase is used, the internal TPM counter is not used by the channels but can be used to generate a periodic interruptor DMA request using the Modulo register and timer overflow flag.
0 All channels use the internally generated TPM counter as their timebase
1 All channels use an externally generated global timebase as their timebase
This field is reserved.
This read-only field is reserved and always has the value 0.
Debug Mode
Configures the TPM behavior in debug mode. All other configurations are reserved.
00 TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.
11 TPM counter continues in debug mode.
Doze Enable
Configures the TPM behavior in wait mode.
0 Internal TPM counter continues in Doze mode.
1 Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.
This field is reserved.
This read-only field is reserved and always has the value 0.
31.4 Functional description
The following sections describe the TPM features.
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31.4.1 Clock domains
The TPM module supports two clock domains.
The bus clock domain is used by the register interface and for synchronizing interrupts and DMA requests.
The TPM counter clock domain is used to clock the counter and prescaler along with the output compare and input capture logic. The TPM counter clock is considered asynchronous to the bus clock, can be a higher or lower frequency than the bus clock and can remain operational in Stop mode. Multiple TPM instances are all clocked by the same TPM counter clock in support of the external timebase feature.
31.4.1.1 Counter Clock Mode
The CMOD[1:0] bits in the SC register either disable the TPM counter or select one of two possible clock modes for the TPM counter. After any reset, CMOD[1:0] = 0:0 so the
TPM counter is disabled.
The CMOD[1:0] bits may be read or written at any time. Disabling the TPM counter by writing zero to the CMOD[1:0] bits does not affect the TPM counter value or other registers, but must be acknowledged by the TPM counter clock domain before they read as zero.
The external clock input passes through a synchronizer clocked by the TPM counter clock to assure that counter transitions are properly aligned to counter clock transitions.
Therefore, to meet Nyquist criteria considering also jitter, the frequency of the external clock source must be less than half of the counter clock frequency.
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Chapter 31 Timer/PWM Module (TPM)
31.4.2 Prescaler
The selected counter clock source passes through a prescaler that is a 7-bit counter.
The value of the prescaler is selected by the PS[2:0] bits. The following figure shows an example of the prescaler counter and TPM counter.
timer module counting is up.
PS[2:0] = 001
CNTIN = 0x0000 selected input clock prescaler counter 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 timer module counter
0 1 2 3 0 1 2 3
Figure 31-78. Example of the Prescaler Counter
0 1
31.4.3 Counter
The TPM has a 16-bit counter that is used by the channels either for input or output modes.
The counter updates from the selected clock divided by the prescaler.
The TPM counter has these modes of operation:
• up counting (see Up counting
)
• up-down counting (see
31.4.3.1 Up counting
Up counting is selected when SC[CPWMS] = 0.
The value of zero is loaded into the TPM counter, and the counter increments until the value of MOD is reached, at which point the counter is reloaded with zero.
The TPM period when using up counting is (MOD + 0x0001) × period of the TPM counter clock.
The TOF bit is set when the TPM counter changes from MOD to zero.
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Functional description
MOD = 0x0004 timer module counter 3 4
TOF bit
0 set TOF bit
1 2 3 4 0 1 2 3 4 0 1 2 set TOF bit set TOF bit period of timer module counter clock period of counting = (MOD + 0x0001) x period of timer module counter clock
Figure 31-79. Example of TPM Up Counting
Note
• MOD = 0000 is a redundant condition. In this case, the
TPM counter is always equal to MOD and the TOF bit is set in each rising edge of the TPM counter clock.
31.4.3.2 Up-down counting
Up-down counting is selected when SC[CPWMS] = 1. When configured for up-down counting, configuring CONF[MOD] to less than 2 is not supported.
The value of 0 is loaded into the TPM counter, and the counter increments until the value of MOD is reached, at which point the counter is decremented until it returns to zero and the up-down counting restarts.
The TPM period when using up-down counting is 2 × MOD × period of the TPM counter clock.
The TOF bit is set when the TPM counter changes from MOD to (MOD – 1).
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MOD = 0x0004
Timer module counter 0 1 2 3 4 3 2 1 0 1 2 3 4 3 2 1 0 1 2 3 4
TOF bit set TOF bit set TOF bit period of timer module counter clock period of counting = 2 x MOD x period of timer module counter clock
Figure 31-80. Example of up-down counting
31.4.3.3 Counter Reset
Any write to CNT resets the TPM counter and the channel outputs to their initial values
(except for channels in output compare mode).
31.4.3.4 Global time base (GTB)
The global time base (GTB) is a TPM function that allows multiple TPM modules to share the same timebase. When the global time base is enabled (CONF[GTBEEN] = 1), the local TPM channels use the counter value, counter enable and overflow indication from the TPM generating the global time base. If the local TPM counter is not generating the global time base, then it can be used as an independent counter or pulse accumulator.
31.4.3.5 Counter trigger
The TPM counter can be configured to start, stop or reset in response to a hardware trigger input. The trigger input is synchronized to the asynchronous counter clock, so there is a 3 counter clock delay between the trigger assertion and the counter responding.
• When (CSOT = 1), the counter will not start incrementing until a rising edge is detected on the trigger input.
• When (CSOO= 1), the counter will stop incrementing whenever the TOF flag is set.
The counter does not increment again unless it is disabled, or if CSOT = 1 and a rising edge is detected on the trigger input.
• When (CROT= 1), the counter will reset to zero as if an overflow occurred whenever a rising edge is detected on the trigger input.
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Functional description
31.4.4 Input Capture Mode
The input capture mode is selected when (CPWMS = 0), (MSnB:MSnA = 0:0), and
(ELSnB:ELSnA ≠ 0:0).
When a selected edge occurs on the channel input, the current value of the TPM counter is captured into the CnV register, at the same time the CHnF bit is set and the channel interrupt is generated if enabled by CHnIE = 1 (see the following figure).
When a channel is configured for input capture, the TPM_CHn pin is an edge-sensitive input. ELSnB:ELSnA control bits determine which edge, falling or rising, triggers inputcapture event. Note that the maximum frequency for the channel input signal to be detected correctly is counter clock divided by 4, which is required to meet Nyquist criteria for signal sampling.
Writes to the CnV register are ignored in input capture mode.
was rising edge selected?
CHnIE
CHnF channel (n) interrupt channel (n) input timer module clock
D synchronizer
Q D Q
CLK CLK
0 0 rising edge
1 edge detector falling edge
0
1
0
CnV was falling edge selected?
timer module counter
Figure 31-81. Input capture mode
The CHnF bit is set on the third rising edge of the counter clock after a valid edge occurs on the channel input.
31.4.5 Output Compare Mode
The output compare mode is selected when (CPWMS = 0), and (MSnB:MSnA = X:1).
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Chapter 31 Timer/PWM Module (TPM)
In output compare mode, the TPM can generate timed pulses with programmable position, polarity, duration, and frequency. When the counter matches the value in the
CnV register of an output compare channel, the channel (n) output can be set, cleared or toggled if MSnB is clear. If MSnB is set then the channel (n) output is pulsed high or low for as long as the counter matches the value in the CnV register.
When a channel is initially configured to output compare mode, the channel output updates with its negated value (logic 0 for set/toggle/pulse high and logic one for clear/ pulse low).
The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the channel (n) match (TPM counter = CnV).
MOD = 0x0005
CnV = 0x0003 counter overflow channel (n) match counter overflow channel (n) match counter overflow
CNT ...
0 1 previous value
2 3 4 5 0 1 2 3 4 5 0 1 ...
channel (n) output
CHnF bit
TOF bit previous value
Figure 31-82. Example of the output compare mode when the match toggles the channel output
MOD = 0x0005
CnV = 0x0003 counter overflow channel (n) match counter overflow channel (n) match counter overflow
CNT channel (n) output
...
0 1 previous value
2 3 4 5 0 1 2 3 4 5 0 1 ...
CHnF bit
TOF bit previous value
Figure 31-83. Example of the output compare mode when the match clears the channel output
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Functional description
MOD = 0x0005
CnV = 0x0003 counter overflow channel (n) match counter overflow channel (n) match counter overflow
CNT channel (n) output
...
0 1 previous value
2 3 4 5 0
CHnF bit previous value
1 2 3 4 5 0 1 ...
TOF bit
Figure 31-84. Example of the output compare mode when the match sets the channel output
It is possible to use the output compare mode with (ELSnB:ELSnA = 0:0). In this case, when the counter reaches the value in the CnV register, the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however the channel (n) output is not modified and controlled by TPM.
31.4.6 Edge-Aligned PWM (EPWM) Mode
The edge-aligned mode is selected when (CPWMS = 0), and (MSnB:MSnA = 1:0).
The EPWM period is determined by (MOD + 0x0001) and the pulse width (duty cycle) is determined by CnV.
The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the channel (n) match (TPM counter = CnV), that is, at the end of the pulse width.
This type of PWM signal is called edge-aligned because the leading edges of all PWM signals are aligned with the beginning of the period, which is the same for all channels within an TPM.
counter overflow period pulse width counter overflow counter overflow channel (n) output channel (n) match channel (n) match channel (n) match
Figure 31-85. EPWM period and pulse width with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = 0:0) when the counter reaches the value in the CnV register, the
CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however the channel (n) output is not controlled by TPM.
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Chapter 31 Timer/PWM Module (TPM)
If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the counter overflow (when the zero is loaded into the TPM counter), and it is forced low at the channel (n) match (TPM counter = CnV) (see the following figure).
MOD = 0x0008
CnV = 0x0005 counter overflow channel (n) match counter overflow
CNT channel (n) output
...
0 1 2 3 4 5 6 7 8 0 1 2 ...
CHnF bit
TOF bit previous value
Figure 31-86. EPWM signal with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the counter overflow (when zero is loaded into the TPM counter), and it is forced high at the channel
(n) match (TPM counter = CnV) (see the following figure).
MOD = 0x0008
CnV = 0x0005 counter overflow channel (n) match counter overflow
CNT channel (n) output
...
0 1 2 3 4 5 6 7 8 0 1 2 ...
CHnF bit
TOF bit previous value
Figure 31-87. EPWM signal with ELSnB:ELSnA = X:1
If (CnV = 0x0000), then the channel (n) output is a 0% duty cycle EPWM signal. If (CnV
> MOD), then the channel (n) output is a 100% duty cycle EPWM signal and CHnF bit is not set since there is never a channel (n) match. Therefore, MOD must be less than
0xFFFF in order to get a 100% duty cycle EPWM signal.
31.4.7 Center-Aligned PWM (CPWM) Mode
The center-aligned mode is selected when (CPWMS = 1) and (MSnB:MSnA = 1:0).
The CPWM pulse width (duty cycle) is determined by 2 × CnV and the period is determined by 2 × MOD (see the following figure). MOD must be kept in the range of
0x0001 to 0x7FFF because values outside this range can produce ambiguous results.
In the CPWM mode, the TPM counter counts up until it reaches MOD and then counts down until it reaches zero.
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Functional description
The CHnF bit is set and channel (n) interrupt is generated (if CHnIE = 1) at the channel
(n) match (TPM counter = CnV) when the TPM counting is down (at the begin of the pulse width) and when the TPM counting is up (at the end of the pulse width).
This type of PWM signal is called center-aligned because the pulse width centers for all channels are when the TPM counter is zero.
The other channel modes are not designed to be used with the up-down counter (CPWMS
= 1). Therefore, all TPM channels should be used in CPWM mode when (CPWMS = 1).
counter overflow timer module counter =
MOD timer module counter = 0 channel (n) match
(timer module counting is down) channel (n) match
(timer module counting is up) counter overflow timer module counter =
MOD channel (n) output pulse width
(2 x CnV) period
(2 x MOD)
Figure 31-88. CPWM period and pulse width with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = 0:0) when the TPM counter reaches the value in the CnV register, the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however the channel (n) output is not controlled by TPM.
If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the channel (n) match (TPM counter = CnV) when counting down, and it is forced low at the channel (n) match when counting up (see the following figure).
MOD = 0x0008
CnV = 0x0005 counter overflow channel (n) match in down counting channel (n) match in up counting counter overflow channel (n) match in down counting
CNT channel (n) output
...
7 8 7 previous value CHnF bit
TOF bit
6 5 4 3 2 1 0 1 2 3 4 5 6 7
Figure 31-89. CPWM signal with ELSnB:ELSnA = 1:0
8 7 6 5 ...
If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the channel (n) match (TPM counter = CnV) when counting down, and it is forced high at the channel (n) match when counting up (see the following figure).
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MOD = 0x0008
CnV = 0x0005 counter overflow channel (n) match in down counting
Chapter 31 Timer/PWM Module (TPM) channel (n) match in up counting counter overflow channel (n) match in down counting
CNT channel (n) output
...
7 8
CHnF bit
TOF bit
7 previous value
6 5 4 3 2 1 0 1 2 3 4 5 6 7
Figure 31-90. CPWM signal with ELSnB:ELSnA = X:1
8 7 6 5 ...
If (CnV = 0x0000) then the channel (n) output is a 0% duty cycle CPWM signal.
If (CnV > MOD), then the channel (n) output is a 100% duty cycle CPWM signal, although the CHnF bit is set when the counter changes from incrementing to decrementing. Therefore, MOD must be less than 0xFFFF in order to get a 100% duty cycle CPWM signal.
31.4.8 Registers Updated from Write Buffers
31.4.8.1 MOD Register Update
If (CMOD[1:0] = 0:0) then MOD register is updated when MOD register is written.
If (CMOD[1:0] ≠ 0:0), then MOD register is updated according to the CPWMS bit, that is:
• If the selected mode is not CPWM then MOD register is updated after MOD register was written and the TPM counter changes from MOD to zero.
• If the selected mode is CPWM then MOD register is updated after MOD register was written and the TPM counter changes from MOD to (MOD – 1).
31.4.8.2 CnV Register Update
If (CMOD[1:0] = 0:0) then CnV register is updated when CnV register is written.
If (CMOD[1:0] ≠ 0:0), then CnV register is updated according to the selected mode, that is:
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Functional description
• If the selected mode is output compare then CnV register is updated on the next TPM counter increment (end of the prescaler counting) after CnV register was written.
• If the selected mode is EPWM then CnV register is updated after CnV register was written and the TPM counter changes from MOD to zero.
• If the selected mode is CPWM then CnV register is updated after CnV register was written and the TPM counter changes from MOD to (MOD – 1).
31.4.9 DMA
The channel generates a DMA transfer request according to DMA and CHnIE bits.
See the following table for more information.
Table 31-110. Channel DMA Transfer Request
DMA
0
0
1
1
CHnIE Channel DMA Transfer Request
0
1
0
1
The channel DMA transfer request is not generated.
Channel Interrupt
The channel interrupt is not generated.
The channel DMA transfer request is not generated.
The channel DMA transfer request is generated if
(CHnF = 1).
The channel interrupt is generated if (CHnF = 1).
The channel interrupt is not generated.
The channel DMA transfer request is generated if
(CHnF = 1).
The channel interrupt is generated if (CHnF = 1).
If DMA = 1, the CHnF bit can be cleared either by channel DMA transfer done or writing a one to CHnF bit (see the following table).
DMA
0
1
Table 31-111. Clear CHnF Bit
How CHnF Bit Can Be Cleared
CHnF bit is cleared by writing a 1 to CHnF bit.
CHnF bit is cleared either when the channel DMA transfer is done or by writing a 1 to CHnF bit.
31.4.10 Output triggers
The TPM generates output triggers for the counter and each channel that can be used to trigger events in other peripherals.
The counter trigger asserts whenever the TOF is set and remains asserted until the next increment.
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Chapter 31 Timer/PWM Module (TPM)
Each TPM channel generates both a pre-trigger output and a trigger output. The pretrigger output asserts whenever the CHnF is set, the trigger output asserts on the first counter increment after the pre-trigger asserts, and then both the trigger and pre-trigger negate on the first counter increment after the trigger asserts.
31.4.11 Reset Overview
The TPM is reset whenever any chip reset occurs.
When the TPM exits from reset:
• the TPM counter and the prescaler counter are zero and are stopped (CMOD[1:0] =
0:0);
• the timer overflow interrupt is zero;
• the channels interrupts are zero;
• the channels are in input capture mode;
• the channels outputs are zero;
• the channels pins are not controlled by TPM (ELS(n)B:ELS(n)A = 0:0).
31.4.12 TPM Interrupts
This section describes TPM interrupts.
31.4.12.1 Timer Overflow Interrupt
The timer overflow interrupt is generated when (TOIE = 1) and (TOF = 1).
31.4.12.2 Channel (n) Interrupt
The channel (n) interrupt is generated when (CHnIE = 1) and (CHnF = 1).
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Chapter 32
Periodic interrupt timer (PIT)
The periodic interrupt timer (PIT) module consists of an array of timers that can be used to generate interrupts and trigger DMA channels.
32.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
The PIT module is an array of timers that can be used to raise interrupts and trigger DMA channels.
32.1.1 Block diagram
The following figure shows the block diagram of the PIT module.
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Signal description
Peripheral bus
Iinterrupts
Triggers
PIT
PIT registers load_value
Timer 1
Timer n
Peripheral bus clock
Figure 32-1. Block diagram of the PIT
NOTE
See the chip configuration details for the number of PIT channels used in this MCU.
32.1.2 Features
The main features of this block are:
• Ability of timers to generate DMA trigger pulses
• Ability of timers to generate interrupts
• Maskable interrupts
• Independent timeout periods for each timer
32.2 Signal description
The PIT module has no external pins.
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Chapter 32 Periodic interrupt timer (PIT)
32.3 Memory map/register description
This section provides a detailed description of all registers accessible in the PIT module.
• Reserved registers will read as 0, writes will have no effect.
• See the chip configuration details for the number of PIT channels used in this MCU.
PIT memory map
Absolute address
(hex)
Register name
4003_7000 PIT Module Control Register (PIT_MCR)
4003_70E0 PIT Upper Lifetime Timer Register (PIT_LTMR64H)
4003_70E4 PIT Lower Lifetime Timer Register (PIT_LTMR64L)
4003_7100 Timer Load Value Register (PIT_LDVAL0)
4003_7104 Current Timer Value Register (PIT_CVAL0)
4003_7108 Timer Control Register (PIT_TCTRL0)
4003_710C Timer Flag Register (PIT_TFLG0)
4003_7110 Timer Load Value Register (PIT_LDVAL1)
4003_7114 Current Timer Value Register (PIT_CVAL1)
4003_7118 Timer Control Register (PIT_TCTRL1)
4003_711C Timer Flag Register (PIT_TFLG1)
Width
(in bits)
Access Reset value
32
32
32
32
32
32
32
32
32
32
32
R/W
R
R
R/W
R
R/W
R/W
R/W
R
R/W
R/W
Section/ page
0000_0006h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
32.3.1 PIT Module Control Register (PIT_MCR)
This register enables or disables the PIT timer clocks and controls the timers when the
PIT enters the Debug mode.
Address: 4003_7000h base + 0h offset = 4003_7000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Memory map/register description
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0
Field
31–3
Reserved
2
Reserved
1
MDIS
0 0 0 0 0 0 0 0 0
PIT_MCR field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
0
0
FRZ
0 0
Module Disable - (PIT section)
Disables the standard timers. This field must be enabled before any other setup is done.
0 Clock for standard PIT timers is enabled.
1 Clock for standard PIT timers is disabled.
Freeze
Allows the timers to be stopped when the device enters the Debug mode.
0 Timers continue to run in Debug mode.
1 Timers are stopped in Debug mode.
1 1 0
32.3.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H)
This register is intended for applications that chain timer 0 and timer 1 to build a 64-bit lifetimer.
Address: 4003_7000h base + E0h offset = 4003_70E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Field
31–0
LTH
Chapter 32 Periodic interrupt timer (PIT)
PIT_LTMR64H field descriptions
Description
Life Timer value
Shows the timer value of timer 1. If this register is read at a time t1, LTMR64L shows the value of timer 0 at time t1.
32.3.3 PIT Lower Lifetime Timer Register (PIT_LTMR64L)
This register is intended for applications that chain timer 0 and timer 1 to build a 64-bit lifetimer.
To use LTMR64H and LTMR64L, timer 0 and timer 1 need to be chained. To obtain the correct value, first read LTMR64H and then LTMR64L. LTMR64H will have the value of CVAL1 at the time of the first access, LTMR64L will have the value of CVAL0 at the time of the first access, therefore the application does not need to worry about carry-over effects of the running counter.
Address: 4003_7000h base + E4h offset = 4003_70E4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
LTL
PIT_LTMR64L field descriptions
Description
Life Timer value
Shows the value of timer 0 at the time LTMR64H was last read. It will only update if LTMR64H is read.
32.3.4 Timer Load Value Register (PIT_LDVALn)
These registers select the timeout period for the timer interrupts.
Address: 4003_7000h base + 100h offset + (16d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Memory map/register description
Field
31–0
TSV
PIT_LDVALn field descriptions
Description
Timer Start Value
Sets the timer start value. The timer will count down until it reaches 0, then it will generate an interrupt and load this register value again. Writing a new value to this register will not restart the timer; instead the value will be loaded after the timer expires. To abort the current cycle and start a timer period with the new value, the timer must be disabled and enabled again.
32.3.5 Current Timer Value Register (PIT_CVALn)
These registers indicate the current timer position.
Address: 4003_7000h base + 104h offset + (16d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
TVL
PIT_CVALn field descriptions
Description
Current Timer Value
Represents the current timer value, if the timer is enabled.
NOTE: • If the timer is disabled, do not use this field as its value is unreliable.
• The timer uses a downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is set.
32.3.6 Timer Control Register (PIT_TCTRLn)
These registers contain the control bits for each timer.
Address: 4003_7000h base + 108h offset + (16d × i), where i=0d to 1d
Bit
R
W
Reset
31
0
30
0
29
0
28
0
27
0
26
0
25
0
24
0
23
0
Bit
R
W
Reset
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
22
0
6
0
21
0
0
5
20
0
0
4
19 18 17 16
0
3
0
0 0 0
2 1 0
0 0 0
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Field
31–3
Reserved
2
CHN
1
TIE
0
TEN
Chapter 32 Periodic interrupt timer (PIT)
PIT_TCTRLn field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Chain Mode
When activated, Timer n-1 needs to expire before timer n can decrement by 1.
Timer 0 cannot be chained.
0 Timer is not chained.
1 Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to
Timer 1.
Timer Interrupt Enable
When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt will immediately cause an interrupt event. To avoid this, the associated TFLGn[TIF] must be cleared first.
0 Interrupt requests from Timer n are disabled.
1 Interrupt will be requested whenever TIF is set.
Timer Enable
Enables or disables the timer.
0 Timer n is disabled.
1 Timer n is enabled.
32.3.7 Timer Flag Register (PIT_TFLGn)
These registers hold the PIT interrupt flags.
Address: 4003_7000h base + 10Ch offset + (16d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23
R
W
Reset 0 0 0 0 0 0 0 0 0
Bit
R
W
Reset
15
0
14 13 12 11 10 9 8
7
Field
31–1
Reserved
22
0
6
21
0 0 0 0 0 0 0 0 0
PIT_TFLGn field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
0
0
5
20
0
0
4
19 18 17 16
0
3
0
0
2
0
0
1
0
0
0
0
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Functional description
Field
0
TIF
PIT_TFLGn field descriptions (continued)
Description
Timer Interrupt Flag
Sets to 1 at the end of the timer period. Writing 1 to this flag clears it. Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an interrupt request.
0 Timeout has not yet occurred.
1 Timeout has occurred.
32.4 Functional description
This section provides the functional description of the module.
32.4.1 General operation
This section gives detailed information on the internal operation of the module. Each timer can be used to generate trigger pulses and interrupts. Each interrupt is available on a separate interrupt line.
32.4.1.1 Timers
The timers generate triggers at periodic intervals, when enabled. The timers load the start values as specified in their LDVAL registers, count down to 0 and then load the respective start value again. Each time a timer reaches 0, it will generate a trigger pulse and set the interrupt flag.
All interrupts can be enabled or masked by setting TCTRLn[TIE]. A new interrupt can be generated only after the previous one is cleared.
If desired, the current counter value of the timer can be read via the CVAL registers.
The counter period can be restarted, by first disabling, and then enabling the timer with
TCTRLn[TEN]. See the following figure.
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Timer enabled
Start value = p1
Disable timer
Re-enable timer
Chapter 32 Periodic interrupt timer (PIT)
Trigger event p1 p1 p1 p1
Figure 32-17. Stopping and starting a timer
The counter period of a running timer can be modified, by first disabling the timer, setting a new load value, and then enabling the timer again. See the following figure.
Timer enabled
Start value = p1
Disable timer,
Set new load value
Re-enable timer
Trigger event p1 p2 p1
Figure 32-18. Modifying running timer period p2 p2
It is also possible to change the counter period without restarting the timer by writing
LDVAL with the new load value. This value will then be loaded after the next trigger event. See the following figure.
Timer enabled
Start value = p1
New start
Value p2 set
Trigger event p1 p1 p1 p2 p2
Figure 32-19. Dynamically setting a new load value
32.4.1.2 Debug mode
In Debug mode, the timers will be frozen based on MCR[FRZ]. This is intended to aid software development, allowing the developer to halt the processor, investigate the current state of the system, for example, the timer values, and then continue the operation.
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Initialization and application information
32.4.2 Interrupts
All the timers support interrupt generation. See the MCU specification for related vector addresses and priorities.
Timer interrupts can be enabled by setting TCTRLn[TIE]. TFLGn[TIF] are set to 1 when a timeout occurs on the associated timer, and are cleared to 0 by writing a 1 to the corresponding TFLGn[TIF].
32.4.3 Chained timers
When a timer has chain mode enabled, it will only count after the previous timer has expired. So if timer n-1 has counted down to 0, counter n will decrement the value by one. This allows to chain some of the timers together to form a longer timer. The first timer (timer 0) cannot be chained to any other timer.
32.5 Initialization and application information
In the example configuration:
• The PIT clock has a frequency of 50 MHz.
• Timer 1 creates an interrupt every 5.12 ms.
• Timer 3 creates a trigger event every 30 ms.
The PIT module must be activated by writing a 0 to MCR[MDIS].
The 50 MHz clock frequency equates to a clock period of 20 ns. Timer 1 needs to trigger every 5.12 ms/20 ns = 256,000 cycles and Timer 3 every 30 ms/20 ns = 1,500,000 cycles.
The value for the LDVAL register trigger is calculated as:
LDVAL trigger = (period / clock period) -1
This means LDVAL1 and LDVAL3 must be written with 0x0003E7FF and 0x0016E35F respectively.
The interrupt for Timer 1 is enabled by setting TCTRL1[TIE]. The timer is started by writing 1 to TCTRL1[TEN].
Timer 3 shall be used only for triggering. Therefore, Timer 3 is started by writing a 1 to
TCTRL3[TEN]. TCTRL3[TIE] stays at 0.
The following example code matches the described setup:
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Chapter 32 Periodic interrupt timer (PIT)
// turn on PIT
PIT_MCR = 0x00;
// Timer 1
PIT_LDVAL1 = 0x0003E7FF; // setup timer 1 for 256000 cycles
PIT_TCTRL1 = TIE; // enable Timer 1 interrupts
PIT_TCTRL1 |= TEN; // start Timer 1
// Timer 3
PIT_LDVAL3 = 0x0016E35F; // setup timer 3 for 1500000 cycles
PIT_TCTRL3 |= TEN; // start Timer 3
32.6 Example configuration for chained timers
In the example configuration:
• The PIT clock has a frequency of 100 MHz.
• Timers 1 and 2 are available.
• An interrupt shall be raised every 1 hour.
The PIT module needs to be activated by writing a 0 to MCR[MDIS].
The 100 MHz clock frequency equates to a clock period of 10 ns, so the PIT needs to count for 6000 million cycles, which is more than a single timer can do. So, Timer 1 is set up to trigger every 6 s (600 million cycles). Timer 2 is chained to Timer 1 and programmed to trigger 10 times.
The value for the LDVAL register trigger is calculated as number of cycles-1, so
LDVAL1 receives the value 0x23C345FF and LDVAL2 receives the value 0x00000009.
The interrupt for Timer 2 is enabled by setting TCTRL2[TIE], the Chain mode is activated by setting TCTRL2[CHN], and the timer is started by writing a 1 to
TCTRL2[TEN]. TCTRL1[TEN] needs to be set, and TCTRL1[CHN] and TCTRL1[TIE] are cleared.
The following example code matches the described setup:
// turn on PIT
PIT_MCR = 0x00;
// Timer 2
PIT_LDVAL2 = 0x00000009; // setup Timer 2 for 10 counts
PIT_TCTRL2 = TIE; // enable Timer 2 interrupt
PIT_TCTRL2 |= CHN; // chain Timer 2 to Timer 1
PIT_TCTRL2 |= TEN; // start Timer 2
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Example configuration for the lifetime timer
// Timer 1
PIT_LDVAL1 = 0x23C345FF; // setup Timer 1 for 600 000 000 cycles
PIT_TCTRL1 = TEN; // start Timer 1
32.7 Example configuration for the lifetime timer
To configure the lifetimer timer, channels 0 and 1 need to be chained together.
First the PIT module needs to be activated by writing a 0 to the MDIS bit in the CTRL register, then the LDVAL registers need to be set to the maximum value.
The timer is a downcounter.
The following example code matches the described setup:
// turn on PIT
PIT_MCR = 0x00;
// Timer 1
PIT_LDVAL1 = 0xFFFFFFFF; // setup timer 1 for maximum counting period
PIT_TCTRL1 = 0x0; // disable timer 1 interrupts
PIT_TCTRL1 |= CHN; // chain timer 1 to timer 0
PIT_TCTRL1 |= TEN; // start timer 1
// Timer 0
PIT_LDVAL0 = 0xFFFFFFFF; // setup timer 0 for maximum counting period
PIT_TCTRL0 = TEN; // start timer 0
To access the lifetime, read first LTMR64H and then LTMR64L.
current_uptime = PIT_LTMR64H<<32;
current_uptime = current_uptime + PIT_LTMR64L;
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Chapter 33
Low-power timer (LPTMR)
The low-power timer (LPTMR) can be configured to operate as a time counter (with optional prescaler) or as a pulse counter (with optional glitch filter) across all power modes, including the low leakage modes.
33.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
The low-power timer (LPTMR) can be configured to operate as a time counter with optional prescaler, or as a pulse counter with optional glitch filter, across all power modes, including the low-leakage modes. It can also continue operating through most system reset events, allowing it to be used as a time of day counter.
33.1.1 Features
The features of the LPTMR module include:
• 16-bit time counter or pulse counter with compare
• Optional interrupt can generate asynchronous wakeup from any low-power mode
• Hardware trigger output
• Counter supports free-running mode or reset on compare
• Configurable clock source for prescaler/glitch filter
• Configurable input source for pulse counter
• Rising-edge or falling-edge
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LPTMR signal descriptions
33.1.2 Modes of operation
The following table describes the operation of the LPTMR module in various modes.
Modes
Run
Wait
Stop
Debug
Table 33-1. Modes of operation
Low-Leakage
Description
The LPTMR operates normally.
The LPTMR continues to operate normally and may be configured to exit the low-power mode by generating an interrupt request.
The LPTMR continues to operate normally and may be configured to exit the low-power mode by generating an interrupt request.
The LPTMR continues to operate normally and may be configured to exit the low-power mode by generating an interrupt request.
The LPTMR operates normally in Pulse Counter mode, but counter does not increment in Time
Counter mode.
33.2 LPTMR signal descriptions
Table 33-2. LPTMR signal descriptions
Signal
LPTMR_ALT n
I/O
I
Description
Pulse Counter Input pin
33.2.1 Detailed signal descriptions
Table 33-3. LPTMR interface—detailed signal descriptions
Signal
LPTMR_ALT n
I/O
I Pulse Counter Input
Description
The LPTMR can select one of the input pins to be used in Pulse Counter mode.
State meaning Assertion—If configured for pulse counter mode with active-high input, then assertion causes the CNR to increment.
Timing
Deassertion—If configured for pulse counter mode with active-low input, then deassertion causes the CNR to increment.
Assertion or deassertion may occur at any time; input may assert asynchronously to the bus clock.
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Chapter 33 Low-power timer (LPTMR)
33.3 Memory map and register definition
LPTMR memory map
Absolute address
(hex)
Register name
4004_0000 Low Power Timer Control Status Register (LPTMR0_CSR)
4004_0004 Low Power Timer Prescale Register (LPTMR0_PSR)
4004_0008 Low Power Timer Compare Register (LPTMR0_CMR)
4004_000C Low Power Timer Counter Register (LPTMR0_CNR)
Width
(in bits)
Access Reset value
32
32
32
32
R/W
R/W
R/W
R
Section/ page
0000_0000h
0000_0000h
0000_0000h
0000_0000h
33.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)
Address: 4004_0000h base + 0h offset = 4004_0000h
Bit
R
31 30 29 28 27 26 25
W
Reset 0 0 0 0 0 0 0
Bit
R
W
Reset
15
Field
31–8
Reserved
7
TCF
6
TIE
0
5–4
TPS
14
0
13
0
12
0
11
0
10
0
9
0
24
0
8
0
23
0
7
0
22
0
6
0
21
LPTMRx_CSR field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Timer Compare Flag
0
5
0
20
0
4
0
19
0
3
18
0
17
0
16
0
0
2
0
1
0
TCF is set when the LPTMR is enabled and the CNR equals the CMR and increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
0 The value of CNR is not equal to CMR and increments.
1 The value of CNR is equal to CMR and increments.
Timer Interrupt Enable
When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
0 Timer interrupt disabled.
1 Timer interrupt enabled.
Timer Pin Select
0
0
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Memory map and register definition
LPTMRx_CSR field descriptions (continued)
Field Description
Configures the input source to be used in Pulse Counter mode. TPS must be altered only when the
LPTMR is disabled. The input connections vary by device. See the chip configuration details for information on the connections to these inputs.
3
TPP
2
TFC
1
TMS
0
TEN
00 Pulse counter input 0 is selected.
01 Pulse counter input 1 is selected.
10 Pulse counter input 2 is selected.
11 Pulse counter input 3 is selected.
Timer Pin Polarity
Configures the polarity of the input source in Pulse Counter mode. TPP must be changed only when the
LPTMR is disabled.
0 Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
1 Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
Timer Free-Running Counter
When clear, TFC configures the CNR to reset whenever TCF is set. When set, TFC configures the CNR to reset on overflow. TFC must be altered only when the LPTMR is disabled.
0 CNR is reset whenever TCF is set.
1 CNR is reset on overflow.
Timer Mode Select
Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is disabled.
0 Time Counter mode.
1 Pulse Counter mode.
Timer Enable
When TEN is clear, it resets the LPTMR internal logic, including the CNR and TCF. When TEN is set, the
LPTMR is enabled. While writing 1 to this field, CSR[5:1] must not be altered.
0 LPTMR is disabled and internal logic is reset.
1 LPTMR is enabled.
33.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)
Address: 4004_0000h base + 4h offset = 4004_0004h
31 30 29 28 27 26 Bit
R
W
Reset 0 0 0 0 0 0
25
0
Bit
R
W
Reset
15
0
14
0
13
0
12
0
11
0
10
0
9
0
0
8
24
23
0
0
7
0
22
0
6
0
21 20
0 0
5 4
0 0
19
0
3
0
18
0
2
0
17 16
0
1
0
0
0 0
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Field
31–7
Reserved
6–3
PRESCALE
2
PBYP
1–0
PCS
LPTMRx_PSR field descriptions
Chapter 33 Low-power timer (LPTMR)
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Prescale Value
Configures the size of the Prescaler in Time Counter mode or width of the glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR is disabled.
0000 Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.
0001 Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.
0010 Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.
0011 Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.
0100 Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.
0101 Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.
0110 Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.
0111 Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.
1000 Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.
1001 Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.
1010 Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after
1024 rising clock edges.
1011 Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after
2048 rising clock edges.
1100 Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after
4096 rising clock edges.
1101 Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after
8192 rising clock edges.
1110 Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after
16,384 rising clock edges.
1111 Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after
32,768 rising clock edges.
Prescaler Bypass
When PBYP is set, the selected prescaler clock in Time Counter mode or selected input source in Pulse
Counter mode directly clocks the CNR. When PBYP is clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP must be altered only when the LPTMR is disabled.
0 Prescaler/glitch filter is enabled.
1 Prescaler/glitch filter is bypassed.
Prescaler Clock Select
Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must be altered only when the
LPTMR is disabled. The clock connections vary by device.
NOTE: See the chip configuration details for information on the connections to these inputs.
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Memory map and register definition
LPTMRx_PSR field descriptions (continued)
Field Description
00 Prescaler/glitch filter clock 0 selected.
01 Prescaler/glitch filter clock 1 selected.
10 Prescaler/glitch filter clock 2 selected.
11 Prescaler/glitch filter clock 3 selected.
33.3.3 Low Power Timer Compare Register (LPTMRx_CMR)
Address: 4004_0000h base + 8h offset = 4004_0008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–16
Reserved
15–0
COMPARE
LPTMRx_CMR field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Compare Value
When the LPTMR is enabled and the CNR equals the value in the CMR and increments, TCF is set and the hardware trigger asserts until the next time the CNR increments. If the CMR is 0, the hardware trigger will remain asserted until the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only when TCF is set.
33.3.4 Low Power Timer Counter Register (LPTMRx_CNR)
Address: 4004_0000h base + Ch offset = 4004_000Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–16
Reserved
15–0
COUNTER
LPTMRx_CNR field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Counter Value
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Chapter 33 Low-power timer (LPTMR)
33.4 Functional description
33.4.1 LPTMR power and reset
The LPTMR remains powered in all power modes, including low-leakage modes. If the
LPTMR is not required to remain operating during a low-power mode, then it must be disabled before entering the mode.
The LPTMR is reset only on global Power On Reset (POR) or Low Voltage Detect
(LVD). When configuring the LPTMR registers, the CSR must be initially written with the timer disabled, before configuring the PSR and CMR. Then, CSR[TIE] must be set as the last step in the initialization. This ensures the LPTMR is configured correctly and the
LPTMR counter is reset to zero following a warm reset.
33.4.2 LPTMR clocking
The LPTMR prescaler/glitch filter can be clocked by one of the four clocks. The clock source must be enabled before the LPTMR is enabled.
NOTE
The clock source selected may need to be configured to remain enabled in low-power modes, otherwise the LPTMR will not operate during low-power modes.
In Pulse Counter mode with the prescaler/glitch filter bypassed, the selected input source directly clocks the CNR and no other clock source is required. To minimize power in this case, configure the prescaler clock source for a clock that is not toggling.
NOTE
The clock source or pulse input source selected for the LPTMR should not exceed the frequency f
LPTMR datasheet.
defined in the device
33.4.3 LPTMR prescaler/glitch filter
The LPTMR prescaler and glitch filter share the same logic which operates as a prescaler in Time Counter mode and as a glitch filter in Pulse Counter mode.
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Functional description
NOTE
The prescaler/glitch filter configuration must not be altered when the LPTMR is enabled.
33.4.3.1 Prescaler enabled
In Time Counter mode, when the prescaler is enabled, the output of the prescaler directly clocks the CNR. When the LPTMR is enabled, the CNR will increment every 2 2 to 2 16 prescaler clock cycles. After the LPTMR is enabled, the first increment of the CNR will take an additional one or two prescaler clock cycles due to synchronization logic.
33.4.3.2 Prescaler bypassed
In Time Counter mode, when the prescaler is bypassed, the selected prescaler clock increments the CNR on every clock cycle. When the LPTMR is enabled, the first increment will take an additional one or two prescaler clock cycles due to synchronization logic.
33.4.3.3 Glitch filter
In Pulse Counter mode, when the glitch filter is enabled, the output of the glitch filter directly clocks the CNR. When the LPTMR is first enabled, the output of the glitch filter is asserted, that is, logic 1 for active-high and logic 0 for active-low. The following table shows the change in glitch filter output with the selected input source.
If
The selected input source remains deasserted for at least 2 1 to 2 15 consecutive prescaler clock rising edges
The selected input source remains asserted for at least 2 1
2 15 consecutive prescaler clock rising-edges
to
Then
The glitch filter output will also deassert.
The glitch filter output will also assert.
NOTE
The input is only sampled on the rising clock edge.
The CNR will increment each time the glitch filter output asserts. In Pulse Counter mode, the maximum rate at which the CNR can increment is once every 2 2 to 2 16 prescaler clock edges. When first enabled, the glitch filter will wait an additional one or two prescaler clock edges due to synchronization logic.
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Chapter 33 Low-power timer (LPTMR)
33.4.3.4 Glitch filter bypassed
In Pulse Counter mode, when the glitch filter is bypassed, the selected input source increments the CNR every time it asserts. Before the LPTMR is first enabled, the selected input source is forced to be asserted. This prevents the CNR from incrementing if the selected input source is already asserted when the LPTMR is first enabled.
33.4.4 LPTMR compare
When the CNR equals the value of the CMR and increments, the following events occur:
• CSR[TCF] is set.
• LPTMR interrupt is generated if CSR[TIE] is also set.
• LPTMR hardware trigger is generated.
• CNR is reset if CSR[TFC] is clear.
When the LPTMR is enabled, the CMR can be altered only when CSR[TCF] is set. When updating the CMR, the CMR must be written and CSR[TCF] must be cleared before the
LPTMR counter has incremented past the new LPTMR compare value.
33.4.5 LPTMR counter
The CNR increments by one on every:
• Prescaler clock in Time Counter mode with prescaler bypassed
• Prescaler output in Time Counter mode with prescaler enabled
• Input source assertion in Pulse Counter mode with glitch filter bypassed
• Glitch filter output in Pulse Counter mode with glitch filter enabled
The CNR is reset when the LPTMR is disabled or if the counter register overflows. If
CSR[TFC] is cleared, then the CNR is also reset whenever CSR[TCF] is set.
The CNR continues incrementing when the core is halted in Debug mode when configured for Pulse Counter mode, the CNR will stop incrementing when the core is halted in Debug mode when configured for Time Counter mode.
The CNR cannot be initialized, but can be read at any time. On each read of the CNR, software must first write to the CNR with any value. This will synchronize and register the current value of the CNR into a temporary register. The contents of the temporary register are returned on each read of the CNR.
When reading the CNR, the bus clock must be at least two times faster than the rate at which the LPTMR counter is incrementing, otherwise incorrect data may be returned.
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33.4.6 LPTMR hardware trigger
The LPTMR hardware trigger asserts at the same time the CSR[TCF] is set and can be used to trigger hardware events in other peripherals without software intervention. The hardware trigger is always enabled.
When
The CMR is set to 0 with CSR[TFC] clear
The CMR is set to a nonzero value, or, if CSR[TFC] is set
Then
The LPTMR hardware trigger will assert on the first compare and does not deassert.
The LPTMR hardware trigger will assert on each compare and deassert on the following increment of the CNR.
33.4.7 LPTMR interrupt
The LPTMR interrupt is generated whenever CSR[TIE] and CSR[TCF] are set.
CSR[TCF] is cleared by disabling the LPTMR or by writing a logic 1 to it.
CSR[TIE] can be altered and CSR[TCF] can be cleared while the LPTMR is enabled.
The LPTMR interrupt is generated asynchronously to the system clock and can be used to generate a wakeup from any low-power mode, including the low-leakage modes, provided the LPTMR is enabled as a wakeup source.
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Chapter 34
Real Time Clock (RTC)
The Real Time Clock (RTC) presents a detail description about the features of RTC that operates in one of two modes of operation—chip power-up and chip power-down.
34.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
34.1.1 Features
The RTC module features include:
• 32-bit seconds counter with roll-over protection and 32-bit alarm
• 16-bit prescaler with compensation that can correct errors between 0.12 ppm and
3906 ppm
• Register write protection
• Lock register requires POR or software reset to enable write access
• 1 Hz square wave output
34.1.2 Modes of operation
The RTC remains functional in all low power modes and can generate an interrupt to exit any low power mode.
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Register definition
34.1.3 RTC signal descriptions
Table 34-1. RTC signal descriptions
Signal
RTC_CLKOUT
Description
1 Hz square-wave output
I/O
O
34.1.3.1 RTC clock output
The clock to the seconds counter is available on the RTC_CLKOUT signal. It is a 1 Hz square wave output.
34.2 Register definition
All registers must be accessed using 32-bit writes and all register accesses incur three wait states.
Write accesses to any register by non-supervisor mode software, when the supervisor access bit in the control register is clear, will terminate with a bus error.
Read accesses by non-supervisor mode software complete as normal.
Writing to a register protected by the lock register does not generate a bus error, but the write will not complete.
RTC memory map
Absolute address
(hex)
Register name
4003_D000 RTC Time Seconds Register (RTC_TSR)
4003_D004 RTC Time Prescaler Register (RTC_TPR)
4003_D008 RTC Time Alarm Register (RTC_TAR)
4003_D00C RTC Time Compensation Register (RTC_TCR)
4003_D010 RTC Control Register (RTC_CR)
4003_D014 RTC Status Register (RTC_SR)
4003_D018 RTC Lock Register (RTC_LR)
4003_D01C RTC Interrupt Enable Register (RTC_IER)
Width
(in bits)
Access Reset value
32
32
32
32
32
32
32
32
Section/ page
R/W
R/W
R/W
R/W
0000_0000h
0000_0000h
0000_0000h
0000_0000h
R/W
R/W
0000_0000h
0000_0001h
R/W 0000_00FFh
R/W 0000_0007h
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34.2.1 RTC Time Seconds Register (RTC_TSR)
Address: 4003_D000h base + 0h offset = 4003_D000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
TSR
Time Seconds Register
RTC_TSR field descriptions
Description
When the time counter is enabled, the TSR is read only and increments once a second provided SR[TOF] or SR[TIF] are not set. The time counter will read as zero when SR[TOF] or SR[TIF] are set. When the time counter is disabled, the TSR can be read or written. Writing to the TSR when the time counter is disabled will clear the SR[TOF] and/or the SR[TIF]. Writing to TSR with zero is supported, but not recommended because TSR will read as zero when SR[TIF] or SR[TOF] are set (indicating the time is invalid).
34.2.2 RTC Time Prescaler Register (RTC_TPR)
Address: 4003_D000h base + 4h offset = 4003_D004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–16
Reserved
15–0
TPR
RTC_TPR field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Time Prescaler Register
When the time counter is enabled, the TPR is read only and increments every 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or SR[TIF] are set. When the time counter is disabled, the
TPR can be read or written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one to a logic zero.
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34.2.3 RTC Time Alarm Register (RTC_TAR)
Address: 4003_D000h base + 8h offset = 4003_D008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_TAR field descriptions
Description Field
31–0
TAR
Time Alarm Register
When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR] equals the TSR[TSR] and the TSR[TSR] increments. Writing to the TAR clears the SR[TAF].
34.2.4 RTC Time Compensation Register (RTC_TCR)
Address: 4003_D000h base + Ch offset = 4003_D00Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–24
CIC
23–16
TCV
15–8
CIR
RTC_TCR field descriptions
Description
Compensation Interval Counter
Current value of the compensation interval counter. If the compensation interval counter equals zero then it is loaded with the contents of the CIR. If the CIC does not equal zero then it is decremented once a second.
Time Compensation Value
Current value used by the compensation logic for the present second interval. Updated once a second if the CIC equals 0 with the contents of the TCR field. If the CIC does not equal zero then it is loaded with zero (compensation is not enabled for that second increment).
Compensation Interval Register
7–0
TCR
Configures the compensation interval in seconds from 1 to 256 to control how frequently the TCR should adjust the number of 32.768 kHz cycles in each second. The value written should be one less than the number of seconds. For example, write zero to configure for a compensation interval of one second. This register is double buffered and writes do not take affect until the end of the current compensation interval.
Time Compensation Register
Configures the number of 32.768 kHz clock cycles in each second. This register is double buffered and writes do not take affect until the end of the current compensation interval.
Table continues on the next page...
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Field
Chapter 34 Real Time Clock (RTC)
RTC_TCR field descriptions (continued)
Description
80h Time Prescaler Register overflows every 32896 clock cycles.
...
...
FFh Time Prescaler Register overflows every 32769 clock cycles.
00h Time Prescaler Register overflows every 32768 clock cycles.
01h Time Prescaler Register overflows every 32767 clock cycles.
...
...
7Fh Time Prescaler Register overflows every 32641 clock cycles.
34.2.5 RTC Control Register (RTC_CR)
Address: 4003_D000h base + 10h offset = 4003_D010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R
W 0
Reset 0
Field
31–15
Reserved
0 0 0 0 0 0 0 0 0
RTC_CR field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
0 0 0 0 0 0
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Register definition
Field
14
Reserved
13
SC2P
RTC_CR field descriptions (continued)
Description
This field is reserved.
It must always be written to 0.
Oscillator 2pF Load Configure
12
SC4P
0 Disable the load.
1 Enable the additional load.
Oscillator 4pF Load Configure
11
SC8P
0 Disable the load.
1 Enable the additional load.
Oscillator 8pF Load Configure
10
SC16P
0 Disable the load.
1 Enable the additional load.
Oscillator 16pF Load Configure
9
CLKO
0 Disable the load.
1 Enable the additional load.
Clock Output
8
OSCE
0 The 32 kHz clock is output to other peripherals.
1 The 32 kHz clock is not output to other peripherals.
Oscillator Enable
7–5
Reserved
4
WPS
0 32.768 kHz oscillator is disabled.
1 32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.
This field is reserved.
This read-only field is reserved and always has the value 0.
Wakeup Pin Select
The wakeup pin is optional and not available on all devices.
3
UM
2
SUP
1
WPE
0 Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on.
1 Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the
32kHz clock is output to other peripherals.
Update Mode
Allows SR[TCE] to be written even when the Status Register is locked. When set, the SR[TCE] can always be written if the SR[TIF] or SR[TOF] are set or if the SR[TCE] is clear.
0 Registers cannot be written when locked.
1 Registers can be written when locked under limited conditions.
Supervisor Access
0 Non-supervisor mode write accesses are not supported and generate a bus error.
1 Non-supervisor mode write accesses are supported.
Wakeup Pin Enable
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Field
0
SWR
RTC_CR field descriptions (continued)
Chapter 34 Real Time Clock (RTC)
Description
The wakeup pin is optional and not available on all devices.
0 Wakeup pin is disabled.
1 Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.
Software Reset
0 No effect.
1 Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it.
34.2.6 RTC Status Register (RTC_SR)
Address: 4003_D000h base + 14h offset = 4003_D014h
Bit
R
31 30 29 28 27 26 25
W
Reset 0 0 0 0 0 0 0
Bit
R
W
Reset
15
0
14 13 12 11 10
9
Field
31–5
Reserved
4
TCE
3
Reserved
2
TAF
24
0
8
23
0
7
22
0
6
21
0
5
20
0
4
19
0
3
18 17 16
0 0 0
2 1 0
0 0 0 0 0 0 0 0 0
RTC_SR field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Time Counter Enable
0 0 0 0 0 1
When time counter is disabled the TSR register and TPR register are writeable, but do not increment.
When time counter is enabled the TSR register and TPR register are not writeable, but increment.
0 Time counter is disabled.
1 Time counter is enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
Time Alarm Flag
Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR] increments. This bit is cleared by writing the TAR register.
0 Time alarm has not occurred.
1 Time alarm has occurred.
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Register definition
Field
1
TOF
RTC_SR field descriptions (continued)
Description
Time Overflow Flag
Time overflow flag is set when the time counter is enabled and overflows. The TSR and TPR do not increment and read as zero when this bit is set. This bit is cleared by writing the TSR register when the time counter is disabled.
0
TIF
0 Time overflow has not occurred.
1 Time overflow has occurred and time counter is read as zero.
Time Invalid Flag
The time invalid flag is set on POR or software reset. The TSR and TPR do not increment and read as zero when this bit is set. This bit is cleared by writing the TSR register when the time counter is disabled.
0 Time is valid.
1 Time is invalid and time counter is read as zero.
34.2.7 RTC Lock Register (RTC_LR)
Address: 4003_D000h base + 18h offset = 4003_D018h
31 30 29 28 27 26 25 Bit
R
W
Reset 0 0 0 0 0 0 0
Bit
R
W
Reset
15
0
Field
31–8
Reserved
7
Reserved
6
LRL
5
SRL
14
0
13 12
11 10 9
24
0
8
23
0
7
22
0
21
0
20
0
19
0
6 5 4 3
1 1 1 1 0 0 0 0 0 0 1
RTC_LR field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 1.
Lock Register Lock
After being cleared, this bit can be set only by POR or software reset.
0 Lock Register is locked and writes are ignored.
1 Lock Register is not locked and writes complete as normal.
Status Register Lock
After being cleared, this bit can be set only by POR or software reset.
0 Status Register is locked and writes are ignored.
1 Status Register is not locked and writes complete as normal.
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18
0
2
1
17
0
1
1
16
0
0
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Field
4
CRL
3
TCL
2–0
Reserved
RTC_LR field descriptions (continued)
Chapter 34 Real Time Clock (RTC)
Description
Control Register Lock
After being cleared, this bit can only be set by POR.
0 Control Register is locked and writes are ignored.
1 Control Register is not locked and writes complete as normal.
Time Compensation Lock
After being cleared, this bit can be set only by POR or software reset.
0 Time Compensation Register is locked and writes are ignored.
1 Time Compensation Register is not locked and writes complete as normal.
This field is reserved.
This read-only field is reserved and always has the value 1.
34.2.8 RTC Interrupt Enable Register (RTC_IER)
Address: 4003_D000h base + 1Ch offset = 4003_D01Ch
Bit 31 30 29 28 27 26 25
R
24
23 22 21 20 19 18 17 16
W
Reset
Bit
R
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
W
Reset 0
Field
31–8
Reserved
7
WPON
0 0 0 0 0 0 0 0 0
RTC_IER field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Wakeup Pin On
0 0 0 1 1 1
The wakeup pin is optional and not available on all devices. Whenever the wakeup pin is enabled and this bit is set, the wakeup pin will assert.
0 No effect.
1 If the wakeup pin is enabled, then the wakeup pin will assert.
This field is reserved.
6–5
Reserved
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Functional description
Field
4
TSIE
RTC_IER field descriptions (continued)
Description
Time Seconds Interrupt Enable
The seconds interrupt is an edge-sensitive interrupt with a dedicated interrupt vector. It is generated once a second and requires no software overhead (there is no corresponding status flag to clear).
0 Seconds interrupt is disabled.
1 Seconds interrupt is enabled.
This field is reserved.
3
Reserved
2
TAIE
1
TOIE
0
TIIE
Time Alarm Interrupt Enable
0 Time alarm flag does not generate an interrupt.
1 Time alarm flag does generate an interrupt.
Time Overflow Interrupt Enable
0 Time overflow flag does not generate an interrupt.
1 Time overflow flag does generate an interrupt.
Time Invalid Interrupt Enable
0 Time invalid flag does not generate an interrupt.
1 Time invalid flag does generate an interrupt.
34.3 Functional description
34.3.1 Power, clocking, and reset
The RTC is an always powered block that remains active in all low power modes.
The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an external crystal using the oscillator.
The power-on-reset signal initializes all RTC registers to their default state. A software reset bit can also initialize all RTC registers.
34.3.1.1 Oscillator control
The 32.768 kHz crystal oscillator is disabled at POR and must be enabled by software.
After enabling the cystal oscillator, wait the oscillator startup time before setting
SR[TCE] or using the oscillator clock external to the RTC.
The crystal oscillator includes tunable capacitors that can be configured by software. Do not change the capacitance unless the oscillator is disabled.
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34.3.1.2 Software reset
Writing 1 to CR[SWR] forces the equivalent of a POR to the rest of the RTC module.
CR[SWR] is not affected by the software reset and must be cleared by software.
34.3.1.3 Supervisor access
When the supervisor access control bit is clear, only supervisor mode software can write to the RTC registers, non-supervisor mode software will generate a bus error. Both supervisor and non-supervisor mode software can always read the RTC registers.
34.3.2 Time counter
The time counter consists of a 32-bit seconds counter that increments once every second and a 16-bit prescaler register that increments once every 32.768 kHz clock cycle.
Reading the time counter (either seconds or prescaler) while is is incrementing may return invalid data due to synchronization of the read data bus. If it is necessary for software to read the prescaler or seconds counter when they could be incrementing, it is recommended that two read accesses are performed and that software verifies that the same data was returned for both reads.
The time seconds register and time prescaler register can be written only when SR[TCE] is clear. Always write to the prescaler register before writing to the seconds register, because the seconds register increments on the falling edge of bit 14 of the prescaler register.
The time prescaler register increments provided SR[TCE] is set, SR[TIF] is clear,
SR[TOF] is clear, and the 32.768 kHz clock source is present. After enabling the oscillator, wait the oscillator startup time before setting SR[TCE] to allow time for the oscillator clock output to stabilize.
If the time seconds register overflows then the SR[TOF] will set and the time prescaler register will stop incrementing. Clear SR[TOF] by initializing the time seconds register.
The time seconds register and time prescaler register read as zero whenever SR[TOF] is set.
SR[TIF] is set on POR and software reset and is cleared by initializing the time seconds register. The time seconds register and time prescaler register read as zero whenever
SR[TIF] is set.
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Functional description
34.3.3 Compensation
The compensation logic provides an accurate and wide compensation range and can correct errors as high as 3906 ppm and as low as 0.12 ppm. The compensation factor must be calculated externally to the RTC and supplied by software to the compensation register. The RTC itself does not calculate the amount of compensation that is required, although the 1 Hz clock is output to an external pin in support of external calibration logic.
Crystal compensation can be supported by using firmware and crystal characteristics to determine the compensation amount. Temperature compensation can be supported by firmware that periodically measures the external temperature via ADC and updates the compensation register based on a look-up table that specifies the change in crystal frequency over temperature.
The compensation logic alters the number of 32.768 kHz clock cycles it takes for the prescaler register to overflow and increment the time seconds counter. The time compensation value is used to adjust the number of clock cycles between -127 and +128.
Cycles are added or subtracted from the prescaler register when the prescaler register equals 0x3FFF and then increments. The compensation interval is used to adjust the frequency at which the time compensation value is used, that is, from once a second to once every 256 seconds.
Updates to the time compensation register will not take effect until the next time the time seconds register increments and provided the previous compensation interval has expired.
When the compensation interval is set to other than once a second then the compensation is applied in the first second interval and the remaining second intervals receive no compensation.
Compensation is disabled by configuring the time compensation register to zero.
34.3.4 Time alarm
The Time Alarm register (TAR), SR[TAF], and IER[TAIE] allow the RTC to generate an interrupt at a predefined time. The 32-bit TAR is compared with the 32-bit Time Seconds register (TSR) each time it increments. SR[TAF] will set when TAR equals TSR and
TSR increments.
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Chapter 34 Real Time Clock (RTC)
SR[TAF] is cleared by writing TAR. This will usually be the next alarm value, although writing a value that is less than TSR, such as 0, will prevent SR[TAF] from setting again.
SR[TAF] cannot otherwise be disabled, although the interrupt it generates is enabled or disabled by IER[TAIE].
34.3.5 Update mode
The Update Mode field in the Control register (CR[UM]) configures software write access to the Time Counter Enable (SR[TCE]) field. When CR[UM] is clear, SR[TCE] can be written only when LR[SRL] is set. When CR[UM] is set, SR[TCE] can also be written when SR[TCE] is clear or when SR[TIF] or SR[TOF] are set. This allows the time seconds and prescaler registers to be initialized whenever time is invalidated, while preventing the time seconds and prescaler registers from being changed on the fly. When
LR[SRL] is set, CR[UM] has no effect on SR[TCE].
34.3.6 Register lock
The Lock register (LR) can be used to block write accesses to certain registers until the next POR or software reset. Locking the Control register (CR) will disable the software reset. Locking LR will block future updates to LR.
Write accesses to a locked register are ignored and do not generate a bus error.
34.3.7 Interrupt
The RTC interrupt is asserted whenever a status flag and the corresponding interrupt enable bit are both set. It is always asserted on POR, and software reset. The RTC interrupt is enabled at the chip level by enabling the chip-specific RTC clock gate control bit. The RTC interrupt can be used to wakeup the chip from any low-power mode.
The optional RTC seconds interrupt is an edge-sensitive interrupt with a dedicated interrupt vector that is generated once a second and requires no software overhead (there is no corresponding status flag to clear). It is enabled in the RTC by the time seconds interrupt enable bit and enabled at the chip level by setting the chip-specific RTC clock gate control bit. This interrupt is optional and may not be implemented on all devices.
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Chapter 35
Universal Serial Bus OTG Controller (USBOTG)
This section describes the USB. The OTG implementation in this module provides limited host functionality as well as device solutions for implementing a USB 2.0
fullspeed/ low-speed compliant peripheral.
35.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
This section describes the USB full speed OTG controller. The OTG implementation in this module provides limited host functionality and device solutions for implementing a
USB 2.0 full-speed/low-speed compliant peripheral. The OTG implementation supports the On-The-Go (OTG) addendum to the USB 2.0 Specification. The USB full speed controller interfaces to a USB FS/LS transceiver.
35.1.1 USB
The USB is a cable bus that supports data exchange between a host computer and a wide range of simultaneously accessible peripherals. The attached peripherals share USB bandwidth through a host-scheduled, token-based protocol. The bus allows peripherals to be attached, configured, used, and detached while the host and other peripherals are in operation.
USB software provides a uniform view of the system for all application software, hiding implementation details making application software more portable. It manages the dynamic attach and detach of peripherals.
There is only one host in any USB system. The USB interface to the host computer system is referred to as the Host Controller.
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Introduction
There may be multiple USB devices in any system such as joysticks, speakers, printers, etc. USB devices present a standard USB interface in terms of comprehension, response, and standard capability.
The host initiates transactions to specific peripherals, whereas the device responds to control transactions. The device sends and receives data to and from the host using a standard USB data format. USB 2.0 full-speed /low-speed peripherals operate at 12Mbit/s or 1.5 Mbit/s.
For additional information, see the USB 2.0 specification.
Host PC
External Hub
Host
Software
Root
Hub
USB Cable
USB Cable
External Hub
USB Cable
USB Cables USB Peripherals
Figure 35-1. Example USB 2.0 system configuration
35.1.2 USB On-The-Go
USB is a popular standard for connecting peripherals and portable consumer electronic devices such as digital cameras and hand-held computers to host PCs. The On-The-Go
(OTG) Supplement to the USB Specification extends USB to peer-to-peer application.
Using USB OTG technology consumer electronics, peripherals, and portable devices can connect to each other to exchange data. For example, a digital camera can connect directly to a printer, or a keyboard can connect to a Personal Digital Assistant to exchange data.
With the USB On-The-Go product, you can develop a fully USB-compliant peripheral device that can also assume the role of a USB host. Software determines the role of the device based on hardware signals, and then initializes the device in the appropriate mode
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Download Songs
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) of operation (host or peripheral) based on how it is connected. After connecting the devices can negotiate using the OTG protocols to assume the role of host or peripheral based on the task to be accomplished.
For additional information, see the On-The-Go Supplement to the USB 2.0 Specification.
Print Photos
Keyboard Input
Swap Songs
Hot Sync
Figure 35-2. Example USB 2.0 On-The-Go configurations
35.1.3 USB-FS Features
• USB 1.1 and 2.0 compliant full-speed device controller
• 16 bidirectional end points
• DMA or FIFO data stream interfaces
• Low-power consumption
• On-The-Go protocol logic
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35.2 Functional description
The USB-FS 2.0 full-speed/low-speed module communicates with the processor core through status registers, control registers, and data structures in memory.
35.2.1 Data Structures
The function of the device operation is to transfer a request in the memory image to and from the Universal Serial Bus. To efficiently manage USB endpoint communications the
USB-FS implements a Buffer Descriptor Table (BDT) in system memory. See
.
35.3 Programmers interface
This section discusses the major components of the programming model for the USB module.
35.3.1 Buffer Descriptor Table
To efficiently manage USB endpoint communications the USB-FS implements a Buffer
Descriptor Table (BDT) in system memory. The BDT resides on a 512-byte boundary in system memory and is pointed to by the BDT Page Registers. Every endpoint direction requires two 8-byte Buffer Descriptor (BD) entries. Therefore, a system with 16 fully bidirectional endpoints would require 512 bytes of system memory to implement the
BDT. The two BD entries allows for an EVEN BD and ODD BD entry for each endpoint direction. This allows the microprocessor to process one BD while the USB-FS is processing the other BD. Double buffering BDs in this way allows the USB-FS to transfer data easily at the maximum throughput provided by USB.
The software API intelligently manages buffers for the USB-FS by updating the BDT when needed. This allows the USB-FS to efficiently manage data transmission and reception, while the microprocessor performs communication overhead processing and other function dependent applications. Because the buffers are shared between the microprocessor and the USB-FS, a simple semaphore mechanism is used to distinguish who is allowed to update the BDT and buffers in system memory. A semaphore, the
OWN bit, is cleared to 0 when the BD entry is owned by the microprocessor. The microprocessor is allowed read and write access to the BD entry and the buffer in system memory when the OWN bit is 0. When the OWN bit is set to 1, the BD entry and the buffer in system memory are owned by the USB-FS. The USB-FS now has full read and
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End of Buffer
Chapter 35 Universal Serial Bus OTG Controller (USBOTG) write access and the microprocessor must not modify the BD or its corresponding data buffer. The BD also contains indirect address pointers to where the actual buffer resides in system memory. This indirect address mechanism is shown in the following diagram.
System Memory
BDT_PAGE Registers END_POINT TX ODD 000
BDT Page
Current
Endpoint
BDT
Buffer in Memory
Start of Buffer
Figure 35-3. Buffer descriptor table
35.3.2 RX vs. TX as a USB target device or USB host
The USB-FS core uses software control to switch between two modes of operation:
• USB target device
• USB hosts
In either mode, USB host or USB target device, the same data paths and buffer descriptors are used for the transmission and reception of data. For this reason, a USB-FS core centric nomenclature is used to describe the direction of the data transfer between the USB-FS core and the USB:
• RX (or receive) describes transfers that move data from the USB to memory.
• TX (or transmit) describes transfers that move data from memory to the USB.
The following table shows how the data direction corresponds to the USB token type in host and target device applications.
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Device
Host
Table 35-1. Data direction for USB host or USB target
RX
OUT or SETUP
IN
TX
IN
OUT or SETUP
35.3.3 Addressing BDT entries
An understanding of the addressing mechanism of the Buffer Descriptor Table is useful when accessing endpoint data via the USB-FS or microprocessor. Some points of interest are:
• The BDT occupies up to 512 bytes of system memory.
• 16 bidirectional endpoints can be supported with a full BDT of 512 bytes.
• 16 bytes are needed for each USB endpoint direction.
• Applications with less than 16 endpoints require less RAM to implement the BDT.
• The BDT Page Registers (BDT_PAGE) point to the starting location of the BDT.
• The BDT must be located on a 512-byte boundary in system memory.
• All enabled TX and RX endpoint BD entries are indexed into the BDT to allow easy access via the USB-FS or MCU core.
When a USB token on an enabled endpoint is received, the USB-FS uses its integrated
DMA controller to interrogate the BDT. The USB-FS reads the corresponding endpoint
BD entry to determine whether it owns the BD and corresponding buffer in system memory.
To compute the entry point in to the BDT, the BDT_PAGE registers is concatenated with the current endpoint and the TX and ODD fields to form a 32-bit address. This address mechanism is shown below:
Table 35-2. BDT address calculation fields
Field
BDT_PAGE
END_POINT
TX
ODD
Description
BDT_PAGE registers in the Control Register Block
END POINT field from the USB TOKEN
1 for transmit transfers and 0 for receive transfers
Maintained within the USB-FS SIE. It corresponds to the buffer currently in use. The buffers are used in a ping-pong fashion.
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Chapter 35 Universal Serial Bus OTG Controller (USBOTG)
35.3.4 Buffer Descriptors (BDs)
A buffer descriptor provides endpoint buffer control information for the USB-FS and processor. The Buffer Descriptors have different meaning based on whether it is the
USB-FS or processor reading the BD in memory.
The USB-FS Controller uses the data stored in the BDs to determine:
• Who owns the buffer in system memory
• Data0 or Data1 PID
• Whether to release ownership upon packet completion
• No address increment (FIFO mode)
• Whether data toggle synchronization is enabled
• How much data is to be transmitted or received
• Where the buffer resides in system memory
While the processor uses the data stored in the BDs to determine:
• Who owns the buffer in system memory
• Data0 or Data1 PID
• The received TOKEN PID
• How much data was transmitted or received
• Where the buffer resides in system memory
The format for the BD is shown in the following figure.
31:26
RSVD
25:16
BC
(10 bits)
Table 35-3. Buffer descriptor format
15:8 7 6 5
KEEP/
4
NINC/
RSVD OWN DATA0/1
TOK_PID[3] TOK_PID[2]
Buffer Address (32-Bits)
3
DTS/
TOK_PID[1]
2
BDT_STALL/
TOK_PID[0]
1 0
0 0
Field
31–26
RSVD
Table 35-4. Buffer descriptor fields
Description
Reserved
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Field
25–16
BC
15–8
RSVD
7
OWN
Table 35-4. Buffer descriptor fields (continued)
Description
Byte Count
Represents the 10-bit byte count. The USB-FS SIE changes this field upon the completion of a RX transfer with the byte count of the data received.
Reserved
6
DATA0/1
5
KEEP/
TOK_PID[3]
4
NINC/
TOK_PID[2]
3
DTS/
TOK_PID[1]
Determines whether the processor or the USB-FS currently owns the buffer. Except when KEEP=1, the SIE hands ownership back to the processor after completing the token by clearing this bit.
This must always be the last byte of the BD that the processor updates when it initializes a BD.
0 The processor has exclusive access to the BD. The USB-FS ignores all other fields in the BD.
1 USB-FS has exclusive access to the BD. After the BD has been assigned to the USB-FS, the processor should not change it in any way.
Defines whether a DATA0 field (DATA0/1=0) or a DATA1 (DATA0/1=1) field was transmitted or received. It is unchanged by the USB-FS.
Typically, this bit is 1 with ISO endpoints feeding a FIFO. The microprocessor is not informed that a token has been processed, the data is simply transferred to or from the FIFO. When KEEP is set, normally the NINC bit is also set to prevent address increment.
0 Bit 3 of the current token PID is written back to the BD by the USB-FS. Allows the USB-FS to release the BD when a token has been processed.
1 This bit is unchanged by the USB-FS. If the OWN bit also is set, the BD remains owned by the
USB-FS forever.
No Increment (NINC)
Disables the DMA engine address increment. This forces the DMA engine to read or write from the same address. This is useful for endpoints when data needs to be read from or written to a single location such as a FIFO. Typically this bit is set with the KEEP bit for ISO endpoints that are interfacing to a FIFO.
0 The USB-FS writes bit 2 of the current token PID to the BD.
1 This bit is unchanged by the USB-FS.
Setting this bit enables the USB-FS to perform Data Toggle Synchronization.
• If KEEP=0, bit 1 of the current token PID is written back to the BD.
• If KEEP=1, this bit is unchanged by the USB-FS.
0 Data Toggle Synchronization is disabled.
1 Enables the USB-FS to perform Data Toggle Synchronization.
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Field
2
BDT_STALL
TOK_PID[0]
TOK_PID[n]
1–0
Reserved
ADDR[31:0]
Chapter 35 Universal Serial Bus OTG Controller (USBOTG)
Table 35-4. Buffer descriptor fields (continued)
Description
Setting this bit causes the USB-FS to issue a STALL handshake if a token is received by the SIE that would use the BDT in this location. The BDT is not consumed by the SIE (the owns bit remains set and the rest of the BDT is unchanged) when a BDT-STALL bit is set.
• If KEEP=0, bit 0 of the current token PID is written back to the BD.
• If KEEP=1, this bit is unchanged by the USB-FS.
0 No stall issued.
1 The BDT is not consumed by the SIE (the OWN bit remains set and the rest of the BDT is unchanged).
Setting BDT_STALL also causes the corresponding USB_ENDPT n [EPSTALL] bit to set. This causes the USBOTG to issue a STALL handshake for both directions of the associated endpoint.
To clear the stall condition:
1. Clear the associated USB_ENDPT n [EPSTALL] bit.
2. Write the BDT to clear OWN and BDT_STALL.
Bits [5:2] can also represent the current token PID. The current token PID is written back in to the
BD by the USB-FS when a transfer completes. The values written back are the token PID values from the USB specification:
• 0x1h for an OUT token.
• 0x9h for an IN token.
• 0xDh for a SETUP token.
In host mode, this field is used to report the last returned PID or a transfer status indication. The possible values returned are:
• 0x3h DATA0
• 0xBh DATA1
• 0x2h ACK
• 0xEh STALL
• 0xAh NAK
• 0x0h Bus Timeout
• 0xFh Data Error
Reserved, should read as zeroes.
Address
Represents the 32-bit buffer address in system memory. These bits are unchanged by the USB-
FS.
35.3.5 USB transaction
When the USB-FS transmits or receives data, it computes the BDT address using the address generation shown in "Addressing Buffer Descriptor Entries" table.
If OWN =1, the following process occurs:
1. The USB-FS reads the BDT.
2. The SIE transfers the data via the DMA to or from the buffer pointed to by the
ADDR field of the BD.
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3. When the TOKEN is complete, the USB-FS updates the BDT and, if KEEP=0, changes the OWN bit to 0.
4. The STAT register is updated and the TOK_DNE interrupt is set.
5. When the processor processes the TOK_DNE interrupt, it reads from the status register all the information needed to process the endpoint.
6. At this point, the processor allocates a new BD so that additional USB data can be transmitted or received for that endpoint, and then processes the last BD.
The following figure shows a timeline of how a typical USB token is processed after the
BDT is read and OWN=1.
USB RST
USB_RST
Interrupt Generated
SETUP TOKEN
SOF
SOF Interrupt Generated
DATA ACK
TOK_DNE
Interrupt Generated
IN TOKEN DATA ACK
TOK_DNE
Interrupt Generated
OUT TOKEN DATA ACK
USB Host Function
Figure 35-4. USB token transaction
TOK_DNE
Interrupt Generated
The USB has two sources for the DMA overrun error:
Memory Latency
The memory latency may be too high and cause the receive FIFO to overflow. This is predominantly a hardware performance issue, usually caused by transient memory access issues.
Oversized Packets
The packet received may be larger than the negotiated MaxPacket size. Typically, this is caused by a software bug. For DMA overrun errors due to oversized data packets, the
USB specification is ambiguous. It assumes correct software drivers on both sides.
NAKing the packet can result in retransmission of the already oversized packet data.
Therefore, in response to oversized packets, the USB core continues ACKing the packet for non-isochronous transfers.
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Table 35-5. USB responses to DMA overrun errors
Errors due to Memory Latency
Non-Acknowledgment (NAK) or Bus Timeout (BTO) — See bit 4 in "Error Interrupt Status Register (ERRSTAT)" as appropriate for the class of transaction.
Errors due to Oversized Packets
Continues acknowledging (ACKing) the packet for nonisochronous transfers.
—
The DMAERR bit is set in the ERRSTAT register for host and device modes of operation. Depending on the values of the
INTENB and ERRENB register, the core may assert an interrupt to notify the processor of the DMA error.
• For host mode, the TOKDNE interrupt is generated and the TOK_PID field of the BDT is 1111 to indicate the
DMA latency error. Host mode software can decide to retry or move to next scheduled item.
• In device mode, the BDT is not written back nor is the
TOKDNE interrupt triggered because it is assumed that a second attempt is queued and will succeed in the future.
The data written to memory is clipped to the MaxPacket size so as not to corrupt system memory.
Asserts ERRSTAT[DMAERR] ,which can trigger an interrupt and TOKDNE interrupt fires. Note: The TOK_PID field of the
BDT is not 1111 because the DMAERR is not due to latency.
The packet length field written back to the BDT is the
MaxPacket value that represents the length of the clipped data actually written to memory.
From here, the software can decide an appropriate course of action for future transactions such as stalling the endpoint, canceling the transfer, disabling the endpoint, etc.
35.4 Memory map/Register definitions
This section provides the memory map and detailed descriptions of all USB interface registers.
USB memory map
Absolute address
(hex)
Register name
4007_2000 Peripheral ID register (USB0_PERID)
4007_2004 Peripheral ID Complement register (USB0_IDCOMP)
4007_2008 Peripheral Revision register (USB0_REV)
4007_200C Peripheral Additional Info register (USB0_ADDINFO)
4007_2010 OTG Interrupt Status register (USB0_OTGISTAT)
4007_2014 OTG Interrupt Control register (USB0_OTGICR)
4007_2018 OTG Status register (USB0_OTGSTAT)
4007_201C OTG Control register (USB0_OTGCTL)
4007_2080 Interrupt Status register (USB0_ISTAT)
Width
(in bits)
Access Reset value
8
8
8
8
8
8
8
8
8
R
R
R
R
R/W
R/W
R/W
R/W
R/W
04h
FBh
33h
01h
00h
00h
00h
00h
00h
Section/ page
4007_2084 Interrupt Enable register (USB0_INTEN)
4007_2088 Error Interrupt Status register (USB0_ERRSTAT)
8
8
R/W
R/W
00h
00h
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Memory map/Register definitions
USB memory map (continued)
Absolute address
(hex)
Register name
4007_208C Error Interrupt Enable register (USB0_ERREN)
Width
(in bits)
Access Reset value
8 R/W 00h
4007_2090 Status register (USB0_STAT)
4007_2094 Control register (USB0_CTL)
4007_2098 Address register (USB0_ADDR)
4007_209C BDT Page register 1 (USB0_BDTPAGE1)
4007_20A0 Frame Number register Low (USB0_FRMNUML)
4007_20A4 Frame Number register High (USB0_FRMNUMH)
4007_20A8 Token register (USB0_TOKEN)
4007_20AC SOF Threshold register (USB0_SOFTHLD)
4007_20B0 BDT Page Register 2 (USB0_BDTPAGE2)
4007_20B4 BDT Page Register 3 (USB0_BDTPAGE3)
4007_20C0 Endpoint Control register (USB0_ENDPT0)
4007_20C4 Endpoint Control register (USB0_ENDPT1)
4007_20C8 Endpoint Control register (USB0_ENDPT2)
4007_20CC Endpoint Control register (USB0_ENDPT3)
4007_20D0 Endpoint Control register (USB0_ENDPT4)
4007_20D4 Endpoint Control register (USB0_ENDPT5)
4007_20D8 Endpoint Control register (USB0_ENDPT6)
4007_20DC Endpoint Control register (USB0_ENDPT7)
4007_20E0 Endpoint Control register (USB0_ENDPT8)
4007_20E4 Endpoint Control register (USB0_ENDPT9)
8
8
4007_20E8 Endpoint Control register (USB0_ENDPT10)
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8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Section/ page
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USB memory map (continued)
Absolute address
(hex)
Register name
4007_20EC Endpoint Control register (USB0_ENDPT11)
4007_20F0 Endpoint Control register (USB0_ENDPT12)
4007_20F4 Endpoint Control register (USB0_ENDPT13)
4007_20F8 Endpoint Control register (USB0_ENDPT14)
4007_20FC Endpoint Control register (USB0_ENDPT15)
4007_2100 USB Control register (USB0_USBCTRL)
4007_2104 USB OTG Observe register (USB0_OBSERVE)
4007_2108 USB OTG Control register (USB0_CONTROL)
4007_210C USB Transceiver Control register 0 (USB0_USBTRC0)
4007_2114 Frame Adjust Register (USB0_USBFRMADJUST)
Width
(in bits)
Access Reset value
8
8
8
8
8
8
8
8
8
8
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
00h
00h
00h
00h
00h
C0h
50h
00h
00h
00h
Section/ page
35.4.1 Peripheral ID register (USBx_PERID)
Reads back the value of 0x04. This value is defined for the USB peripheral.
Address: 4007_2000h base + 0h offset = 4007_2000h
7 6 5 Bit
Read
Write
Reset
Field
7–6
Reserved
5–0
ID
4 3
0 0 0 0 0
USBx_PERID field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Peripheral Identification
This field always reads 0x4h.
2
1
1
0
0
0
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35.4.2 Peripheral ID Complement register (USBx_IDCOMP)
Reads back the complement of the Peripheral ID register. For the USB peripheral, the value is 0xFB.
Address: 4007_2000h base + 4h offset = 4007_2004h
7 6 5 Bit
Read
Write
Reset 1
1 1
Field
7–6
Reserved
5–0
NID
4 3
1 1
USBx_IDCOMP field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 1.
Ones complement of peripheral identification bits.
2
0
1
1
0
1
35.4.3 Peripheral Revision register (USBx_REV)
Contains the revision number of the USB module.
Address: 4007_2000h base + 8h offset = 4007_2008h
7 6 5 Bit
Read
Write
Reset 0 0
4
3
1 1 0
USBx_REV field descriptions
Description Field
7–0
REV
Revision
Indicate the revision number of the USB Core.
2
0
1
1
0
1
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35.4.4 Peripheral Additional Info register (USBx_ADDINFO)
Reads back the value of the fixed Interrupt Request Level (IRQNUM) along with the
Host Enable bit.
Address: 4007_2000h base + Ch offset = 4007_200Ch
Bit
Read
Write
Reset
7
0
6
0
5
0
4 3
0 0
USBx_ADDINFO field descriptions
Description
Assigned Interrupt Request Number
Field
7–3
IRQNUM
2–1
Reserved
0
IEHOST
This field is reserved.
This read-only field is reserved and always has the value 0.
When this bit is set, the USB peripheral is operating in host mode.
2
0
1
0
0
1
35.4.5 OTG Interrupt Status register (USBx_OTGISTAT)
Records changes of the ID sense and VBUS signals. Software can read this register to determine the event that triggers interrupt. Only bits that have changed since the last software read are set. Writing a one to a bit clears the associated interrupt.
Address: 4007_2000h base + 10h offset = 4007_2010h
7 6 Bit
Read
Write
Reset
0
0
5
0
Field
7
IDCHG
6
ONEMSEC
4
3
2
0 0 0
USBx_OTGISTAT field descriptions
Description
This bit is set when a change in the ID Signal from the USB connector is sensed.
1
0
0
0
This bit is set when the 1 millisecond timer expires. This bit stays asserted until cleared by software. The interrupt must be serviced every millisecond to avoid losing 1msec counts.
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USBx_OTGISTAT field descriptions (continued)
Field
5
LINE_STATE_
CHG
4
Reserved
3
SESSVLDCHG
2
B_SESS_CHG
1
Reserved
0
AVBUSCHG
Description
This bit is set when the USB line state changes. The interrupt associated with this bit can be used to detect Reset, Resume, Connect, and Data Line Pulse signaling
This field is reserved.
This read-only field is reserved and always has the value 0.
This bit is set when a change in VBUS is detected indicating a session valid or a session no longer valid.
This bit is set when a change in VBUS is detected on a B device.
This field is reserved.
This read-only field is reserved and always has the value 0.
This bit is set when a change in VBUS is detected on an A device.
35.4.6 OTG Interrupt Control register (USBx_OTGICR)
Enables the corresponding interrupt status bits defined in the OTG Interrupt Status
Register.
Address: 4007_2000h base + 14h offset = 4007_2014h
Bit
Read
Write
Reset
7
0
6
0
5
0
4
0
3
0
Field
7
IDEN
ID Interrupt Enable
USBx_OTGICR field descriptions
Description
0 The ID interrupt is disabled
1 The ID interrupt is enabled
One Millisecond Interrupt Enable 6
ONEMSECEN
5
LINESTATEEN
0 Diables the 1ms timer interrupt.
1 Enables the 1ms timer interrupt.
Line State Change Interrupt Enable
4
Reserved
3
SESSVLDEN
0 Disables the LINE_STAT_CHG interrupt.
1 Enables the LINE_STAT_CHG interrupt.
This field is reserved.
This read-only field is reserved and always has the value 0.
Session Valid Interrupt Enable
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2
0
1
0
0
0
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Field
2
BSESSEN
1
Reserved
0
AVBUSEN
Chapter 35 Universal Serial Bus OTG Controller (USBOTG)
USBx_OTGICR field descriptions (continued)
Description
0 Disables the SESSVLDCHG interrupt.
1 Enables the SESSVLDCHG interrupt.
B Session END Interrupt Enable
0 Disables the B_SESS_CHG interrupt.
1 Enables the B_SESS_CHG interrupt.
This field is reserved.
This read-only field is reserved and always has the value 0.
A VBUS Valid Interrupt Enable
0 Disables the AVBUSCHG interrupt.
1 Enables the AVBUSCHG interrupt.
35.4.7 OTG Status register (USBx_OTGSTAT)
Displays the actual value from the external comparator outputs of the ID pin and VBUS.
Address: 4007_2000h base + 18h offset = 4007_2018h
Bit
Read
Write
Reset
7
0
6
0
5
0
4
0
Bit
Read
Write
Reset
3
0
2
0
1
0
0 0
USBx_OTGSTAT field descriptions
Field
7
ID
Description
Indicates the current state of the ID pin on the USB connector
0 Indicates a Type A cable is plugged into the USB connector.
1 Indicates no cable is attached or a Type B cable is plugged into the USB connector.
This bit is reserved for the 1ms count, but it is not useful to software.
6
ONEMSECEN
5
LINESTATESTABLE
Indicates that the internal signals that control the LINE_STATE_CHG field of OTGISTAT are stable for at least 1 millisecond. First read LINE_STATE_CHG field and then read this field. If this field reads as
1, then the value of LINE_STATE_CHG can be considered stable.
4
Reserved
0 The LINE_STAT_CHG bit is not yet stable.
1 The LINE_STAT_CHG bit has been debounced and is stable.
This field is reserved.
This read-only field is reserved and always has the value 0.
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USBx_OTGSTAT field descriptions (continued)
Field
3
SESS_VLD
Session Valid
Description
2
BSESSEND
0 The VBUS voltage is below the B session valid threshold
1 The VBUS voltage is above the B session valid threshold.
B Session End
1
Reserved
0
AVBUSVLD
0 The VBUS voltage is above the B session end threshold.
1 The VBUS voltage is below the B session end threshold.
This field is reserved.
This read-only field is reserved and always has the value 0.
A VBUS Valid
0 The VBUS voltage is below the A VBUS Valid threshold.
1 The VBUS voltage is above the A VBUS Valid threshold.
35.4.8 OTG Control register (USBx_OTGCTL)
Controls the operation of VBUS and Data Line termination resistors.
Address: 4007_2000h base + 1Ch offset = 4007_201Ch
Bit
Read
Write
Reset
7
0
6
0
5
0
Field
7
DPHIGH
4
0
3
0
USBx_OTGCTL field descriptions
Description
D+ Data Line pullup resistor enable
6
Reserved
5
DPLOW
0 D+ pullup resistor is not enabled
1 D+ pullup resistor is enabled
This field is reserved.
This read-only field is reserved and always has the value 0.
D+ Data Line pull-down resistor enable
This bit should always be enabled together with bit 4 (DMLOW)
2
0
4
DMLOW
3
Reserved
0 D+ pulldown resistor is not enabled.
1 D+ pulldown resistor is enabled.
D– Data Line pull-down resistor enable
0 D- pulldown resistor is not enabled.
1 D- pulldown resistor is enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
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Field
2
OTGEN
1–0
Reserved
Chapter 35 Universal Serial Bus OTG Controller (USBOTG)
USBx_OTGCTL field descriptions (continued)
Description
On-The-Go pullup/pulldown resistor enable
0 If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+ and D– Data Line pull-down resistors are engaged.
1 The pull-up and pull-down controls in this register are used.
This field is reserved.
This read-only field is reserved and always has the value 0.
35.4.9 Interrupt Status register (USBx_ISTAT)
Contains fields for each of the interrupt sources within the USB Module. Each of these fields are qualified with their respective interrupt enable bits. All fields of this register are logically OR'd together along with the OTG Interrupt Status Register (OTGSTAT) to form a single interrupt source for the processor's interrupt controller. After an interrupt bit has been set it may only be cleared by writing a one to the respective interrupt bit.
This register contains the value of 0x00 after a reset.
Address: 4007_2000h base + 80h offset = 4007_2080h
Bit
Read
Write
Reset
7
0
6
0
5
0
Field
7
STALL
6
ATTACH
4
0
3
0
2
0
1
0
0
0
USBx_ISTAT field descriptions
Description
Stall Interrupt
In Target mode this bit is asserted when a STALL handshake is sent by the SIE.
In Host mode this bit is set when the USB Module detects a STALL acknowledge during the handshake phase of a USB transaction.This interrupt can be used to determine whether the last USB transaction was completed successfully or stalled.
Attach Interrupt
5
RESUME
4
SLEEP
3
TOKDNE
This bit is set when the USB Module detects an attach of a USB device. This signal is only valid if
HOSTMODEEN is true. This interrupt signifies that a peripheral is now present and must be configured.
This bit is set depending upon the DP/DM signals, and can be used to signal remote wake-up signaling on the USB bus. When not in suspend mode this interrupt must be disabled.
This bit is set when the USB Module detects a constant idle on the USB bus for 3 ms. The sleep timer is reset by activity on the USB bus.
This bit is set when the current token being processed has completed. The processor must immediately read the STATUS (STAT) register to determine the EndPoint and BD used for this token. Clearing this bit
(by writing a one) causes STAT to be cleared or the STAT holding register to be loaded into the STAT register.
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USBx_ISTAT field descriptions (continued)
Field
2
SOFTOK
1
ERROR
0
USBRST
Description
This bit is set when the USB Module receives a Start Of Frame (SOF) token.
In Host mode this field is set when the SOF threshold is reached, so that software can prepare for the next
SOF.
This bit is set when any of the error conditions within Error Interrupt Status (ERRSTAT) register occur. The processor must then read the ERRSTAT register to determine the source of the error.
This bit is set when the USB Module has decoded a valid USB reset. This informs the processor that it should write 0x00 into the address register and enable endpoint 0. USBRST is set after a USB reset has been detected for 2.5 microseconds. It is not asserted again until the USB reset condition has been removed and then reasserted.
35.4.10 Interrupt Enable register (USBx_INTEN)
Contains enable fields for each of the interrupt sources within the USB Module. Setting any of these bits enables the respective interrupt source in the ISTAT register. This register contains the value of 0x00 after a reset.
Address: 4007_2000h base + 84h offset = 4007_2084h
Bit
Read
Write
Reset
7
0
6
0
5
0
4
ATTACHEN RESUMEEN SLEEPEN TOKDNEEN SOFTOKEN ERROREN USBRSTEN
0
3
0
2
0
1
0
0
0
Field
7
STALLEN
USBx_INTEN field descriptions
Description
STALL Interrupt Enable
6
ATTACHEN
0 Diasbles the STALL interrupt.
1 Enables the STALL interrupt.
ATTACH Interrupt Enable
5
RESUMEEN
0 Disables the ATTACH interrupt.
1 Enables the ATTACH interrupt.
RESUME Interrupt Enable
4
SLEEPEN
0 Disables the RESUME interrupt.
1 Enables the RESUME interrupt.
SLEEP Interrupt Enable
3
TOKDNEEN
0 Disables the SLEEP interrupt.
1 Enables the SLEEP interrupt.
TOKDNE Interrupt Enable
0 Disables the TOKDNE interrupt.
1 Enables the TOKDNE interrupt.
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Field
2
SOFTOKEN
1
ERROREN
0
USBRSTEN
Chapter 35 Universal Serial Bus OTG Controller (USBOTG)
USBx_INTEN field descriptions (continued)
Description
SOFTOK Interrupt Enable
0 Disbles the SOFTOK interrupt.
1 Enables the SOFTOK interrupt.
ERROR Interrupt Enable
0 Disables the ERROR interrupt.
1 Enables the ERROR interrupt.
USBRST Interrupt Enable
0 Disables the USBRST interrupt.
1 Enables the USBRST interrupt.
35.4.11 Error Interrupt Status register (USBx_ERRSTAT)
Contains enable bits for each of the error sources within the USB Module. Each of these bits are qualified with their respective error enable bits. All bits of this register are logically OR'd together and the result placed in the ERROR bit of the ISTAT register.
After an interrupt bit has been set it may only be cleared by writing a one to the respective interrupt bit. Each bit is set as soon as the error conditions is detected.
Therefore, the interrupt does not typically correspond with the end of a token being processed. This register contains the value of 0x00 after a reset.
Address: 4007_2000h base + 88h offset = 4007_2088h
Bit
Write
Reset
7
Read
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
USBx_ERRSTAT field descriptions
Description
This bit is set when a bit stuff error is detected. If set, the corresponding packet is rejected due to the error.
Field
7
BTSERR
6
Reserved
5
DMAERR
This field is reserved.
This read-only field is reserved and always has the value 0.
This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given the bus before it needs to receive or transmit data. If processing a TX transfer this would cause a transmit data underflow condition. If processing a RX transfer this would cause a receive data overflow condition.
This interrupt is useful when developing device arbitration hardware for the microprocessor and the USB module to minimize bus request and bus grant latency. This bit is also set if a data packet to or from the host is larger than the buffer size allocated in the BDT. In this case the data packet is truncated as it is put in buffer memory.
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USBx_ERRSTAT field descriptions (continued)
Field
4
BTOERR
3
DFN8
2
CRC16
1
CRC5EOF
Description
This bit is set when a bus turnaround timeout error occurs. The USB module contains a bus turnaround timer that keeps track of the amount of time elapsed between the token and data phases of a SETUP or
OUT TOKEN or the data and handshake phases of a IN TOKEN. If more than 16 bit times are counted from the previous EOP before a transition from IDLE, a bus turnaround timeout error occurs.
This bit is set if the data field received was not 8 bits in length. USB Specification 1.0 requires that data fields be an integral number of bytes. If the data field was not an integral number of bytes, this bit is set.
This bit is set when a data packet is rejected due to a CRC16 error.
0
PIDERR
This error interrupt has two functions. When the USB Module is operating in peripheral mode
(HOSTMODEEN=0), this interrupt detects CRC5 errors in the token packets generated by the host. If set the token packet was rejected due to a CRC5 error.
When the USB Module is operating in host mode (HOSTMODEEN=1), this interrupt detects End Of Frame
(EOF) error conditions. This occurs when the USB Module is transmitting or receiving data and the SOF counter reaches zero. This interrupt is useful when developing USB packet scheduling software to ensure that no USB transactions cross the start of the next frame.
This bit is set when the PID check field fails.
35.4.12 Error Interrupt Enable register (USBx_ERREN)
Contains enable bits for each of the error interrupt sources within the USB module.
Setting any of these bits enables the respective interrupt source in ERRSTAT. Each bit is set as soon as the error conditions is detected. Therefore, the interrupt does not typically correspond with the end of a token being processed. This register contains the value of
0x00 after a reset.
Address: 4007_2000h base + 8Ch offset = 4007_208Ch
Bit
Read
Write
Reset
7
0
Field
7
BTSERREN
6
Reserved
5
DMAERREN
6
0
5 4 3
0 0 0
USBx_ERREN field descriptions
Description
BTSERR Interrupt Enable
0 Disables the BTSERR interrupt.
1 Enables the BTSERR interrupt.
This field is reserved.
This read-only field is reserved and always has the value 0.
DMAERR Interrupt Enable
2
0
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0
0
0
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Field
4
BTOERREN
3
DFN8EN
2
CRC16EN
1
CRC5EOFEN
0
PIDERREN
Chapter 35 Universal Serial Bus OTG Controller (USBOTG)
USBx_ERREN field descriptions (continued)
Description
0 Disables the DMAERR interrupt.
1 Enables the DMAERR interrupt.
BTOERR Interrupt Enable
0 Disables the BTOERR interrupt.
1 Enables the BTOERR interrupt.
DFN8 Interrupt Enable
0 Disables the DFN8 interrupt.
1 Enables the DFN8 interrupt.
CRC16 Interrupt Enable
0 Disables the CRC16 interrupt.
1 Enables the CRC16 interrupt.
CRC5/EOF Interrupt Enable
0 Disables the CRC5/EOF interrupt.
1 Enables the CRC5/EOF interrupt.
PIDERR Interrupt Enable
0 Disables the PIDERR interrupt.
1 Enters the PIDERR interrupt.
35.4.13 Status register (USBx_STAT)
Reports the transaction status within the USB module. When the processor's interrupt controller has received a TOKDNE, interrupt the Status Register must be read to determine the status of the previous endpoint communication. The data in the status register is valid when TOKDNE interrupt is asserted. The Status register is actually a read window into a status FIFO maintained by the USB module. When the USB module uses a BD, it updates the Status register. If another USB transaction is performed before the TOKDNE interrupt is serviced, the USB module stores the status of the next transaction in the STAT FIFO. Thus STAT is actually a four byte FIFO that allows the processor core to process one transaction while the SIE is processing the next transaction.
Clearing the TOKDNE bit in the ISTAT register causes the SIE to update STAT with the contents of the next STAT value. If the data in the STAT holding register is valid, the
SIE immediately reasserts to TOKDNE interrupt.
Address: 4007_2000h base + 90h offset = 4007_2090h
7 6 5 Bit
Read
Write
Reset 0 0
0
4
0
3
0
2
0
1
0
0
0
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Field
7–4
ENDP
3
TX
USBx_STAT field descriptions
Description
This four-bit field encodes the endpoint address that received or transmitted the previous token. This allows the processor core to determine the BDT entry that was updated by the last USB transaction.
Transmit Indicator
0 The most recent transaction was a receive operation.
1 The most recent transaction was a transmit operation.
This bit is set if the last buffer descriptor updated was in the odd bank of the BDT.
2
ODD
1–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
35.4.14 Control register (USBx_CTL)
Provides various control and configuration information for the USB module.
Address: 4007_2000h base + 94h offset = 4007_2094h
Bit
Read
Write
Reset
7
0
6
0
5
0
4
0
Bit
Read
Write
Reset
3
0
2
0
1
0
0
0
USBx_CTL field descriptions
Field
7
JSTATE
Description
Live USB differential receiver JSTATE signal
6
SE0
5
TXSUSPENDTOKENBUSY
The polarity of this signal is affected by the current state of LSEN .
Live USB Single Ended Zero signal
In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB token.
Software must not write more token commands to the Token Register when TOKEN_BUSY is set.. Software should check this field before writing any tokens to the Token Register to ensure that token commands are not lost.
4
RESET
In Target mode, TXD_SUSPEND is set when the SIE has disabled packet transmission and reception. Clearing this bit allows the SIE to continue token processing. This bit is set by the
SIE when a SETUP Token is received allowing software to dequeue any pending packet transactions in the BDT before resuming token processing.
Setting this bit enables the USB Module to generate USB reset signaling. This allows the USB
Module to reset USB peripherals. This control signal is only valid in Host mode
(HOSTMODEEN=1). Software must set RESET to 1 for the required amount of time and then
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Field
3
HOSTMODEEN
2
RESUME
1
ODDRST
0
USBENSOFEN
Chapter 35 Universal Serial Bus OTG Controller (USBOTG)
USBx_CTL field descriptions (continued)
Description clear it to 0 to end reset signaling. For more information on reset signaling see Section 7.1.4.3
of the USB specification version 1.0.
When set to 1, this bit enables the USB Module to operate in Host mode. In host mode, the
USB module performs USB transactions under the programmed control of the host processor.
When set to 1 this bit enables the USB Module to execute resume signaling. This allows the
USB Module to perform remote wake-up. Software must set RESUME to 1 for the required amount of time and then clear it to 0. If the HOSTMODEEN bit is set, the USB module appends a Low Speed End of Packet to the Resume signaling when the RESUME bit is cleared. For more information on RESUME signaling see Section 7.1.4.5 of the USB specification version
1.0.
Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which then specifies the
EVEN BDT bank.
USB Enable
Setting this bit causes the SIE to reset all of its ODD bits to the BDTs. Therefore, setting this bit resets much of the logic in the SIE. When host mode is enabled, clearing this bit causes the
SIE to stop sending SOF tokens.
0 Disables the USB Module.
1 Enables the USB Module.
35.4.15 Address register (USBx_ADDR)
Holds the unique USB address that the USB module decodes when in Peripheral mode
(HOSTMODEEN=0). When operating in Host mode (HOSTMODEEN=1) the USB module transmits this address with a TOKEN packet. This enables the USB module to uniquely address an USB peripheral. In either mode, USB_EN within the control register must be 1. The Address register is reset to 0x00 after the reset input becomes active or the
USB module decodes a USB reset signal. This action initializes the Address register to decode address 0x00 as required by the USB specification.
Address: 4007_2000h base + 98h offset = 4007_2098h
6 5 Bit
Read
Write
Reset
7
0 0 0
Field
7
LSEN
4
0
3
0
Low Speed Enable bit
USBx_ADDR field descriptions
Description
2
0
1
0
0
0
Informs the USB module that the next token command written to the token register must be performed at low speed. This enables the USB module to perform the necessary preamble required for low-speed data transmissions.
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USBx_ADDR field descriptions (continued)
Field
6–0
ADDR
USB Address
Description
Defines the USB address that the USB module decodes in peripheral mode, or transmits when in host mode.
35.4.16 BDT Page register 1 (USBx_BDTPAGE1)
Provides address bits 15 through 9 of the base address where the current Buffer
Descriptor Table (BDT) resides in system memory. The 32-bit BDT Base Address is always aligned on 512-byte boundaries, so bits 8 through 0 of the base address are always zero.
Address: 4007_2000h base + 9Ch offset = 4007_209Ch
Bit
Read
Write
Reset
Field
7–1
BDTBA
0
Reserved
7 6 5 4
0
3
0 0 0 0
USBx_BDTPAGE1 field descriptions
Description
Provides address bits 15 through 9 of the BDT base address.
This field is reserved.
This read-only field is reserved and always has the value 0.
2
0
1
0
0
0
35.4.17 Frame Number register Low (USBx_FRMNUML)
Contains an 11-bit value used to compute the address where the current Buffer Descriptor
Table (BDT) resides in system memory.
Address: 4007_2000h base + A0h offset = 4007_20A0h
Bit
Read
Write
Reset
Field
7–0
FRM[7:0]
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
USBx_FRMNUML field descriptions
Description
This 8-bit field and the 3-bit field in the Frame Number Register High are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory.
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35.4.18 Frame Number register High (USBx_FRMNUMH)
Contains an 11-bit value used to compute the address where the current Buffer Descriptor
Table (BDT) resides in system memory.
Address: 4007_2000h base + A4h offset = 4007_20A4h
Bit
Read
Write
Reset
7
0
6
0
5
0
Field
7–3
Reserved
2–0
FRM[10:8]
4 3 2 1
0
0
0 0 0 0
USBx_FRMNUMH field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
This 3-bit field and the 8-bit field in the Frame Number Register Low are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory.
35.4.19 Token register (USBx_TOKEN)
Used to initiate USB transactions when in host mode (HOSTMODEEN=1). When the software needs to execute a USB transaction to a peripheral, it writes the TOKEN type and endpoint to this register. After this register has been written, the USB module begins the specified USB transaction to the address contained in the address register. The processor core must always check that the TOKEN_BUSY bit in the control register is not 1 before writing to the Token Register. This ensures that the token commands are not overwritten before they can be executed. The address register and endpoint control register 0 are also used when performing a token command and therefore must also be written before the Token Register. The address register is used to select the USB peripheral address transmitted by the token command. The endpoint control register determines the handshake and retry policies used during the transfer.
Address: 4007_2000h base + A8h offset = 4007_20A8h
7 Bit
Read
Write
Reset 0
6 5
0
0
4
0
3
0
2 1
0 0
USBx_TOKEN field descriptions
Field
7–4
TOKENPID
Description
Contains the token type executed by the USB module.
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0
657
Memory map/Register definitions
USBx_TOKEN field descriptions (continued)
Field
3–0
TOKENENDPT
Description
0001 OUT Token. USB Module performs an OUT (TX) transaction.
1001 IN Token. USB Module performs an In (RX) transaction.
1101 SETUP Token. USB Module performs a SETUP (TX) transaction
Holds the Endpoint address for the token command. The four bit value written must be a valid endpoint.
35.4.20 SOF Threshold register (USBx_SOFTHLD)
The SOF Threshold Register is used only in Host mode (HOSTMODEEN=1). When in
Host mode, the 14-bit SOF counter counts the interval between SOF frames. The SOF must be transmitted every 1ms so therefore the SOF counter is loaded with a value of
12000. When the SOF counter reaches zero, a Start Of Frame (SOF) token is transmitted.
The SOF threshold register is used to program the number of USB byte times before the
SOF to stop initiating token packet transactions. This register must be set to a value that ensures that other packets are not actively being transmitted when the SOF time counts to zero. When the SOF counter reaches the threshold value, no more tokens are transmitted until after the SOF has been transmitted.
The value programmed into the threshold register must reserve enough time to ensure the worst case transaction completes. In general the worst case transaction is an IN token followed by a data packet from the target followed by the response from the host. The actual time required is a function of the maximum packet size on the bus.
Typical values for the SOF threshold are:
• 64-byte packets=74;
• 32-byte packets=42;
• 16-byte packets=26;
• 8-byte packets=18.
Address: 4007_2000h base + ACh offset = 4007_20ACh
Bit
Read
Write
Reset
Field
7–0
CNT
7 6 5 4 3
0 0 0 0 0
USBx_SOFTHLD field descriptions
Description
Represents the SOF count threshold in byte times.
2
0
1
0
0
0
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Chapter 35 Universal Serial Bus OTG Controller (USBOTG)
35.4.21 BDT Page Register 2 (USBx_BDTPAGE2)
Contains an 8-bit value used to compute the address where the current Buffer Descriptor
Table (BDT) resides in system memory.
Address: 4007_2000h base + B0h offset = 4007_20B0h
7 6 5 Bit
Read
Write
Reset 0 0 0
Field
7–0
BDTBA
4
3 2 1 0
0 0 0 0 0
USBx_BDTPAGE2 field descriptions
Description
Provides address bits 23 through 16 of the BDT base address that defines the location of Buffer Descriptor
Table resides in system memory.
35.4.22 BDT Page Register 3 (USBx_BDTPAGE3)
Contains an 8-bit value used to compute the address where the current Buffer Descriptor
Table (BDT) resides in system memory.
Address: 4007_2000h base + B4h offset = 4007_20B4h
Bit
Read
Write
Reset
Field
7–0
BDTBA
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
USBx_BDTPAGE3 field descriptions
Description
Provides address bits 31 through 24 of the BDT base address that defines the location of Buffer Descriptor
Table resides in system memory.
35.4.23 Endpoint Control register (USBx_ENDPTn)
Contains the endpoint control bits for each of the 16 endpoints available within the USB module for a decoded address. The format for these registers is shown in the following figure. Endpoint 0 (ENDPT0) is associated with control pipe 0, which is required for all
USB functions. Therefore, after a USBRST interrupt occurs the processor core should set
ENDPT0 to contain 0x0D.
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In Host mode ENDPT0 is used to determine the handshake, retry and low speed characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the
EPHSHK bit should be 1. For Isochronous transfers it should be 0. Common values to use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers, and
0x4C for Isochronous transfers.
Address: 4007_2000h base + C0h offset + (4d × i), where i=0d to 15d
Bit 7
Write
Reset 0
Field
7
HOSTWOHUB
6
RETRYDIS
5
Reserved
4
EPCTLDIS
3
EPRXEN
2
EPTXEN
1
EPSTALL
0
EPHSHK
6
0
5
0
4 3
0
2
1
0
USBx_ENDPTn field descriptions
Description
This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only. When set this bit allows the host to communicate to a directly connected low speed device. When cleared, the host produces the PRE_PID. It then switches to low-speed signaling when sends a token to a low speed device as required to communicate with a low speed device through a hub.
This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only. When set this bit causes the host to not retry NAK'ed (Negative Acknowledgement) transactions. When a transaction is NAKed, the BDT PID field is updated with the NAK PID, and the TOKEN_DNE interrupt is set. When this bit is cleared NAKed transactions is retried in hardware. This bit must be set when the host is attempting to poll an interrupt endpoint.
This field is reserved.
This read-only field is reserved and always has the value 0.
This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This applies if and only if the EPRXEN and EPTXEN bits are also set.
This bit, when set, enables the endpoint for RX transfers.
This bit, when set, enables the endpoint for TX transfers.
0 0 0 0
When set this bit indicates that the endpoint is called. This bit has priority over all other control bits in the
EndPoint Enable Register, but it is only valid if EPTXEN=1 or EPRXEN=1. Any access to this endpoint causes the USB Module to return a STALL handshake. After an endpoint is stalled it requires intervention from the Host Controller.
When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint. This bit is generally 1 unless the endpoint is Isochronous.
35.4.24 USB Control register (USBx_USBCTRL)
Address: 4007_2000h base + 100h offset = 4007_2100h
5 Bit
Read
Write
Reset
7
1
6
1 0
660
4
0
3
0
2
0
1
0
0
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Field
7
SUSP
6
PDE
5–0
Reserved
Chapter 35 Universal Serial Bus OTG Controller (USBOTG)
USBx_USBCTRL field descriptions
Description
Places the USB transceiver into the suspend state.
0 USB transceiver is not in suspend state.
1 USB transceiver is in suspend state.
Enables the weak pulldowns on the USB transceiver.
0 Weak pulldowns are disabled on D+ and D–.
1 Weak pulldowns are enabled on D+ and D–.
This field is reserved.
This read-only field is reserved and always has the value 0.
35.4.25 USB OTG Observe register (USBx_OBSERVE)
Provides visibility on the state of the pull-ups and pull-downs at the transceiver. Useful when interfacing to an external OTG control module via a serial interface.
Address: 4007_2000h base + 104h offset = 4007_2104h
Bit
Read
Write
Reset
7
6
5
Field
7
DPPU
4
3 2
0 1 0 1 0 0
USBx_OBSERVE field descriptions
Description
Provides observability of the D+ Pullup . signal output from the USB OTG module
6
DPPD
0 D+ pullup disabled.
1 D+ pullup enabled.
Provides observability of the D+ Pulldown . signal output from the USB OTG module
5
Reserved
4
DMPD
0 D+ pulldown disabled.
1 D+ pulldown enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
Provides observability of the D- Pulldown signal output from the USB OTG module
3–1
Reserved
0
Reserved
0 D– pulldown disabled.
1 D– pulldown enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
1
0
0
0
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Memory map/Register definitions
35.4.26 USB OTG Control register (USBx_CONTROL)
Address: 4007_2000h base + 108h offset = 4007_2108h
7 Bit
Read
Write
Reset 0
6
0
5
0
4
0
Bit
Read
Write
Reset
3 2
1 0
0 0 0 0
USBx_CONTROL field descriptions
Field
7–5
Reserved
4
DPPULLUPNONOTG
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Provides control of the DP Pullup in the USB OTG module, if USB is configured in non-OTG device mode.
3–0
Reserved
0 DP Pullup in non-OTG device mode is not enabled.
1 DP Pullup in non-OTG device mode is enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
35.4.27 USB Transceiver Control register 0 (USBx_USBTRC0)
Includes signals for basic operation of the on-chip USB Full Speed transceiver and configuration of the USB data connection that are not otherwise included in the USB Full
Speed controller registers.
Address: 4007_2000h base + 10Ch offset = 4007_210Ch
7 Bit
Read
Write
Reset
0
Bit
Read
Write
Reset
3
0
6
0
2
0
5
0
1
0
4
0
0
0
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Field
7
USBRESET
Chapter 35 Universal Serial Bus OTG Controller (USBOTG)
USBx_USBTRC0 field descriptions
Description
USB Reset
Generates a hard reset to the USB_OTG module. After this bit is set and the reset occurs, this bit is automatically cleared.
NOTE: This bit is always read as zero. Wait two USB clock cycles after setting this bit.
0 Normal USB module operation.
1 Returns the USB module to its reset state.
This field is reserved.
6
Reserved
5
USBRESMEN
NOTE: Software must set this bit to 1b.
Asynchronous Resume Interrupt Enable
This bit, when set, allows the USB module to send an asynchronous wakeup event to the MCU upon detection of resume signaling on the USB bus. The MCU then re-enables clocks to the USB module. It is used for low-power suspend mode when USB module clocks are stopped or the USB transceiver is in
Suspend mode. Async wakeup only works in device mode.
4–2
Reserved
1
SYNC_DET
0 USB asynchronous wakeup from suspend mode disabled.
1 USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs from the synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered state of the D+ and D– pins. This interupt should only be enabled when the Transceiver is suspended.
This field is reserved.
This read-only field is reserved and always has the value 0.
Synchronous USB Interrupt Detect
0 Synchronous interrupt has not been detected.
1 Synchronous interrupt has been detected.
USB Asynchronous Interrupt 0
USB_RESUME_
INT 0 No interrupt was generated.
1 Interrupt was generated because of the USB asynchronous interrupt.
35.4.28 Frame Adjust Register (USBx_USBFRMADJUST)
Address: 4007_2000h base + 114h offset = 4007_2114h
7 6 5 Bit
Read
Write
Reset 0 0 0
Field
7–0
ADJ
4
3 2
0 0 0
USBx_USBFRMADJUST field descriptions
Description
Frame Adjustment
1
0
0
0
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OTG and Host mode operation
USBx_USBFRMADJUST field descriptions (continued)
Field Description
In Host mode, the frame adjustment is a twos complement number that adjusts the period of each USB frame in 12-MHz clock periods. A SOF is normally generated every 12,000 12-MHz clock cycles. The
Frame Adjust Register can adjust this by -128 to +127 to compensate for inaccuracies in the USB 48-MHz clock. Changes to the ADJ bit take effect at the next start of the next frame.
35.5 OTG and Host mode operation
The Host mode logic allows devices such as digital cameras and palmtop computers to function as a USB Host Controller. The OTG logic adds an interface to allow the OTG
Host Negotiation and Session Request Protocols (HNP and SRP) to be implemented in software. Host Mode allows a peripheral such as a digital camera to be connected directly to a USB compliant printer. Digital photos can then be easily printed without having to upload them to a PC. In the palmtop computer application, a USB compliant keyboard/ mouse can be connected to the palmtop computer with the obvious advantages of easier interaction.
Host mode is intended for use in handheld-portable devices to allow easy connection to simple HID class devices such as printers and keyboards. It is not intended to perform the functions of a full OHCI or UHCI compatible host controller found on PC motherboards.
The USB-FS is not supported by Windows 98 as a USB host controller. Host mode allows bulk, isochronous, interrupt and control transfers. Bulk data transfers are performed at nearly the full USB interface bandwidth. Support is provided for ISO transfers, but the number of ISO streams that can be practically supported is affected by the interrupt latency of the processor servicing the token during interrupts from the SIE.
Custom drivers must be written to support Host mode operation.
Setting the HOST_MODE_EN bit in the CTL register enables Host mode. The USB-FS core can only operate as a peripheral device or in Host mode. It cannot operate in both modes simultaneously. When HOST_MODE is enabled, only endpoint zero is used. All other endpoints should be disabled by software.
35.6 Host Mode Operation Examples
The following sections illustrate the steps required to perform USB host functions using the USB-FS core. While it is useful to understand the interaction of the hardware and the software at a detailed level, an understanding of the interactions at this level is not required to write host applications using the API software.
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Chapter 35 Universal Serial Bus OTG Controller (USBOTG)
To enable host mode and discover a connected device:
1. Enable Host Mode (CTL[HOST_MODE_EN]=1). The pull-down resistors are enabled, and pull-up disabled. Start of Frame (SOF) generation begins. SOF counter loaded with 12,000. Disable SOF packet generation to eliminate noise on the USB by writing the USB enable bit to 0 (CTL[USB_EN]=0).
2. Enable the ATTACH interrupt (INT_ENB[ATTACH]=1).
3. Wait for ATTACH interrupt (INT_STAT[ATTACH]). Signaled by USB Target pullup resistor changing the state of DPLUS or DMINUS from 0 to 1 (SE0 to J or K state).
4. Check the state of the JSTATE and SE0 bits in the control register. If the connecting device is low speed (JSTATE bit is 0), set the low-speed bit in the address registers
(ADDR[LS_EN]=1) and the Host Without Hub bit in endpoint 0 register control
(ENDPT0[HOSTWOHUB]=1).
5. Enable RESET (CTL[RESET]=1) for 10 ms.
6. Enable SOF packet to keep the connected device from going to suspend
(CTL[USB_EN=1]).
7. Start enumeration by sending a sequence of device framework commands, device frame work packets to the default control pipe of the connected device. See the
Universal Serial Bus Revision 2.0 specification, "Chapter 9 USB Device Framework"
(http://www.usb.org/developers/docs).
To complete a control transaction to a connected device:
1. Complete all the steps to discover a connected device
2. Set up the endpoint control register for bidirectional control transfers ENDPT0[4:0]
= 0x0d.
3. Place a copy of the device framework setup command in a memory buffer. See the
Universal Serial Bus Revision 2.0 specification, "Chapter 9 USB Device Framework"
(http://www.usb.org/developers/docs).
4. Initialize current even or odd TX EP0 BDT to transfer the 8 bytes of command data for a device framework command (for example, a GET DEVICE DESCRIPTOR).
• Set the BDT command word to 0x00080080 –Byte count to 8, OWN bit to 1.
• Set the BDT buffer address field to the start address of the 8 byte command buffer.
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Host Mode Operation Examples
5. Set the USB device address of the target device in the address register (ADDR[6:0]).
After the USB bus reset, the device USB address is zero. It is set to some other value usually 1 by the Set Address device framework command.
6. Write the token register with a SETUP to Endpoint 0 the target device default control pipe (TOKEN=0xD0). This initiates a setup token on the bus followed by a data packet. The device handshake is returned in the BDT PID field after the packets complete. When the BDT is written, a token done (ISTAT[TOKDNE]) interrupt is asserted. This completes the setup phase of the setup transaction. Se the Universal
Serial Bus Revision 2.0 specification, "Chapter 9 USB Device Framework" (http:// www.usb.org/developers/docs).
7. To initiate the data phase of the setup transaction (that is, get the data for the GET
DEVICE DESCRIPTOR command), set up a buffer in memory for the data to be transferred.
8. Initialize the current even or odd TX EP0 BDT to transfer the data.
• Set the BDT command word to 0x004000C0 – BC to 64 (the byte count of the data buffer in this case), OWN bit to 1, Data toggle to Data1.
• Set the BDT buffer address field to the start address of the data buffer
9. Write the token register with a IN or OUT token to Endpoint 0 the target device default control pipe, an IN token for a GET DEVICE DESCRIPTOR command
(TOKEN=0x90). This initiates an IN token on the bus followed by a data packet from the device to the host. When the data packet completes, the BDT is written and a token done (ISTAT[DNE]) interrupt is asserted. For control transfers with a single packet data phase this completes the data phase of the setup transaction. See the
Universal Serial Bus Revision 2.0 specification, "Chapter 9 USB Device Framework"
(http://www.usb.org/developers/docs).
10. To initiate the status phase of the setup transaction, set up a buffer in memory to receive or send the zero length status phase data packet.
11. Initialize the current even or odd TX EP0 BDT to transfer the status data.
• Set the BDT command word to 0x00000080 – BC to 0 (the byte count of the data buffer in this case), OWN bit to 1, Data toggle to Data1.
• Set the BDT buffer address field to the start address of the data buffer
12. Write the token register with a IN or OUT token to Endpoint 0 the target device default control pipe, an OUT token for a GET DEVICE DESCRIPTOR command
(TOKEN=0x10). This initiates an OUT token on the bus followed by a zero length data packet from the host to the device. When the data packet completes, the BDT is written with the handshake from the device and a Token Done (ISTAT[TOKDNE])
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Chapter 35 Universal Serial Bus OTG Controller (USBOTG) interrupt is asserted. This completes the data phase of the setup transaction. See the
Universal Serial Bus Revision 2.0 specification, "Chapter 9 USB Device Framework"
(http://www.usb.org/developers/docs).
To send a full speed bulk data transfer to a target device:
1. Complete all steps to discover a connected device and to configure a connected device. Write the ADDR register with the address of the target device. Typically, there is only one other device on the USB bus in host mode so it is expected that the address is 0x01 and should remain constant.
2. Write 0x1D to ENDPT0 register to enable transmit and receive transfers with handshaking enabled.
3. Setup the even TX EP0 BDT to transfer up to 64 bytes.
4. Set the USB device address of the target device in the address register (ADDR[6:0]).
5. Write the TOKEN register with an OUT token to the desired endpoint. The write to this register triggers the USB-FS transmit state machines to begin transmitting the
TOKEN and the data.
6. Setup the odd TX EP0 BDT to transfer up to 64 bytes.
7. Write the TOKEN register with an OUT token as in step 4. Two tokens can be queued at a time to allow the packets to be double buffered to achieve maximum throughput.
8. Wait for the TOKDNE interrupt. This indicates that one of the BDTs has been released back to the processor and the transfer has completed. If the target device asserts NAKs, the USB-FS continues to retry the transfer indefinitely without processor intervention unless the ENDPT0[RETRYDIS] is 1. If the retry disable field is set, the handshake (ACK, NAK, STALL, or ERROR (0xf)) is returned in the BDT
PID field. If a stall interrupt occurs, the pending packet must be dequeued and the error condition in the target device cleared. If a Reset interrupt occurs (SE0 for more than 2.5 μ s), the target has detached.
9. After the TOK_DNE interrupt occurs, the BDTs can be examined and the next data packet queued by returning to step 2.
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On-The-Go operation
35.7 On-The-Go operation
The USB-OTG core provides sensors and controls to enable On-The-Go (OTG) operation. These sensors are used by the OTG API software to implement the Host
Negotiation Protocol (HNP) and Session Request Protocol (SRP). API calls are provided to give access the OTG protocol control signals, and include the OTG capabilities in the device application. The following state machines show the OTG operations involved with
HNP and SRP protocols from either end of the USB cable.
35.7.1 OTG dual role A device operation
A device is considered the A device because of the type of cable attached. If the USB
Type A connector or the USB Type Mini A connector is plugged into the device, it is considered the A device.
A dual role A device operates as the following flow diagram and state description table illustrates.
A_IDLE B_IDLE
A_WAIT_VFALL
A_PERIPHERAL
A_WAIT_VRISE
A_WAIT_BCON
A_SUSPEND A_HOST
Figure 35-93. Dual role A device flow diagram
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State
A_IDLE
A_WAIT_VRISE
A_WAIT_BCON
A_HOST
A_SUSPEND
A_PERIPHERAL
A_WAIT_VFALL
Chapter 35 Universal Serial Bus OTG Controller (USBOTG)
Table 35-96. State descriptions for the dual role A device flow
Action
If ID Interrupt.
The cable has been un-plugged or a Type B cable has been attached. The device now acts as a Type B device.
If the A application wants to use the bus or if the B device is doing an SRP as indicated by an A_SESS_VLD Interrupt or Attach or Port
Status Change Interrupt check data line for 5 –10 msec pulsing.
If ID Interrupt or if A_VBUS_VLD is false after 100 msec
The cable has been changed or the A device cannot support the current required from the B device.
If A_VBUS_VLD interrupt
After 200 ms without Attach or ID Interrupt. (This could wait forever if desired.)
A_VBUS_VLD Interrupt and B device attaches
Response
Go to B_IDLE
Go to A_WAIT_VRISE
Turn on DRV_VBUS
Go to A_WAIT_VFALL
Turn off DRV_VBUS
Go to A_WAIT_BCON
Go to A_WAIT_FALL
Turn off DRV_VBUS
Go to A_HOST
Turn on Host mode
Enumerate Device determine OTG Support.
If A_VBUS_VLD/ Interrupt or A device is done and doesn't think he wants to do something soon or the B device disconnects
Go to A_WAIT_VFALL
Turn off Host mode
Turn off DRV_VBUS
Go to A_SUSPEND If the A device is finished with session or if the A device wants to allow the B device to take bus.
ID Interrupt or the B device disconnects
If ID Interrupt, or if 150 ms B disconnect timeout (This timeout value could be longer) or if A_VBUS_VLD\ Interrupt
If HNP enabled, and B disconnects in 150 ms then B device is becoming the host.
If A wants to start another session
If ID Interrupt or if A_VBUS_VLD interrupt
If 3 –200 ms of Bus Idle
If ID Interrupt or (A_SESS_VLD/ & b_conn/)
Go to A_WAIT_BCON
Go to A_WAIT_VFALL
Turn off DRV_VBUS
Go to A_PERIPHERAL
Turn off Host mode
Go to A_HOST
Go to A_WAIT_VFALL
Turn off DRV_VBUS.
Go to A_WAIT_BCON
Turn on Host mode
Go to A_IDLE
35.7.2 OTG dual role B device operation
A device is considered a B device if it connected to the bus with a USB Type B cable or a
USB Type Mini B cable.
A dual role B device operates as the following flow diagram and state description table illustrates.
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B_IDLE A_IDLE
B_SRP_INIT B_HOST
B_WAIT_ACON B_PERIPHERAL
Figure 35-94. Dual role B device flow diagram
State
B_IDLE
B_SRP_INIT
B_PERIPHERAL
B_WAIT_ACON
B_HOST
Table 35-97. State descriptions for the dual role B device flow
Action
If ID\ Interrupt.
A Type A cable has been plugged in and the device should now respond as a Type A device.
If B_SESS_VLD Interrupt.
The A device has turned on VBUS and begins a session.
If B application wants the bus and Bus is Idle for 2 ms and the
B_SESS_END bit is set, the B device can perform an SRP.
Response
Go to A_IDLE
Go to B_PERIPHERAL
Turn on DP_HIGH
Go to B_SRP_INIT
Pulse CHRG_VBUS
Pulse DP_HIGH 5-10 ms
Go to B_IDLE If ID\ Interrupt or SRP Done (SRP must be done in less than 100 ms.)
If HNP enabled and the bus is suspended and B wants the bus, the
B device can become the host.
If A connects, an attach interrupt is received
Go to B_WAIT_ACON
Turn off DP_HIGH
Go to B_HOST
If ID\ Interrupt or B_SESS_VLD/ Interrupt
If the cable changes or if VBUS goes away, the host doesn't support us.
Turn on Host Mode
Go to B_IDLE
Go to B_IDLE
If 3.125 ms expires or if a Resume occurs
If ID\ Interrupt or B_SESS_VLD\ Interrupt
If the cable changes or if VBUS goes away, the host doesn't support us.
If B application is done or A disconnects
Go to B_PERIPHERAL
Go to B_IDLE
Go to B_PERIPHERAL
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Chapter 36
USB Voltage Regulator
The USB Voltage Regulator module is a LDO linear voltage regulator to provide 3.3V
power from an input power supply varying from 2.7 V to 5.5 V.
36.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
The USB Voltage Regulator module is a LDO linear voltage regulator to provide 3.3V
power from an input power supply varying from 2.7 V to 5.5 V. It consists of one 3.3 V power channel. When the input power supply is below 3.6 V, the regulator goes to passthrough mode. The following figure shows the ideal relation between the regulator output and input power supply.
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Introduction
OUTPUT
(Volt)
3.3
2.1
2.7
3.6
5.5
INPUT (Volt)
Figure 36-1. Ideal Relation Between the Regulator Output and Input Power Supply
36.1.1 Overview
A simplified block diagram for the USB Voltage Regulator module is shown below.
STANDBY Regulator
No
Yes
STANDBY
Other Modules
Power
Supply reg33_in
RUN Regulator reg33_out
Regulated Output
Voltage
ESR: 5m -> 100m Ohms
External Capacitor typical = 2.2uF
Chip
Figure 36-2. USB Voltage Regulator Block Diagram
This module uses 2 regulators in parallel. In run mode, the RUN regulator with the bandgap voltage reference is enabled and can provide up to 120 mA load current. In run mode, the STANDBY regulator and the low power reference are also enabled, but a switch disconnects its output from the external pin. In STANDBY mode, the RUN regulator is disabled and the STANDBY regulator output is connected to the external pin.
Internal power mode signals control whether the module is in RUN or STANDBY mode.
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Chapter 36 USB Voltage Regulator
36.1.2 Features
• Low drop-out linear voltage regulator with one power channel (3.3 V).
• Low drop-out voltage: 300 mV.
• Output current: 120 mA.
• Three different power modes: RUN, STANDBY and SHUTDOWN.
• Low quiescent current in RUN mode.
• Typical value is around 120 µA (one thousand times smaller than the maximum load current).
• Very low quiescent current in STANDBY mode.
• Typical value is around 1 µA.
• Automatic current limiting if the load current is greater than 290 mA.
• Automatic power-up once some voltage is applied to the regulator input.
• Pass-through mode for regulator input voltages less than 3.6 V
• Small output capacitor: 2.2 µF
• Stable with aluminum, tantalum or ceramic capacitors.
36.1.3 Modes of Operation
The regulator has these power modes:
• RUN—The regulating loop of the RUN regulator and the STANDBY regulator are active, but the switch connecting the STANDBY regulator output to the external pin is open.
• STANDBY—The regulating loop of the RUN regulator is disabled and the standby regulator is active. The switch connecting the STANDBY regulator output to the external pin is closed.
• SHUTDOWN—The module is disabled.
The regulator is enabled by default. This means that once the power supply is provided, the module power-up sequence to RUN mode starts.
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USB Voltage Regulator Module Signal Descriptions
36.2 USB Voltage Regulator Module Signal Descriptions
The following table shows the external signals for the regulator.
Table 36-1. USB Voltage Regulator Module Signal Descriptions
Signal reg33_in reg33_out
Description
Unregulated power supply
Regulator output voltage
I/O
I
O
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Chapter 37
Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) module provides for full-duplex, synchronous, serial communication between the MCU and peripheral devices. These peripheral devices can include other microcontrollers, analog-to-digital converters, shift registers, sensors, and memories, among others.
37.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
The serial peripheral interface (SPI) module provides for full-duplex, synchronous, serial communication between the MCU and peripheral devices. These peripheral devices can include other microcontrollers, analog-to-digital converters, shift registers, sensors, and memories, among others.
The SPI runs at a baud rate up to the SPI module clock divided by two in master mode and up to the SPI module clock divided by four in slave mode. Software can poll the status flags, or SPI operation can be interrupt driven.
NOTE
For the actual maximum SPI baud rate, refer to the Chip
Configuration details and to the device’s Data Sheet.
The SPI also supports a data length of 8 or 16 bits and includes a hardware match feature for the receive data buffer.
The SPI includes an internal DMA interface to support continuous SPI transmission through an on-chip DMA controller instead of through the CPU. This feature decreases
CPU loading, allowing CPU time to be used for other work.
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37.1.1 Features
The SPI includes these distinctive features:
• Master mode or slave mode operation
• Full-duplex or single-wire bidirectional mode
• Programmable transmit bit rate
• Double-buffered transmit and receive data register
• Serial clock phase and polarity options
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Control of SPI operation during wait mode
• Selectable MSB-first or LSB-first shifting
• Programmable 8- or 16-bit data transmission length
• Receive data buffer hardware match feature
• 64-bit FIFO mode for high speed/large amounts of data transfers
• Support transmission of both Transmit and Receive by DMA
37.1.2 Modes of operation
The SPI functions in the following three modes.
• Run mode
This is the basic mode of operation.
• Wait mode
SPI operation in Wait mode is a configurable low power mode, controlled by the
SPISWAI bit located in the SPIx_C2 register. In Wait mode, if C2[SPISWAI] is clear, the SPI operates like in Run mode. If C2[SPISWAI] is set, the SPI goes into a power conservative state, with the SPI clock generation turned off. If the SPI is
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Chapter 37 Serial Peripheral Interface (SPI) configured as a master, any transmission in progress stops, but is resumed after CPU enters Run mode. If the SPI is configured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master.
• Stop mode
To reduce power consumption, the SPI is inactive in stop modes where the peripheral bus clock is stopped but internal logic states are retained. If the SPI is configured as a master, any transmission in progress stops, but is resumed after the CPU enters run mode. If the SPI is configured as a slave, reception and transmission of a data continues, so that the slave stays synchronized to the master.
The SPI is completely disabled in Stop modes where the peripheral bus clock is stopped and internal logic states are not retained. When the CPU wakes from these
Stop modes, all SPI register content is reset.
Detailed descriptions of operating modes appear in Low-power mode options
.
37.1.3 Block diagrams
This section includes block diagrams showing SPI system connections, the internal organization of the SPI module, and the SPI clock dividers that control the master mode bit rate.
37.1.3.1 SPI system block diagram
The following figure shows the SPI modules of two MCUs connected in a master-slave arrangement. The master device initiates all SPI data transfers. During a transfer, the master shifts data out (on the MOSI pin) to the slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively exchanges the data that was in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock output from the master and an input to the slave. The slave device must be selected by a low level on the slave select input (SS pin). In this system, the master device has configured its SS pin as an optional slave select output.
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MASTER
SPI SHIFTER
8 OR 16 BITS
CLOCK
GENERATOR
MOSI
MISO
MOSI
MISO
SPSCK SPSCK
SS SS
Figure 37-1. SPI system connections
SLAVE
SPI SHIFTER
8 OR 16 BITS
37.1.3.2 SPI module block diagram
The following is a block diagram of the SPI module. The central element of the SPI is the
SPI shift register. Data is written to the double-buffered transmitter (write to
SPIx_DH:SPIx_DL) and gets transferred to the SPI Shift Register at the start of a data transfer. After shifting in 8 bits or 16 bits (as determined by the SPIMODE bit) of data, the data is transferred into the double-buffered receiver where it can be read from
SPIx_DH:SPIx_DL. Pin multiplexing logic controls connections between MCU pins and the SPI module.
When the FIFO feature is supported: Additionally there is an 8-byte receive FIFO and an
8-byte transmit FIFO that (once enabled) provide features to allow fewer CPU interrupts to occur when transmitting/receiving high volume/high speed data. When FIFO mode is enabled, the SPI can still function in either 8-bit or 16-bit mode (as per SPIMODE bit) and three additional flags help monitor the FIFO status. Two of these flags can provide
CPU interrupts.
When the SPI is configured as a master, the clock output is routed to the SPSCK pin, the shifter output is routed to MOSI, and the shifter input is routed from the MISO pin.
When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the
SPI, the shifter output is routed to MISO, and the shifter input is routed from the MOSI pin.
In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all MOSI pins together. Peripheral devices often use slightly different names for these pins.
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SPE Tx FIFO (64 bits deep)
Tx BUFFER (WRITE DH:DL)
ENABLE
SPI SYSTEM
SPIMODE
FIFOMODE
LSBFE
SHIFT
OUT
SPI SHIFT REGISTER
SHIFT
IN
8 OR 16
BIT MODE
Rx BUFFER (READ DH:DL)
Rx FIFO (64 bits deep)
SHIFT
DIRECTION
SHIFT
CLOCK
Rx BUFFER
FULL
Tx BUFFER
EMPTY
SPC0
BIDIROE
Chapter 37 Serial Peripheral Interface (SPI)
PIN CONTROL
M
S
MOSI
(MOMI)
M
S
MISO
(SISO)
BUS RATE
CLOCK
MSTR
SPI BR
CLOCK GENERATOR
MASTER/SLAVE
MODE SELECT
CLOCK
LOGIC
RX DMA DONE
RX DMA REQ
TX DMA DONE
TX DMA REQ
MASTER CLOCK
SLAVE CLOCK
M
S
MASTER/
SLAVE
MODFEN
SSOE
MODE FAULT
DETECTION
RX BUFFER
NOT EMPTY
RXDMAE
TX BUFFER
NOT FULL
TXDMAE
SPRF
SPTEF
16-BIT COMPARATOR
MH:ML
16-BIT LATCH
RNFULLF
RNFULLIEN
TNEAREF
TNEARIEN
MODF
SPTIE
SPIE
Figure 37-2. SPI Module Block Diagram with FIFO
SPMF
SPMIE
SPI
INTERRUPT
REQUEST
SPSCK
SS
37.2 External signal description
The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control bits. When the SPI is disabled (SPE = 0), these four pins revert to other functions that are not controlled by the SPI (based on chip configuration).
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External signal description
37.2.1 SPSCK — SPI Serial Clock
When the SPI is enabled as a slave, this pin is the serial clock input. When the SPI is enabled as a master, this pin is the serial clock output.
37.2.2 MOSI — Master Data Out, Slave Data In
When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data output. When the SPI is enabled as a slave and SPC0 is 0, this pin is the serial data input. If SPC0 is 1 to select single-wire bidirectional mode, and master mode is selected, this pin becomes the bidirectional data
I/O pin (MOMI). Also, the bidirectional mode output enable bit determines whether the pin acts as an input (BIDIROE is 0) or an output (BIDIROE is 1). If SPC0 is 1 and slave mode is selected, this pin is not used by the SPI and reverts to other functions (based on chip configuration).
37.2.3 MISO — Master Data In, Slave Data Out
When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data input. When the SPI is enabled as a slave and SPC0 is 0, this pin is the serial data output. If SPC0 is 1 to select single-wire bidirectional mode, and slave mode is selected, this pin becomes the bidirectional data I/
O pin (SISO), and the bidirectional mode output enable bit determines whether the pin acts as an input (BIDIROE is 0) or an output (BIDIROE is 1). If SPC0 is 1 and master mode is selected, this pin is not used by the SPI and reverts to other functions (based on chip configuration).
37.2.4 SS — Slave Select
When the SPI is enabled as a slave, this pin is the low-true slave select input. When the
SPI is enabled as a master and mode fault enable is off (MODFEN is 0), this pin is not used by the SPI and reverts to other functions (based on chip configuration). When the
SPI is enabled as a master and MODFEN is 1, the slave select output enable bit determines whether this pin acts as the mode fault input (SSOE is 0) or as the slave select output (SSOE is 1).
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Chapter 37 Serial Peripheral Interface (SPI)
37.3 Memory map/register definition
The SPI has 8-bit registers to select SPI options, to control baud rate, to report SPI status, to hold an SPI data match value, and for transmit/receive data.
SPI memory map
Absolute address
(hex)
Register name
4007_6000 SPI Status Register (SPI0_S)
4007_6001 SPI Baud Rate Register (SPI0_BR)
4007_6002 SPI Control Register 2 (SPI0_C2)
4007_6003 SPI Control Register 1 (SPI0_C1)
4007_6004 SPI Match Register low (SPI0_ML)
4007_6005 SPI match register high (SPI0_MH)
4007_6006 SPI Data Register low (SPI0_DL)
4007_6007 SPI data register high (SPI0_DH)
4007_600A SPI clear interrupt register (SPI0_CI)
4007_600B SPI control register 3 (SPI0_C3)
4007_7000 SPI Status Register (SPI1_S)
4007_7001 SPI Baud Rate Register (SPI1_BR)
4007_7002 SPI Control Register 2 (SPI1_C2)
4007_7003 SPI Control Register 1 (SPI1_C1)
4007_7004 SPI Match Register low (SPI1_ML)
4007_7005 SPI match register high (SPI1_MH)
4007_7006 SPI Data Register low (SPI1_DL)
4007_7007 SPI data register high (SPI1_DH)
4007_700A SPI clear interrupt register (SPI1_CI)
4007_700B SPI control register 3 (SPI1_C3)
Width
(in bits)
Access Reset value
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00h
20h
00h
00h
04h
00h
00h
00h
00h
00h
20h
00h
00h
04h
00h
00h
00h
00h
00h
00h
Section/ page
37.3.1 SPI Status Register (SPIx_S)
This register contains read-only status bits. Writes have no meaning or effect.
When the FIFO is supported and enabled (FIFOMODE is 1): This register has four flags that provide mechanisms to support an 8-byte FIFO mode: RNFULLF, TNEARF,
TXFULLF, and RFIFOEF. When the SPI is in 8-byte FIFO mode, the function of SPRF
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Memory map/register definition and SPTEF differs slightly from their function in the normal buffered modes, mainly regarding how these flags are cleared by the amount available in the transmit and receive
FIFOs.
• The RNFULLF and TNEAREF help improve the efficiency of FIFO operation when transfering large amounts of data. These flags provide a "watermark" feature of the
FIFOs to allow continuous transmissions of data when running at high speed.
• The RNFULLF can generate an interrupt if the RNFULLIEN bit in the C3 register is set, which allows the CPU to start emptying the receive FIFO without delaying the reception of subsequent bytes. The user can also determine if all data in the receive
FIFO has been read by monitoring the RFIFOEF.
• The TNEAREF can generate an interrupt if the TNEARIEN bit in the C3 register is set, which allows the CPU to start filling the transmit FIFO before it is empty and thus to prevent breaks in SPI transmission.
NOTE
At an initial POR, the values of TNEAREF and RFIFOEF are
0. However, the status (S) register and both TX and RX FIFOs are reset due to a change of SPIMODE, FIFOMODE or SPE. If this type of reset occurs and FIFOMODE is 0, TNEAREF and
RFIFOEF continue to reset to 0. If this type of reset occurs and
FIFOMODE is 1, TNEAREF and RFIFOEF reset to 1.
Address: Base address + 0h offset
Bit
Read
7
6
Write
Reset 0 0
Field
7
SPRF
5
1
4
0
3 2 1
0 0 0
0
0
SPIx_S field descriptions
Description
SPI Read Buffer Full Flag (when FIFO is not supported or not enabled) or SPI read FIFO FULL flag (when
FIFO is supported and enabled)
When the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI data (DH:DL) register. When the receive DMA request is disabled (RXDMAE is 0), SPRF is cleared by reading SPRF while it is set and then reading the SPI data register. When the receive DMA request is enabled (RXDMAE is 1), SPRF is automatically cleared when the DMA transfer for the receive DMA request is completed (RX
DMA Done is asserted).
When FIFOMODE is 1: This bit indicates the status of the read FIFO when FIFOMODE is enabled. The
SPRF is set when the read FIFO has received 64 bits (4 words or 8 bytes) of data from the shifter and there have been no CPU reads of the SPI data (DH:DL) register. When the receive DMA request is disabled (RXDMAE is 0), SPRF is cleared by reading the SPI data register, resulting in the FIFO no longer being full, assuming another SPI message is not received. When the receive DMA request is enabled
(RXDMAE is 1), SPRF is automatically cleared when the first DMA transfer for the receive DMA request is completed (RX DMA Done is asserted).
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Field
6
SPMF
5
SPTEF
4
MODF
Chapter 37 Serial Peripheral Interface (SPI)
SPIx_S field descriptions (continued)
Description
0 No data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is not full (when FIFOMODE is 1)
1
Data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is full
(when FIFOMODE is 1)
SPI Match Flag
SPMF is set after SPRF is 1 when the value in the receive data buffer matches the value in the MH:ML registers. To clear the flag, read SPMF when it is set and then write a 1 to it.
0 Value in the receive data buffer does not match the value in the MH:ML registers
1 Value in the receive data buffer matches the value in the MH:ML registers
SPI Transmit Buffer Empty Flag (when FIFO is not supported or not enabled) or SPI transmit FIFO empty flag (when FIFO is supported and enabled)
When the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): This bit is set when the transmit data buffer is empty. When the transmit DMA request is disabled (TXDMAE is 0), SPTEF is cleared by reading the S register with SPTEF set and then writing a data value to the transmit buffer at
DH:DL. The S register must be read with SPTEF set to 1 before writing data to the DH:DL register; otherwise, the DH:DL write is ignored. When the transmit DMA request is enabled (TXDMAE is 1), SPTEF is automatically cleared when the DMA transfer for the transmit DMA request is completed (TX DMA Done is asserted). SPTEF is automatically set when all data from the transmit buffer transfers into the transmit shift register. For an idle SPI, data written to DH:DL is transferred to the shifter almost immediately so that
SPTEF is set within two bus cycles, allowing a second set of data to be queued into the transmit buffer.
After completion of the transfer of the data in the shift register, the queued data from the transmit buffer automatically moves to the shifter, and SPTEF is set to indicate that room exists for new data in the transmit buffer. If no new data is waiting in the transmit buffer, SPTEF simply remains set and no data moves from the buffer to the shifter.
When the FIFO is supported and enabled (FIFOMODE is 1): This bit provides the status of the FIFO rather than an 8-bit or a 16-bit buffer. This bit is set when the transmit FIFO is empty. When the transmit DMA request is disabled (TXDMAE is 0), SPTEF is cleared by writing a data value to the transmit FIFO at
DH:DL. When the transmit DMA request is enabled (TXDMAE is 1), SPTEF is automatically cleared when the DMA transfer for the transmit DMA request is completed (TX DMA Done is asserted). SPTEF is automatically set when all data from the transmit FIFO transfers into the transmit shift register. For an idle
SPI, data written to the DH:DL register is transferred to the shifter almost immediately, so that SPTEF is set within two bus cycles. A second write of data to the DH:DL register clears this SPTEF flag. After completion of the transfer of the data in the shift register, the queued data from the transmit FIFO automatically moves to the shifter, and SPTEF will be set only when all data written to the transmit FIFO has been transfered to the shifter. If no new data is waiting in the transmit FIFO, SPTEF simply remains set and no data moves from the buffer to the shifter.
0 SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when
FIFOMODE is 1)
1
SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when
FIFOMODE is 1)
Master Mode Fault Flag
MODF is set if the SPI is configured as a master and the slave select input goes low, indicating some other SPI device is also configured as a master. The SS pin acts as a mode fault error input only when
C1[MSTR] is 1, C2[MODFEN] is 1, and C1[SSOE] is 0; otherwise, MODF will never be set. MODF is cleared by reading MODF while it is 1 and then writing to the SPI Control Register 1 (C1).
0 No mode fault error
1 Mode fault error detected
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Memory map/register definition
Field
3
RNFULLF
SPIx_S field descriptions (continued)
Description
Receive FIFO nearly full flag
This flag is set when more than three 16-bit words or six 8-bit bytes of data remain in the receive FIFO, provided C3[RNFULLF_MARK] is 0, or when more than two 16-bit words or four 8-bit bytes of data remain in the receive FIFO, provided C3[RNFULLF_MARK] is 1. It has no function if FIFOMODE is not present or is 0.
2
TNEAREF
1
TXFULLF
0
RFIFOEF
0 Receive FIFO has received less than 48 bits (when C3[RNFULLF_MARK] is 0) or less than 32 bits
(when C3[RNFULLF_MARK] is 1)
1 Receive FIFO has received data of an amount equal to or greater than 48 bits (when
C3[RNFULLF_MARK] is 0) or 32 bits (when C3[RNFULLF_MARK] is 1)
Transmit FIFO nearly empty flag
This flag is set when only one 16-bit word or two 8-bit bytes of data remain in the transmit FIFO, provided
C3[TNEAREF_MARK] is 0, or when only two 16-bit words or four 8-bit bytes of data remain in the transmit
FIFO, provided C3[TNEAREF_MARK] is 1. If FIFOMODE is not enabled, ignore this bit.
NOTE: At an initial POR, the values of TNEAREF and RFIFOEF are 0. However, the status (S) register and both TX and RX FIFOs are reset due to a change of SPIMODE, FIFOMODE or SPE. If this type of reset occurs and FIFOMODE is 0, TNEAREF and RFIFOEF continue to reset to 0. If this type of reset occurs and FIFOMODE is 1, TNEAREF and RFIFOEF reset to 1.
0 Transmit FIFO has more than 16 bits (when C3[TNEAREF_MARK] is 0) or more than 32 bits (when
C3[TNEAREF_MARK] is 1) remaining to transmit
1 Transmit FIFO has an amount of data equal to or less than 16 bits (when C3[TNEAREF_MARK] is 0) or 32 bits (when C3[TNEAREF_MARK] is 1) remaining to transmit
Transmit FIFO full flag
This bit indicates the status of the transmit FIFO when FIFOMODE is enabled. This flag is set when there are 8 bytes in the transmit FIFO. If FIFOMODE is not enabled, ignore this bit.
When FIFOMODE and DMA are both enabled, the inverted TXFULLF is used to trigger a DMA transfer.
So when the transmit FIFO is not full, the DMA request is active, and remains active until the FIFO is full.
0 Transmit FIFO has less than 8 bytes
1 Transmit FIFO has 8 bytes of data
SPI read FIFO empty flag
This bit indicates the status of the read FIFO when FIFOMODE is enabled. If FIFOMODE is not enabled, ignore this bit.
When FIFOMODE and DMA are both enabled, the inverted RXIFOEF is used to trigger a DMA transfer.
So when the receive FIFO is not empty, the DMA request is active, and remains active until the FIFO is empty.
NOTE: At an initial POR, the values of TNEAREF and RFIFOEF are 0. However, the status (S) register and both TX and RX FIFOs are reset due to a change of SPIMODE, FIFOMODE or SPE. If this type of reset occurs and FIFOMODE is 0, TNEAREF and RFIFOEF continue to reset to 0. If this type of reset occurs and FIFOMODE is 1, TNEAREF and RFIFOEF reset to 1.
0 Read FIFO has data. Reads of the DH:DL registers in 16-bit mode or the DL register in 8-bit mode will empty the read FIFO.
1 Read FIFO is empty.
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Chapter 37 Serial Peripheral Interface (SPI)
37.3.2 SPI Baud Rate Register (SPIx_BR)
Use this register to set the prescaler and bit rate divisor for an SPI master. This register may be read or written at any time.
Address: Base address + 1h offset
Bit
Read
Write
Reset
7
0
6
0
Field
7
Reserved
6–4
SPPR[2:0]
5
0
4
0
3
0
2
0
1
0
0
0
SPIx_BR field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
SPI Baud Rate Prescale Divisor
This 3-bit field selects one of eight divisors for the SPI baud rate prescaler. The input to this prescaler is the SPI module clock. The output of this prescaler drives the input of the SPI baud rate divider. Refer to the description of “SPI Baud Rate Generation” for details.
3–0
SPR[3:0]
000 Baud rate prescaler divisor is 1.
001 Baud rate prescaler divisor is 2.
010 Baud rate prescaler divisor is 3.
011 Baud rate prescaler divisor is 4.
100 Baud rate prescaler divisor is 5.
101 Baud rate prescaler divisor is 6.
110 Baud rate prescaler divisor is 7.
111 Baud rate prescaler divisor is 8.
SPI Baud Rate Divisor
This 4-bit field selects one of nine divisors for the SPI baud rate divider. The input to this divider comes from the SPI baud rate prescaler. Refer to the description of “SPI Baud Rate Generation” for details.
0000
0001
0010
0011
0100
0101
0110
Baud rate divisor is 2.
Baud rate divisor is 4.
Baud rate divisor is 8.
Baud rate divisor is 16.
Baud rate divisor is 32.
Baud rate divisor is 64.
Baud rate divisor is 128.
0111
1000
Baud rate divisor is 256.
Baud rate divisor is 512.
All others Reserved
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37.3.3 SPI Control Register 2 (SPIx_C2)
This read/write register is used to control optional features of the SPI system.
Address: Base address + 2h offset
Bit
Read
Write
Reset
7
0
6
0
Field
7
SPMIE
5
0
4
0
3
0
2
0
1
0
SPIx_C2 field descriptions
Description
SPI Match Interrupt Enable
This is the interrupt enable bit for the SPI receive data buffer hardware match (SPMF) function.
0
0
6
SPIMODE
5
TXDMAE
4
MODFEN
3
BIDIROE
0 Interrupts from SPMF inhibited (use polling)
1 When SPMF is 1, requests a hardware interrupt
SPI 8-bit or 16-bit mode
This bit allows the user to select either an 8-bit or 16-bit SPI data transmission length. In master mode, a change of this bit aborts a transmission in progress, forces the SPI system into an idle state, and resets all status bits in the S register. Refer to the description of “Data Transmission Length” for details.
0 8-bit SPI shift register, match register, and buffers
1 16-bit SPI shift register, match register, and buffers
Transmit DMA enable
This bit enables a transmit DMA request. When this bit is set to 1, a transmit DMA request is asserted when both SPTEF and SPE are set, and the interrupt from SPTEF is disabled.
0 DMA request for transmit is disabled and interrupt from SPTEF is allowed
1 DMA request for transmit is enabled and interrupt from SPTEF is disabled
Master Mode-Fault Function Enable
When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used. For details, refer to the description of the SSOE bit in the C1 register.
0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
Bidirectional Mode Output Enable
When bidirectional mode is enabled because SPI pin control 0 (SPC0) is set to 1, BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin. Depending on whether the SPI is configured as a master or a slave, it uses the MOSI (MOMI) or MISO (SISO) pin, respectively, as the single SPI data I/O pin. When SPC0 is 0, BIDIROE has no meaning or effect.
0 Output driver disabled so SPI data I/O pin acts as an input
1 SPI I/O pin enabled as an output
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Field
2
RXDMAE
1
SPISWAI
0
SPC0
Chapter 37 Serial Peripheral Interface (SPI)
SPIx_C2 field descriptions (continued)
Description
Receive DMA enable
This is the enable bit for a receive DMA request. When this bit is set to 1, a receive DMA request is asserted when both SPRF and SPE are set, and the interrupt from SPRF is disabled.
0 DMA request for receive is disabled and interrupt from SPRF is allowed
1 DMA request for receive is enabled and interrupt from SPRF is disabled
SPI Stop in Wait Mode
This bit is used for power conservation while the device is in Wait mode.
0 SPI clocks continue to operate in Wait mode.
1 SPI clocks stop when the MCU enters Wait mode.
SPI Pin Control 0
Enables bidirectional pin configurations.
0 SPI uses separate pins for data input and data output (pin mode is normal).
In master mode of operation: MISO is master in and MOSI is master out.
In slave mode of operation: MISO is slave out and MOSI is slave in.
1 SPI configured for single-wire bidirectional operation (pin mode is bidirectional).
In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1.
In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1;
MOSI is not used by SPI.
37.3.4 SPI Control Register 1 (SPIx_C1)
This read/write register includes the SPI enable control, interrupt enables, and configuration options.
Address: Base address + 3h offset
Bit
Read
Write
Reset
7
0
6
0
Field
7
SPIE
5
0
4
0
3
0
2
1
1
0
0
0
SPIx_C1 field descriptions
Description
SPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO
(when FIFO is supported and enabled)
When the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): Enables the interrupt for SPI receive buffer full (SPRF) and mode fault (MODF) events.
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Field
SPIx_C1 field descriptions (continued)
Description
When the FIFO is supported and enabled (FIFOMODE is 1): This bit enables the SPI to interrupt the CPU when the receive FIFO is full. An interrupt occurs when the SPRF bit is set or the MODF bit is set.
6
SPE
5
SPTIE
4
MSTR
3
CPOL
2
CPHA
1
SSOE
0 Interrupts from SPRF and MODF are inhibited—use polling (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are disabled (when FIFOMODE is 1)
1
Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or
Read FIFO Full Interrupts are enabled (when FIFOMODE is 1)
SPI System Enable
Enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is cleared, the
SPI is disabled and forced into an idle state, and all status bits in the S register are reset.
0 SPI system inactive
1 SPI system enabled
SPI Transmit Interrupt Enable
When the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): This is the interrupt enable bit for SPI transmit buffer empty (SPTEF). An interrupt occurs when the SPI transmit buffer is empty (SPTEF is set).
When the FIFO is supported and enabled (FIFOMODE is 1): This is the interrupt enable bit for SPI transmit FIFO empty (SPTEF). An interrupt occurs when the SPI transmit FIFO is empty (SPTEF is set).
0 Interrupts from SPTEF inhibited (use polling)
1 When SPTEF is 1, hardware interrupt requested
Master/Slave Mode Select
Selects master or slave mode operation.
0 SPI module configured as a slave SPI device
1 SPI module configured as a master SPI device
Clock Polarity
Selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI modules must have identical CPOL values.
This bit effectively places an inverter in series with the clock signal either from a master SPI device or to a slave SPI device. Refer to the description of “SPI Clock Formats” for details.
0 Active-high SPI clock (idles low)
1 Active-low SPI clock (idles high)
Clock Phase
Selects one of two clock formats for different kinds of synchronous serial peripheral devices. Refer to the description of “SPI Clock Formats” for details.
0 First edge on SPSCK occurs at the middle of the first cycle of a data transfer.
1 First edge on SPSCK occurs at the start of the first cycle of a data transfer.
Slave Select Output Enable
This bit is used in combination with the Mode Fault Enable (MODFEN) field in the C2 register and the
Master/Slave (MSTR) control bit to determine the function of the SS pin.
0 When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input.
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Field
0
LSBFE
Chapter 37 Serial Peripheral Interface (SPI)
SPIx_C1 field descriptions (continued)
Description
When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode,
SS pin function is slave select input.
1 When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input.
When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.
LSB First (shifter direction)
This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data register always have the MSB in bit 7 (or bit 15 in 16-bit mode).
0 SPI serial data transfers start with the most significant bit.
1 SPI serial data transfers start with the least significant bit.
37.3.5 SPI Match Register low (SPIx_ML)
This register, together with the MH register, contains the hardware compare value. When the value received in the SPI receive data buffer equals this hardware compare value, the
SPI Match Flag in the S register (S[SPMF]) sets.
In 8-bit mode, only the ML register is available. Reads of the MH register return all zeros. Writes to the MH register are ignored.
In 16-bit mode, reading either byte (the MH or ML register) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. Writing to either byte (the MH or ML register) latches the value into a buffer. When both bytes have been written, they are transferred as a coherent value into the SPI match registers.
Address: Base address + 4h offset
Bit
Read
Write
Reset
7
0
6
0
Field
7–0
Bits[7:0]
5
0
4
0
3
0
SPIx_ML field descriptions
Description
Hardware compare value (low byte)
2
0
1
0
0
0
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Memory map/register definition
37.3.6 SPI match register high (SPIx_MH)
Refer to the description of the ML register.
Address: Base address + 5h offset
Bit
Read
Write
Reset
7
0
6
0
Field
7–0
Bits[15:8]
5
0
4
0
3
0
SPIx_MH field descriptions
Description
Hardware compare value (high byte)
2
0
1
0
0
0
37.3.7 SPI Data Register low (SPIx_DL)
This register, together with the DH register, is both the input and output register for SPI data. A write to the registers writes to the transmit data buffer, allowing data to be queued and transmitted.
When the SPI is configured as a master, data queued in the transmit data buffer is transmitted immediately after the previous transmission has completed.
The SPTEF bit in the S register indicates when the transmit data buffer is ready to accept new data. When the transmit DMA request is disabled (TXDMAE is 0): The S register must be read when S[SPTEF] is set before writing to the SPI data registers; otherwise, the write is ignored. When the transmit DMA request is enabled (TXDMAE is 1) when
S[SPTEF] is set, the SPI data registers can be written automatically by DMA without reading the S register first.
Data may be read from the SPI data registers any time after S[SPRF] is set and before another transfer is finished. Failure to read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition, and the data from the new transfer is lost. The new data is lost because the receive buffer still held the previous character and was not ready to accept the new data. There is no indication for a receive overrun condition, so the application system designer must ensure that previous data has been read from the receive buffer before a new transfer is initiated.
In 8-bit mode, only the DL register is available. Reads of the DH register return all zeros.
Writes to the DH register are ignored.
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In 16-bit mode, reading either byte (the DH or DL register) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. Writing to either byte (the DH or DL register) latches the value into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the transmit data buffer.
Address: Base address + 6h offset
Bit
Read
Write
Reset
7
0
6
0
5 4 3
0 0 0
SPIx_DL field descriptions
Description
2
0
1
0
0
0
Field
7–0
Bits[7:0]
Data (low byte)
37.3.8 SPI data register high (SPIx_DH)
Refer to the description of the DL register.
Address: Base address + 7h offset
Bit
Read
Write
Reset
7
0
6
0
5 4 3
0 0 0
SPIx_DH field descriptions
Description Field
7–0
Bits[15:8]
Data (high byte)
2
0
1
0
0
0
37.3.9 SPI clear interrupt register (SPIx_CI)
This register applies only for an instance of the SPI module that supports the FIFO feature.
The register has four bits dedicated to clearing the interrupts. Writing 1 to these bits clears the corresponding interrupts if the INTCLR bit in the C3 register is 1. Reading these bits always returns 0.
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This register also has two read-only bits to indicate the transmit FIFO and receive FIFO overrun conditions. When the receive FIFO is full and data is received, RXFOF is set.
Similarily, when the transmit FIFO is full and a write to the data register occurs, TXFOF is set. These flags are cleared when the CI register is read while the flags are set.
The register has two more read-only bits to indicate the error flags. These flags are set when, due to some spurious reason, entries in the FIFO total more than 64 bits of data. At this point, all the flags in the status register are reset, and entries in the FIFO are flushed with the corresponding error flags set. These flags are cleared when the CI register is read while the flags are set.
Address: Base address + Ah offset
Bit 7 6
Read
Write
Reset 0 0
Field
7
TXFERR
5
0
4
0
3
0
2
0
0 0
1
0
0
0
0
0
SPIx_CI field descriptions
Description
Transmit FIFO error flag
This flag indicates that a transmit FIFO error occurred because entries in the FIFO total more than 64 bits of data.
6
RXFERR
5
TXFOF
4
RXFOF
0 No transmit FIFO error occurred
1 A transmit FIFO error occurred
Receive FIFO error flag
This flag indicates that a receive FIFO error occurred because entries in the FIFO total more than 64 bits of data.
0 No receive FIFO error occurred
1 A receive FIFO error occurred
Transmit FIFO overflow flag
This flag indicates that a transmit FIFO overflow condition has occurred.
0 Transmit FIFO overflow condition has not occurred
1 Transmit FIFO overflow condition occurred
Receive FIFO overflow flag
This flag indicates that a receive FIFO overflow condition has occurred.
3
TNEAREFCI
2
RNFULLFCI
0 Receive FIFO overflow condition has not occurred
1 Receive FIFO overflow condition occurred
Transmit FIFO nearly empty flag clear interrupt
Writing 1 to this bit clears the TNEAREF interrupt provided that C3[3] is set.
Receive FIFO nearly full flag clear interrupt
Writing 1 to this bit clears the RNFULLF interrupt provided that C3[3] is set.
Table continues on the next page...
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Field
1
SPTEFCI
0
SPRFCI
Chapter 37 Serial Peripheral Interface (SPI)
SPIx_CI field descriptions (continued)
Description
Transmit FIFO empty flag clear interrupt
Writing 1 to this bit clears the SPTEF interrupt provided that C3[3] is set.
Receive FIFO full flag clear interrupt
Writing 1 to this bit clears the SPRF interrupt provided that C3[3] is set.
37.3.10 SPI control register 3 (SPIx_C3)
This register introduces a 64-bit FIFO function on both transmit and receive buffers. It applies only for an instance of the SPI module that supports the FIFO feature.
FIFO mode is enabled by setting the FIFOMODE bit to 1. A write to this register occurs only when it sets the FIFOMODE bit to 1.
Using this FIFO feature allows the SPI to provide high speed transfers of large amounts of data without consuming large amounts of the CPU bandwidth.
Enabling this FIFO function affects the behavior of some of the read/write buffer flags in the S register as follows:
• When the receive FIFO has data in it, S[RFIFOEF] is 0. As a result:
• If C2[RXDMAE] is 1, RFIFOEF_b generates a receive DMA request. The DMA request remains active until RFIFOEF is set to 1, indicating the receive buffer is empty.
• If C2[RXDMAE] is 0 and C1[SPIE] is 1, SPRF interrupts the CPU.
• When the transmit FIFO is not full, S[TXFULLF] is 0. As a result:
• If C2[TXDMAE] is 1, TXFULLF_b generates a transmit DMA request. The
DMA request remains active until TXFULLF is set to 1, indicating the transmit
FIFO is full.
• If C2[TXDMAE] is 0 and C1[SPTIE] is 1, SPTEF interrupts the CPU.
Two interrupt enable bits, TNEARIEN and RNFULLIEN, provide CPU interrupts based on the "watermark" feature of the TNEARF and RNFULLF flags of the S register.
Address: Base address + Bh offset
Bit
Read
Write
Reset
7
0
6
0
5
0
4
0
3
0
2 1 0
0 0 0
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Functional description
Field
7–6
Reserved
5
TNEAREF_
MARK
SPIx_C3 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Transmit FIFO nearly empty watermark
This bit selects the mark after which the TNEAREF flag is asserted.
4
RNFULLF_
MARK
0 TNEAREF is set when the transmit FIFO has 16 bits or less
1 TNEAREF is set when the transmit FIFO has 32 bits or less
Receive FIFO nearly full watermark
This bit selects the mark after which the RNFULLF flag is asserted.
3
INTCLR
0 RNFULLF is set when the receive FIFO has 48 bits or more
1 RNFULLF is set when the receive FIFO has 32 bits or more
Interrupt clearing mechanism select
This bit selects the mechanism by which the SPRF, SPTEF, TNEAREF, and RNFULLF interrupts are cleared.
2
TNEARIEN
1
RNFULLIEN
0
FIFOMODE
0 These interrupts are cleared when the corresponding flags are cleared depending on the state of the
FIFOs
1 These interrupts are cleared by writing the corresponding bits in the CI register
Transmit FIFO nearly empty interrupt enable
Writing 1 to this bit enables the SPI to interrupt the CPU when the TNEAREF flag is set. This bit is ignored and has no function if the FIFOMODE bit is 0.
0 No interrupt upon TNEAREF being set
1 Enable interrupts upon TNEAREF being set
Receive FIFO nearly full interrupt enable
Writing 1 to this bit enables the SPI to interrupt the CPU when the RNFULLF flag is set. This bit is ignored and has no function if the FIFOMODE bit is 0.
0 No interrupt upon RNFULLF being set
1 Enable interrupts upon RNFULLF being set
FIFO mode enable
This bit enables the SPI to use a 64-bit FIFO (8 bytes or four 16-bit words) for both transmit and receive buffers.
0 Buffer mode disabled
1 Data available in the receive data buffer
37.4 Functional description
This section provides the functional description of the module.
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Chapter 37 Serial Peripheral Interface (SPI)
37.4.1 General
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI Control Register 1.
While C1[SPE] is set, the four associated SPI port pins are dedicated to the SPI function as:
• Slave select (SS)
• Serial clock (SPSCK)
• Master out/slave in (MOSI)
• Master in/slave out (MISO)
An SPI transfer is initiated in the master SPI device by reading the SPI status register
(SPIx_S) when S[SPTEF] = 1 and then writing data to the transmit data buffer (write to
SPIx_DH:SPIx_DL). When a transfer is complete, received data is moved into the receive data buffer. The SPIx_DH:SPIx_DL registers act as the SPI receive data buffer for reads and as the SPI transmit data buffer for writes.
The Clock Phase Control (CPHA) and Clock Polarity Control (CPOL) bits in the SPI
Control Register 1 (SPIx_C1) select one of four possible clock formats to be used by the
SPI system. The CPOL bit simply selects a non-inverted or inverted clock. C1[CPHA] is used to accommodate two fundamentally different protocols by sampling data on odd numbered SPSCK edges or on even numbered SPSCK edges.
The SPI can be configured to operate as a master or as a slave. When the MSTR bit in
SPI Control Register 1 is set, master mode is selected; when C1[MSTR] is clear, slave mode is selected.
37.4.2 Master mode
The SPI operates in master mode when C1[MSTR] is set. Only a master SPI module can initiate transmissions. A transmission begins by reading the SPIx_S register while
S[SPTEF] = 1 and writing to the master SPI data registers. If the shift register is empty, the byte immediately transfers to the shift register. The data begins shifting out on the
MOSI pin under the control of the serial clock.
• SPSCK
• The SPR3, SPR2, SPR1, and SPR0 baud rate selection bits in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI Baud Rate register control the baud rate generator and determine the speed of the
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Functional description transmission. The SPSCK pin is the SPI clock output. Through the SPSCK pin, the baud rate generator of the master controls the shift register of the slave peripheral.
• MOSI, MISO pin
• In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is determined by the SPC0 and BIDIROE control bits.
• SS pin
• If C2[MODFEN] and C1[SSOE] are set, the SS pin is configured as slave select output. The SS output becomes low during each transmission and is high when the SPI is in idle state. If C2[MODFEN] is set and C1[SSOE] is cleared, the SS pin is configured as input for detecting mode fault error. If the SS input becomes low this indicates a mode fault error where another master tries to drive the
MOSI and SPSCK lines. In this case, the SPI immediately switches to slave mode by clearing C1[MSTR] and also disables the slave output buffer MISO (or
SISO in bidirectional mode). As a result, all outputs are disabled, and SPSCK,
MOSI and MISO are inputs. If a transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state. This mode fault error also sets the Mode Fault (MODF) flag in the SPI Status Register
(SPIx_S). If the SPI Interrupt Enable bit (SPIE) is set when S[ MODF] gets set, then an SPI interrupt sequence is also requested. When a write to the SPI Data
Register in the master occurs, there is a half SPSCK-cycle delay. After the delay,
SPSCK is started within the master. The rest of the transfer operation differs slightly, depending on the clock format specified by the SPI clock phase bit,
CPHA, in SPI Control Register 1 (see SPI clock formats ).
Note
A change of C1[CPOL], C1[CPHA], C1[SSOE], C1[LSBFE],
C2[MODFEN], C2[SPC0], C2[BIDIROE] with C2[SPC0] set,
SPIMODE, FIFOMODE, SPPR2-SPPR0 and SPR3-SPR0 in master mode abort a transmission in progress and force the SPI into idle state. The remote slave cannot detect this, therefore the master has to ensure that the remote slave is set back to idle state.
37.4.3 Slave mode
The SPI operates in slave mode when the MSTR bit in SPI Control Register 1 is clear.
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Chapter 37 Serial Peripheral Interface (SPI)
• SPSCK
In slave mode, SPSCK is the SPI clock input from the master.
• MISO, MOSI pin
In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI Control Register
2.
• SS pin
The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI must be low. SS must remain low until the transmission is complete. If
SS goes high, the SPI is forced into an idle state.
The SS input also controls the serial data output pin. If SS is high (not selected), the serial data output pin is high impedance. If SS is low, the first bit in the SPI Data
Register is driven out of the serial data output pin. Also, if the slave is not selected
(SS is high), then the SPSCK input is ignored and no internal shifting of the SPI shift register occurs.
Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin.
Note
When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave's serial data output line.
As long as no more than one slave device drives the system slave's serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves.
If the CPHA bit in SPI Control Register 1 is clear, odd numbered edges on the SPSCK input cause the data at the serial data input pin to be latched. Even numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.
If C1[CPHA] is set, even numbered edges on the SPSCK input cause the data at the serial data input pin to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on C1[LSBFE].
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Functional description
When C1[CPHA] is set, the first edge is used to get the first data bit onto the serial data output pin. When C1[CPHA] is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data output pin. After the eighth (SPIMODE =
0) or sixteenth (SPIMODE = 1) shift, the transfer is considered complete and the received data is transferred into the SPI Data register. To indicate transfer is complete, the SPRF flag in the SPI Status Register is set.
Note
A change of the bits FIFOMODE,SPIMODE, C2[BIDIROE] with C2[SPC0] set, C1[CPOL], C1[CPHA], C1[SSOE],
C1[LSBFE], C2[MODFEN], and C2[SPC0] in slave mode will corrupt a transmission in progress and must be avoided.
37.4.4 SPI FIFO Mode
When the FIFO feature is supported: The SPI works in FIFO mode when the
C3[FIFOMODE] bit is set. When the module is in FIFO mode, the SPI RX buffer and
SPI TX buffer are replaced by an 8-byte-deep FIFO, as the following figures show.
IPBus (ips_rdata[7:0])
Read Access
SPI_REG_BLOCK
FIFO Ctrlr spidh:l_rx_reg SPI Data Register
FIFO depth = 8 bytes
RX- FIFO
SPI_CORE_SHFR
Load
Control shfr_rx_reg
Figure 37-33. SPIH:L read side structural overview in FIFO mode
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IPBus (ips_rdata[7:0])
Read Access
SPI_REG_BLOCK
SPI Data Register
FIFO Ctrlr spidh:l_tx_reg
TX- FIFO
FIFO depth = 8 bytes
SPI_CORE_SHFR
Read
Control shfr_tx_reg
Figure 37-34. SPIH:L write side structural overview in FIFO mode
37.4.5 SPI Transmission by DMA
SPI supports both Transmit and Receive by DMA. The basic flow of SPI transmission by
DMA is as below.
RESET
Configure DMA Controller for SPI Transmission
Configure SPI before Transmission
Set TXDMAE/RXDMAE=1 to enable
Transmit/Receive by DMA
Set SPE=1 to start transmission in master mode or enable SPI for transmission in slave moe
Wait for interrupt(s) of DMA Controller indicating end of SPI transmission
Figure 37-35. Basic Flow of SPI Transmission by DMA
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Functional description
37.4.5.1 Transmit by DMA
Transmit by DMA is supported only when TXDMAE is set. A transmit DMA request is asserted when both SPE and SPTEF are set. Then the on-chip DMA controller detects this request and transfers data from memory into the SPI data register. After that, TX
DMA DONE is asserted to clear SPTEF automatically. This process repeats until all data for transmission (the number is decided by the configuration register[s] of the DMA controller) is sent.
When the FIFO feature is supported: In FIFO mode (FIFOMODE=1) and when a data length of 8 bits is selected (SPIMODE=0), the DMA transfer for one transmit DMA request can write more than 1 byte (up to 8 bytes) to the DL register because the TX
FIFO can store 8 bytes of transmit data. In FIFO mode (FIFOMODE=1) and when a data length of 16 bits is selected (SPIMODE=1), the DMA transfer for one transmit DMA request can write more than 1 word (up to 4 words) to the DH:DL registers because the
TX FIFO can store 4 words of transmit data. A larger number of bytes or words transferred from memory to the SPI data register for each transmit DMA request results in a lower total number of transmit DMA requests.
When FIFOMODE is 0: Cycle Steal (DMA_DCRn[CS] = 1) should be enabled when using the DMA controller to transfer data from memory to the SPI data register. The
DMA performs a single data transfer per DMA request in cycle steal mode. Therefore, a single byte/word is written to the SPI data register from memory and transmitted by the
SPI module for each DMA request, as long as the BCR value is greater than zero
(DMA_DSR_BCRn[BCR] > 0). Once the BCR has reached zero, software must reconfigure the DMA controller if more data is to be transmitted. If a configuration error occurs (DMA_DSR_BCRn[CE] = 1) when the BCR is equal to 0, software must:
• disable peripheral requests when the BCR is equal to 0,
• perform 16-bit transfers (SPIMODE = 1), or
• decrease the SPI baud rate.
Software can disable peripheral requests by setting DMA_DCRn[D_REQ] = 1 when initializing the DMA controller, or by clearing DMA_DCRn[ERQ] once the BCR is equal to zero. Also, to continue transmitting data software must re-enable peripheral requests (DMA_DCRn[ERQ] = 1) after reconfiguring the DMA controller.
If continuous mode (DMA_DCRn[CS] = 0) is used when FIFOMODE = 0, the DMA controller transfers data continuously to the SPI data register once one DMA request is asserted; therefore, it is necessary to limit the BCR to 1 byte or 2 bytes for 8-bit and 16bit modes, respectively. In addition, the initial SPI data transmission is repeated one or more times unless peripheral requests are disabled when the BCR is equal to zero or the
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Chapter 37 Serial Peripheral Interface (SPI) first SPI transmit byte/word is written to the SPI data register prior to enabling DMA requests. Due to these limitations, continuous mode is not a practical configuration of the
DMA controller to write data to the SPI data register and is not recommended.
RESET
Configure DMA Controller for SPI transmission
Configure SPI before Transmission
Set SPE=1 to start transmission in master mode or enable SPI for transmission in slave mode
Read SPI status register
Write the first byte to SPI data register via CPU
Set TXDMAE to enable Transmit by
DMA
Wait for interrupt(s) of DMA Controller indicating end of SPI transmission
Figure 37-36. Recommended startup of SPI transmit by DMA
37.4.5.2 Receive by DMA
Receive by DMA is supported only when RXDMAE is set. A receive DMA request is asserted when both SPE and SPRF are set. Then the on-chip DMA controller detects this request and transfers data from the SPI data register into memory. After that, RX DMA
DONE is asserted to clear SPRF automatically. This process repeats until all data to be received (the number is decided by configuration register[s] of the DMA controller) is received or no receive DMA request is generated again because the SPI transmission is finished.
When the FIFO feature is supported: In FIFO mode (FIFOMODE=1) and when a data length of 8 bits is selected (SPIMODE=0), the DMA transfer for one receive DMA request can read more than 1 byte (up to 8 bytes) from the SPI data register because the
RX FIFO can hold 8 bytes. In FIFO mode (FIFOMODE=1) and when a data length of 16
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Functional description bits is selected (SPIMODE=1), the DMA transfer for one receive DMA request can read more than 1 word (up to 4 words) from the DH:DL registers because the RX FIFO can hold 4 words. A larger number of bytes or words transferred from the SPI data register to memory for one receive DMA request results in a lower total number of receive DMA requests.
37.4.6 Data Transmission Length
The SPI can support data lengths of 8 or 16 bits. The length can be configured with the
SPIMODE bit in the SPIx_C2 register.
In 8-bit mode (SPIMODE = 0), the SPI Data Register is comprised of one byte:
SPIx_DL. The SPI Match Register is also comprised of only one byte: SPIx_ML. Reads of SPIx_DH and SPIx_MH will return zero. Writes to SPIx_DH and SPIx_MH will be ignored.
In 16-bit mode (SPIMODE = 1), the SPI Data Register is comprised of two bytes:
SPIx_DH and SPIx_DL. Reading either byte (SPIx_DH or SPIx_DL) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. Writing to either byte (SPIx_DH or SPIx_DL) latches the value into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the transmit data buffer.
In 16-bit mode, the SPI Match Register is also comprised of two bytes: SPIx_MH and
SPIx_ML. There is no buffer mechanism for the reading of SPIxMH and SPIxML since they can only be changed by writing at CPU side. Writing to either byte (SPIx_MH or
SPIx_ML) latches the value into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the SPI Match Register.
Any switching between 8- and 16-bit data transmission length (controlled by SPIMODE bit) in master mode will abort a transmission in progress, force the SPI system into idle state, and reset all status bits in the SPIx_S register. To initiate a transfer after writing to
SPIMODE, the SPIx_S register must be read with SPTEF = 1, and data must be written to SPIx_DH:SPIx_DL in 16-bit mode (SPIMODE = 1) or SPIx_DL in 8-bit mode
(SPIMODE = 0).
In slave mode, user software should write to SPIMODE only once to prevent corrupting a transmission in progress.
Note
Data can be lost if the data length is not the same for both master and slave devices.
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37.4.7 SPI clock formats
To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI system has a Clock Polarity (CPOL) bit and a Clock Phase
(CPHA) control bit in the Control Register 1 to select one of four clock formats for data transfers. C1[CPOL] selectively inserts an inverter in series with the clock. C1[CPHA] chooses between two different clock phase relationships between the clock and data.
The following figure shows the clock formats when SPIMODE = 0 (8-bit mode) and
CPHA = 1. At the top of the figure, the eight bit times are shown for reference with bit 1 starting at the first SPSCK edge and bit 8 ending one-half SPSCK cycle after the eighth
SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on the setting in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in
C1[CPOL]. The SAMPLE IN waveform applies to the MOSI input of a slave or the
MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided C2[MODFEN] and
C1[SSOE] = 1). The master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer.
The SS IN waveform applies to the slave select input of a slave.
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Functional description
BIT TIME #
(REFERENCE)
SPSCK
(CPOL = 0)
1 2 ...
6 7 8
SPSCK
(CPOL = 1)
SAMPLE IN
(MISO OR MOSI)
MOSI
(MASTER OUT)
MSB FIRST
LSB FIRST
MISO
(SLAVE OUT)
SS OUT
(MASTER)
BIT 7
BIT 0
BIT 6
BIT 1
...
...
BIT 2
BIT 5
BIT 1
BIT 6
BIT 0
BIT 7
SS IN
(SLAVE)
Figure 37-37. SPI clock formats (CPHA = 1)
When C1[CPHA] = 1, the slave begins to drive its MISO output when SS goes to active low, but the data is not defined until the first SPSCK edge. The first SPSCK edge shifts the first bit of data from the shifter onto the MOSI output of the master and the MISO output of the slave. The next SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the third SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled, and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave, respectively.
When C1[CPHA] = 1, the slave's SS input is not required to go to its inactive high level between transfers. In this clock format, a back-to-back transmission can occur, as follows:
1. A transmission is in progress.
2. A new data byte is written to the transmit buffer before the in-progress transmission is complete.
3. When the in-progress transmission is complete, the new, ready data byte is transmitted immediately.
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SPSCK
(CPOL = 1)
SAMPLE IN
(MISO OR MOSI)
MOSI
(MASTER OUT)
MSB FIRST
LSB FIRST
MISO
(SLAVE OUT)
SS OUT
(MASTER)
SS IN
(SLAVE)
Chapter 37 Serial Peripheral Interface (SPI)
Between these two successive transmissions, no pause is inserted; the SS pin remains low.
The following figure shows the clock formats when SPIMODE = 0 and C1[CPHA] = 0.
At the top of the figure, the eight bit times are shown for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit 8 ends at the last SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on the setting in
LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided C2[MODFEN] and C1[SSOE] = 1). The master SS output goes to active low at the start of the first bit time of the transfer and goes back high one-half SPSCK cycle after the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave.
BIT TIME #
(REFERENCE)
1 2 ...
6 7 8
SPSCK
(CPOL = 0)
BIT 7
BIT 0
BIT 6
BIT 1
...
...
BIT 2
BIT 5
BIT 1
BIT 6
BIT 0
BIT 7
Figure 37-38. SPI clock formats (CPHA = 0)
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When C1[CPHA] = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB depending on LSBFE) when SS goes to active low. The first SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave, respectively. When C1[CPHA] = 0, the slave's SS input must go to its inactive high level between transfers.
37.4.8 SPI baud rate generation
As shown in the following figure, the clock source for the SPI baud rate generator is the
SPI module clock. The prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of
1, 2, 3, 4, 5, 6, 7, or 8. The rate-select bits (SPR3:SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, 256, or 512 to get the internal SPI master mode bit-rate clock.
The baud rate generator is activated only when the SPI is in the master mode and a serial transfer is taking place. In the other cases, the divider is disabled to decrease I
DD
current.
The baud rate divisor equation is as follows (except those reserved combinations in the
SPI Baud Rate Divisor table).
BaudRateDivisor = (SPPR + 1) × 2 (SPR + 1)
The baud rate can be calculated with the following equation:
BaudRate = SPI Module Clock / BaudRateDivisor
SPI MODULE
CLOCK
PRESCALER
DIVIDE BY
1, 2, 3, 4, 5, 6, 7, or 8
BAUD RATE DIVIDER
DIVIDE BY
2, 4, 8, 16, 32, 64, 128,
256, or 512
MASTER
SPI
BIT RATE
SPPR2:SPPR1:SPPR0 SPR3:SPR2:SPR1:SPR0
Figure 37-39. SPI baud rate generation
37.4.9 Special features
The following section describes the special features of SPI module.
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Chapter 37 Serial Peripheral Interface (SPI)
37.4.9.1 SS Output
The SS output feature automatically drives the SS pin low during transmission to select external devices and drives the SS pin high during idle to deselect external devices. When the SS output is selected, the SS output pin is connected to the SS input pin of the external device.
The SS output is available only in master mode during normal SPI operation by asserting
C1[SSOE] and C2[MODFEN] as shown in the description of C1[SSOE].
The mode fault feature is disabled while SS output is enabled.
Note
Be careful when using the SS output feature in a multimaster system because the mode fault feature is not available for detecting system errors between masters.
37.4.9.2 Bidirectional mode (MOMI or SISO)
The bidirectional mode is selected when the SPC0 bit is set in SPI Control Register 2 (see the following table). In this mode, the SPI uses only one serial data pin for the interface with one or more external devices. C1[MSTR] decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI.
When SPE = 1
Table 37-34. Normal Mode and Bidirectional Mode
Master Mode MSTR = 1 Slave Mode MSTR = 0
Normal Mode
SPC0 = 0
Serial Out
SPI
Serial In
MOSI
MISO
Serial In
SPI
Serial Out
MOSI
MISO
Bidirectional Mode
SPC0 = 1
Serial Out
SPI
Serial In
BIDIROE
MOMI Serial In
SPI
Serial Out
BIDIROE
SISO
The direction of each serial I/O pin depends on C2[BIDIROE]. If the pin is configured as an output, serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift register.
The SPSCK is an output for the master mode and an input for the slave mode.
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SS is the input or output for the master mode, and it is always the input for the slave mode.
The bidirectional mode does not affect SPSCK and SS functions.
Note
In bidirectional master mode, with the mode fault feature enabled, both data pins MISO and MOSI can be occupied by the SPI, though MOSI is normally used for transmissions in bidirectional mode and MISO is not used by the SPI. If a mode fault occurs, the SPI is automatically switched to slave mode. In this case, MISO becomes occupied by the SPI and MOSI is not used. Consider this scenario if the MISO pin is used for another purpose.
37.4.10 Error conditions
The SPI module has one error condition: the mode fault error.
37.4.10.1 Mode fault error
If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more than one master may be trying to drive the MOSI and SPSCK lines simultaneously. This condition is not permitted in normal operation, and it sets the
MODF bit in the SPI status register automatically provided that C2[MODFEN] is set.
In the special case where the SPI is in master mode and C2[MODFEN] is cleared, the SS pin is not used by the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. If the SPI system is configured as a slave, the SS pin is a dedicated input pin. A mode fault error does not occur in slave mode.
If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output buffer is disabled. So the SPSCK, MISO and MOSI pins are forced to be high impedance inputs to avoid any possibility of conflict with another output driver. A transmission in progress is aborted and the SPI is forced into idle state.
If the mode fault error occurs in the bidirectional mode for an SPI system configured in master mode, the output enable of MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in the bidirectional mode for the SPI system configured in slave mode.
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The mode fault flag is cleared automatically by a read of the SPI Status Register (with
MODF set) followed by a write to SPI Control Register 1. If the mode fault flag is cleared, the SPI becomes a normal master or slave again.
37.4.11 Low-power mode options
This section describes the low-power mode options.
37.4.11.1 SPI in Run mode
In Run mode, with the SPI system enable (SPE) bit in the SPI Control Register 1 clear, the SPI system is in a low-power, disabled state. SPI registers can still be accessed, but clocks to the core of this module are disabled.
37.4.11.2 SPI in Wait mode
SPI operation in Wait mode depends upon the state of the SPISWAI bit in SPI Control
Register 2.
• If C2[SPISWAI] is clear, the SPI operates normally when the CPU is in Wait mode.
• If C2[SPISWAI] is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU is in wait mode.
• If C2[SPISWAI] is set and the SPI is configured for master, any transmission and reception in progress stops at Wait mode entry. The transmission and reception resumes when the SPI exits Wait mode.
• If C2[SPISWAI] is set and the SPI is configured as a slave, any transmission and reception in progress continues if the SPSCK continues to be driven from the master. This keeps the slave synchronized to the master and the SPSCK.
If the master transmits data while the slave is in wait mode, the slave continues to send data consistent with the operation mode at the start of wait mode (that is, if the slave is currently sending its SPIx_DH:SPIx_DL to the master, it continues to send the same byte. Otherwise, if the slave is currently sending the last data received byte from the master, it continues to send each previously received data from the master byte).
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Note
Care must be taken when expecting data from a master while the slave is in a Wait mode or a Stop mode where the peripheral bus clock is stopped but internal logic states are retained. Even though the shift register continues to operate, the rest of the SPI is shut down (that is, an SPRF interrupt is not generated until an exit from Stop or Wait mode). Also, the data from the shift register is not copied into the SPIx_DH:SPIx_DL registers until after the slave SPI has exited Wait or Stop mode. An SPRF flag and SPIx_DH:SPIx_DL copy is only generated if Wait mode is entered or exited during a transmission. If the slave enters Wait mode in idle mode and exits Wait mode in idle mode, neither an
SPRF nor a SPIx_DH:SPIx_DL copy occurs.
37.4.11.3 SPI in Stop mode
Operation in a Stop mode where the peripheral bus clock is stopped but internal logic states are retained depends on the SPI system. The Stop mode does not depend on
C2[SPISWAI]. Upon entry to this type of stop mode, the SPI module clock is disabled
(held high or low).
• If the SPI is in master mode and exchanging data when the CPU enters the Stop mode, the transmission is frozen until the CPU exits stop mode. After the exit from stop mode, data to and from the external SPI is exchanged correctly.
• In slave mode, the SPI remains synchronized with the master.
The SPI is completely disabled in a stop mode where the peripheral bus clock is stopped and internal logic states are not retained. After an exit from this type of stop mode, all registers are reset to their default values, and the SPI module must be reinitialized.
37.4.12 Reset
The reset values of registers and signals are described in the Memory Map and Register
Descriptions content, which details the registers and their bitfields.
• If a data transmission occurs in slave mode after a reset without a write to
SPIx_DH:SPIx_DL, the transmission consists of "garbage" or the data last received from the master before the reset.
• Reading from SPIx_DH:SPIx_DL after reset always returns zeros.
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37.4.13 Interrupts
The SPI originates interrupt requests only when the SPI is enabled (the SPE bit in the
SPIx_C1 register is set). The following is a description of how the SPI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt priority are chip dependent.
Four flag bits, three interrupt mask bits, and one interrupt vector are associated with the
SPI system. The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI transmit buffer empty flag (SPTEF). The
SPI match interrupt enable mask bit (SPIMIE) enables interrupts from the SPI match flag
(SPMF). When one of the flag bits is set, and the associated interrupt mask bit is set, a hardware interrupt request is sent to the CPU. If the interrupt mask bits are cleared, software can poll the associated flag bits instead of using interrupts. The SPI interrupt service routine (ISR) should check the flag bits to determine which event caused the interrupt. The service routine should also clear the flag bit(s) before returning from the
ISR (usually near the beginning of the ISR).
37.4.13.1 MODF
MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the MODF feature (see the description of the C1[SSOE] bit). Once MODF is set, the current transfer is aborted and the master (MSTR) bit in the SPIx_C1 register resets to 0.
The MODF interrupt is reflected in the status register's MODF flag. Clearing the flag also clears the interrupt. This interrupt stays active while the MODF flag is set. MODF has an automatic clearing process that is described in the SPI Status Register.
37.4.13.2 SPRF
SPRF occurs when new data has been received and copied to the SPI receive data buffer.
In 8-bit mode, SPRF is set only after all 8 bits have been shifted out of the shift register and into SPIx_DL. In 16-bit mode, SPRF is set only after all 16 bits have been shifted out of the shift register and into SPIx_DH:SPIx_DL.
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After SPRF is set, it does not clear until it is serviced. SPRF has an automatic clearing process that is described in the SPI Status Register details. If the SPRF is not serviced before the end of the next transfer (that is, SPRF remains active throughout another transfer), the subsequent transfers are ignored and no new data is copied into the Data register.
37.4.13.3 SPTEF
SPTEF occurs when the SPI transmit buffer is ready to accept new data. In 8-bit mode,
SPTEF is set only after all 8 bits have been moved from SPIx_DL into the shifter. In 16bit mode, SPTEF is set only after all 16 bits have been moved from SPIx_DH:SPIx_DL into the shifter.
After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process that is described in the SPI Status Register details.
37.4.13.4 SPMF
SPMF occurs when the data in the receive data buffer is equal to the data in the SPI
Match Register. In 8-bit mode, SPMF is set only after bits 7–0 in the receive data buffer are determined to be equivalent to the value in SPIx_ML. In 16-bit mode, SPMF is set after bits 15–0 in the receive data buffer are determined to be equivalent to the value in
SPIx_MH:SPIx_ML.
37.4.13.5 TNEAREF
The TNEAREF bit applies when the FIFO feature is supported.
The TNEAREF flag is set when only one 16-bit word or two 8-bit bytes of data remain in the transmit FIFO provided C3[5] = 0 or when only two 16-bit words or four 8-bit bytes of data remain in the transmit FIFO provided C3[5] =1. If FIFOMODE is not enabled, ignore this bit.
Clearing this interrupt depends on the state of C3[3] and the status of TNEAREF. Refer to the description of the SPI status (S) register.
37.4.13.6 RNFULLF
The RNFULLF bit applies when the FIFO feature is supported.
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RNFULLF is set when more than three 16-bit words or six 8-bit bytes of data remain in the receive FIFO provided C3[4] = 0 or when more than two 16-bit words or four 8-bit bytes of data remain in the receive FIFO provided C3[4] = 1.
Clearing this interrupt depends on the state of C3[3] and the status of RNFULLF. Refer to the description of the SPI status (S) register.
37.4.13.7 Asynchronous interrupt in low-power modes
When the CPU is in Wait mode or Stop mode and the SPI module receives a transmission, the SPI module can generate an asynchronous interrupt to wake the CPU from the low power mode. The module generates the asynchronous interrupt only when all of the following conditions apply:
1. C2[SPLPIE] is set to 1.
2. The CPU is in Wait mode—in which case C2[SPISWAI] must be 1—or in Stop mode where the peripheral bus clock is stopped but internal logic states are retained.
3. The SPI module is in slave mode.
4. The received transmission ends.
5. When the FIFO feature is supported, FIFO mode is disabled: C3[FIFOMODE] is 0.
After the interrupt wakes the CPU and the peripheral bus clock is active again, the SPI module copies the received data from the shifter into the Data register and generates flags or DMA request signals. During the wakeup phase, a continuous transmission from a master would destroy the first received data.
37.5 Initialization/application information
This section discusses an example of how to initialize and use the SPI.
NOTE
When operating the SPI at the maximum baud rate it must be configured for 16 bit operation.
37.5.1 Initialization sequence
Before the SPI module can be used for communication, an initialization procedure must be carried out, as follows:
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1. Update the Control Register 1 (SPIx_C1) to enable the SPI and to control interrupt enables. This register also sets the SPI as master or slave, determines clock phase and polarity, and configures the main SPI options.
2. Update the Control Register 2 (SPIx_C2) to enable additional SPI functions such as the SPI match interrupt feature, the master mode-fault function, and bidirectional mode output as well as to control 8- or 16-bit mode selection and other optional features.
3. Update the Baud Rate Register (SPIx_BR) to set the prescaler and bit rate divisor for an SPI master.
4. Update the Hardware Match Register (SPIx_MH:SPIx_ML) with the value to be compared to the receive data register for triggering an interrupt if hardware match interrupts are enabled.
5. In the master, read SPIx_S while S[SPTEF] = 1, and then write to the transmit data register (SPIx_DH:SPIx_DL) to begin transfer.
37.5.2 Pseudo-Code Example
In this example, the SPI module is set up for master mode with only hardware match interrupts enabled. The SPI runs in 16-bit mode at a maximum baud rate of SPI module clock divided by 2. Clock phase and polarity are set for an active-high SPI clock where the first edge on SPSCK occurs at the start of the first cycle of a data transfer.
SPIx_C1=0x54(%01010100)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
0
0
0
1
0
1
0
1
=
=
=
=
=
=
=
=
Disables receive and mode fault interrupts
Enables the SPI system
Disables SPI transmit interrupts
Sets the SPI module as a master SPI device
Configures SPI clock as active-high
First edge on SPSCK at start of first data transfer cycle
Determines SS pin function when mode fault enabled
SPI serial data transfers start with most significant bit
SPIx_C2 = 0xC0(%11000000)
Bit 7
Bit 6
Bit 5
Bit 4
SPMIE
SPIMODE
TXDMAE
MODFEN
=
=
=
=
1
1
0
0
SPI hardware match interrupt enabled
Configures SPI for 16-bit mode
DMA request disabled
Disables mode fault function
Table continues on the next page...
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SPIx_C2 = 0xC0(%11000000)
Bit 3
Bit 2
Bit 1
Bit 0
BIDIROE
RXDMAE
SPISWAI
SPC0
Chapter 37 Serial Peripheral Interface (SPI)
=
=
=
=
0
0
0
0
SPI data I/O pin acts as input
DMA request disabled
SPI clocks operate in wait mode uses separate pins for data input and output
SPIx_BR = 0x00(%00000000)
Bit 7
Bit 6:4
Bit 3:0
SPIx_S = 0x00(%00000000)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3:0
SPRF
SPMF
SPTEF
MODF
=
=
=
0 Reserved
000 Sets prescale divisor to 1
0000 Sets baud rate divisor to 2
=
=
=
=
=
0
0
0
0
0
Flag is set when receive data buffer is full
Flag is set when SPIx_MH/ML = receive data buffer
Flag is set when transmit data buffer is empty
Mode fault flag for master mode
FIFOMODE is not enabled
SPIx_MH = 0xXX
In 16-bit mode, this register holds bits 8–15 of the hardware match buffer. In 8-bit mode, writes to this register will be ignored.
SPIx_ML = 0xXX
Holds bits 0–7 of the hardware match buffer.
SPIx_DH = 0xxx
In 16-bit mode, this register holds bits 8–15 of the data to be transmitted by the transmit buffer and received by the receive buffer.
SPIx_DL = 0xxx
Holds bits 0–7 of the data to be transmitted by the transmit buffer and received by the receive buffer.
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RESET
INITIALIZE SPI
SPIxC1 = 0x54
SPIxC2 = 0xC0
SPIxBR = 0x00
SPIxMH = 0xXX
YES
SPTEF = 1
?
YES
WRITE TO
SPIxDH:SPIxDL
NO
SPRF = 1
?
YES
READ
SPIxDH:SPIxDL
NO
SPMF = 1
?
YES
READ SPMF WHILE SET
TO CLEAR FLAG,
THEN WRITE A 1 TO IT
NO
CONTINUE
Figure 37-40. Initialization Flowchart Example for SPI Master Device in 16-bit Mode for
FIFOMODE = 0
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RESET
INITIALIZE SPI
SPIxC1 = 0x54
SPIxC2 = 0xC0
SPIxBR = 0x00
SPIxMH = 0xXX
Set FIFOMODE
WRITE TO
SPIxDH:SPIxDL
YES
TXFULLF = 1
?
YES
RNFULLF = 1/
SPRF = 1
?
YES
READ
SPIxDH:SPIxDL
RFIFOEF = 1
?
YES
CONTINUE
Figure 37-41. Initialization Flowchart Example for SPI Master Device in 16-bit Mode for
FIFOMODE = 1
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Chapter 38
Inter-Integrated Circuit (I2C)
The inter-integrated circuit (I 2 C, I2C, or IIC) module provides a method of communication between a number of devices.
38.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
The inter-integrated circuit (I 2 C, I2C, or IIC) module provides a method of communication between a number of devices.
The interface is designed to operate up to 100 kbit/s with maximum bus loading and timing. The I2C device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of
400 pF. The I2C module also complies with the System Management Bus (SMBus)
Specification, version 2 .
38.1.1 Features
The I2C module has the following features:
• Compatible with The I 2 C-Bus Specification
• Multimaster operation
• Software programmable for one of 64 different serial clock frequencies
• Software-selectable acknowledge bit
• Interrupt-driven byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave
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Introduction
• Calling address identification interrupt
• START and STOP signal generation and detection
• Repeated START signal generation and detection
• Acknowledge bit generation and detection
• Bus busy detection
• General call recognition
• 10-bit address extension
• Support for System Management Bus (SMBus) Specification, version 2
• Programmable glitch input filter
• Low power mode wakeup on slave address match
• Range slave address support
• DMA support
38.1.2 Modes of operation
The I2C module's operation in various low power modes is as follows:
• Run mode: This is the basic mode of operation. To conserve power in this mode, disable the module.
• Wait mode: The module continues to operate when the core is in Wait mode and can provide a wakeup interrupt.
• Stop mode: The module is inactive in Stop mode for reduced power consumption, except that address matching is enabled in Stop mode. The STOP instruction does not affect the I2C module's register states.
38.1.3 Block diagram
The following figure is a functional block diagram of the I2C module.
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Module Enable Address
ADDR_DECODE
Chapter 38 Inter-Integrated Circuit (I2C)
Write/Read
Interrupt
DATA_MUX
CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG
Input
Sync
Clock
Control
START
STOP
Arbitration
Control
In/Out
Data
Shift
Register
Address
Compare
SCL SDA
Figure 38-1. I2C Functional block diagram
38.2 I
2
C signal descriptions
The signal properties of I 2 C are shown in the table found here.
Table 38-1. I 2 C signal descriptions
Signal
SCL
SDA
Description
Bidirectional serial clock line of the I 2 C system.
Bidirectional serial data line of the I 2 C system.
I/O
I/O
I/O
38.3 Memory map/register definition
This section describes in detail all I2C registers accessible to the end user.
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I2C memory map
Absolute address
(hex)
Register name
4006_6000 I2C Address Register 1 (I2C0_A1)
4006_6001 I2C Frequency Divider register (I2C0_F)
4006_6002 I2C Control Register 1 (I2C0_C1)
4006_6003 I2C Status register 1 (I2C0_S1)
4006_6004 I2C Data I/O register (I2C0_D)
4006_6005 I2C Control Register 2 (I2C0_C2)
4006_6006 I2C Programmable Input Glitch Filter register (I2C0_FLT)
4006_6007 I2C Range Address register (I2C0_RA)
4006_6008 I2C SMBus Control and Status register (I2C0_SMB)
4006_6009 I2C Address Register 2 (I2C0_A2)
Width
(in bits)
Access Reset value
8
8
8
8
8
8
8
8
8
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00h
00h
00h
80h
00h
00h
00h
00h
00h
C2h
4006_600A I2C SCL Low Timeout Register High (I2C0_SLTH)
4006_600B I2C SCL Low Timeout Register Low (I2C0_SLTL)
4006_7000 I2C Address Register 1 (I2C1_A1)
4006_7001 I2C Frequency Divider register (I2C1_F)
4006_7002 I2C Control Register 1 (I2C1_C1)
4006_7003 I2C Status register 1 (I2C1_S1)
4006_7004 I2C Data I/O register (I2C1_D)
4006_7005 I2C Control Register 2 (I2C1_C2)
4006_7006 I2C Programmable Input Glitch Filter register (I2C1_FLT)
4006_7007 I2C Range Address register (I2C1_RA)
4006_7008 I2C SMBus Control and Status register (I2C1_SMB)
4006_7009 I2C Address Register 2 (I2C1_A2)
4006_700A I2C SCL Low Timeout Register High (I2C1_SLTH)
4006_700B I2C SCL Low Timeout Register Low (I2C1_SLTL)
8
8
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
8
8
8
8
8
8
8
8
8
8
R/W
R/W
00h
00h
00h
00h
00h
00h
00h
00h
00h
80h
00h
C2h
00h
00h
Section/ page
38.3.1 I2C Address Register 1 (I2Cx_A1)
This register contains the slave address to be used by the I2C module.
Address: Base address + 0h offset
Bit
Read
Write
Reset
7
0
6
0
722
5
0
4
0
3
0
2
0
1
0
0
0
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Field
7–1
AD[7:1]
0
Reserved
Chapter 38 Inter-Integrated Circuit (I2C)
I2Cx_A1 field descriptions
Description
Address
Contains the primary slave address used by the I2C module when it is addressed as a slave. This field is used in the 7-bit address scheme and the lower seven bits in the 10-bit address scheme.
This field is reserved.
This read-only field is reserved and always has the value 0.
38.3.2 I2C Frequency Divider register (I2Cx_F)
Address: Base address + 1h offset
Bit
Read
Write
Reset
7
0
6
0
Field
7–6
MULT
5
0
4
0
3
0
2
0
1
0
0
0
I2Cx_F field descriptions
Description
Multiplier Factor
Defines the multiplier factor (mul). This factor is used along with the SCL divider to generate the I2C baud rate.
5–0
ICR
00 mul = 1
01 mul = 2
10 mul = 4
11 Reserved
ClockRate
Prescales the I2C module clock for bit rate selection. This field and the MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold time, and the SCL stop hold time. For a list of values corresponding to each ICR setting, see
The SCL divider multiplied by multiplier factor (mul) determines the I2C baud rate.
I2C baud rate = I2C module clock speed (Hz)/(mul × SCL divider)
The SDA hold time is the delay from the falling edge of SCL (I2C clock) to the changing of SDA (I2C data).
SDA hold time = I2C module clock period (s) × mul × SDA hold value
The SCL start hold time is the delay from the falling edge of SDA (I2C data) while SCL is high (start condition) to the falling edge of SCL (I2C clock).
SCL start hold time = I2C module clock period (s) × mul × SCL start hold value
The SCL stop hold time is the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C data) while SCL is high (stop condition).
SCL stop hold time = I2C module clock period (s) × mul × SCL stop hold value
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Field
I2Cx_F field descriptions (continued)
Description
For example, if the I2C module clock speed is 8 MHz, the following table shows the possible hold time values with different ICR and MULT selections to achieve an I 2 C baud rate of 100 kbit/s.
MULT
2h
1h
1h
0h
0h
ICR
00h
07h
0Bh
14h
18h
SDA
3.500
2.500
2.250
2.125
1.125
Hold times (μs)
SCL Start
3.000
4.000
4.000
4.250
4.750
SCL Stop
5.500
5.250
5.250
5.125
5.125
38.3.3 I2C Control Register 1 (I2Cx_C1)
Address: Base address + 2h offset
Bit 7 6
Read
Write
Reset 0 0
Field
7
IICEN
5
0
4
0
3
0
I2Cx_C1 field descriptions
Description
I2C Enable
Enables I2C module operation.
6
IICIE
5
MST
2
0
0
1
0
0
0
0 Disabled
1 Enabled
I2C Interrupt Enable
Enables I2C interrupt requests.
0 Disabled
1 Enabled
Master Mode Select
When MST is changed from 0 to 1, a START signal is generated on the bus and master mode is selected.
When this bit changes from 1 to 0, a STOP signal is generated and the mode of operation changes from master to slave.
0 Slave mode
1 Master mode
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Field
4
TX
3
TXAK
2
RSTA
1
WUEN
0
DMAEN
Chapter 38 Inter-Integrated Circuit (I2C)
I2Cx_C1 field descriptions (continued)
Description
Transmit Mode Select
Selects the direction of master and slave transfers. In master mode this bit must be set according to the type of transfer required. Therefore, for address cycles, this bit is always set. When addressed as a slave this bit must be set by software according to the SRW bit in the status register.
0 Receive
1 Transmit
Transmit Acknowledge Enable
Specifies the value driven onto the SDA during data acknowledge cycles for both master and slave receivers. The value of SMB[FACK] affects NACK/ACK generation.
NOTE: SCL is held low until TXAK is written.
0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).
1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).
Repeat START
Writing 1 to this bit generates a repeated START condition provided it is the current master. This bit will always be read as 0. Attempting a repeat at the wrong time results in loss of arbitration.
Wakeup Enable
The I2C module can wake the MCU from low power mode with no peripheral bus running when slave address matching occurs.
0 Normal operation. No interrupt generated when address matching in low power mode.
1 Enables the wakeup function in low power mode.
DMA Enable
Enables or disables the DMA function.
0 All DMA signalling disabled.
1
DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request:
• a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic)
• the first byte received matches the A1 register or is a general call address.
If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the
C1 register operation. With this assumption, DMA cannot be used.
When FACK = 1, an address or a data byte is transmitted.
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38.3.4 I2C Status register 1 (I2Cx_S1)
Address: Base address + 3h offset
Bit
Read
7
6
Write
Reset 1 0
Field
7
TCF
Transfer Complete Flag
5
0
4
0
3
0
I2Cx_S1 field descriptions
Description
6
IAAS
5
BUSY
2
0
1
0
0
0
Acknowledges a byte transfer; TCF sets on the completion of a byte transfer. This bit is valid only during or immediately following a transfer to or from the I2C module. TCF is cleared by reading the I2C data register in receive mode or by writing to the I2C data register in transmit mode.
0 Transfer in progress
1 Transfer complete
Addressed As A Slave
This bit is set by one of the following conditions:
• The calling address matches the programmed slave primary address in the A1 register or range address in the RA register (which must be set to a nonzero value).
• C2[GCAEN] is set and a general call is received.
• SMB[SIICAEN] is set and the calling address matches the second programmed slave address.
• ALERTEN is set and an SMBus alert response address is received
• RMEN is set and an address is received that is within the range between the values of the A1 and
RA registers.
IAAS sets before the ACK bit. The CPU must check the SRW bit and set TX/RX accordingly. Writing the
C1 register with any value clears this bit.
0 Not addressed
1 Addressed as a slave
Bus Busy
Indicates the status of the bus regardless of slave or master mode. This bit is set when a START signal is detected and cleared when a STOP signal is detected.
4
ARBL
3
RAM
0 Bus is idle
1 Bus is busy
Arbitration Lost
This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared by software, by writing 1 to it.
0 Standard bus operation.
1 Loss of arbitration.
Range Address Match
This bit is set to 1 by any of the following conditions:
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Field
2
SRW
1
IICIF
0
RXAK
Chapter 38 Inter-Integrated Circuit (I2C)
I2Cx_S1 field descriptions (continued)
Description
• Any nonzero calling address is received that matches the address in the RA register.
• The RMEN bit is set and the calling address is within the range of values of the A1 and RA registers.
NOTE: For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.
Writing the C1 register with any value clears this bit to 0.
0 Not addressed
1 Addressed as a slave
Slave Read/Write
When addressed as a slave, SRW indicates the value of the R/W command bit of the calling address sent to the master.
0 Slave receive, master writing to slave
1 Slave transmit, master reading from slave
Interrupt Flag
This bit sets when an interrupt is pending. This bit must be cleared by software by writing 1 to it, such as in the interrupt routine. One of the following events can set this bit:
• One byte transfer, including ACK/NACK bit, completes if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK after this bit is set in receive mode.
• One byte transfer, excluding ACK/NACK bit, completes if FACK is 1.
• Match of slave address to calling address including primary slave address, range slave address, alert response address, second slave address, or general call address.
• Arbitration lost
• In SMBus mode, any timeouts except SCL and SDA high timeouts
• I2C bus stop detection if the STOPIE bit in the Input Glitch Filter register is 1
NOTE: To clear the I2C bus stop detection interrupt: In the interrupt service routine, first clear the STOPF bit in the Input Glitch Filter register by writing 1 to it, and then clear the IICIF bit. If this sequence is reversed, the IICIF bit is asserted again.
0 No interrupt pending
1 Interrupt pending
Receive Acknowledge
0 Acknowledge signal was received after the completion of one byte of data transmission on the bus
1 No acknowledge signal detected
38.3.5 I2C Data I/O register (I2Cx_D)
Address: Base address + 4h offset
Bit
Read
Write
Reset
7
0
6
0
5
0
4
0
0
3 2
0
1
0
0
0
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Memory map/register definition
Field
7–0
DATA
I2Cx_D field descriptions
Description
Data
In master transmit mode, when data is written to this register, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
NOTE: When making the transition out of master receive mode, switch the I2C mode before reading the
Data register to prevent an inadvertent initiation of a master receive data transfer.
In slave mode, the same functions are available after an address match occurs.
The C1[TX] bit must correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin. For example, if the I2C module is configured for master transmit but a master receive is desired, reading the Data register does not initiate the receive.
Reading the Data register returns the last byte received while the I2C module is configured in master receive or slave receive mode. The Data register does not reflect every byte that is transmitted on the I2C bus, and neither can software verify that a byte has been written to the Data register correctly by reading it back.
In master transmit mode, the first byte of data written to the Data register following assertion of MST (start bit) or assertion of RSTA (repeated start bit) is used for the address transfer and must consist of the calling address (in bits 7-1) concatenated with the required R/W bit (in position bit 0).
38.3.6 I2C Control Register 2 (I2Cx_C2)
Address: Base address + 5h offset
Bit
Read
Write
Reset
7
0
6
0
Field
7
GCAEN
5
0
4
0
3
0
I2Cx_C2 field descriptions
Description
General Call Address Enable
Enables general call address.
6
ADEXT
5
HDRS
0 Disabled
1 Enabled
Address Extension
Controls the number of bits used for the slave address.
0 7-bit address scheme
1 10-bit address scheme
High Drive Select
Controls the drive capability of the I2C pads.
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2
0
1
0
0
0
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Field
4
SBRC
3
RMEN
2–0
AD[10:8]
Chapter 38 Inter-Integrated Circuit (I2C)
I2Cx_C2 field descriptions (continued)
Description
0 Normal drive mode
1 High drive mode
Slave Baud Rate Control
Enables independent slave mode baud rate at maximum frequency, which forces clock stretching on SCL in very fast I2C modes. To a slave, an example of a "very fast" mode is when the master transfers at 40 kbit/s but the slave can capture the master's data at only 10 kbit/s.
0 The slave baud rate follows the master baud rate and clock stretching may occur
1 Slave baud rate is independent of the master baud rate
Range Address Matching Enable
This bit controls slave address matching for addresses between the values of the A1 and RA registers.
When this bit is set, a slave address match occurs for any address greater than the value of the A1 register and less than or equal to the value of the RA register.
0 Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers.
1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
Slave Address
Contains the upper three bits of the slave address in the 10-bit address scheme. This field is valid only while the ADEXT bit is set.
38.3.7 I2C Programmable Input Glitch Filter register (I2Cx_FLT)
Address: Base address + 6h offset
Bit 7 6
Read
Write
Reset 0
0
Field
7
SHEN
5
0
4
0
3
0
2
0
1
0
I2Cx_FLT field descriptions
Description
Stop Hold Enable
Set this bit to hold off entry to stop mode when any data transmission or reception is occurring.
The following scenario explains the holdoff functionality:
1. The I2C module is configured for a basic transfer, and the SHEN bit is set to 1.
2. A transfer begins.
3. The MCU signals the I2C module to enter stop mode.
4. The byte currently being transferred, including both address and data, completes its transfer.
5. The I2C slave or master acknowledges that the in-transfer byte completed its transfer and acknowledges the request to enter stop mode.
6. After receiving the I2C module's acknowledgment of the request to enter stop mode, the MCU determines whether to shut off the I2C module's clock.
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Field
I2Cx_FLT field descriptions (continued)
Description
If the SHEN bit is set to 1 and the I2C module is in an idle or disabled state when the MCU signals to enter stop mode, the module immediately acknowledges the request to enter stop mode.
If SHEN is cleared to 0 and the overall data transmission or reception that was suspended by stop mode entry was incomplete: To resume the overall transmission or reception after the MCU exits stop mode, software must reinitialize the transfer by resending the address of the slave.
If the I2C Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode, system software will receive the interrupt triggered by the I2C Status Register's TCF bit after the MCU wakes from the stop mode.
6
STOPF
5
STOPIE
4–0
FLT
0 Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
1 Stop holdoff is enabled.
I2C Bus Stop Detect Flag
Hardware sets this bit when the I2C bus's stop status is detected. The STOPF bit must be cleared by writing 1 to it.
0 No stop happens on I2C bus
1 Stop detected on I2C bus
I2C Bus Stop Interrupt Enable
This bit enables the interrupt for I2C bus stop detection.
NOTE: To clear the I2C bus stop detection interrupt: In the interrupt service routine, first clear the STOPF bit by writing 1 to it, and then clear the IICIF bit in the status register. If this sequence is reversed, the IICIF bit is asserted again.
0 Stop detection interrupt is disabled
1 Stop detection interrupt is enabled
I2C Programmable Filter Factor
Controls the width of the glitch, in terms of I2C module clock cycles, that the filter must absorb. For any glitch whose size is less than or equal to this width setting, the filter does not allow the glitch to pass.
00h No filter/bypass
01-1Fh Filter glitches up to width of n I2C module clock cycles, where n =1-31d
38.3.8 I2C Range Address register (I2Cx_RA)
Address: Base address + 7h offset
Bit
Read
Write
Reset
7
0
6
0
5 4
0
3
0 0
I2Cx_RA field descriptions
Description Field
7–1
RAD
Range Slave Address
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2
730
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0
0
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Field
0
Reserved
Chapter 38 Inter-Integrated Circuit (I2C)
I2Cx_RA field descriptions (continued)
Description
This field contains the slave address to be used by the I2C module. The field is used in the 7-bit address scheme. Any nonzero write enables this register. This register's use is similar to that of the A1 register, but in addition this register can be considered a maximum boundary in range matching mode.
This field is reserved.
This read-only field is reserved and always has the value 0.
38.3.9 I2C SMBus Control and Status register (I2Cx_SMB)
NOTE
When the SCL and SDA signals are held high for a length of time greater than the high timeout period, the SHTF1 flag sets.
Before reaching this threshold, while the system is detecting how long these signals are being held high, a master assumes that the bus is free. However, the SHTF1 bit is set to 1 in the bus transmission process with the idle bus state.
NOTE
When the TCKSEL bit is set, there is no need to monitor the
SHTF1 bit because the bus speed is too high to match the protocol of SMBus.
Address: Base address + 8h offset
Bit 7 6
Read
Write
Reset 0 0
Field
7
FACK
5
0
4
0
3
0
Fast NACK/ACK Enable
I2Cx_SMB field descriptions
Description
6
ALERTEN
2
0
1
0
0
0
For SMBus packet error checking, the CPU must be able to issue an ACK or NACK according to the result of receiving data byte.
0 An ACK or NACK is sent on the following receiving data byte
1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
SMBus Alert Response Address Enable
Enables or disables SMBus alert response address matching.
NOTE: After the host responds to a device that used the alert response address, you must use software to put the device's address on the bus. The alert protocol is described in the SMBus specification.
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Memory map/register definition
Field
5
SIICAEN
I2Cx_SMB field descriptions (continued)
Description
0 SMBus alert response address matching is disabled
1 SMBus alert response address matching is enabled
Second I2C Address Enable
Enables or disables SMBus device default address.
4
TCKSEL
0 I2C address register 2 matching is disabled
1 I2C address register 2 matching is enabled
Timeout Counter Clock Select
Selects the clock source of the timeout counter.
3
SLTF
2
SHTF1
1
SHTF2
0
SHTF2IE
0 Timeout counter counts at the frequency of the I2C module clock / 64
1 Timeout counter counts at the frequency of the I2C module clock
SCL Low Timeout Flag
This bit is set when the SLT register (consisting of the SLTH and SLTL registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs. Software clears this bit by writing a logic 1 to it.
NOTE: The low timeout function is disabled when the SLT register's value is 0.
0 No low timeout occurs
1 Low timeout occurs
SCL High Timeout Flag 1
This read-only bit sets when SCL and SDA are held high more than clock × LoValue / 512, which indicates the bus is free. This bit is cleared automatically.
0 No SCL high and SDA high timeout occurs
1 SCL high and SDA high timeout occurs
SCL High Timeout Flag 2
This bit sets when SCL is held high and SDA is held low more than clock × LoValue / 512. Software clears this bit by writing 1 to it.
0 No SCL high and SDA low timeout occurs
1 SCL high and SDA low timeout occurs
SHTF2 Interrupt Enable
Enables SCL high and SDA low timeout interrupt.
0 SHTF2 interrupt is disabled
1 SHTF2 interrupt is enabled
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Chapter 38 Inter-Integrated Circuit (I2C)
38.3.10 I2C Address Register 2 (I2Cx_A2)
Address: Base address + 9h offset
Bit
Read
Write
Reset
7
1
6
1
Field
7–1
SAD
0
Reserved
5 4
0
3
0 0
I2Cx_A2 field descriptions
Description
2
0
1
1
0
0
SMBus Address
Contains the slave address used by the SMBus. This field is used on the device default address or other related addresses.
This field is reserved.
This read-only field is reserved and always has the value 0.
38.3.11 I2C SCL Low Timeout Register High (I2Cx_SLTH)
Address: Base address + Ah offset
Bit
Read
Write
Reset
7
0
6
0
Field
7–0
SSLT[15:8]
5
0
4
3
0 0
2
0
1
0
I2Cx_SLTH field descriptions
Description
Most significant byte of SCL low timeout value that determines the timeout period of SCL low.
0
0
38.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL)
Address: Base address + Bh offset
Bit
Read
Write
Reset
7
0
6
0
Field
7–0
SSLT[7:0]
5
0
4
0
3
0
2
0
1
0
I2Cx_SLTL field descriptions
Description
Least significant byte of SCL low timeout value that determines the timeout period of SCL low.
0
0
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Functional description
Field
I2Cx_SLTL field descriptions (continued)
Description
38.4 Functional description
This section provides a comprehensive functional description of the I2C module.
38.4.1 I2C protocol
The I2C bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfers.
All devices connected to it must have open drain or open collector outputs. A logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors depends on the system.
Normally, a standard instance of communication is composed of four parts:
1. START signal
2. Slave address transmission
3. Data transfer
4. STOP signal
The STOP signal should not be confused with the CPU STOP instruction. The following figure illustrates I2C bus system communication.
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S C L
M S B
1 2 3 4 5 6 7
L S B
8 9
M S B
1 2 3
Chapter 38 Inter-Integrated Circuit (I2C)
4 5 6 7
L S B
8 9
S D A A D 7 A D 6 A D 5 A D 4 A D 3 A D 2 A D 1 R /W
Start Signal
SCL
C a llin g A d d re s s R e a d /
W rite
Ack
Bit
M S B
1 2 3 4 5 6 7
L S B
8 9
X X X D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
M S B
1 2
D a ta B y te
3 4 5 6
No
Ack
Bit
Stop
Signal
7
L S B
8 9
S D A
Start
Signal
A D 7 A D 6 A D 5 A D 4 A D 3 A D 2 A D 1 R /W X X A D 7 A D 6 A D 5 A D 4 A D 3 A D 2 A D 1 R /W
C a llin g A d d re s s R e a d /
W rite
Ack
Bit
Repeated
Start
Signal
N e w C a llin g A d d re s s
Figure 38-38. I2C bus transmission signals
R e a d /
W rite
No
Ack
Bit
Stop
Signal
38.4.1.1 START signal
The bus is free when no master device is engaging the bus (both SCL and SDA are high).
When the bus is free, a master may initiate communication by sending a START signal.
A START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer—each data transfer might contain several bytes of data—and brings all slaves out of their idle states.
38.4.1.2 Slave address transmission
Immediately after the START signal, the first byte of a data transfer is the slave address transmitted by the master. This address is a 7-bit calling address followed by an R/W bit.
The R/W bit tells the slave the desired direction of data transfer.
• 1 = Read transfer: The slave transmits data to the master
• 0 = Write transfer: The master transmits data to the slave
Only the slave with a calling address that matches the one transmitted by the master responds by sending an acknowledge bit. The slave sends the acknowledge bit by pulling
SDA low at the ninth clock.
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Functional description
No two slaves in the system can have the same address. If the I2C module is the master, it must not transmit an address that is equal to its own slave address. The I2C module cannot be master and slave at the same time. However, if arbitration is lost during an address cycle, the I2C module reverts to slave mode and operates correctly even if it is being addressed by another master.
38.4.1.3 Data transfers
When successful slave addressing is achieved, data transfer can proceed on a byte-bybyte basis in the direction specified by the R/W bit sent by the calling master.
All transfers that follow an address cycle are referred to as data transfers, even if they carry subaddress information for the slave device.
Each data byte is 8 bits long. Data may be changed only while SCL is low. Data must be held stable while SCL is high. There is one clock pulse on SCL for each data bit, and the
MSB is transferred first. Each data byte is followed by a ninth (acknowledge) bit, which is signaled from the receiving device by pulling SDA low at the ninth clock. In summary, one complete data transfer needs nine clock pulses.
If the slave receiver does not acknowledge the master in the ninth bit, the slave must leave SDA high. The master interprets the failed acknowledgement as an unsuccessful data transfer.
If the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave interprets it as an end to data transfer and releases the SDA line.
In the case of a failed acknowledgement by either the slave or master, the data transfer is aborted and the master does one of two things:
• Relinquishes the bus by generating a STOP signal.
• Commences a new call by generating a repeated START signal.
38.4.1.4 STOP signal
The master can terminate the communication by generating a STOP signal to free the bus. A STOP signal is defined as a low-to-high transition of SDA while SCL is asserted.
The master can generate a STOP signal even if the slave has generated an acknowledgement, at which point the slave must release the bus.
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Chapter 38 Inter-Integrated Circuit (I2C)
38.4.1.5 Repeated START signal
The master may generate a START signal followed by a calling command without generating a STOP signal first. This action is called a repeated START. The master uses a repeated START to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus.
38.4.1.6 Arbitration procedure
The I2C bus is a true multimaster bus that allows more than one master to be connected on it.
If two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock. The bus clock's low period is equal to the longest clock low period, and the high period is equal to the shortest one among the masters.
The relative priority of the contending masters is determined by a data arbitration procedure. A bus master loses arbitration if it transmits logic level 1 while another master transmits logic level 0. The losing masters immediately switch to slave receive mode and stop driving SDA output. In this case, the transition from master to slave mode does not generate a STOP condition. Meanwhile, hardware sets a status bit to indicate the loss of arbitration.
38.4.1.7 Clock synchronization
Because wire AND logic is performed on SCL, a high-to-low transition on SCL affects all devices connected on the bus. The devices start counting their low period and, after a device's clock has gone low, that device holds SCL low until the clock reaches its high state. However, the change of low to high in this device clock might not change the state of SCL if another device clock is still within its low period. Therefore, the synchronized clock SCL is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time; see the following diagram. When all applicable devices have counted off their low period, the synchronized clock SCL is released and pulled high. Afterward there is no difference between the device clocks and the state of SCL, and all devices start counting their high periods. The first device to complete its high period pulls SCL low again.
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Functional description
S C L 1
S C L 2
S C L
D e la y
S ta rt C o u n tin g H ig h P e rio d
In te rn a l C o u n te r R e s e t
Figure 38-39. I2C clock synchronization
38.4.1.8 Handshaking
The clock synchronization mechanism can be used as a handshake in data transfers. A slave device may hold SCL low after completing a single byte transfer (9 bits). In this case, it halts the bus clock and forces the master clock into wait states until the slave releases SCL.
38.4.1.9 Clock stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After the master drives SCL low, a slave can drive SCL low for the required period and then release it. If the slave's SCL low period is greater than the master's SCL low period, the resulting SCL bus signal's low period is stretched. In other words, the
SCL bus signal's low period is increased to be the same length as the slave's SCL low period.
38.4.1.10 I2C divider and hold values
NOTE
For some cases on some devices, the SCL divider value may vary by +/-2 or +/-4 when ICR’s value ranges from 00h to 0Fh.
These potentially varying SCL divider values are highlighted in the following table. For the actual SCL divider values for your device, see the chip-specific details about the I2C module.
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ICR
(hex)
1A
1B
1C
1D
16
17
18
19
1E
1F
12
13
14
15
0E
0F
10
11
0A
0B
0C
0D
06
07
08
09
00
01
02
03
04
05
112
128
144
160
104
128
80
96
192
240
64
72
80
88
56
68
48
56
36
40
44
48
34
40
28
32
20
22
24
26
28
30
SCL divider
SDA hold value
17
17
25
25
21
21
9
9
33
33
13
13
17
17
13
13
9
9
11
11
9
9
10
10
7
7
9
9
8
8
7
7
Chapter 38 Inter-Integrated Circuit (I2C)
Table 38-41. I2C divider and hold values
3A
3B
3C
3D
36
37
38
39
3E
3F
32
33
34
35
2E
2F
30
31
2A
2B
2C
2D
26
27
28
29
20
21
22
23
24
25
46
58
38
46
26
30
34
38
24
30
18
22
14
16
18
20
SCL hold
(start) value
6
7
13
16
10
12
10
11
8
9
54
62
70
78
94
118
53
65
41
49
33
37
41
45
29
35
25
29
19
21
23
25
SCL hold
(stop) value
11
12
18
21
15
17
13
14
15
16
57
65
73
81
97
121
ICR
(hex)
896
1024
1152
1280
1536
1920
1280
1536
768
960
640
768
448
512
576
640
1792
2048
2304
2560
3072
3840
SCL divider
(clocks)
160
192
384
480
320
384
224
256
288
320
SDA hold
(clocks)
766
958
638
766
446
510
574
638
382
478
318
382
222
254
286
318
SCL hold
(start) value
78
94
190
238
158
190
110
126
142
158
894
1022
1150
1278
1534
1918
769
961
641
769
449
513
577
641
385
481
321
385
225
257
289
321
SCL hold
(stop) value
81
97
193
241
161
193
113
129
145
161
897
1025
1153
1281
1537
1921
257
257
385
385
257
257
129
129
513
513
129
129
193
193
129
129
65
65
65
65
97
97
65
65
33
33
17
17
33
33
49
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Functional description
38.4.2 10-bit address
For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte.
Various combinations of read/write formats are possible within a transfer that includes
10-bit addressing.
38.4.2.1 Master-transmitter addresses a slave-receiver
The transfer direction is not changed. When a 10-bit address follows a START condition, each slave compares the first 7 bits of the first byte of the slave address (11110XX) with its own address and tests whether the eighth bit (R/W direction bit) is 0. It is possible that more than one device finds a match and generates an acknowledge (A1). Each slave that finds a match compares the 8 bits of the second byte of the slave address with its own address, but only one slave finds a match and generates an acknowledge (A2). The matching slave remains addressed by the master until it receives a STOP condition (P) or a repeated START condition (Sr) followed by a different slave address.
S
Table 38-42. Master-transmitter addresses slave-receiver with a 10-bit address
Slave address first 7 bits
11110 +
AD10 +
AD9
R/W
0
A1 Slave address second byte
AD[8:1]
A2 Data A ...
Data A/A P
After the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver sees an I2C interrupt. User software must ensure that for this interrupt, the contents of the
Data register are ignored and not treated as valid data.
38.4.2.2 Master-receiver addresses a slave-transmitter
The transfer direction is changed after the second R/W bit. Up to and including acknowledge bit A2, the procedure is the same as that described for a master-transmitter addressing a slave-receiver. After the repeated START condition (Sr), a matching slave remembers that it was addressed before. This slave then checks whether the first seven bits of the first byte of the slave address following Sr are the same as they were after the
START condition (S), and it tests whether the eighth (R/W) bit is 1. If there is a match, the slave considers that it has been addressed as a transmitter and generates acknowledge
A3. The slave-transmitter remains addressed until it receives a STOP condition (P) or a repeated START condition (Sr) followed by a different slave address.
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Chapter 38 Inter-Integrated Circuit (I2C)
After a repeated START condition (Sr), all other slave devices also compare the first seven bits of the first byte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of them are addressed because R/W = 1 (for 10-bit devices), or the 11110XX slave address (for 7-bit devices) does not match.
S
Table 38-43. Master-receiver addresses a slave-transmitter with a 10-bit address
Slave address first 7 bits
11110 +
AD10 +
AD9
R/W
0
A1 Slave address second byte
AD[8:1]
A2 Sr Slave address first 7 bits
11110 +
AD10 +
AD9
R/W
1
A3 Data A ...
Data A P
After the master-receiver has sent the first byte of the 10-bit address, the slave-transmitter sees an I2C interrupt. User software must ensure that for this interrupt, the contents of the
Data register are ignored and not treated as valid data.
38.4.3 Address matching
All received addresses can be requested in 7-bit or 10-bit address format.
• AD[7:1] in Address Register 1, which contains the I2C primary slave address, always participates in the address matching process. It provides a 7-bit address.
• If the ADEXT bit is set, AD[10:8] in Control Register 2 participates in the address matching process. It extends the I2C primary slave address to a 10-bit address.
Additional conditions that affect address matching include:
• If the GCAEN bit is set, general call participates the address matching process.
• If the ALERTEN bit is set, alert response participates the address matching process.
• If the SIICAEN bit is set, Address Register 2 participates in the address matching process.
• If the Range Address register is programmed to a nonzero value, the range address itself participates in the address matching process.
• If the RMEN bit is set, any address within the range of values of Address Register 1 and the Range Address register participates in the address matching process. The
Range Address register must be programmed to a value greater than the value of
Address Register 1.
When the I2C module responds to one of these addresses, it acts as a slave-receiver and the IAAS bit is set after the address cycle. Software must read the Data register after the first byte transfer to determine that the address is matched.
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Functional description
38.4.4 System management bus specification
SMBus provides a control bus for system and power management related tasks. A system can use SMBus to pass messages to and from devices instead of tripping individual control lines.
Removing the individual control lines reduces pin count. Accepting messages ensures future expandability. With the system management bus, a device can provide manufacturer information, tell the system what its model/part number is, save its state for a suspend event, report different types of errors, accept control parameters, and return its status.
38.4.4.1 Timeouts
The T
TIMEOUT,MIN
parameter allows a master or slave to conclude that a defective device is holding the clock low indefinitely or a master is intentionally trying to drive devices off the bus. The slave device must release the bus (stop driving the bus and let SCL and
SDA float high) when it detects any single clock held low longer than T
TIMEOUT,MIN
.
Devices that have detected this condition must reset their communication and be able to receive a new START condition within the timeframe of T
TIMEOUT,MAX
.
SMBus defines a clock low timeout, T
TIMEOUT
, of 35 ms, specifies T
LOW:SEXT cumulative clock low extend time for a slave device, and specifies T
LOW:MEXT cumulative clock low extend time for a master device.
as the
as the
38.4.4.1.1 SCL low timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than a timeout value condition.
Devices that have detected the timeout condition must reset the communication. When the I2C module is an active master, if it detects that SMBCLK low has exceeded the value of T
TIMEOUT,MIN
, it must generate a stop condition within or after the current data byte in the transfer process. When the I2C module is a slave, if it detects the
T
TIMEOUT,MIN
condition, it resets its communication and is then able to receive a new
START condition.
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Chapter 38 Inter-Integrated Circuit (I2C)
38.4.4.1.2 SCL high timeout
When the I2C module has determined that the SMBCLK and SMBDAT signals have been high for at least T
HIGH:MAX
, it assumes that the bus is idle.
A HIGH timeout occurs after a START condition appears on the bus but before a STOP condition appears on the bus. Any master detecting this scenario can assume the bus is free when either of the following occurs:
• SHTF1 rises.
• The BUSY bit is high and SHTF1 is high.
When the SMBDAT signal is low and the SMBCLK signal is high for a period of time, another kind of timeout occurs. The time period must be defined in software. SHTF2 is used as the flag when the time limit is reached. This flag is also an interrupt resource, so it triggers IICIF.
38.4.4.1.3 CSMBCLK TIMEOUT MEXT and CSMBCLK TIMEOUT SEXT
The following figure illustrates the definition of the timeout intervals T
LOW:SEXT
T
LOW:MEXT
and
. When in master mode, the I2C module must not cumulatively extend its clock cycles for a period greater than T
LOW:MEXT
within a byte, where each byte is defined as START-to-ACK, ACK-to-ACK, or ACK-to-STOP. When CSMBCLK
TIMEOUT MEXT occurs, SMBus MEXT rises and also triggers the SLTF.
Start T
LOW:SEXT
Stop
T
LOW:MEXT
ClkAck
T
LOW:MEXT
ClkAck
T
LOW:MEXT
SCL
SDA
Figure 38-40. Timeout measurement intervals
A master is allowed to abort the transaction in progress to any slave that violates the
T
LOW:SEXT
or T
TIMEOUT,MIN
specifications. To abort the transaction, the master issues a
STOP condition at the conclusion of the byte transfer in progress. When a slave, the I2C module must not cumulatively extend its clock cycles for a period greater than
T
LOW:SEXT
during any message from the initial START to the STOP. When CSMBCLK
TIMEOUT SEXT occurs, SEXT rises and also triggers SLTF.
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Functional description
NOTE
CSMBCLK TIMEOUT SEXT and CSMBCLK TIMEOUT
MEXT are optional functions that are implemented in the second step.
38.4.4.2 FAST ACK and NACK
To improve reliability and communication robustness, implementation of packet error checking (PEC) by SMBus devices is optional for SMBus devices but required for devices participating in and only during the address resolution protocol (ARP) process.
The PEC is a CRC-8 error checking byte, calculated on all the message bytes. The PEC is appended to the message by the device that supplied the last data byte. If the PEC is present but not correct, a NACK is issued by the receiver. Otherwise an ACK is issued.
To calculate the CRC-8 by software, this module can hold the SCL line low after receiving the eighth SCL (8th bit) if this byte is a data byte. So software can determine whether an ACK or NACK should be sent to the bus by setting or clearing the TXAK bit if the FACK (fast ACK/NACK enable) bit is enabled.
SMBus requires a device always to acknowledge its own address, as a mechanism to detect the presence of a removable device (such as a battery or docking station) on the bus. In addition to indicating a slave device busy condition, SMBus uses the NACK mechanism to indicate the reception of an invalid command or invalid data. Because such a condition may occur on the last byte of the transfer, SMBus devices are required to have the ability to generate the not acknowledge after the transfer of each byte and before the completion of the transaction. This requirement is important because SMBus does not provide any other resend signaling. This difference in the use of the NACK signaling has implications on the specific implementation of the SMBus port, especially in devices that handle critical system data such as the SMBus host and the SBS components.
NOTE
In the last byte of master receive slave transmit mode, the master must send a NACK to the bus, so FACK must be switched off before the last byte transmits.
38.4.5 Resets
The I2C module is disabled after a reset. The I2C module cannot cause a core reset.
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Chapter 38 Inter-Integrated Circuit (I2C)
38.4.6 Interrupts
The I2C module generates an interrupt when any of the events in the table found here occur, provided that the IICIE bit is set.
The interrupt is driven by the IICIF bit (of the I2C Status Register) and masked with the
IICIE bit (of the I2C Control Register 1). The IICIF bit must be cleared (by software) by writing 1 to it in the interrupt routine. The SMBus timeouts interrupt is driven by SLTF and masked with the IICIE bit. The SLTF bit must be cleared by software by writing 1 to it in the interrupt routine. You can determine the interrupt type by reading the Status
Register.
NOTE
In master receive mode, the FACK bit must be set to zero before the last byte transfer.
Table 38-44. Interrupt summary
Interrupt source
Complete 1-byte transfer
Match of received calling address
Arbitration lost
I 2 C bus stop detection
SMBus SCL low timeout
SMBus SCL high SDA low timeout
Wakeup from stop or wait mode
Status
TCF
IAAS
ARBL
STOPF
SLTF
SHTF2
IAAS
Flag
IICIF
IICIF
IICIF
IICIF
IICIF
IICIF
IICIF
Local enable
IICIE
IICIE
IICIE
IICIE & STOPIE
IICIE
IICIE & SHTF2IE
IICIE & WUEN
38.4.6.1 Byte transfer interrupt
The Transfer Complete Flag (TCF) bit is set at the falling edge of the ninth clock to indicate the completion of a byte and acknowledgement transfer. When FACK is enabled,
TCF is then set at the falling edge of eighth clock to indicate the completion of byte.
38.4.6.2 Address detect interrupt
When the calling address matches the programmed slave address (I2C Address Register) or when the GCAEN bit is set and a general call is received, the IAAS bit in the Status
Register is set. The CPU is interrupted, provided the IICIE bit is set. The CPU must check the SRW bit and set its Tx mode accordingly.
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Functional description
38.4.6.3 Stop Detect Interrupt
When the stop status is detected on the I 2 C bus, the STOPF bit is set to 1. The CPU is interrupted, provided the IICIE and STOPIE bits are both set to 1.
38.4.6.4 Exit from low-power/stop modes
The slave receive input detect circuit and address matching feature are still active on low power modes (wait and stop). An asynchronous input matching slave address or general call address brings the CPU out of low power/stop mode if the interrupt is not masked.
Therefore, TCF and IAAS both can trigger this interrupt.
38.4.6.5 Arbitration lost interrupt
The I2C is a true multimaster bus that allows more than one master to be connected on it.
If two or more masters try to control the bus at the same time, the relative priority of the contending masters is determined by a data arbitration procedure. The I2C module asserts the arbitration-lost interrupt when it loses the data arbitration process and the ARBL bit in the Status Register is set.
Arbitration is lost in the following circumstances:
1. SDA is sampled as low when the master drives high during an address or data transmit cycle.
2. SDA is sampled as low when the master drives high during the acknowledge bit of a data receive cycle.
3. A START cycle is attempted when the bus is busy.
4. A repeated START cycle is requested in slave mode.
5. A STOP condition is detected when the master did not request it.
The ARBL bit must be cleared (by software) by writing 1 to it.
38.4.6.6 Timeout interrupt in SMBus
When the IICIE bit is set, the I2C module asserts a timeout interrupt (outputs SLTF and
SHTF2) upon detection of any of the mentioned timeout conditions, with one exception.
The SCL high and SDA high TIMEOUT mechanism must not be used to influence the timeout interrupt output, because this timeout indicates an idle condition on the bus.
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Chapter 38 Inter-Integrated Circuit (I2C)
SHTF1 rises when it matches the SCL high and SDA high TIMEOUT and falls automatically just to indicate the bus status. The SHTF2's timeout period is the same as that of SHTF1, which is short compared to that of SLTF, so another control bit,
SHTF2IE, is added to enable or disable it.
38.4.7 Programmable input glitch filter
An I2C glitch filter has been added outside legacy I2C modules but within the I2C package. This filter can absorb glitches on the I2C clock and data lines for the I2C module.
The width of the glitch to absorb can be specified in terms of the number of (half) I2C module clock cycles. A single Programmable Input Glitch Filter control register is provided. Effectively, any down-up-down or up-down-up transition on the data line that occurs within the number of clock cycles programmed in this register is ignored by the
I2C module. The programmer must specify the size of the glitch (in terms of I2C module clock cycles) for the filter to absorb and not pass.
Noise suppress circuits
SCL, SDA internal signals
SCL, SDA external signals
DFF DFF DFF DFF
Figure 38-41. Programmable input glitch filter diagram
38.4.8 Address matching wakeup
When a primary, range, or general call address match occurs when the I2C module is in slave receive mode, the MCU wakes from a low power mode where no peripheral bus is running.
Data sent on the bus that is the same as a target device address might also wake the target
MCU.
After the address matching IAAS bit is set, an interrupt is sent at the end of address matching to wake the core. The IAAS bit must be cleared after the clock recovery.
NOTE
After the system recovers and is in Run mode, restart the I2C module if it is needed to transfer packets. The SCL line is not held low until the I2C module resets after address matching.
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Initialization/application information
The main purpose of this feature is to wake the MCU from a low power mode where no peripheral bus is running. When the
MCU is in such a mode: addressing as a slave, slave read/write, and sending an acknowledge bit are not fully supported. To avoid I2C transfer problems resulting from this situation, firmware should prevent the MCU execution of a STOP instruction when the I2C module is in the middle of a transfer unless the Stop mode holdoff feature is used during this period
(set FLT[SHEN] to 1).
38.4.9 DMA support
If the DMAEN bit is cleared and the IICIE bit is set, an interrupt condition generates an interrupt request.
If the DMAEN bit is set and the IICIE bit is set, an interrupt condition generates a DMA request instead. DMA requests are generated by the transfer complete flag (TCF).
If the DMAEN bit is set, the only arbitration lost is to another I2C module (error), and
SCL low timeouts (error) generate CPU interrupts. All other events initiate a DMA transfer.
NOTE
Before the last byte of master receive mode, TXAK must be set to send a NACK after the last byte’s transfer. Therefore, the
DMA must be disabled before the last byte’s transfer.
NOTE
In 10-bit address mode transmission, the addresses to send occupy 2-3 bytes. During this transfer period, the DMA must be disabled because the C1 register is written to send a repeat start or to change the transfer direction.
38.5 Initialization/application information
Module Initialization (Slave)
1. Write: Control Register 2
• to enable or disable general call
• to select 10-bit or 7-bit addressing mode
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Chapter 38 Inter-Integrated Circuit (I2C)
2. Write: Address Register 1 to set the slave address
3. Write: Control Register 1 to enable the I2C module and interrupts
4. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data
5. Initialize RAM variables used to achieve the routine shown in the following figure
Module Initialization (Master)
1. Write: Frequency Divider register to set the I2C baud rate (see example in
)
2. Write: Control Register 1 to enable the I2C module and interrupts
3. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data
4. Initialize RAM variables used to achieve the routine shown in the following figure
5. Write: Control Register 1 to enable TX
6. Write: Control Register 1 to enable MST (master mode)
7. Write: Data register with the address of the target slave (the LSB of this byte determines whether the communication is master receive or transmit)
The routine shown in the following figure encompasses both master and slave I2C operations. For slave operation, an incoming I2C message that contains the proper address begins I2C communication. For master operation, communication must be initiated by writing the Data register. An example of an I2C driver which implements many of the steps described here is available in AN4342: Using the Inter-Integrated
Circuit on ColdFire+ and Kinetis .
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Initialization/application information
Clear IICIF
Y
Tx
Last byte transmitted?
Y
N
RXAK=0?
N
Y
Y
End of address cycle
(master Rx)?
N
Tx/Rx?
Rx
Y
Last byte to be read?
N
2nd to last byte to be read?
N
Y
Write next byte to Data reg
Set TXACK
Generate stop signal (MST=0)
Master mode?
N
Clear ARBL
Y
Arbitration lost?
N
N Y
Y
(read)
IIAAS=1?
Y
SRW=1?
Address transfer see note 1
N (write)
IIAAS=1?
N
Data transfer see note 2
Rx
Tx/Rx?
Tx
Set TX mode
Write data to Data reg
Y
Transmit next byte
ACK from receiver?
N
Read data from
Data reg and store
Switch to
Rx mode
Set Rx mode
Switch to
Rx mode
Dummy read from Data reg
Generate stop signal (MST=0)
Read data from
Data reg and store
Dummy read from Data reg
Dummy read from Data reg
750
RTI
Notes:
1. If general call is enabled, check to determine if the received address is a general call address (0x00).
If the received address is a general call address, the general call must be handled by user software.
2. When 10-bit addressing addresses a slave, the slave sees an interrupt following the first byte of the extended address.
Ensure that for this interrupt, the contents of the Data register are ignored and not treated as a valid data transfer.
Figure 38-42. Typical I2C interrupt routine
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Chapter 38 Inter-Integrated Circuit (I2C)
Entry of ISR
Clear IICIF
Y
SLTF=1 or
SHTF2=1?
N
Y
Y
Last byte transmitted?
Y
N
RXAK=0?
Y
End of address cycle
(master Rx)?
N
Clear IICIF
Tx
N
Rx
Tx/Rx?
Delay (note 2)
Last byte to be read?
N
Y
2nd to last byte to be read?
N
Read data from
Data reg and soft CRC
Read data and
Soft CRC
Set TXAK to proper value
Y
Generate stop signal (MST=0)
Set TXACK=1,
Clear FACK=0
Write next byte to Data reg
Set TXAK to proper value
FACK=1?
Y
Master mode?
N
N
N
Y
(read)
Read data from
Data reg and soft CRC
Set TXAK to proper value,
Clear IICIF
Delay (note 2)
See typical I2C interrupt routine flow chart
Clear ARBL
Y
Y
IAAS=1?
Y
SRW=1?
Address transfer
(see note 1)
Rx
N (write)
Read data from
Data reg and soft CRC
Switch to
Rx mode
Clear IICIF
Delay (note 2)
Set Tx mode
Set TXAK to proper value,
Clear IICIF
Delay (note 2)
Arbitration lost?
N
IAAS=1?
N
Tx/Rx?
Tx
ACK from receiver?
N
Y
Clear IICIF
Transmit next byte
Switch to
Rx mode
Dummy read from Data reg
Generate stop signal (MST=0)
Read data from
Data reg and store
Write data to Data reg
Read data from
Data reg and store (note 3)
Dummy read from Data reg
RTI
Notes:
1. If general call or SIICAEN is enabled, check to determine if the received address is a general call address (0x00) or an SMBus
device default address. In either case, they must be handled by user software.
2. In receive mode, one bit time delay may be needed before the first and second data reading, to wait for the possible longest time
period (in worst case) of the 9th SCL cycle.
3. This read is a dummy read in order to reset the SMBus receiver state machine.
Figure 38-43. Typical I2C SMBus interrupt routine
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Initialization/application information
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Chapter 39
Universal Asynchronous Receiver/Transmitter
(UART0)
The UART supports full-duplex, asynchronous, NRZ serial communication and comprises a baud rate generator, transmitter, and receiver block. The transmitter and receiver operate independently, although they use the same baud rate generator.
39.1 Introduction
39.1.1 Features
Features of the UART module include:
• Full-duplex, standard non-return-to-zero (NRZ) format
• Double-buffered transmitter and receiver with separate enables
• Programmable baud rates (13-bit modulo divider)
• Transmit and receive baud rate can operate asynchronous to the bus clock:
• Baud rate can be configured independently of the bus clock frequency
• Supports operation in Stop modes
• Configurable receiver buad rate oversampling ratio from 4x to 32x
• Interrupt, DMA or polled operation:
• Transmit data register empty and transmission complete
• Receive data register full
• Receive overrun, parity error, framing error, and noise error
• Idle receiver detect
• Active edge on receive pin
• Break detect supporting LIN
• Hardware parity generation and checking
• Programmable 8-bit, 9-bit or 10-bit character length
• Programmable 1-bit or 2-bit stop bits
• Receiver wakeup by idle-line, address-mark or address match
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Introduction
• Optional 13-bit break character generation / 11-bit break character detection
• Selectable transmitter output and receiver input polarity
An example of using several of the asynchronous features of UART0, including asynchronous DMA, is described in AN4631: Using the Asynchronous DMA features of the Kinetis L Series .
39.1.2 Modes of operation
39.1.2.1 Stop mode
The UART will remain functional during Stop mode, provided the asynchronous transmit and receive clock remains enabled. The UART can generate an interrupt or DMA request to cause a wakeup from Stop mode.
39.1.2.2 Wait mode
The UART can be configured to Stop in Wait modes, when the DOZEEN bit is set. The transmitter and receiver will finish transmitting/receiving the current word.
39.1.2.3 Debug mode
The UART remains functional in debug mode.
39.1.3 Block diagram
The following figure shows the transmitter portion of the UART.
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ASYNCH
MODULE
CLOCK
BAUD
Divider
Divider
Internal Bus
M
Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0)
(Write-Only)
UART_D – Tx Buffer
11-BIT Transmit Shift Register
H 8 7 6 5 4 3 2 1 0 L
SHIFT DIRECTION
LOOPS
RSRC
Loop
Control
To Receive
Data In
To TxD Pin
TXINV
PE
PT
TE
SBK
TXDIR
BRK13
T8
Parity
Generation
Transmit Control
UART Controls TxD
TxD Direction
TO TxD
Pin Logic
TDRE
TIE
TC
TCIE
Figure 39-1. UART transmitter block diagram
The following figure shows the receiver portion of the UART.
Tx Interrupt
Request
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Register definition
SBR12:0
ASYNCH
MODULE
CLOCK
RE
RAF
BAUDRATE
GENERATOR
RECEIVE
CONTROL
RxD
LOOPS
RSRC
From Transmitter
RxD
RECEIVER
SOURCE
CONTROL
ACTIVE EDGE
DETECT
INTERNAL BUS
DATA BUFFER
VARIABLE 12-BIT RECEIVE
SHIFT REGISTER
SHIFT DIRECTION
PE
PT
M
M10
LBKDE
MSBF
RXINV
PARITY
LOGIC
WAKEUP
LOGIC
IRQ / DMA
LOGIC
DMA Requests
IRQ Requests
Figure 39-2. UART receiver block diagram
39.2 Register definition
The UART includes registers to control baud rate, select UART options, report UART status, and for transmit/receive data.
Accesses to address outside the valid memory map will generate a bus error.
UART memory map
Absolute address
(hex)
Register name
4006_A000 UART Baud Rate Register High (UART0_BDH)
4006_A001 UART Baud Rate Register Low (UART0_BDL)
4006_A002 UART Control Register 1 (UART0_C1)
4006_A003 UART Control Register 2 (UART0_C2)
4006_A004 UART Status Register 1 (UART0_S1)
4006_A005 UART Status Register 2 (UART0_S2)
4006_A006 UART Control Register 3 (UART0_C3)
4006_A007 UART Data Register (UART0_D)
Width
(in bits)
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8
8
8
8
8
8
8
8
Access Reset value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00h
04h
00h
00h
C0h
00h
00h
00h
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Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0)
UART memory map (continued)
Absolute address
(hex)
Register name
4006_A008 UART Match Address Registers 1 (UART0_MA1)
4006_A009 UART Match Address Registers 2 (UART0_MA2)
4006_A00A UART Control Register 4 (UART0_C4)
4006_A00B UART Control Register 5 (UART0_C5)
Width
(in bits)
Access Reset value
8
8
8
8
R/W
R/W
R/W
R/W
00h
00h
0Fh
00h
Section/ page
39.2.1 UART Baud Rate Register High (UARTx_BDH)
This register, along with UART_BDL, controls the prescale divisor for UART baud rate generation. The 13-bit baud rate setting [SBR12:SBR0] should only be updated when the transmitter and receiver are both disabled.
Address: Base address + 0h offset
Bit
Read
Write
Reset
7
0
6
0
Field
7
LBKDIE
5
0
4
0
3
0
UARTx_BDH field descriptions
LIN Break Detect Interrupt Enable (for LBKDIF)
Description
6
RXEDGIE
0 Hardware interrupts from UART_S2[LBKDIF] disabled (use polling).
1 Hardware interrupt requested when UART_S2[LBKDIF] flag is 1.
RX Input Active Edge Interrupt Enable (for RXEDGIF)
5
SBNS
2
0
0 Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling).
1 Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1.
Stop Bit Number Select
1
0
0
0
SBNS determines whether data characters are one or two stop bits. This bit should only be changed when the transmitter and receiver are both disabled.
4–0
SBR
0 One stop bit.
1 Two stop bit.
Baud Rate Modulo Divisor.
The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the baud rate generator. When BR is 1 - 8191, the baud rate equals baud clock / ((OSR+1) × BR).
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Register definition
39.2.2 UART Baud Rate Register Low (UARTx_BDL)
This register, along with UART_BDH, control the prescale divisor for UART baud rate generation. The 13-bit baud rate setting [SBR12:SBR0] can only be updated when the transmitter and receiver are both disabled.
UART_BDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first time the receiver or transmitter is enabled; that is, UART_C2[RE] or UART_C2[TE] bits are written to 1.
Address: Base address + 1h offset
Bit
Read
Write
Reset
Field
7–0
SBR
7 6 5 4 3
0 0 0 0 0
UARTx_BDL field descriptions
Description
Baud Rate Modulo Divisor
2
1
1
0
0
0
These 13 bits in SBR[12:0] are referred to collectively as BR. They set the modulo divide rate for the baud rate generator. When BR is 1 - 8191, the baud rate equals baud clock/((OSR+1) × BR).
39.2.3 UART Control Register 1 (UARTx_C1)
This read/write register controls various optional features of the UART system. This register should only be altered when the transmitter and receiver are both disabled.
Address: Base address + 2h offset
Bit
Read
Write
Reset
7
0
6
0
Field
7
LOOPS
5
0
4
0
3
0
UARTx_C1 field descriptions
Description
2
0
1
0
Loop Mode Select
Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS is set, the transmitter output is internally connected to the receiver input.
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0
0
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Field
6
DOZEEN
5
RSRC
4
M
3
WAKE
2
ILT
1
PE
0
PT
Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0)
UARTx_C1 field descriptions (continued)
Description
0 Normal operation - UART_RX and UART_TX use separate pins.
1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input.
(See RSRC bit.) UART_RX pin is not used by UART.
Doze Enable
0 UART is enabled in Wait mode.
1 UART is disabled in Wait mode.
Receiver Source Select
This bit has no meaning or effect unless the LOOPS bit is set to 1. When LOOPS is set, the receiver input is internally connected to the UART_TX pin and RSRC determines whether this connection is also connected to the transmitter output.
0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the UART_RX pins.
1 Single-wire UART mode where the UART_TX pin is connected to the transmitter output and receiver input.
9-Bit or 8-Bit Mode Select
0 Receiver and transmitter use 8-bit data characters.
1 Receiver and transmitter use 9-bit data characters.
Receiver Wakeup Method Select
0 Idle-line wakeup.
1 Address-mark wakeup.
Idle Line Type Select
Setting this bit to 1 ensures that the stop bits and logic 1 bits at the end of a character do not count toward the 10 to 13 bit times of logic high level needed by the idle line detection logic.
0 Idle character bit count starts after start bit.
1 Idle character bit count starts after stop bit.
Parity Enable
Enables hardware parity generation and checking. When parity is enabled, the bit immediately before the stop bit is treated as the parity bit.
0 No hardware parity generation or checking.
1 Parity enabled.
Parity Type
Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including the parity bit, is even.
0 Even parity.
1 Odd parity.
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Register definition
39.2.4 UART Control Register 2 (UARTx_C2)
This register can be read or written at any time.
Address: Base address + 3h offset
Bit
Read
Write
Reset
7
0
6
0
Field
7
TIE
5
0
4
0
3
0
UARTx_C2 field descriptions
Description
Transmit Interrupt Enable for TDRE
6
TCIE
0 Hardware interrupts from TDRE disabled; use polling.
1 Hardware interrupt requested when TDRE flag is 1.
Transmission Complete Interrupt Enable for TC
5
RIE
0 Hardware interrupts from TC disabled; use polling.
1 Hardware interrupt requested when TC flag is 1.
Receiver Interrupt Enable for RDRF
4
ILIE
0 Hardware interrupts from RDRF disabled; use polling.
1 Hardware interrupt requested when RDRF flag is 1.
Idle Line Interrupt Enable for IDLE
3
TE
2
0
1
0
0
0
0 Hardware interrupts from IDLE disabled; use polling.
1 Hardware interrupt requested when IDLE flag is 1.
Transmitter Enable
TE must be 1 to use the UART transmitter. When TE is set, the UART forces the UART_TX pin to act as an output for the UART system.
When the UART is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of traffic on the single UART communication line ( UART_TX pin).
TE can also queue an idle character by clearing TE then setting TE while a transmission is in progress.
When TE is written to 0, the transmitter keeps control of the port UART_TX pin until any data, queued idle, or queued break character finishes transmitting before allowing the pin to tristate.
2
RE
1
RWU
0 Transmitter disabled.
1 Transmitter enabled.
Receiver Enable
When the UART receiver is off or LOOPS is set, the UART_RX pin is not used by the UART .
When RE is written to 0, the receiver finishes receiving the current character (if any).
0 Receiver disabled.
1 Receiver enabled.
Receiver Wakeup Control
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Field
0
SBK
Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0)
UARTx_C2 field descriptions (continued)
Description
This bit can be written to 1 to place the UART receiver in a standby state where it waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is an idle line between messages, WAKE = 0, idle-line wakeup, or a logic 1 in the most significant data bit in a character, WAKE =
1, address-mark wakeup. Application software sets RWU and, normally, a selected hardware condition automatically clears RWU.
0 Normal UART receiver operation.
1 UART receiver in standby waiting for wakeup condition.
Send Break
Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional break characters of 10 to 13, or 13 to 16 if BRK13 = 1, bit times of logic 0 are queued as long as SBK is set.
Depending on the timing of the set and clear of SBK relative to the information currently being transmitted, a second break character may be queued before software clears SBK.
0 Normal transmitter operation.
1 Queue break character(s) to be sent.
39.2.5 UART Status Register 1 (UARTx_S1)
Address: Base address + 4h offset
Bit
Read
Write
Reset
7
1
6
1
Field
7
TDRE
5
0
4
0
3
0
UARTx_S1 field descriptions
Description
Transmit Data Register Empty Flag
2
0
1
0
TDRE is set out of reset and whenever there is room to write data to the transmit data buffer. To clear
TDRE, write to the UART data register ( UART_D).
0
0
6
TC
0 Transmit data buffer full.
1 Transmit data buffer empty.
Transmission Complete Flag
TC is set out of reset and when TDRE is set and no data, preamble, or break character is being transmitted.
TC is cleared automatically by one of the following:
• Write to the UART data register ( UART_D) to transmit new data
• Queue a preamble by changing TE from 0 to 1
• Queue a break character by writing 1 to UART_C2[SBK]
0 Transmitter active (sending data, a preamble, or a break).
1 Transmitter idle (transmission activity complete).
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Register definition
Field
5
RDRF
UARTx_S1 field descriptions (continued)
Description
Receive Data Register Full Flag
RDRF becomes set whenever the receive data buffer is full. To clear RDRF, read the UART data register
( UART_D).
4
IDLE
3
OR
2
NF
1
FE
0
PF
0 Receive data buffer empty.
1 Receive data buffer full.
Idle Line Flag
IDLE is set when the UART receive line becomes idle for a full character time after a period of activity.
When ILT is cleared, the receiver starts counting idle bit times after the start bit. If the receive character is all 1s, these bit times and the stop bits time count toward the full character time of logic high, 10 to 13 bit times, needed for the receiver to detect an idle line. When ILT is set, the receiver doesn't start counting idle bit times until after the stop bits. The stop bits and any logic high bit times at the end of the previous character do not count toward the full character time of logic high needed for the receiver to detect an idle line.
To clear IDLE, write logic 1 to the IDLE flag. After IDLE has been cleared, it cannot become set again until after a new character has been received and RDRF has been set. IDLE is set only once even if the receive line remains idle for an extended period.
0 No idle line detected.
1 Idle line was detected.
Receiver Overrun Flag
OR is set when a new serial character is ready to be transferred to the receive data buffer, but the previously received character has not been read from UART_D yet. In this case, the new character, and all associated error information, is lost because there is no room to move it into UART_D. To clear OR, write a logic 1 to the OR flag.
0 No overrun.
1 Receive overrun (new UART data lost).
Noise Flag
The advanced sampling technique used in the receiver takes three samples in each of the received bits. If any of these samples disagrees with the rest of the samples within any bit time in the frame, the flag NF is set at the same time as RDRF is set for the character. To clear NF, write logic one to the NF.
0 No noise detected.
1 Noise detected in the received character in UART_D.
Framing Error Flag
FE is set at the same time as RDRF when the receiver detects a logic 0 where a stop bit was expected.
This suggests the receiver was not properly aligned to a character frame. To clear FE, write a logic one to the FE flag.
0 No framing error detected. This does not guarantee the framing is correct.
1 Framing error.
Parity Error Flag
PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in the received character does not agree with the expected parity value. To clear PF, write a logic one to the PF.
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Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0)
UARTx_S1 field descriptions (continued)
Description
0 No parity error.
1 Parity error.
39.2.6 UART Status Register 2 (UARTx_S2)
This register contains one read-only status flag.
When using an internal oscillator in a LIN system, it is necessary to raise the break detection threshold one bit time. Under the worst case timing conditions allowed in LIN, it is possible that a 0x00 data character can appear to be 10.26 bit times long at a slave running 14% faster than the master. This would trigger normal break detection circuitry designed to detect a 10-bit break symbol. When the LBKDE bit is set, framing errors are inhibited and the break detection threshold increases, preventing false detection of a 0x00 data character as a LIN break symbol.
Address: Base address + 5h offset
7 Bit
Read
Write
Reset
6
Field
7
LBKDIF
5
4
3
0 0 0 0 0
UARTx_S2 field descriptions
Description
LIN Break Detect Interrupt Flag
2
0
1
0
LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break character is detected.
LBKDIF is cleared by writing a 1 to it.
0
0
6
RXEDGIF
5
MSBF
0 No LIN break character has been detected.
1 LIN break character has been detected.
UART_RX Pin Active Edge Interrupt Flag
RXEDGIF is set when an active edge, falling if RXINV = 0, rising if RXINV=1, on the UART_RX pin occurs.
RXEDGIF is cleared by writing a 1 to it.
0 No active edge on the receive pin has occurred.
1 An active edge on the receive pin has occurred.
MSB First
Setting this bit reverses the order of the bits that are transmitted and received on the wire. This bit does not affect the polarity of the bits, the location of the parity bit or the location of the start or stop bits. This bit should only be changed when the transmitter and receiver are both disabled.
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Register definition
Field
4
RXINV
UARTx_S2 field descriptions (continued)
Description
0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M], C1[PE] and C4[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE].
Receive Data Inversion
Setting this bit reverses the polarity of the received data input.
NOTE: Setting RXINV inverts the UART_RXD input for all cases: data bits, start and stop bits, break, and idle.
3
RWUID
2
BRK13
1
LBKDE
0
RAF
0 Receive data not inverted.
1 Receive data inverted.
Receive Wake Up Idle Detect
RWUID controls whether the idle character that wakes up the receiver sets the IDLE bit. This bit should only be changed when the receiver is disabled.
0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character.
1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.
Break Character Generation Length
BRK13 selects a longer transmitted break character length. Detection of a framing error is not affected by the state of this bit. This bit should only be changed when the transmitter is disabled.
0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS =
0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS =
0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).
LIN Break Detection Enable
LBKDE selects a longer break character detection length. While LBKDE is set, framing error (FE) and receive data register full (RDRF) flags are prevented from setting.
0 Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M
= 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
1 Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or
M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
Receiver Active Flag
RAF is set when the UART receiver detects the beginning of a valid start bit, and RAF is cleared automatically when the receiver detects an idle line.
0 UART receiver idle waiting for a start bit.
1 UART receiver active ( UART_RXD input not idle).
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Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0)
39.2.7 UART Control Register 3 (UARTx_C3)
Address: Base address + 6h offset
Bit
Read
Write
Reset
Field
7
R8T9
6
R9T8
5
TXDIR
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
UARTx_C3 field descriptions
Description
Receive Bit 8 / Transmit Bit 9
When the UART is configured for 9-bit data (M = 1), R8 can be thought of as a ninth receive data bit to the left of the msb of the buffered data in the UART_D register. When reading 9-bit data, read R8 before reading UART_D because reading UART_D completes automatic flag clearing sequences that could allow
R8 and UART_D to be overwritten with new data.
When the UART is configured for 10-bit data (M10 = 1), T9 may be thought of as a tenth transmit data bit.
When writing 10-bit data, the entire 10-bit value is transferred to the UART transmit buffer when UART_D is written so T9 and T8 should be written, if it needs to change from its previous value, before UART_D is written. If T9 and T8 do not need to change in the new value, such as when it is used to generate mark or space parity, they need not be written each time UART_D is written.
Receive Bit 9 / Transmit Bit 8
When the UART is configured for 9-bit data (M = 1), T8 may be thought of as a ninth transmit data bit to the left of the msb of the data in the UART_D register. When writing 9-bit data, the entire 9-bit value is transferred to the UART transmit buffer after UART_D is written so T8 should be written, if it needs to change from its previous value, before UART_D is written. If T8 does not need to change in the new value, such as when it is used to generate mark or space parity, it need not be written each time UART_D is written.
When the UART is configured for 10-bit data (M10 = 1), R9 can be thought of as a tenth receive data bit.
When reading 10-bit data, read R9 and R8 before reading UART_D because reading UART_D completes automatic flag clearing sequences that could allow R8, R9 and UART_D to be overwritten with new data.
UART_TX Pin Direction in Single-Wire Mode
When the UART is configured for single-wire half-duplex operation (LOOPS = RSRC = 1), this bit determines the direction of data at the UART_TXD pin. When clearing TXDIR, the transmitter will finish receiving the current character (if any) before the receiver starts receiving data from the UART_TXD pin.
4
TXINV
3
ORIE
0 UART_TXD pin is an input in single-wire mode.
1 UART_TXD pin is an output in single-wire mode.
Transmit Data Inversion
Setting this bit reverses the polarity of the transmitted data output.
NOTE: Setting TXINV inverts the UART_TXD output for all cases: data bits, start and stop bits, break, and idle.
0 Transmit data not inverted.
1 Transmit data inverted.
Overrun Interrupt Enable
This bit enables the overrun flag (OR) to generate hardware interrupt requests.
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Register definition
Field
2
NEIE
UARTx_C3 field descriptions (continued)
Description
0 OR interrupts disabled; use polling.
1 Hardware interrupt requested when OR is set.
Noise Error Interrupt Enable
This bit enables the noise flag (NF) to generate hardware interrupt requests.
1
FEIE
0 NF interrupts disabled; use polling.
1 Hardware interrupt requested when NF is set.
Framing Error Interrupt Enable
This bit enables the framing error flag (FE) to generate hardware interrupt requests.
0
PEIE
0 FE interrupts disabled; use polling.
1 Hardware interrupt requested when FE is set.
Parity Error Interrupt Enable
This bit enables the parity error flag (PF) to generate hardware interrupt requests.
0 PF interrupts disabled; use polling).
1 Hardware interrupt requested when PF is set.
39.2.8 UART Data Register (UARTx_D)
This register is actually two separate registers. Reads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also involved in the automatic flag clearing mechanisms for some of the UART status flags.
Address: Base address + 7h offset
Bit
Read
Write
Reset
7
0
6
0
5
0
4
0
3
0
UARTx_D field descriptions
Description
Read receive data buffer 7 or write transmit data buffer 7.
Field
7
R7T7
6
R6T6
5
R5T5
Read receive data buffer 6 or write transmit data buffer 6.
Read receive data buffer 5 or write transmit data buffer 5.
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2
0
1
0
0
0
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Field
4
R4T4
3
R3T3
2
R2T2
1
R1T1
0
R0T0
Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0)
UARTx_D field descriptions (continued)
Description
Read receive data buffer 4 or write transmit data buffer 4.
Read receive data buffer 3 or write transmit data buffer 3.
Read receive data buffer 2 or write transmit data buffer 2.
Read receive data buffer 1 or write transmit data buffer 1.
Read receive data buffer 0 or write transmit data buffer 0.
39.2.9 UART Match Address Registers 1 (UARTx_MA1)
The MA1 and MA2 registers are compared to input data addresses when the most significant bit is set and the associated C4[MAEN] bit is set. If a match occurs, the following data is transferred to the data register. If a match fails, the following data is discarded. Software should only write a MA register when the associated C4[MAEN] bit is clear.
Address: Base address + 8h offset
7 Bit
Read
Write
Reset 0
6
0
5 4 3
0 0 0
UARTx_MA1 field descriptions
Description
2
0
1
0
0
0
Field
7–0
MA
Match Address
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Register definition
39.2.10 UART Match Address Registers 2 (UARTx_MA2)
The MA1 and MA2 registers are compared to input data addresses when the most significant bit is set and the associated C4[MAEN] bit is set. If a match occurs, the following data is transferred to the data register. If a match fails, the following data is discarded. Software should only write a MA register when the associated C4[MAEN] bit is clear.
Address: Base address + 9h offset
7 Bit
Read
Write
Reset 0
6
0
5 4 3
0 0 0
UARTx_MA2 field descriptions
Description
2
0
1
0
0
0
Field
7–0
MA
Match Address
39.2.11 UART Control Register 4 (UARTx_C4)
Address: Base address + Ah offset
Bit
Read
Write
Reset
7
0
6
0
Field
7
MAEN1
5
0
4
0
3
1
UARTx_C4 field descriptions
Description
Match Address Mode Enable 1
Refer to
for more information.
6
MAEN2
2
1
1
1
0
1
0 All data received is transferred to the data buffer if MAEN2 is cleared.
1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.
Match Address Mode Enable 2
Refer to
for more information.
0 All data received is transferred to the data buffer if MAEN1 is cleared.
1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.
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Field
5
M10
4–0
OSR
Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0)
UARTx_C4 field descriptions (continued)
Description
10-bit Mode select
The M10 bit causes a tenth bit to be part of the serial transmission. This bit should only be changed when the transmitter and receiver are both disabled.
0 Receiver and transmitter use 8-bit or 9-bit data characters.
1 Receiver and transmitter use 10-bit data characters.
Over Sampling Ratio
This field configures the oversampling ratio for the receiver between 4x (00011) and 32x (11111). Writing an invalid oversampling ratio will default to an oversampling ratio of 16 (01111). This field should only be changed when the transmitter and receiver are both disabled.
39.2.12 UART Control Register 5 (UARTx_C5)
Address: Base address + Bh offset
Bit
Read
Write
Reset
7
6
Field
7
TDMAE
5
4 3
0 0 0 0 0
UARTx_C5 field descriptions
Description
Transmitter DMA Enable
2
0
1
0
0
0
TDMAE configures the transmit data register empty flag, S1[TDRE], to generate a DMA request.
6
Reserved
5
RDMAE
0 DMA request disabled.
1 DMA request enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
Receiver Full DMA Enable
RDMAE configures the receiver data register full flag, S1[RDRF], to generate a DMA request.
4–2
Reserved
1
BOTHEDGE
0 DMA request disabled.
1 DMA request enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
Both Edge Sampling
Enables sampling of the received data on both edges of the baud rate clock, effectively doubling the number of times the receiver samples the input data for a given oversampling ratio. This bit must be set for oversampling ratios between x4 and x7 and is optional for higher oversampling ratios. This bit should only be changed when the receiver is disabled.
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Functional description
Field
0
RESYNCDIS
UARTx_C5 field descriptions (continued)
Description
0 Receiver samples input data using the rising edge of the baud rate clock.
1 Receiver samples input data using the rising and falling edge of the baud rate clock.
Resynchronization Disable
When set, disables the resynchronization of the received data word when a data one followed by data zero transition is detected. This bit should only be changed when the receiver is disabled.
0 Resynchronization during received data word is supported
1 Resynchronization during received data word is disabled
39.3 Functional description
The UART supports full-duplex, asynchronous, NRZ serial communication and comprises a baud rate generator, transmitter, and receiver block.
The transmitter and receiver operate independently, although they use the same baud rate generator. The following describes each of the blocks of the UART.
39.3.1 Baud rate generation
A 13-bit modulus counter in the baud rate generator derive the baud rate for both the receiver and the transmitter.
The value from 1 to 8191 written to SBR[12:0] determines the baud clock divisor for the asynchronous UART baud clock. The SBR bits are in the UART baud rate registers,
BDH and BDL. The baud rate clock drives the receiver, while the transmitter is driven by the baud rate clock divided by the over sampling ratio. Depending on the over sampling ratio, the receiver has an acquisition rate of 4 to 32 samples per bit time.
UART ASYNCH
Module Clock
Modulo Divide By
(1 through 8191)
OSR
SBR[12:0]
Baud Rate Generator
Off If [SBR12:SBR0] =0
Divide By
Tx Baud Rate
(OSR+1)
Rx Sampling Clock
[(OSR+1) × Baud Rate]
Baud Rate =
UART ASYNCH Module Clock
SBR[12:0] × (OSR+1)
Figure 39-27. UART baud rate generation
Baud rate generation is subject to two sources of error:
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Chapter 39 Universal Asynchronous Receiver/Transmitter (UART0)
• Integer division of the module clock may not give the exact target frequency.
• Synchronization with the asynchronous UART baud clock can cause phase shift.
39.3.2 Transmitter functional description
This section describes the overall block diagram for the UART transmitter, as well as specialized functions for sending break and idle characters.
The transmitter output (UART_TX) idle state defaults to logic high, C3[TXINV] is cleared following reset. The transmitter output is inverted by setting C3[TXINV]. The transmitter is enabled by setting the C2[TE] bit. This queues a preamble character that is one full character frame of the idle state. The transmitter then remains idle until data is available in the transmit data buffer. Programs store data into the transmit data buffer by writing to the UART data register.
The central element of the UART transmitter is the transmit shift register that is 10-bit to
13 bits long depending on the setting in the C1[M], C2[M10] and BDH[SBNS] control bits. For the remainder of this section, assume C1[M], C2[M10] and BDH[SBNS] are cleared, selecting the normal 8-bit data mode. In 8-bit data mode, the shift register holds a start bit, eight data bits, and a stop bit. When the transmit shift register is available for a new UART character, the value waiting in the transmit data register is transferred to the shift register, synchronized with the baud rate clock, and the transmit data register empty
(S1[TDRE]) status flag is set to indicate another character may be written to the transmit data buffer at UART_D.
If no new character is waiting in the transmit data buffer after a stop bit is shifted out the
UART_TX pin, the transmitter sets the transmit complete flag and enters an idle mode, with UART_TX high, waiting for more characters to transmit.
Writing 0 to C2[TE] does not immediately disable the transmitter. The current transmit activity in progress must first be completed. This includes data characters in progress, queued idle characters, and queued break characters.
39.3.2.1 Send break and queued idle
The UART_C2[SBK] bit sends break characters originally used to gain the attention of old teletype receivers. Break characters are a full character time of logic 0, 10-bit to 12bit times including the start and stop bits. A longer break of 13-bit times can be enabled by setting UART_S2[BRK13]. Normally, a program would wait for UART_S1[TDRE] to become set to indicate the last character of a message has moved to the transmit
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Functional description shifter, write 1, and then write 0 to the UART_C2[SBK] bit. This action queues a break character to be sent as soon as the shifter is available. If UART_C2[SBK] remains 1 when the queued break moves into the shifter, synchronized to the baud rate clock, an additional break character is queued. If the receiving device is another Freescale
Semiconductor UART, the break characters are received as 0s in all data bits and a framing error (UART_S1[FE] = 1) occurs.
1
1
1
1
1
0
1
0
0
0
0
0
When idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping receivers. Normally, a program would wait for
UART_S1[TDRE] to become set to indicate the last character of a message has moved to the transmit shifter, then write 0 and then write 1 to the UART_C2[TE] bit. This action queues an idle character to be sent as soon as the shifter is available. As long as the character in the shifter does not finish whileUART_C2[TE] is cleared, the UART transmitter never actually releases control of the UART_TX pin.
The length of the break character is affected by the UART_S2[BRK13], UART_C1[M] and UART_C4[M10] bits as shown below.
BRK13
Table 39-27. Break character length
M M10 SBNS
1
X
X
0
1
X
0
0
1
X
0
1
0
1
1
0
0
1
0
0
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
0
Break character length
10 bit times
11 bit times
11 bit times
12 bit times
12 bit times
13 bit times
13 bit times
14 bit times
14 bit times
15 bit times
15 bit times
16 bit times
39.3.3 Receiver functional description
In this section, the receiver block diagram is a guide for the overall receiver functional description.
Next, the data sampling technique used to reconstruct receiver data is described in more detail. Finally, two variations of the receiver wakeup function are explained.
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The receiver input is inverted by setting UART_S2[RXINV]. The receiver is enabled by setting the UART_C2[RE] bit. Character frames consist of a start bit of logic 0, eight to ten data bits (msb or lsb first), and one or two stop bits of logic 1. For information about
9-bit or 10-bit data mode, refer to
8-bit, 9-bit and 10-bit data modes
. For the remainder of this discussion, assume the UART is configured for normal 8-bit data mode.
After receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred to the receive data register and the receive data register full (UART_S1[RDRF]) status flag is set. If UART_S1[RDRF] was already set indicating the receive data register (buffer) was already full, the overrun (OR) status flag is set and the new data is lost. Because the UART receiver is double-buffered, the program has one full character time after UART_S1[RDRF] is set before the data in the receive data buffer must be read to avoid a receiver overrun.
When a program detects that the receive data register is full (UART_S1[RDRF] = 1), it gets the data from the receive data register by reading UART_D. Refer to
Interrupts and status flags for details about flag clearing.
39.3.3.1 Data sampling technique
The UART receiver supports an oversampling rate of between 4× and 32× of the baud rate clock for sampling. The receiver starts by taking logic level samples at the oversampling rate times the baud rate to search for a falling edge on the UART_RX serial data input pin. A falling edge is defined as a logic 0 sample after three consecutive logic
1 samples. The oversampling baud rate clock divides the bit time into 4 to 32 segments from 1 to OSR (where OSR is the configured oversampling ratio). When a falling edge is located, three more samples are taken at (OSR/2), (OSR/2)+1, and (OSR/2)+2 to make sure this was a real start bit and not merely noise. If at least two of these three samples are 0, the receiver assumes it is synchronized to a receive character. If another falling edge is detected before the receiver is considered synchronized, the receiver restarts the sampling from the first segment.
The receiver then samples each bit time, including the start and stop bits, at (OSR/2),
(OSR/2)+1, and (OSR/2)+2 to determine the logic level for that bit. The logic level is interpreted to be that of the majority of the samples taken during the bit time. If any sample in any bit time, including the start and stop bits, in a character frame fails to agree with the logic level for that bit, the noise flag (UART_S1[NF]) is set when the received character is transferred to the receive data buffer.
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Functional description
When the UART receiver is configured to sample on both edges of the baud rate clock, the number of segments in each received bit is effectively doubled (from 1 to OSR*2).
The start and data bits are then sampled at OSR, OSR+1 and OSR+2. Sampling on both edges of the clock must be enabled for oversampling rates of 4× to 7× and is optional for higher oversampling rates.
The falling edge detection logic continuously looks for falling edges. If an edge is detected, the sample clock is resynchronized to bit times (unless resynchronization has been disabled). This improves the reliability of the receiver in the presence of noise or mismatched baud rates. It does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame.
In the case of a framing error, provided the received character was not a break character, the sampling logic that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately.
39.3.3.2 Receiver wakeup operation
Receiver wakeup is a hardware mechanism that allows an UART receiver to ignore the characters in a message intended for a different UART receiver. In such a system, all receivers evaluate the first character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up control bit(UART_C2[RWU]). When RWU bit is set, the status flags associated with the receiver, with the exception of the idle bit, IDLE, when UART_S2[RWUID] bit is set, are inhibited from setting, thus eliminating the software overhead for handling the unimportant message characters. At the end of a message, or at the beginning of the next message, all receivers automatically force UART_C2[RWU] to 0 so all receivers wake up in time to look at the first character(s) of the next message.
39.3.3.2.1 Idle-line wakeup
When wake is cleared, the receiver is configured for idle-line wakeup. In this mode,
UART_C2[RWU] is cleared automatically when the receiver detects a full character time of the idle-line level. The UART_C1[M] and UART_C4[M10] control bit selects 8-bit to
10-bit data mode and the UART_BDH[SBNS] bit selects 1-bit or 2-bit stop bit number that determines how many bit times of idle are needed to constitute a full character time,
10 to 13 bit times because of the start and stop bits.
When UART_C2[RWU] is one and UART_S2[RWUID] is zero, the idle condition that wakes up the receiver does not set the UART_S1[IDLE] flag. The receiver wakes up and waits for the first data character of the next message that sets the UART_S1[RDRF] flag
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The idle-line type (UART_C1[ILT]) control bit selects one of two ways to detect an idle line. When UART_C1[ILT] is cleared, the idle bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward the full character time of idle. When UART_C1[ILT] is set, the idle bit counter does not start until after the stop bit time, so the idle detection is not affected by the data in the last character of the previous message.
39.3.3.2.2 Address-mark wakeup
When wake is set, the receiver is configured for address-mark wakeup. In this mode,
UART_C2[RWU] is cleared automatically when the receiver detects a logic 1 in the most significant bit of a received character.
Address-mark wakeup allows messages to contain idle characters, but requires the msb be reserved for use in address frames. The logic 1 in the msb of an address frame clears the UART_C2[RWU] bit before the stop bits are received and sets the UART_S1[RDRF] flag. In this case, the character with the msb set is received even though the receiver was sleeping during most of this character time.
39.3.3.2.3 Match address operation
Match address operation is enabled when the UART_C4[MAEN1] or
UART_C4[MAEN2] bit is set. In this function, a frame received by the UART_RX pin with a logic 1 in the bit position immediately preceding the stop bit is considered an address and is compared with the associated MA1 or MA2 register. The frame is only transferred to the receive buffer, and UART_S1[RDRF] is set, if the comparison matches.
All subsequent frames received with a logic 0 in the bit position immediately preceding the stop bit are considered to be data associated with the address and are transferred to the receive data buffer. If no marked address match occurs then no transfer is made to the receive data buffer, and all following frames with logic zero in the bit position immediately preceding the stop bit are also discarded. If both the UART_C4[MAEN1] and UART_C4[MAEN2] bits are negated, the receiver operates normally and all data received is transferred to the receive data buffer.
Match Address operation functions in the same way for both MA1 and MA2 registers.
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Functional description
• If only one of UART_C4[MAEN1] and UART_C4[MAEN2] is asserted, a marked address is compared only with the associated match register and data is transferred to the receive data buffer only on a match.
• If UART_C4[MAEN1] and UART_C4[MAEN2] are asserted, a marked address is compared with both match registers and data is transferred only on a match with either register.
39.3.4 Additional UART functions
The following sections describe additional UART functions.
39.3.4.1 8-bit, 9-bit and 10-bit data modes
The UART system, transmitter and receiver, can be configured to operate in 9-bit data mode by setting the UART_C1[M] or 10-bit data mode by setting UART_C4[M10]. In 9bit mode, there is a ninth data bit to the left of the msb of the UART data register, in 10bit mode there is a tenth data bit. For the transmit data buffer, these bits are stored in T8 and T9 in UART_C3. For the receiver, these bits are held in UART_C3[R8] and
UART_C3[R9].
For coherent writes to the transmit data buffer, write to UART_C3[T8] and
UART_C3[T9] before writing to UART_D.
If the bit values to be transmitted as the ninth and tenth bit of a new character are the same as for the previous character, it is not necessary to write to T8 and T9 again. When data is transferred from the transmit data buffer to the transmit shifter, the value in T8 and T9 is copied at the same time data is transferred from UART_D to the shifter.
The 9-bit data mode is typically used with parity to allow eight bits of data plus the parity in the ninth bit, or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. The 10-bit data mode is typically used with parity and address-mark wakeup so the ninth data bit can serve as the wakeup bit and the tenth bit as the parity bit.
In custom protocols, the ninth and/or tenth bits can also serve as software-controlled markers.
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39.3.4.2 Loop mode
When UART_C1[LOOPS] is set, the UART_C1[RSRC] bit in the same register chooses between loop mode (UART_C1[RSRC] = 0) or single-wire mode (UART_C1[RSRC] =
1). Loop mode is sometimes used to check software, independent of connections in the external system, to help isolate system problems. In this mode, the transmitter output is internally connected to the receiver input and the UART_RX pin is not used by the
UART.
39.3.4.3 Single-wire operation
When UART_C1[LOOPS] is set, the RSRC bit in the same register chooses between loop mode (UART_C1[RSRC] = 0) or single-wire mode (UART_C1[RSRC] = 1).
Single-wire mode implements a half-duplex serial connection. The receiver is internally connected to the transmitter output and to the UART_TX pin (the UART_RX pin is not used).
In single-wire mode, the UART_C3[TXDIR] bit controls the direction of serial data on the UART_TX pin. When UART_C3[TXDIR] is cleared, the UART_TX pin is an input to the UART receiver and the transmitter is temporarily disconnected from the
UART_TX pin so an external device can send serial data to the receiver. When
UART_C3[TXDIR] is set, the UART_TXD pin is an output driven by the transmitter, the internal loop back connection is disabled, and as a result the receiver cannot receive characters that are sent out by the transmitter.
39.3.5 Interrupts and status flags
The UART system generates three separate interrupts to reduce the amount of software needed to isolate the cause of the interrupt.
One interrupt is associated with the transmitter for TDRE and TC events. Another interrupt is associated with the receiver for RDRF, IDLE, RXEDGIF, and LBKDIF events. A third interrupt is used for OR, NF, FE, and PF error conditions. Each of these ten interrupt sources can be separately masked by local interrupt enable masks. The flags can be polled by software when the local masks are cleared to disable generation of hardware interrupt requests.
The UART transmitter has two status flags that can optionally generate hardware interrupt requests. Transmit data register empty (UART_S1[TDRE]) indicates when there is room in the transmit data buffer to write another transmit character to UART_D. If the transmit interrupt enable (UART_C2[TIE]) bit is set, a hardware interrupt is requested when UART_S1[TDRE] is set. Transmit complete (UART_S1[TC]) indicates that the
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Functional description transmitter is finished transmitting all data, preamble, and break characters and is idle with UART_TX at the inactive level. This flag is often used in systems with modems to determine when it is safe to turn off the modem. If the transmit complete interrupt enable
(UART_C2[TCIE]) bit is set, a hardware interrupt is requested when UART_S1[TC] is set. Instead of hardware interrupts, software polling may be used to monitor the
UART_S1[TDRE] and UART_S1[TC] status flags if the corresponding UART_C2[TIE] or UART_C2[TCIE] local interrupt masks are cleared.
When a program detects that the receive data register is full (UART_S1[RDRF] = 1), it gets the data from the receive data register by reading UART_D. The UART_S1[RDRF] flag is cleared by reading UART_D.
The IDLE status flag includes logic that prevents it from getting set repeatedly when the
UART_RX line remains idle for an extended period of time. IDLE is cleared by writing 1 to the UART_S1[IDLE] flag. After UART_S1[IDLE] has been cleared, it cannot become set again until the receiver has received at least one new character and has set
UART_S1[RDRF].
If the associated error was detected in the received character that caused
UART_S1[RDRF] to be set, the error flags - noise flag (UART_S1[NF]), framing error
(UART_S1[FE]), and parity error flag (UART_S1[PF]) - are set at the same time as
UART_S1[RDRF]. These flags are not set in overrun cases.
If UART_S1[RDRF] was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer, the overrun (UART_S1[OR]) flag is set instead of the data along with any associated NF, FE, or PF condition is lost.
At any time, an active edge on the UART_RX serial data input pin causes the
UART_S2[RXEDGIF] flag to set. The UART_S2[RXEDGIF] flag is cleared by writing a
1 to it. This function depends on the receiver being enabled (UART_C2[RE] = 1).
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Chapter 40
Universal Asynchronous Receiver/Transmitter
(UART1 and UART2)
The UART allows full-duplex, asynchronous, NRZ serial communication among the
MCU and remote devices, including other MCUs. The UART comprises a baud rate generator, transmitter, and receiver block.
40.1 Introduction
40.1.1 Features
Features of UART module include:
• Full-duplex, standard non-return-to-zero (NRZ) format
• Double-buffered transmitter and receiver with separate enables
• Programmable baud rates (13-bit modulo divider)
• Interrupt-driven or polled operation:
• Transmit data register empty and transmission complete
• Receive data register full
• Receive overrun, parity error, framing error, and noise error
• Idle receiver detect
• Active edge on receive pin
• Break detect supporting LIN
• Hardware parity generation and checking
• Programmable 8-bit or 9-bit character length
• Programmable 1-bit or 2-bit stop bits
• Receiver wakeup by idle-line or address-mark
• Optional 13-bit break character generation / 11-bit break character detection
• Selectable transmitter output polarity
• 5-channel DMA interface
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Introduction
40.1.2 Modes of operation
See Section
for details concerning UART operation in these modes:
• 8- and 9-bit data modes
• Stop mode operation
• Loop mode
• Single-wire mode
40.1.3 Block diagram
The following figure shows the transmitter portion of the UART.
INTERNAL BUS
MODULE
CLOCK
BAUD DIVIDER
SBR12–SBR0
÷ 16
M
TXINV
UART DATA REGISTER (UART_D)
11-BIT TRANSMIT SHIFT REGISTER
H 8 7 6 5 4 3 2 1 0 L
SHIFT DIRECTION
TXINV
TxD
PE
PT
T8
PARITY
GENERATION
TRANSMITTER CONTROL
LOOP
CONTROL
TO
RECEIVER
LOOPS
RSRC
TxD Pin Control
Tx Pin Logic
TDRE INTERRUPT/DMA
REQUEST
TDRE
TIE
TE SBK TXDIR
TC INTERRUPT/DMA
REQUEST
TC
TCIE
Figure 40-1. UART transmitter block diagram
The following figure shows the receiver portion of the UART.
DMA done
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Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
INTERNAL BUS
SBR12–SBR0
MODULE
CLOCK
RE
RAF
BAUD DIVIDER
DATA
RECOVERY
M
LBKDE FROM
TRANSMITTER
LOOPS
RSRC
SINGLE-WIRE
LOOP CONTROL
WAKE
ILT
From RxD Pin
(ipp_ind_sci_rx)
RXINV
WAKEUP
LOGIC
UART DATA REGISTER (UART_D)
11-BIT RECEIVE SHIFT REGISTER
H 8 7 6 5 4 3 2 1 0 L
SHIFT DIRECTION
RWU RWUID
From RxD Pin
(ipp_i nd_sci _r x)
ACTIVE EDGE
DETECT
RDRF
RIE
IDLE
ILIE
LBKDIF
LBKDIE
RXEDGIF
RXEDGIE
Rx
Interrupt/DMA
Request
R8
OR
ORIE
FE
FEIE
NF
NEIE
PE
PT
PARITY
CHECKING PF
PEIE
Figure 40-2. UART receiver block diagram
Error
Interrupt
Requestt
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Register definition
40.2 UART signal descriptions
The UART signals are shown in the table found here.
Table 40-1. UART signal descriptions
Signal
RxD
TxD
Description
Receive data
Transmit data
I/O
I
I/O
40.2.1 Detailed signal descriptions
The detailed signal descriptions of the UART are shown in the following table.
Signal
RxD
TxD
Table 40-2. UART—Detailed signal descriptions
I/O
I
I/O
State meaning
Timing
State meaning
Timing
Description
Receive data. Serial data input to receiver.
Whether RxD is interpreted as a 1 or 0 depends on the bit encoding method along with other configuration settings.
Sampled at a frequency determined by the module clock divided by the baud rate.
Transmit data. Serial data output from transmitter.
Whether TxD is interpreted as a 1 or 0 depends on the bit encoding method along with other configuration settings.
Driven at the beginning or within a bit time according to the bit encoding method along with other configuration settings.
Otherwise, transmissions are independent of reception timing.
40.3 Register definition
The UART has 8-bit registers to control baud rate, select UART options, report UART status, select DMA options, and for transmit/receive data.
Refer to the direct-page register summary in the memory chapter of this document or the absolute address assignments for all UART registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses.
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Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
UART memory map
Absolute address
(hex)
Register name
4006_B000 UART Baud Rate Register: High (UART1_BDH)
4006_B001 UART Baud Rate Register: Low (UART1_BDL)
4006_B002 UART Control Register 1 (UART1_C1)
4006_B003 UART Control Register 2 (UART1_C2)
4006_B004 UART Status Register 1 (UART1_S1)
4006_B005 UART Status Register 2 (UART1_S2)
4006_B006 UART Control Register 3 (UART1_C3)
4006_B007 UART Data Register (UART1_D)
4006_B008 UART Control Register 4 (UART1_C4)
4006_C000 UART Baud Rate Register: High (UART2_BDH)
4006_C001 UART Baud Rate Register: Low (UART2_BDL)
4006_C002 UART Control Register 1 (UART2_C1)
4006_C003 UART Control Register 2 (UART2_C2)
4006_C004 UART Status Register 1 (UART2_S1)
4006_C005 UART Status Register 2 (UART2_S2)
4006_C006 UART Control Register 3 (UART2_C3)
4006_C007 UART Data Register (UART2_D)
4006_C008 UART Control Register 4 (UART2_C4)
Width
(in bits)
Access Reset value
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
04h
00h
00h
C0h
00h
00h
00h
00h
00h
00h
00h
00h
00h
04h
00h
00h
C0h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
Section/ page
40.3.1 UART Baud Rate Register: High (UARTx_BDH)
This register, along with UART_BDL, controls the prescale divisor for UART baud rate generation. To update the 13-bit baud rate setting SBR[12:0], first write to UART_BDH to buffer the high half of the new value and then write to UART_BDL. The working value in UART_BDH does not change until UART_BDL is written.
Address: Base address + h offset
Bit
Read
Write
Reset
7
0
6
0
Field
7
LBKDIE
5
0
4
0
3
0
UARTx_BDH field descriptions
LIN Break Detect Interrupt Enable (for LBKDIF)
Description
Table continues on the next page...
2
0
1
0
0
0
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Register definition
Field
6
RXEDGIE
UARTx_BDH field descriptions (continued)
Description
0 Hardware interrupts from UART_S2[LBKDIF] disabled (use polling).
1 Hardware interrupt requested when UART_S2[LBKDIF] flag is 1.
RxD Input Active Edge Interrupt Enable (for RXEDGIF)
5
SBNS
0 Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling).
1 Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1.
Stop Bit Number Select
SBNS determines whether data characters are one or two stop bits.
4–0
SBR
0 One stop bit.
1 Two stop bit.
Baud Rate Modulo Divisor.
The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the
UART baud rate generator. When BR is cleared, the UART baud rate generator is disabled to reduce supply current. When BR is 1 - 8191, the UART baud rate equals BUSCLK/(16×BR).
40.3.2 UART Baud Rate Register: Low (UARTx_BDL)
This register, along with UART_BDH, control the prescale divisor for UART baud rate generation. To update the 13-bit baud rate setting [SBR12:SBR0], first write to
UART_BDH to buffer the high half of the new value and then write to UART_BDL. The working value in UART_BDH does not change until UART_BDL is written.
UART_BDL is reset to a non-zero value, so after reset, the baud rate generator remains disabled until the first time the receiver or transmitter is enabled; that is, 1 is written to
UART_C2[RE] or UART_C2[TE].
Address: Base address + h offset
Bit
Read
Write
Reset
7
0
6
0
Field
7–0
SBR
5
0
4
0
3
0
UARTx_BDL field descriptions
Description
Baud Rate Modulo Divisor
2
1
1
0
0
0
These 13 bits in SBR[12:0] are referred to collectively as BR, which set the modulo divide rate for the
UART baud rate generator. When BR is cleared, the UART baud rate generator is disabled to reduce supply current. When BR is 1 - 8191, the UART baud rate equals BUSCLK/(16×BR).
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Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
40.3.3 UART Control Register 1 (UARTx_C1)
This read/write register controls various optional features of the UART system.
Address: Base address + h offset
Bit
Read
Write
Reset
7
0
6
0
5
0
4
0
3
0
UARTx_C1 field descriptions
Description Field
7
LOOPS
Loop Mode Select
2
0
1
0
Selects between loop mode and normal 2-pin full-duplex modes. When LOOPS is set, the transmitter output is internally connected to the receiver input.
0
0
6
UARTSWAI
5
RSRC
4
M
3
WAKE
2
ILT
0 Normal operation - RxD and TxD use separate pins.
1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input.
(See RSRC bit.) RxD pin is not used by UART.
UART Stops in Wait Mode
0 UART clocks continue to run in Wait mode so the UART can be the source of an interrupt that wakes up the CPU.
1 UART clocks freeze while CPU is in Wait mode.
Receiver Source Select
This field has no meaning or effect unless LOOPS is set to 1. When LOOPS is set, the receiver input is internally connected to the TxD pin and RSRC determines whether this connection is also connected to the transmitter output.
0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the RxD pins.
1 Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input.
9-Bit or 8-Bit Mode Select
This field configures the UART to be operated in 9-bit or 8-bit data mode.
0 Normal - start + 8 data bits (lsb first) + stop.
1 Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop.
Receiver Wakeup Method Select
This field selects the receiver wakeup method.
0 Idle-line wake-up.
1 Address-mark wake-up.
Idle Line Type Select
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Register definition
Field
UARTx_C1 field descriptions (continued)
Description
Setting this field to 1 ensures that the stop bits and logic 1 bits at the end of a character do not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic.
1
PE
0 Idle character bit count starts after start bit.
1 Idle character bit count starts after stop bit.
Parity Enable
Enables hardware parity generation and checking. When parity is enabled, the most significant bit (msb) of the data character, eighth or ninth data bit, is treated as the parity bit.
0
PT
0 No hardware parity generation or checking.
1 Parity enabled.
Parity Type
Provided parity is enabled (PE = 1), this field selects even or odd parity. Odd parity means the total number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of
1s in the data character, including the parity bit, is even.
0 Even parity.
1 Odd parity.
40.3.4 UART Control Register 2 (UARTx_C2)
This register can be read or written at any time.
Address: Base address + h offset
Bit
Read
Write
Reset
7
0
6
0
Field
7
TIE
5
0
4
0
3
0
UARTx_C2 field descriptions
Description
Transmit Interrupt Enable for TDRE
6
TCIE
0 Hardware interrupts from TDRE disabled; use polling.
1 Hardware interrupt requested when TDRE flag is 1.
Transmission Complete Interrupt Enable for TC
5
RIE
0 Hardware interrupts from TC disabled; use polling.
1 Hardware interrupt requested when TC flag is 1.
Receiver Interrupt Enable for RDRF
4
ILIE
0 Hardware interrupts from S1[RDRF] disabled; use polling.
1 Hardware interrupt requested when S1[RDRF] flag is 1.
Idle Line Interrupt Enable for IDLE
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2
0
786
1
0
0
0
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Field
3
TE
2
RE
1
RWU
0
SBK
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
UARTx_C2 field descriptions (continued)
Description
0 Hardware interrupts from S1[IDLE] disabled; use polling.
1 Hardware interrupt requested when S1[IDLE] flag is 1.
Transmitter Enable
TE must be 1 to use the UART transmitter. When TE is set, the UART forces the TxD pin to act as an output for the UART system.
When the UART is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of traffic on the single UART communication line (TxD pin).
TE can also queue an idle character by clearing TE and then setting TE while a transmission is in progress.
When 0 is written to TE, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin.
0 Transmitter off.
1 Transmitter on.
Receiver Enable
When the UART receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If C1[LOOPS] is set, the RxD pin reverts to being a general-purpose I/O pin even if RE is set.
0 Receiver off.
1 Receiver on.
Receiver Wakeup Control
A 1 can be written to this field to place the UART receiver in a standby state where it waits for automatic hardware detection of a selected wake-up condition. The wake-up condition is an idle line between messages, WAKE = 0, idle-line wake-up, or a logic 1 in the most significant data bit in a character, WAKE
= 1, address-mark wake-up. Application software sets RWU and, normally, a selected hardware condition automatically clears RWU.
0 Normal UART receiver operation.
1 UART receiver in standby waiting for wake-up condition.
Send Break
Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional break characters of 10 or 11 or 12, 13 or 14 or 15 if BRK13 = 1, bit times of logic 0 are queued as long as SBK is set. Depending on the timing of the set and clear of SBK relative to the information currently being transmitted, a second break character may be queued before software clears SBK.
0 Normal transmitter operation.
1 Queue break character(s) to be sent.
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Register definition
40.3.5 UART Status Register 1 (UARTx_S1)
This register has eight read-only status flags. Writes have no effect. Special software sequences, which do not involve writing to this register, clear these status flags.
Address: Base address + h offset
Bit 7
Read
6
Write
Reset 1 1
Field
7
TDRE
5
0
4
0
3
0
UARTx_S1 field descriptions
Description
Transmit Data Register Empty Flag
2
0
1
0
0
0
TDRE is set out of reset and when a transmit data value transfers from the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read UART_S1 with TDRE set and then write to the UART data register (UART_D).
6
TC
5
RDRF
4
IDLE
0 Transmit data register (buffer) full.
1 Transmit data register (buffer) empty.
Transmission Complete Flag
TC is set out of reset and when TDRE is set and no data, preamble, or break character is being transmitted.
TC is cleared automatically by reading UART_S1 with TC set and then executing one of the following operations:
• Write to the UART data register (UART_D) to transmit new data
• Queue a preamble by changing TE from 0 to 1
• Queue a break character by writing 1 to UART_C2[SBK]
0 Transmitter active (sending data, a preamble, or a break).
1 Transmitter idle (transmission activity complete).
Receive Data Register Full Flag
RDRF becomes set when a character transfers from the receive shifter into the receive data register
(UART_D). To clear RDRF, read UART_S1 with RDRF set and then read the UART data register
(UART_D).
0 Receive data register empty.
1 Receive data register full.
Idle Line Flag
IDLE is set when the UART receive line becomes idle for a full character time after a period of activity.
When C1[ILT] is cleared, the receiver starts counting idle bit times after the start bit. If the receive character is all 1s, these bit times and the stop bits time count toward the full character time of logic high,
10 or 11 bit times depending on the M control bit, needed for the receiver to detect an idle line. When ILT is set, the receiver doesn't start counting idle bit times until the stop bits. The stop bits and any logic high bit times at the end of the previous character do not count toward the full character time of logic high needed for the receiver to detect an idle line.
Table continues on the next page...
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Field
3
OR
2
NF
1
FE
0
PF
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
UARTx_S1 field descriptions (continued)
Description
To clear IDLE, read UART_S1 with IDLE set and then read the UART data register (UART_D). After IDLE has been cleared, it cannot become set again until after a new character has been received and RDRF has been set. IDLE is set only once even if the receive line remains idle for an extended period.
0 No idle line detected.
1 Idle line was detected.
Receiver Overrun Flag
OR is set when a new serial character is ready to be transferred to the receive data register (buffer), but the previously received character has not been read from UART_D yet. In this case, the new character, and all associated error information, is lost because there is no room to move it into UART_D. To clear
OR, read UART_S1 with OR set and then read the UART data register (UART_D).
0 No overrun.
1 Receive overrun (new UART data lost).
Noise Flag
The advanced sampling technique used in the receiver takes seven samples during the start bit and three samples in each data bit and the stop bits. If any of these samples disagrees with the rest of the samples within any bit time in the frame, the flag NF is set at the same time as RDRF is set for the character. To clear NF, read UART_S1 and then read the UART data register (UART_D).
0 No noise detected.
1 Noise detected in the received character in UART_D.
Framing Error Flag
FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop bits were expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read
UART_S1 with FE set and then read the UART data register (UART_D).
0 No framing error detected. This does not guarantee the framing is correct.
1 Framing error.
Parity Error Flag
PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in the received character does not agree with the expected parity value. To clear PF, read UART_S1 and then read the
UART data register (UART_D).
0 No parity error.
1 Parity error.
40.3.6 UART Status Register 2 (UARTx_S2)
This register contains one read-only status flag.
When using an internal oscillator in a LIN system, it is necessary to raise the break detection threshold one bit time. Under the worst case timing conditions allowed in LIN, it is possible that a 0x00 data character can appear to be 10.26 bit times long at a slave running 14% faster than the master. This would trigger normal break detection circuitry
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Register definition designed to detect a 10-bit break symbol. When the LBKDE bit is set, framing errors are inhibited and the break detection threshold changes from 10 bits to 11 bits, preventing false detection of a 0x00 data character as a LIN break symbol.
Address: Base address + h offset
Bit
Read
7
6
Write
Reset 0 0
Field
7
LBKDIF
5
0
4
0
3
0
UARTx_S2 field descriptions
Description
LIN Break Detect Interrupt Flag
2
0
1
0
LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break character is detected.
LBKDIF is cleared by writing a 1 to it.
0
0
6
RXEDGIF
5
Reserved
4
RXINV
3
RWUID
2
BRK13
0 No LIN break character has been detected.
1 LIN break character has been detected.
RxD Pin Active Edge Interrupt Flag
RXEDGIF is set when an active edge, falling if RXINV = 0, rising if RXINV=1, on the RxD pin occurs.
RXEDGIF is cleared by writing a 1 to it.
0 No active edge on the receive pin has occurred.
1 An active edge on the receive pin has occurred.
This field is reserved.
This read-only field is reserved and always has the value 0.
Receive Data Inversion
Setting this field reverses the polarity of the received data input.
NOTE: Setting RXINV inverts the RxD input for all cases: data bits, start and stop bits, break, and idle.
0 Receive data not inverted.
1 Receive data inverted.
Receive Wake Up Idle Detect
RWUID controls whether the idle character that wakes up the receiver sets S1[IDLE].
0 During receive standby state (RWU = 1), S1[IDLE] does not get set upon detection of an idle character.
1 During receive standby state (RWU = 1), S1[IDLE] gets set upon detection of an idle character.
Break Character Generation Length
BRK13 selects a longer transmitted break character length. Detection of a framing error is not affected by the state of this field.
0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS =
0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).
1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS =
0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1).
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Field
1
LBKDE
0
RAF
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
UARTx_S2 field descriptions (continued)
Description
LIN Break Detection Enable
LBKDE enables the break detection. While LBKDE is set, S1[FE] and S1[RDRF] flags are prevented from setting.
0 Break detection is disabled.
1 Break detection is enabled (Break character is detected at length 11 bit times (if C1[M] = 0,
BDH[SBNS] = 0) or 12 (if C1[M] = 1, BDH[SBNS] = 0 or C1[M] = 0, BDH[SBNS] = 1) or 13 (if C1[M] =
1, BDH[SBNS] = 1)).
Receiver Active Flag
RAF is set when the UART receiver detects the beginning of a valid start bit, and RAF is cleared automatically when the receiver detects an idle line. This status flag can be used to check whether an
UART character is being received before instructing the MCU to go to stop mode.
0 UART receiver idle waiting for a start bit.
1 UART receiver active (RxD input not idle).
40.3.7 UART Control Register 3 (UARTx_C3)
Address: Base address + h offset
Bit
Read
7
6
Write
Reset 0 0
Field
7
R8
5
0
4
0
3
0
UARTx_C3 field descriptions
Description
Ninth Data Bit for Receiver
6
T8
2
0
1
0
0
0
When the UART is configured for 9-bit data (C1[M] = 1), R8 can be thought of as a ninth receive data bit to the left of the msb of the buffered data in the UART_D register. When reading 9-bit data, read R8 before reading UART_D because reading UART_D completes automatic flag clearing sequences that could allow
R8 and UART_D to be overwritten with new data.
Ninth Data Bit for Transmitter
5
TXDIR
When the UART is configured for 9-bit data (C1[M] = 1), T8 may be thought of as a ninth transmit data bit to the left of the msb of the data in the UART_D register. When writing 9-bit data, the entire 9-bit value is transferred to the UART shift register after UART_D is written so T8 should be written, if it needs to change from its previous value, before UART_D is written. If T8 does not need to change in the new value, such as when it is used to generate mark or space parity, it need not be written each time UART_D is written.
TxD Pin Direction in Single-Wire Mode
When the UART is configured for single-wire half-duplex operation (LOOPS = RSRC = 1), this field determines the direction of data at the TxD pin.
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Register definition
Field
4
TXINV
UARTx_C3 field descriptions (continued)
Description
0 TxD pin is an input in single-wire mode.
1 TxD pin is an output in single-wire mode.
Transmit Data Inversion
Setting this field reverses the polarity of the transmitted data output.
NOTE: Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle.
3
ORIE
2
NEIE
1
FEIE
0
PEIE
0 Transmit data not inverted.
1 Transmit data inverted.
Overrun Interrupt Enable
Enables the overrun flag (OR) to generate hardware interrupt requests.
0 OR interrupts disabled; use polling.
1 Hardware interrupt requested when OR is set.
Noise Error Interrupt Enable
Enables the noise flag (NF) to generate hardware interrupt requests.
0 NF interrupts disabled; use polling).
1 Hardware interrupt requested when NF is set.
Framing Error Interrupt Enable
Enables the framing error flag (FE) to generate hardware interrupt requests.
0 FE interrupts disabled; use polling).
1 Hardware interrupt requested when FE is set.
Parity Error Interrupt Enable
Enables the parity error flag (PF) to generate hardware interrupt requests.
0 PF interrupts disabled; use polling).
1 Hardware interrupt requested when PF is set.
40.3.8 UART Data Register (UARTx_D)
This register is actually two separate registers. Reads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also involved in the automatic flag clearing mechanisms for the UART status flags.
Address: Base address + h offset
Bit
Read
Write
Reset
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
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Field
7
R7T7
6
R6T6
5
R5T5
4
R4T4
3
R3T3
2
R2T2
1
R1T1
0
R0T0
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
UARTx_D field descriptions
Description
Read receive data buffer 7 or write transmit data buffer 7.
Read receive data buffer 6 or write transmit data buffer 6.
Read receive data buffer 5 or write transmit data buffer 5.
Read receive data buffer 4 or write transmit data buffer 4.
Read receive data buffer 3 or write transmit data buffer 3.
Read receive data buffer 2 or write transmit data buffer 2.
Read receive data buffer 1 or write transmit data buffer 1.
Read receive data buffer 0 or write transmit data buffer 0.
40.3.9 UART Control Register 4 (UARTx_C4)
Address: Base address + h offset
Bit
Read
Write
Reset
7
0
6
0
Field
7
TDMAS
5
0
4
0
3
0
Transmitter DMA Select
UARTx_C4 field descriptions
Description
2
0
1
0
0
0
TDMAS configures the transmit data register empty flag, TDRE, to generate interrupt or DMA requests if
TIE is set.
NOTE: If UART_C2[TIE] is cleared, TDRE DMA and TDRE interrupt request signals are not asserted when the TDRE flag is set, regardless of the state of TDMAS.
If UART_C2[TIE] and TDMAS are both set, then UART_C2[TCIE] must be cleared, and UART_D must not be written outside of servicing of a DMA request.
6
Reserved
5
RDMAS
0 If TIE is set and the TDRE flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
1 If TIE is set and the TDRE flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
This field is reserved.
This read-only field is reserved and always has the value 0.
Receiver Full DMA Select
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Functional description
Field
UARTx_C4 field descriptions (continued)
Description
RDMAS configures the receiver data register full flag, RDRF, to generate interrupt or DMA requests if RIE is set.
NOTE: If RIE is cleared, the RDRF DMA and RDRF interrupt request signals are not asserted when the
RDRF flag is set, regardless of the state of RDMAS.
4
Reserved
3
Reserved
2–0
Reserved
0 If RIE is set and the RDRF flag is set, the RDRF interrupt request signal is asserted to request interrupt service.
1 If RIE is set and the RDRF flag is set, the RDRF DMA request signal is asserted to request a DMA transfer.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
40.4 Functional description
The UART allows full-duplex, asynchronous, NRZ serial communication among the
MCU and remote devices, including other MCUs.
The UART comprises a baud rate generator, transmitter, and receiver block. The transmitter and receiver operate independently, although they use the same baud rate generator. During normal operation, the MCU monitors the status of the UART, writes the data to be transmitted, and processes received data. The following describes each of the blocks of the UART.
40.4.1 Baud rate generation
As shown in the figure found here, the clock source for the UART baud rate generator is the bus-rate clock.
Modulo Divide By
(1 through 8191)
UART Module Clock SBR[12:0]
Baud Rate Generator
Off If [SBR12:SBR0] = 0
Divide By
16
Tx Baud Rate
Rx Sampling Clock
(16 × Baud Rate)
Baud Rate =
UART Module Clock
SBR[12:0] × 16
Figure 40-30. UART baud rate generation
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Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
UART communications require the transmitter and receiver, which typically derive baud rates from independent clock sources, to use the same baud rate. Allowed tolerance on this baud frequency depends on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is performed.
The MCU resynchronizes to bit boundaries on every high-to-low transition. In the worst case, there are no such transitions in the full 10- or 11-bit or 12-bittime character frame so any mismatch in baud rate is accumulated for the whole character time. For a
Freescale UART system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about ±4.5 percent for 8-bit data format and about ±4 percent for 9-bit data format. Although baud rate modulo divider settings do not always produce baud rates that exactly match standard rates, it is normally possible to get within a few percent, which is acceptable for reliable communications.
40.4.2 Transmitter functional description
This section describes the overall block diagram for the UART transmitter, as well as specialized functions for sending break and idle characters.
The transmitter output (TxD) idle state defaults to logic high, UART_C3[TXINV] is cleared following reset. The transmitter output is inverted by setting UART_C3[TXINV].
The transmitter is enabled by setting the TE bit in UART_C2. This queues a preamble character that is one full character frame of the idle state. The transmitter then remains idle until data is available in the transmit data buffer. Programs store data into the transmit data buffer by writing to the UART data register (UART_D).
The central element of the UART transmitter is the transmit shift register that is 10 or 11 or 12 bits long depending on the setting in the UART_C1[M] control bit and
UART_BDH[SBNS] bit. For the remainder of this section, assume UART_C1[M] is cleared, UART_BDH[SBNS] is also cleared, selecting the normal 8-bit data mode. In 8bit data mode, the shift register holds a start bit, eight data bits, and a stop bit. When the transmit shift register is available for a new UART character, the value waiting in the transmit data register is transferred to the shift register, synchronized with the baud rate clock, and the transmit data register empty (UART_S1[TDRE]) status flag is set to indicate another character may be written to the transmit data buffer at UART_D.
NOTE
Always read UART_S1 before writing to UART_D to allow data to be transmitted.
If no new character is waiting in the transmit data buffer after a stop bit is shifted out the
TxD pin, the transmitter sets the transmit complete flag and enters an idle mode, with
TxD high, waiting for more characters to transmit.
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Functional description
Writing 0 to UART_C2[TE] does not immediately release the pin to be a general-purpose
I/O pin. Any transmit activity in progress must first be completed. This includes data characters in progress, queued idle characters, and queued break characters.
40.4.2.1 Send break and queued idle
UART_C2[SBK] sends break characters originally used to gain the attention of old teletype receivers. Break characters are a full character time of logic 0, 10 bit times including the start and stop bits. A longer break of 13 bit times can be enabled by setting
UART_S2[BRK13]. Normally, a program would wait for UART_S1[TDRE] to become set to indicate the last character of a message has moved to the transmit shifter, write 1, and then write 0 to UART_C2[SBK]. This action queues a break character to be sent as soon as the shifter is available. If UART_C2[SBK] remains 1 when the queued break moves into the shifter, synchronized to the baud rate clock, an additional break character is queued. If the receiving device is another Freescale Semiconductor UART, the break characters are received as 0s in all eight data bits and a framing error (UART_S1[FE] =
1) occurs.
When idle-line wake-up is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping receivers. Normally, a program would wait for
UART_S1[TDRE] to become set to indicate the last character of a message has moved to the transmit shifter, then write 0 and then write 1 to the UART_C2[TE] bit. This action queues an idle character to be sent as soon as the shifter is available. As long as the character in the shifter does not finish while UART_C2[TE] is cleared, the UART transmitter never actually releases control of the TxD pin. If there is a possibility of the shifter finishing while UART_C2[TE] is cleared, set the general-purpose I/O controls so the pin shared with TxD is an output driving a logic 1. This ensures that the TxD line looks like a normal idle line even if the UART loses control of the port pin between writing 0 and then 1 to UART_C2[TE].
The length of the break character is affected by the UART_S2[BRK13] and
UART_C1[M] as shown below.
BRK13
0
0
1
0
0
1
Table 40-33. Break character length
1
0
0
1
0
M
0
Table continues on the next page...
SBNS
0
1
0
1
0
1
Break character length
10 bit times
11 bit times
11 bit times
12 bit times
13 bit times
14 bit times
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BRK13
1
1
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
Table 40-33. Break character length (continued)
M
1
1
SBNS
0
1
Break character length
14 bit times
15 bit times
40.4.3 Receiver functional description
In this section, the receiver block diagram is a guide for the overall receiver functional description.
Next, the data sampling technique used to reconstruct receiver data is described in more detail. Finally, two variations of the receiver wakeup function are explained.
The receiver input is inverted by setting UART_S2[RXINV]. The receiver is enabled by setting the UART_C2[RE] bit. Character frames consist of a start bit of logic 0, eight (or nine) data bits (lsb first), and one (or two) stop bits of logic 1. For information about 9-bit data mode, refer to
. For the remainder of this discussion, assume the UART is configured for normal 8-bit data mode.
After receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred to the receive data register and the receive data register full (UART_S1[RDRF]) status flag is set. If UART_S1[RDRF] was already set indicating the receive data register (buffer) was already full, the overrun (OR) status flag is set and the new data is lost. Because the UART receiver is double-buffered, the program has one full character time after UART_S1[RDRF] is set before the data in the receive data buffer must be read to avoid a receiver overrun.
When a program detects that the receive data register is full (UART_S1[RDRF] = 1), it gets the data from the receive data register by reading UART_D. The UART_S1[RDRF] flag is cleared automatically by a two-step sequence normally satisfied in the course of the user's program that manages receive data. Refer to
for more details about flag clearing.
40.4.3.1 Data sampling technique
The UART receiver uses a 16× baud rate clock for sampling. The oversampling ratio is fixed at 16. The receiver starts by taking logic level samples at 16 times the baud rate to search for a falling edge on the RxD serial data input pin. A falling edge is defined as a logic 0 sample after three consecutive logic 1 samples. The 16× baud rate clock divides the bit time into 16 segments labeled UART_D[RT1] through UART_D[RT16]. When a
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Functional description falling edge is located, three more samples are taken at UART_D[RT3], UART_D[RT5], and UART_D[RT7] to make sure this was a real start bit and not merely noise. If at least two of these three samples are 0, the receiver assumes it is synchronized to a receive character.
The receiver then samples each bit time, including the start and stop bits, at
UART_D[RT8], UART_D[RT9], and UART_D[RT10] to determine the logic level for that bit. The logic level is interpreted to be that of the majority of the samples taken during the bit time. In the case of the start bit, the bit is assumed to be 0 if at least two of the samples at UART_D[RT3], UART_D[RT5], and UART_D[RT7] are 0 even if one or all of the samples taken at UART_D[RT8], UART_D[RT9], and UART_D[RT10] are 1s.
If any sample in any bit time, including the start and stop bits, in a character frame fails to agree with the logic level for that bit, the noise flag (UART_S1[NF]) is set when the received character is transferred to the receive data buffer.
The falling edge detection logic continuously looks for falling edges. If an edge is detected, the sample clock is resynchronized to bit times. This improves the reliability of the receiver in the presence of noise or mismatched baud rates. It does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame.
In the case of a framing error, provided the received character was not a break character, the sampling logic that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately.
In the case of a framing error, the receiver is inhibited from receiving any new characters until the framing error flag is cleared. The receive shift register continues to function, but a complete character cannot transfer to the receive data buffer if UART_S1[FE] remains set.
40.4.3.2 Receiver wake-up operation
Receiver wake-up is a hardware mechanism that allows an UART receiver to ignore the characters in a message intended for a different UART receiver. In such a system, all receivers evaluate the first character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up control field (UART_C2[RWU]). When UART_C2[RWU] is set, the status flags associated with the receiver, (with the exception of the idle bit, IDLE, when
UART_S2[RWUID] is set), are inhibited from setting, thus eliminating the software overhead for handling the unimportant message characters. At the end of a message, or at the beginning of the next message, all receivers automatically force UART_C2[RWU] to
0, so all receivers wake up in time to look at the first character(s) of the next message.
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40.4.3.2.1 Idle-line wakeup
When wake is cleared, the receiver is configured for idle-line wakeup. In this mode,
UART_C2[RWU] is cleared automatically when the receiver detects a full character time of the idle-line level. The UART_C1[M] control field selects 8-bit or 9-bit data mode and
UART_BDH[SBNS] selects 1-bit or 2-bit stop bit number that determines how many bit times of idle are needed to constitute a full character time, 10 or 11 or 12 bit times because of the start and stop bits.
When UARTI_C2[RWU] is 1 and UART_S2[RWUID] is 0, the idle condition that wakes up the receiver does not set UART_S1[IDLE]. The receiver wakes up and waits for the first data character of the next message that sets UART_S1[RDRF] and generates an interrupt, if enabled. When UART_S2[RWUID] is 1, any idle condition sets
UART_S1[IDLE] flag and generates an interrupt if enabled, regardless of whether
UART_C2[RWU] is 0 or 1.
The idle-line type (UART_C1[ILT]) control bit selects one of two ways to detect an idle line. When UART_C1[ILT] is cleared, the idle bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward the full character time of idle. When UART_C1[ILT] is set, the idle bit counter does not start until after a stop bit time, so the idle detection is not affected by the data in the last character of the previous message.
40.4.3.2.2 Address-mark wakeup
When wake is set, the receiver is configured for address-mark wakeup. In this mode,
UART_C2[RWU] is cleared automatically when the receiver detects a, or two, if
UART_BDH[SBNS] = 1, logic 1 in the most significant bits of a received character, eighth bit when UART_C1[M] is cleared and ninth bit when UART_C1[M] is set.
Address-mark wakeup allows messages to contain idle characters, but requires the msb be reserved for use in address frames. The one, or two, if UART_BDH[SBNS] = 1, logic
1s msb of an address frame clears the UART_C2[RWU] bit before the stop bits are received and sets the UART_S1[RDRF] flag. In this case, the character with the msb set is received even though the receiver was sleeping during most of this character time.
40.4.4 Interrupts and status flags
The UART system has three separate interrupt vectors to reduce the amount of software needed to isolate the cause of the interrupt.
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Functional description
One interrupt vector is associated with the transmitter for UART_S1[TDRE] and
UART_S1[TC] events. Another interrupt vector is associated with the receiver for
RDRF, IDLE, RXEDGIF, and LBKDIF events. A third vector is used for OR, NF, FE, and PF error conditions. Each of these ten interrupt sources can be separately masked by local interrupt enable masks. The flags can be polled by software when the local masks are cleared to disable generation of hardware interrupt requests.
The UART transmitter has two status flags that can optionally generate hardware interrupt requests. Transmit data register empty (UART_S1[TDRE]) indicates when there is room in the transmit data buffer to write another transmit character to UART_D. If the transmit interrupt enable (UART_C2[TIE]) bit is set, a hardware interrupt is requested when UART_S1[TDRE] is set. Transmit complete (UART_S1[TC]) indicates that the transmitter is finished transmitting all data, preamble, and break characters and is idle with TxD at the inactive level. This flag is often used in systems with modems to determine when it is safe to turn off the modem. If the transmit complete interrupt enable
(UART_C2[TCIE]) bit is set, a hardware interrupt is requested when UART_S1[TC] is set. Instead of hardware interrupts, software polling may be used to monitor the
UART_S1[TDRE] and UART_S1[TC] status flags if the corresponding UART_C2[TIE] or UART_C2[TCIE] local interrupt masks are cleared.
When a program detects that the receive data register is full (UART_S1[RDRF] = 1), it gets the data from the receive data register by reading UART_D. The UART_S1[RDRF] flag is cleared by reading UART_S1 while UART_S1[RDRF] is set and then reading
UART_D.
When polling is used, this sequence is naturally satisfied in the normal course of the user program. If hardware interrupts are used, UART_S1 must be read in the interrupt service routine (ISR). Normally, this is done in the ISR anyway to check for receive errors, so the sequence is automatically satisfied.
The IDLE status flag includes logic that prevents it from getting set repeatedly when the
RxD line remains idle for an extended period of time. IDLE is cleared by reading
UART_S1 while UART_S1[IDLE] is set and then reading UART_D. After
UART_S1[IDLE] has been cleared, it cannot become set again until the receiver has received at least one new character and has set UART_S1[RDRF].
If the associated error was detected in the received character that caused
UART_S1[RDRF] to be set, the error flags - noise flag (UART_S1[NF]), framing error
(UART_S1[FE]), and parity error flag (UART_S1[PF]) - are set at the same time as
UART_S1[RDRF]. These flags are not set in overrun cases.
If UART_S1[RDRF] was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer, the overrun (UART_S1[OR]) flag is set instead of the data along with any associated NF, FE, or PF condition is lost.
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Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
At any time, an active edge on the RxD serial data input pin causes the
UART_S2[RXEDGIF] flag to set. The UART_S2[RXEDGIF] flag is cleared by writing a
1 to it. This function depends on the receiver being enabled (UART_C2[RE] = 1).
40.4.5 Baud rate tolerance
A transmitting device may operate at a baud rate below or above that of the receiver.
Accumulated bit time misalignment can cause one of the three stop bit data samples
(RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the
RT8, RT9, and RT10 samples are not all the same logical values. A framing error will occur if the receiver clock is misaligned in such a way that the majority of the RT8, RT9, and RT10 stop bit samples are a logic zero.
As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge within the frame. Resynchronization within frames will correct a misalignment between transmitter bit times and receiver bit times.
40.4.5.1 Slow data tolerance
shows how much a slow received frame can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10.
MSB STOP
RECEIVER
RT CLOCK
DATA
SAMPLES
Figure 40-31. Slow data
For an 8-bit data and 1 stop bit character, data sampling of the stop bit takes the receiver
9 bit times x 16 RT cycles +10 RT cycles =154 RT cycles.
With the misaligned character shown in Figure 40-31 , the receiver counts 154 RT cycles
at the point when the count of the transmitting device is 9 bit times x 16 RT cycles + 3
RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data and 1 stop bit character with no errors is:
((154 - 147) / 154) x 100 = 4.54%
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Functional description
For a 9-bit data or 2 stop bits character, data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 40-31 , the receiver counts 170 RT cycles
at the point when the count of the transmitting device is 10 bit times x 16 RT cycles + 3
RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit or 2 stop bits character with no errors is:
((170 - 163) / 170) X 100 = 4.12%
For a 9-bit data and 2 stop bit character, data sampling of the stop bit takes the receiver
11 bit times x 16 RT cycles + 10 RT cycles = 186 RT cycles.
With the misaligned character shown in Figure 40-31 , the receiver counts 186 RT cycles
at the point when the count of the transmitting device is 11 bit times x 16 RT cycles + 3
RT cycles = 179 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit and 2 stop bits character with no errors is: ((186 - 179) / 186) X 100 = 3.76%
40.4.5.2 Fast data tolerance
hows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10.
STOP IDLE OR NEXT FRAME
RECEIVER
RT CLOCK
DATA
SAMPLES
Figure 40-32. Fast data
For an 8-bit data and 1 stop bit character, data sampling of the stop bit takes the receiver
9 bit times x 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 40-32 , the receiver counts 154 RT cycles
at the point when the count of the transmitting device is 10 bit times x 16 RT cycles =
160 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit and 1 stop bit character with no errors is:
((154 - 160) / 154) x 100 = 3.90%
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Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
For a 9-bit data or 2 stop bits character, data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times x 16 RT cycles = 176 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit or 2 stop bits character with no errors is:
((170 - 176) / 170) x 100 = 3.53%
For a 9-bit data and 2 stop bits character, data sampling of the stop bit takes the receiver
11 bit times x 16 RT cycles + 10 RT cycles = 186 RT cycles.
With the misaligned character shown in, the receiver counts 186 RT cycles at the point when the count of the transmitting device is 12 bit times x 16 RT cycles = 192 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit and 2 stop bits character with no errors is:
((186 - 192) / 186) x 100 = 3.23%
40.4.6 DMA Operation
In the transmitter, flags TDRE and TC can be configured to assert a DMA transfer request. In the receiver, flags RDRF, IDLE and LBKDIF can be configured to assert a
DMA transfer request.
The table found here shows the configuration bit settings required to configure each flag for DMA operation.
Table 40-34. DMA configuration
Flag
TDRE
TC
RDRF
IDLE
LBKDIF
Request enable bit
TIE = 1
TCIE = 1
RIE = 1
ILIE = 1
LBKDIE = 1
DMA select bit
TDMAS = 1
TCDMAS = 1
RDMAS = 1
ILDMAS = 1
LBKDDMAS = 1
When a flag is configured for a DMA request, its associated DMA request is asserted when the flag is set. When the RDRF or IDLE flag is configured as a DMA request, the clearing mechanism of reading UART_S1 followed by reading UART_D does not clear the associated flag.The DMA request remains asserted until an indication is received that
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Functional description the DMA transactions are done. When this indication is received, the flag bit and the associated DMA request are cleared. If the DMA operation failed to remove the situation that caused the DMA request another request will be issued.
40.4.7 Additional UART functions
The following sections describe additional UART functions.
40.4.7.1 8- and 9-bit data modes
The UART system, transmitter and receiver, can be configured to operate in 9-bit data mode by setting UART_C1[M]. In 9-bit mode, there is a ninth data bit to the left of the most significant bit of the UART data register. For the transmit data buffer, this bit is stored in T8 in UART_C3. For the receiver, the ninth bit is held in UART_C3[R8].
For coherent writes to the transmit data buffer, write to UART_C3[T8] before writing to
UART_D.
If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character, it is not necessary to write to UART_C3[T8] again. When data is transferred from the transmit data buffer to the transmit shifter, the value in
UART_C3[T8] is copied at the same time data is transferred from UART_D to the shifter.
The 9-bit data mode is typically used with parity to allow eight bits of data plus the parity in the ninth bit, or it is used with address-mark wake-up so the ninth data bit can serve as the wakeup bit. In custom protocols, the ninth bit can also serve as a software-controlled marker.
40.4.7.2 Stop mode operation
During all stop modes, clocks to the UART module are halted.
No UART module registers are affected in Stop3 mode.
The receive input active edge detect circuit remains active in Stop3 mode. An active edge on the receive input brings the CPU out of stop and VLPS mode if the interrupt is not masked (UART_BDH[RXEDGIE] = 1).
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Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
Because the clocks are halted, the UART module resumes operation upon exit from stop, only in stop and VLPS mode. Software must ensure stop mode is not entered while there is a character (including preamble, break and normal data) being transmitted out of or received into the UART module, that means UART_S1[TC] =1, UART_S1[TDRE] = 1, and UART_S2[RAF] = 0 must all meet before entering stop mode.
40.4.7.3 Loop mode
When UART_C1[LOOPS] is set, the UART_C1[RSRC] bit in the same register chooses between loop mode (UART_C1[RSRC] = 0) or single-wire mode (UART_C1[RSRC] =
1). Loop mode is sometimes used to check software, independent of connections in the external system, to help isolate system problems. In this mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter.
40.4.7.4 Single-wire operation
When UART_C1[LOOPS] is set, UART_C1[RSRC] chooses between loop mode
(UART_C1[RSRC] = 0) or single-wire mode (UART_C1[RSRC] = 1). Single-wire mode implements a half-duplex serial connection. The receiver is internally connected to the transmitter output and to the TxD pin. The RxD pin is not used and reverts to a generalpurpose port I/O pin.
In single-wire mode, the UART_C3[TXDIR] bit controls the direction of serial data on the TxD pin. When UART_C3[TXDIR] is cleared, the TxD pin is an input to the UART receiver and the transmitter is temporarily disconnected from the TxD pin so an external device can send serial data to the receiver. When UART_C3[TXDIR] is set, the TxD pin is an output driven by the transmitter. In single-wire mode, the transmitter output is internally connected to the receiver input and the RxD pin is not used by the UART, so it reverts to a general-purpose port I/O pin.
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Functional description
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Chapter 41
Integrated Interchip Sound (I2S) / Synchronous
Audio Interface (SAI)
41.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
The I 2 S (or I2S) module provides a synchronous audio interface (SAI) that supports fullduplex serial interfaces with frame synchronization such as I 2 S, AC97, TDM, and codec/
DSP interfaces.
41.1.1 Features
• Transmitter with independent bit clock and frame sync supporting 1 data channel
• Receiver with independent bit clock and frame sync supporting 1 data channel
• Maximum Frame Size of 2 words
• Word size of between 8-bits and 32-bits
• Word size configured separately for first word and remaining words in frame
• Asynchronous 1 × 32-bit FIFO for each transmit and receive channel
• Supports graceful restart after FIFO error
41.1.2 Block diagram
The following block diagram also shows the module clocks.
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Introduction
Figure 41-1. I 2 S/SAI block diagram
41.1.3 Modes of operation
The module operates in these MCU power modes: Run mode, stop modes, low-leakage modes, and Debug mode.
41.1.3.1 Run mode
In Run mode, the SAI transmitter and receiver operate normally.
41.1.3.2 Stop modes
In Stop mode, the SAI transmitter and/or receiver can continue operating provided the appropriate Stop Enable bit is set (TCSR[STOPE] and/or RCSR[STOPE], respectively), and provided the transmitter and/or receiver is/are using an externally generated bit clock or an Audio Master Clock that remains operating in Stop mode. The SAI transmitter and/ or receiver can generate an asynchronous interrupt to wake the CPU from Stop mode.
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Chapter 41 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
In Stop mode, if the Transmitter Stop Enable (TCSR[STOPE]) bit is clear, the transmitter is disabled after completing the current transmit frame, and, if the Receiver Stop Enable
(RCSR[STOPE]) bit is clear, the receiver is disabled after completing the current receive frame. Entry into Stop mode is prevented–not acknowledged–while waiting for the transmitter and receiver to be disabled at the end of the current frame.
41.1.3.3 Low-leakage modes
When entering low-leakage modes, the Stop Enable (TCSR[STOPE] and
RCSR[STOPE]) bits are ignored and the SAI is disabled after completing the current transmit and receive Frames. Entry into stop mode is prevented (not acknowledged) while waiting for the transmitter and receiver to be disabled at the end of the current frame.
41.1.3.4 Debug mode
In Debug mode, the SAI transmitter and/or receiver can continue operating provided the
Debug Enable bit is set. When TCSR[DBGE] or RCSR[DBGE] bit is clear and Debug mode is entered, the SAI is disabled after completing the current transmit or receive frame. The transmitter and receiver bit clocks are not affected by Debug mode.
41.2 External signals
SAI_TX_BCLK
SAI_TX_SYNC
Name
SAI_TX_DATA
SAI_RX_BCLK
SAI_RX_SYNC
SAI_RX_DATA
SAI_MCLK
Function
Transmit Bit Clock
Transmit Frame Sync
Transmit Data
Receive Bit Clock
Receive Frame Sync
Receive Data
Audio Master Clock
I/O
I/O
O
I/O
I
I/O
I/O
I/O
0
0
0
0
0
0
0
Reset
—
—
—
—
—
—
—
Pull
41.3 Memory map and register definition
A read or write access to an address after the last register will result in a bus error.
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Memory map and register definition
I2S memory map
Absolute address
(hex)
Register name
4002_F000 SAI Transmit Control Register (I2S0_TCSR)
4002_F008 SAI Transmit Configuration 2 Register (I2S0_TCR2)
4002_F00C SAI Transmit Configuration 3 Register (I2S0_TCR3)
4002_F010 SAI Transmit Configuration 4 Register (I2S0_TCR4)
4002_F014 SAI Transmit Configuration 5 Register (I2S0_TCR5)
4002_F020 SAI Transmit Data Register (I2S0_TDR0)
4002_F060 SAI Transmit Mask Register (I2S0_TMR)
4002_F080 SAI Receive Control Register (I2S0_RCSR)
4002_F088 SAI Receive Configuration 2 Register (I2S0_RCR2)
4002_F08C SAI Receive Configuration 3 Register (I2S0_RCR3)
4002_F090 SAI Receive Configuration 4 Register (I2S0_RCR4)
4002_F094 SAI Receive Configuration 5 Register (I2S0_RCR5)
4002_F0A0 SAI Receive Data Register (I2S0_RDR0)
4002_F0E0 SAI Receive Mask Register (I2S0_RMR)
4002_F100 SAI MCLK Control Register (I2S0_MCR)
4002_F104 SAI MCLK Divide Register (I2S0_MDR)
Width
(in bits)
Access Reset value
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
R/W
R/W
R/W
R/W
R/W
W
(always reads 0)
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
0000_0000h
0000_0000h
0000_0000h
Section/ page
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
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Chapter 41 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
41.3.1 SAI Transmit Control Register (I2Sx_TCSR)
Address: 4002_F000h base + 0h offset = 4002_F000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
R
0
9
0
8
W
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Reset 0
Field
31
TE
30
STOPE
29
DBGE
0 0 0 0 0 0 0 0 0
I2Sx_TCSR field descriptions
Description
0 0 0 0 0 0
Transmitter Enable
Enables/disables the transmitter. When software clears this field, the transmitter remains enabled, and this bit remains set, until the end of the current frame.
0 Transmitter is disabled.
1 Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
Stop Enable
Configures transmitter operation in Stop mode. This field is ignored and the transmitter is disabled in all low-leakage stop modes.
0 Transmitter disabled in Stop mode.
1 Transmitter enabled in Stop mode.
Debug Enable
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I2Sx_TCSR field descriptions (continued)
Field Description
Enables/disables transmitter operation in Debug mode. The transmit bit clock is not affected by debug mode.
28
BCE
27–26
Reserved
25
FR
24
SR
23–21
Reserved
20
WSF
19
SEF
18
FEF
0 Transmitter is disabled in Debug mode, after completing the current frame.
1 Transmitter is enabled in Debug mode.
Bit Clock Enable
Enables the transmit bit clock, separately from the TE. This field is automatically set whenever TE is set.
When software clears this field, the transmit bit clock remains enabled, and this bit remains set, until the end of the current frame.
0 Transmit bit clock is disabled.
1 Transmit bit clock is enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
FIFO Reset
Resets the FIFO pointers. Reading this field will always return zero. FIFO pointers should only be reset when the transmitter is disabled or the FIFO error flag is set.
0 No effect.
1 FIFO reset.
Software Reset
When set, resets the internal transmitter logic including the FIFO pointers. Software-visible registers are not affected, except for the status registers.
0 No effect.
1 Software reset.
This field is reserved.
This read-only field is reserved and always has the value 0.
Word Start Flag
Indicates that the start of the configured word has been detected. Write a logic 1 to this field to clear this flag.
0 Start of word not detected.
1 Start of word detected.
Sync Error Flag
Indicates that an error in the externally-generated frame sync has been detected. Write a logic 1 to this field to clear this flag.
0 Sync error not detected.
1 Frame sync error detected.
FIFO Error Flag
Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this field to clear this flag.
0 Transmit underrun not detected.
1 Transmit underrun detected.
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Field
17
FWF
16
Reserved
15–13
Reserved
12
WSIE
11
SEIE
10
FEIE
9
FWIE
8
Reserved
7–5
Reserved
4–2
Reserved
1
FWDE
0
Reserved
Chapter 41 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
I2Sx_TCSR field descriptions (continued)
Description
FIFO Warning Flag
Indicates that an enabled transmit FIFO is empty.
0 No enabled transmit FIFO is empty.
1 Enabled transmit FIFO is empty.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
Word Start Interrupt Enable
Enables/disables word start interrupts.
0 Disables interrupt.
1 Enables interrupt.
Sync Error Interrupt Enable
Enables/disables sync error interrupts.
0 Disables interrupt.
1 Enables interrupt.
FIFO Error Interrupt Enable
Enables/disables FIFO error interrupts.
0 Disables the interrupt.
1 Enables the interrupt.
FIFO Warning Interrupt Enable
Enables/disables FIFO warning interrupts.
0 Disables the interrupt.
1 Enables the interrupt.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
FIFO Warning DMA Enable
Enables/disables DMA requests.
0 Disables the DMA request.
1 Enables the DMA request.
This field is reserved.
This read-only field is reserved and always has the value 0.
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41.3.2 SAI Transmit Configuration 2 Register (I2Sx_TCR2)
This register must not be altered when TCSR[TE] is set.
Address: 4002_F000h base + 8h offset = 4002_F008h
Bit
R
W
Reset
31
0
30
0
29
0
28
0
27
0
26
0
25 24
0 0
Bit
R
W
Reset
15
0
Field
31–30
SYNC
29
BCS
28
BCI
14 13 12 11 10 9 8
23
0
7
22
0
6
21
0
5
20
0
4
19
0
3
18
0
2
17
0
1
16
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_TCR2 field descriptions
Description
Synchronous Mode
Configures between asynchronous and synchronous modes of operation. When configured for a synchronous mode of operation, the receiver must be configured for asynchronous operation.
0 0
00 Asynchronous mode.
01 Synchronous with receiver.
10 Synchronous with another SAI transmitter.
11 Synchronous with another SAI receiver.
Bit Clock Swap
This field swaps the bit clock used by the transmitter. When the transmitter is configured in asynchronous mode and this bit is set, the transmitter is clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and receiver to share the same bit clock, but the transmitter continues to use the transmit frame sync (SAI_TX_SYNC).
When the transmitter is configured in synchronous mode, the transmitter BCS field and receiver BCS field must be set to the same value. When both are set, the transmitter and receiver are both clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync (SAI_RX_SYNC).
0 Use the normal bit clock source.
1 Swap the bit clock source.
Bit Clock Input
When this field is set and using an internally generated bit clock in either synchronous or asynchronous mode, the bit clock actually used by the transmitter is delayed by the pad output delay (the transmitter is clocked by the pad input as if the clock was externally generated). This has the effect of decreasing the data input setup time, but increasing the data output valid time.
The slave mode timing from the datasheet should be used for the transmitter when this bit is set. In synchronous mode, this bit allows the transmitter to use the slave mode timing from the datasheet, while the receiver uses the master mode timing. This field has no effect when configured for an externally generated bit clock .
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Field
27–26
MSEL
25
BCP
24
BCD
23–8
Reserved
7–0
DIV
Chapter 41 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
I2Sx_TCR2 field descriptions (continued)
Description
0 No effect.
1 Internal logic is clocked as if bit clock was externally generated.
MCLK Select
Selects the audio Master Clock option used to generate an internally generated bit clock. This field has no effect when configured for an externally generated bit clock.
NOTE: Depending on the device, some Master Clock options might not be available. See the chip configuration details for the availability and chip-specific meaning of each option.
00 Bus Clock selected.
01 Master Clock (MCLK) 1 option selected.
10 Master Clock (MCLK) 2 option selected.
11 Master Clock (MCLK) 3 option selected.
Bit Clock Polarity
Configures the polarity of the bit clock.
0 Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
1 Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
Bit Clock Direction
Configures the direction of the bit clock.
0 Bit clock is generated externally in Slave mode.
1 Bit clock is generated internally in Master mode.
This field is reserved.
This read-only field is reserved and always has the value 0.
Bit Clock Divide
Divides down the audio master clock to generate the bit clock when configured for an internal bit clock.
The division value is (DIV + 1) * 2.
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41.3.3 SAI Transmit Configuration 3 Register (I2Sx_TCR3)
This register must not be altered when TCSR[TE] is set.
Address: 4002_F000h base + Ch offset = 4002_F00Ch
Bit 31 30 29 28 27 26 25
R
24 23 22
W
Reset
Bit
R
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
21
0
5
0
4
20
19
0
3
18
0
2
17
0
1
16
0
0
W
Reset 0
Field
31–24
Reserved
23–17
Reserved
16
TCE
15–1
Reserved
0
WDFL
0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_TCR3 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
Transmit Channel Enable
Enables the corresponding data channel for transmit operation. A channel must be enabled before its
FIFO is accessed.
0
0 Transmit data channel N is disabled.
1 Transmit data channel N is enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
Word Flag Configuration
Configures which word sets the start of word flag. The value written must be one less than the word number. For example, writing 0 configures the first word in the frame. When configured to a value greater than TCR4[FRSZ], then the start of word flag is never set.
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Chapter 41 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
41.3.4 SAI Transmit Configuration 4 Register (I2Sx_TCR4)
This register must not be altered when TCSR[TE] is set.
Address: 4002_F000h base + 10h offset = 4002_F010h
Bit
R
W
Reset
31
0
30
0
29
0
28
0
27
0
26
0
25
0
24
0
Bit
R
W
Reset
15
0
Field
31–29
Reserved
28
Reserved
27–26
Reserved
25–24
Reserved
23–17
Reserved
16
FRSZ
15–13
Reserved
12–8
SYWD
7–5
Reserved
4
MF
14
0
13 12 11 10
0
9 8
23
0
7
22
0
6
0 0 0 0 0 0 0
I2Sx_TCR4 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
Frame size
21
0
5
0
20
0
19
0
4 3
0 0
18
0
2
0
17
0
16
0
1 0
0 0
Configures the number of words in each frame. The value written must be one less than the number of words in the frame. For example, write 0 for one word per frame. The maximum supported frame size is 2 words.
This field is reserved.
This read-only field is reserved and always has the value 0.
Sync Width
Configures the length of the frame sync in number of bit clocks. The value written must be one less than the number of bit clocks. For example, write 0 for the frame sync to assert for one bit clock only. The sync width cannot be configured longer than the first word of the frame.
This field is reserved.
This read-only field is reserved and always has the value 0.
MSB First
Configures whether the LSB or the MSB is transmitted first.
0 LSB is transmitted first.
1 MSB is transmitted first.
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Memory map and register definition
I2Sx_TCR4 field descriptions (continued)
Field
3
FSE
Frame Sync Early
Description
2
Reserved
1
FSP
0 Frame sync asserts with the first bit of the frame.
1 Frame sync asserts one bit before the first bit of the frame.
This field is reserved.
This read-only field is reserved and always has the value 0.
Frame Sync Polarity
Configures the polarity of the frame sync.
0
FSD
0 Frame sync is active high.
1 Frame sync is active low.
Frame Sync Direction
Configures the direction of the frame sync.
0 Frame sync is generated externally in Slave mode.
1 Frame sync is generated internally in Master mode.
41.3.5 SAI Transmit Configuration 5 Register (I2Sx_TCR5)
This register must not be altered when TCSR[TE] is set.
Address: 4002_F000h base + 14h offset = 4002_F014h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–29
Reserved
28–24
WNW
I2Sx_TCR5 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Word N Width
23–21
Reserved
20–16
W0W
Configures the number of bits in each word, for each word except the first in the frame. The value written must be one less than the number of bits per word. Word width of less than 8 bits is not supported.
This field is reserved.
This read-only field is reserved and always has the value 0.
Word 0 Width
Configures the number of bits in the first word in each frame. The value written must be one less than the number of bits in the first word. Word width of less than 8 bits is not supported if there is only one word per frame.
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Field
15–13
Reserved
12–8
FBT
7–0
Reserved
Chapter 41 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
I2Sx_TCR5 field descriptions (continued)
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
First Bit Shifted
Configures the bit index for the first bit transmitted for each word in the frame. If configured for MSB First, the index of the next bit transmitted is one less than the current bit transmitted. If configured for LSB First, the index of the next bit transmitted is one more than the current bit transmitted. The value written must be greater than or equal to the word width when configured for MSB First. The value written must be less than or equal to 31-word width when configured for LSB First.
This field is reserved.
This read-only field is reserved and always has the value 0.
41.3.6 SAI Transmit Data Register (I2Sx_TDRn)
Address: 4002_F000h base + 20h offset + (4d × i), where i=0d to 0d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
TDR[31:0]
Transmit Data Register
I2Sx_TDRn field descriptions
Description
The corresponding TCR3[TCE] bit must be set before accessing the channel's transmit data register.
Writes to this register when the transmit FIFO is not full will push the data written into the transmit data
FIFO. Writes to this register when the transmit FIFO is full are ignored.
41.3.7 SAI Transmit Mask Register (I2Sx_TMR)
This register is double-buffered and updates:
1. When TCSR[TE] is first set
2. At the end of each frame.
This allows the masked words in each frame to change from frame to frame.
Address: 4002_F000h base + 60h offset = 4002_F060h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Field
31–2
Reserved
1–0
TWM
I2Sx_TMR field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Transmit Word Mask
Configures whether the transmit word is masked (transmit data pin tristated and transmit data not read from FIFO) for the corresponding word in the frame.
0 Word N is enabled.
1 Word N is masked. The transmit data pins are tri-stated when masked.
41.3.8 SAI Receive Control Register (I2Sx_RCSR)
Address: 4002_F000h base + 80h offset = 4002_F080h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
R
0
9
0
8
W
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Reset 0
820
Field
31
RE
0 0 0 0 0 0 0 0 0
I2Sx_RCSR field descriptions
Description
0 0 0 0 0 0
Receiver Enable
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Field
30
STOPE
29
DBGE
28
BCE
27–26
Reserved
25
FR
24
SR
23–21
Reserved
20
WSF
Chapter 41 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
I2Sx_RCSR field descriptions (continued)
Description
Enables/disables the receiver. When software clears this field, the receiver remains enabled, and this bit remains set, until the end of the current frame.
0 Receiver is disabled.
1 Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
Stop Enable
Configures receiver operation in Stop mode. This bit is ignored and the receiver is disabled in all lowleakage stop modes.
0 Receiver disabled in Stop mode.
1 Receiver enabled in Stop mode.
Debug Enable
Enables/disables receiver operation in Debug mode. The receive bit clock is not affected by Debug mode.
0 Receiver is disabled in Debug mode, after completing the current frame.
1 Receiver is enabled in Debug mode.
Bit Clock Enable
Enables the receive bit clock, separately from RE. This field is automatically set whenever RE is set.
When software clears this field, the receive bit clock remains enabled, and this field remains set, until the end of the current frame.
0 Receive bit clock is disabled.
1 Receive bit clock is enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
FIFO Reset
Resets the FIFO pointers. Reading this field will always return zero. FIFO pointers should only be reset when the receiver is disabled or the FIFO error flag is set.
0 No effect.
1 FIFO reset.
Software Reset
Resets the internal receiver logic including the FIFO pointers. Software-visible registers are not affected, except for the status registers.
0 No effect.
1 Software reset.
This field is reserved.
This read-only field is reserved and always has the value 0.
Word Start Flag
Indicates that the start of the configured word has been detected. Write a logic 1 to this field to clear this flag.
0 Start of word not detected.
1 Start of word detected.
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I2Sx_RCSR field descriptions (continued)
Field
19
SEF
Sync Error Flag
Description
Indicates that an error in the externally-generated frame sync has been detected. Write a logic 1 to this field to clear this flag.
18
FEF
17
FWF
16
Reserved
15–13
Reserved
12
WSIE
11
SEIE
10
FEIE
9
FWIE
8
Reserved
7–5
Reserved
0 Sync error not detected.
1 Frame sync error detected.
FIFO Error Flag
Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to this field to clear this flag.
0 Receive overflow not detected.
1 Receive overflow detected.
FIFO Warning Flag
Indicates that an enabled receive FIFO is full.
0 No enabled receive FIFO is full.
1 Enabled receive FIFO is full.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
Word Start Interrupt Enable
Enables/disables word start interrupts.
0 Disables interrupt.
1 Enables interrupt.
Sync Error Interrupt Enable
Enables/disables sync error interrupts.
0 Disables interrupt.
1 Enables interrupt.
FIFO Error Interrupt Enable
Enables/disables FIFO error interrupts.
0 Disables the interrupt.
1 Enables the interrupt.
FIFO Warning Interrupt Enable
Enables/disables FIFO warning interrupts.
0 Disables the interrupt.
1 Enables the interrupt.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
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Field
4–2
Reserved
1
FWDE
0
Reserved
Chapter 41 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
I2Sx_RCSR field descriptions (continued)
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
FIFO Warning DMA Enable
Enables/disables DMA requests.
0 Disables the DMA request.
1 Enables the DMA request.
This field is reserved.
This read-only field is reserved and always has the value 0.
41.3.9 SAI Receive Configuration 2 Register (I2Sx_RCR2)
This register must not be altered when RCSR[RE] is set.
Address: 4002_F000h base + 88h offset = 4002_F088h
Bit
R
W
Reset
31
0
30
0
29
0
28
0
27
0
26
0
25 24
0 0
Bit
R
W
Reset
15
0
Field
31–30
SYNC
29
BCS
14 13 12 11 10 9 8
23
0
7
22
0
6
21
0
5
20
0
4
19
0
3
18
0
2
17
0
1
0 0 0 0 0 0 0 0 0
I2Sx_RCR2 field descriptions
Description
0 0 0 0
Synchronous Mode
Configures between asynchronous and synchronous modes of operation. When configured for a synchronous mode of operation, the transmitter must be configured for asynchronous operation.
0
16
0
0
0
00 Asynchronous mode.
01 Synchronous with transmitter.
10 Synchronous with another SAI receiver.
11 Synchronous with another SAI transmitter.
Bit Clock Swap
This field swaps the bit clock used by the receiver. When the receiver is configured in asynchronous mode and this bit is set, the receiver is clocked by the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and receiver to share the same bit clock, but the receiver continues to use the receiver frame sync (SAI_RX_SYNC).
When the receiver is configured in synchronous mode, the transmitter BCS field and receiver BCS field must be set to the same value. When both are set, the transmitter and receiver are both clocked by the receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync (SAI_TX_SYNC).
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I2Sx_RCR2 field descriptions (continued)
Field
28
BCI
Description
0 Use the normal bit clock source.
1 Swap the bit clock source.
Bit Clock Input
When this field is set and using an internally generated bit clock in either synchronous or asynchronous mode, the bit clock actually used by the receiver is delayed by the pad output delay (the receiver is clocked by the pad input as if the clock was externally generated). This has the effect of decreasing the data input setup time, but increasing the data output valid time.
The slave mode timing from the datasheet should be used for the receiver when this bit is set. In synchronous mode, this bit allows the receiver to use the slave mode timing from the datasheet, while the transmitter uses the master mode timing. This field has no effect when configured for an externally generated bit clock .
27–26
MSEL
25
BCP
24
BCD
23–8
Reserved
7–0
DIV
0 No effect.
1 Internal logic is clocked as if bit clock was externally generated.
MCLK Select
Selects the audio Master Clock option used to generate an internally generated bit clock. This field has no effect when configured for an externally generated bit clock.
NOTE: Depending on the device, some Master Clock options might not be available. See the chip configuration details for the availability and chip-specific meaning of each option.
00 Bus Clock selected.
01 Master Clock (MCLK) 1 option selected.
10 Master Clock (MCLK) 2 option selected.
11 Master Clock (MCLK) 3 option selected.
Bit Clock Polarity
Configures the polarity of the bit clock.
0 Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
1 Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
Bit Clock Direction
Configures the direction of the bit clock.
0 Bit clock is generated externally in Slave mode.
1 Bit clock is generated internally in Master mode.
This field is reserved.
This read-only field is reserved and always has the value 0.
Bit Clock Divide
Divides down the audio master clock to generate the bit clock when configured for an internal bit clock.
The division value is (DIV + 1) * 2.
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41.3.10 SAI Receive Configuration 3 Register (I2Sx_RCR3)
This register must not be altered when RCSR[RE] is set.
Address: 4002_F000h base + 8Ch offset = 4002_F08Ch
Bit 31 30 29 28 27 26 25
R
24 23 22
W
Reset
Bit
R
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
21
0
5
0
4
20
19
0
3
18
0
2
17
0
1
16
0
0
W
Reset 0
Field
31–24
Reserved
23–17
Reserved
16
RCE
15–1
Reserved
0
WDFL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_RCR3 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
Receive Channel Enable
Enables the corresponding data channel for receive operation. A channel must be enabled before its FIFO is accessed.
0 Receive data channel N is disabled.
1 Receive data channel N is enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
Word Flag Configuration
Configures which word the start of word flag is set. The value written should be one less than the word number (for example, write zero to configure for the first word in the frame). When configured to a value greater than the Frame Size field, then the start of word flag is never set.
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41.3.11 SAI Receive Configuration 4 Register (I2Sx_RCR4)
This register must not be altered when RCSR[RE] is set.
Address: 4002_F000h base + 90h offset = 4002_F090h
Bit
R
W
Reset
31
0
30
0
29
0
28
0
27
0
26
0
25
0
24
0
Bit
R
W
Reset
15
0
Field
31–29
Reserved
28
Reserved
27–26
Reserved
25–24
Reserved
23–17
Reserved
16
FRSZ
15–13
Reserved
12–8
SYWD
7–5
Reserved
4
MF
14
0
13 12 11 10
0
9 8
23
0
7
22
0
6
0 0 0 0 0 0 0
I2Sx_RCR4 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
This field is reserved.
This read-only field is reserved and always has the value 0.
Frame Size
21
0
5
0
20
0
19
0
4 3
0 0
18
0
2
0
17
0
16
0
1 0
0 0
Configures the number of words in each frame. The value written must be one less than the number of words in the frame. For example, write 0 for one word per frame. The maximum supported frame size is 2 words.
This field is reserved.
This read-only field is reserved and always has the value 0.
Sync Width
Configures the length of the frame sync in number of bit clocks. The value written must be one less than the number of bit clocks. For example, write 0 for the frame sync to assert for one bit clock only. The sync width cannot be configured longer than the first word of the frame.
This field is reserved.
This read-only field is reserved and always has the value 0.
MSB First
Configures whether the LSB or the MSB is received first.
0 LSB is received first.
1 MSB is received first.
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Field
3
FSE
2
Reserved
1
FSP
0
FSD
Chapter 41 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
I2Sx_RCR4 field descriptions (continued)
Description
Frame Sync Early
0 Frame sync asserts with the first bit of the frame.
1 Frame sync asserts one bit before the first bit of the frame.
This field is reserved.
This read-only field is reserved and always has the value 0.
Frame Sync Polarity
Configures the polarity of the frame sync.
0 Frame sync is active high.
1 Frame sync is active low.
Frame Sync Direction
Configures the direction of the frame sync.
0 Frame Sync is generated externally in Slave mode.
1 Frame Sync is generated internally in Master mode.
41.3.12 SAI Receive Configuration 5 Register (I2Sx_RCR5)
This register must not be altered when RCSR[RE] is set.
Address: 4002_F000h base + 94h offset = 4002_F094h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–29
Reserved
28–24
WNW
I2Sx_RCR5 field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Word N Width
23–21
Reserved
20–16
W0W
Configures the number of bits in each word, for each word except the first in the frame. The value written must be one less than the number of bits per word. Word width of less than 8 bits is not supported.
This field is reserved.
This read-only field is reserved and always has the value 0.
Word 0 Width
Configures the number of bits in the first word in each frame. The value written must be one less than the number of bits in the first word. Word width of less than 8 bits is not supported if there is only one word per frame.
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I2Sx_RCR5 field descriptions (continued)
Field
15–13
Reserved
12–8
FBT
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
First Bit Shifted
7–0
Reserved
Configures the bit index for the first bit received for each word in the frame. If configured for MSB First, the index of the next bit received is one less than the current bit received. If configured for LSB First, the index of the next bit received is one more than the current bit received. The value written must be greater than or equal to the word width when configured for MSB First. The value written must be less than or equal to 31word width when configured for LSB First.
This field is reserved.
This read-only field is reserved and always has the value 0.
41.3.13 SAI Receive Data Register (I2Sx_RDRn)
Reading this register introduces one additional peripheral clock wait state on each read.
Address: 4002_F000h base + A0h offset + (4d × i), where i=0d to 0d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
RDR[31:0]
Receive Data Register
I2Sx_RDRn field descriptions
Description
The corresponding RCR3[RCE] bit must be set before accessing the channel's receive data register.
Reads from this register when the receive FIFO is not empty will return the data from the top of the receive
FIFO. Reads from this register when the receive FIFO is empty are ignored.
41.3.14 SAI Receive Mask Register (I2Sx_RMR)
This register is double-buffered and updates:
1. When RCSR[RE] is first set
2. At the end of each frame
This allows the masked words in each frame to change from frame to frame.
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Address: 4002_F000h base + E0h offset = 4002_F0E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–2
Reserved
1–0
RWM
I2Sx_RMR field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Receive Word Mask
Configures whether the receive word is masked (received data ignored and not written to receive FIFO) for the corresponding word in the frame.
0 Word N is enabled.
1 Word N is masked.
41.3.15 SAI MCLK Control Register (I2Sx_MCR)
The MCLK Control Register (MCR) controls the clock source and direction of the audio master clock.
Address: 4002_F000h base + 100h offset = 4002_F100h
Bit
R
31
30
29 28
27 26 25
W
Reset 0 0 0 0 0 0 0
24
0
15 14 13 12 11 10 9 8 Bit
R
W
Reset 0
Field
31
DUF
30
MOE
23
0
7
22
0
6
21
0
5
20
0
4
19
0
3
18
0
2
17
0
1
16
0
0
0 0 0
Divider Update Flag
0 0 0 0 0 0
I2Sx_MCR field descriptions
Description
0 0 0 0 0 0
Provides the status of on-the-fly updates to the MCLK divider ratio.
0 MCLK divider ratio is not being updated currently.
1 MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while this flag remains set.
MCLK Output Enable
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I2Sx_MCR field descriptions (continued)
Field Description
Enables the MCLK divider and configures the MCLK signal pin as an output. When software clears this field, it remains set until the MCLK divider is fully disabled.
29–26
Reserved
25–24
MICS
23–0
Reserved
0 MCLK signal pin is configured as an input that bypasses the MCLK divider.
1 MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled.
This field is reserved.
This read-only field is reserved and always has the value 0.
MCLK Input Clock Select
Selects the clock input to the MCLK divider. This field cannot be changed while the MCLK divider is enabled. See the chip configuration details for information about the connections to these inputs.
00 MCLK divider input clock 0 selected.
01 MCLK divider input clock 1 selected.
10 MCLK divider input clock 2 selected.
11 MCLK divider input clock 3 selected.
This field is reserved.
This read-only field is reserved and always has the value 0.
41.3.16 SAI MCLK Divide Register (I2Sx_MDR)
The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the
MDR can be changed when the MCLK divider clock is enabled, additional writes to the
MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK divided clock is disabled do not set MCR[DUF].
Address: 4002_F000h base + 104h offset = 4002_F104h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–20
Reserved
19–12
FRACT
I2Sx_MDR field descriptions
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
MCLK Fraction
11–0
DIVIDE
Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT + 1) / (DIVIDE + 1) ).
FRACT must be set equal or less than the value in the DIVIDE field.
MCLK Divide
Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT + 1) / (DIVIDE + 1) ).
FRACT must be set equal or less than the value in the DIVIDE field.
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41.4 Functional description
This section provides a complete functional description of the block.
41.4.1 SAI clocking
The SAI clocks include:
• The audio master clock
• The bit clock
• The bus clock
41.4.1.1 Audio master clock
The audio master clock is used to generate the bit clock when the receiver or transmitter is configured for an internally generated bit clock. The transmitter and receiver can independently select between the bus clock and up to three audio master clocks to generate the bit clock.
Each SAI peripheral can control the input clock selection, pin direction and divide ratio of one audio master clock. The input clock selection and pin direction cannot be altered if an SAI module using that audio master clock has been enabled. The MCLK divide ratio can be altered while an SAI is using that master clock, although the change in the divide ratio takes several cycles. MCR[DUF] can be polled to determine when the divide ratio change has completed.
The audio master clock generation and selection is chip-specific. Refer to chip-specific clocking information about how the audio master clocks are generated. A typical implementation appears in the following figure.
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CLKGEN
PLL_OUT
ALT_CLK
EXTAL
SYS_CLK
11
10
01
00
Fractional
Clock
Divider
MCLK_OUT
MCLK_IN
1
0
MCLK (other SAIs)
MCLK
SAI
BUS_CLK
11
10
01
00
Bit
Clock
Divider
SAI_CLKMODE
SAI_MOE
SAI_FRACT/SAI_DIVIDE
SAI_MICS
BCLK_OUT
1
BCLK
BCLK_IN
0
SAI_BCD
Figure 41-38. SAI master clock generation
The MCLK fractional clock divider uses both clock edges from the input clock to generate a divided down clock that will approximate the output frequency, but without creating any new clock edges. Configuring FRACT and DIVIDE to the same value will result in a divide by 1 clock, while configuring FRACT higher than DIVIDE is not supported. The duty cycle can range from 66/33 when FRACT is set to one less than
DIVIDE down to 50/50 for integer divide ratios, and will approach 50/50 for large noninteger divide ratios. There is no cycle to cycle jitter or duty cycle variance when the divide ratio is an integer or half integer, otherwise the divider output will oscillate between the two divided frequencies that are the closest integer or half integer divisors of the divider input clock frequency. The maximum jitter is therefore equal to half the divider input clock period, since both edges of the input clock are used in generating the divided clock.
41.4.1.2 Bit clock
The SAI transmitter and receiver support asynchronous free-running bit clocks that can be generated internally from an audio master clock or supplied externally. There is also the option for synchronous bit clock and frame sync operation between the receiver and transmitter or between multiple SAI peripherals.
Externally generated bit clocks must be:
• Enabled before the SAI transmitter or receiver is enabled
• Disabled after the SAI transmitter or receiver is disabled and completes its current frames
If the SAI transmitter or receiver is using an externally generated bit clock in asynchronous mode and that bit clock is generated by an SAI that is disabled in stop mode, then the transmitter or receiver should be disabled by software before entering stop mode. This issue does not apply when the transmitter or receiver is in a synchronous mode because all synchronous SAIs are enabled and disabled simultaneously.
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41.4.1.3 Bus clock
The bus clock is used by the control and configuration registers and to generate synchronous interrupts and DMA requests.
41.4.2 SAI resets
The SAI is asynchronously reset on system reset. The SAI has a software reset and a
FIFO reset.
41.4.2.1 Software reset
The SAI transmitter includes a software reset that resets all transmitter internal logic, including the bit clock generation, status flags, and FIFO pointers. It does not reset the configuration registers. The software reset remains asserted until cleared by software.
The SAI receiver includes a software reset that resets all receiver internal logic, including the bit clock generation, status flags and FIFO pointers. It does not reset the configuration registers. The software reset remains asserted until cleared by software.
41.4.2.2 FIFO reset
The SAI transmitter includes a FIFO reset that synchronizes the FIFO write pointer to the same value as the FIFO read pointer. This empties the FIFO contents and is to be used after TCSR[FEF] is set, and before the FIFO is re-initialized and TCSR[FEF] is cleared.
The FIFO reset is asserted for one cycle only.
The SAI receiver includes a FIFO reset that synchronizes the FIFO read pointer to the same value as the FIFO write pointer. This empties the FIFO contents and is to be used after the RCSR[FEF] is set and any remaining data has been read from the FIFO, and before the RCSR[FEF] is cleared. The FIFO reset is asserted for one cycle only.
41.4.3 Synchronous modes
The SAI transmitter and receiver can operate synchronously to each other.
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Functional description
41.4.3.1 Synchronous mode
The SAI transmitter and receiver can be configured to operate with synchronous bit clock and frame sync.
If the transmitter bit clock and frame sync are to be used by both the transmitter and receiver:
• The transmitter must be configured for asynchronous operation and the receiver for synchronous operation.
• In synchronous mode, the receiver is enabled only when both the transmitter and receiver are enabled.
• It is recommended that the transmitter is the last enabled and the first disabled.
If the receiver bit clock and frame sync are to be used by both the transmitter and receiver:
• The receiver must be configured for asynchronous operation and the transmitter for synchronous operation.
• In synchronous mode, the transmitter is enabled only when both the receiver and transmitter are both enabled.
• It is recommended that the receiver is the last enabled and the first disabled.
When operating in synchronous mode, only the bit clock, frame sync, and transmitter/ receiver enable are shared. The transmitter and receiver otherwise operate independently, although configuration registers must be configured consistently across both the transmitter and receiver.
41.4.4 Frame sync configuration
When enabled, the SAI continuously transmits and/or receives frames of data. Each frame consists of a fixed number of words and each word consists of a fixed number of bits. Within each frame, any given word can be masked causing the receiver to ignore that word and the transmitter to tri-state for the duration of that word.
The frame sync signal is used to indicate the start of each frame. A valid frame sync requires a rising edge (if active high) or falling edge (if active low) to be detected and the transmitter or receiver cannot be busy with a previous frame. A valid frame sync is also ignored (slave mode) or not generated (master mode) for the first four bit clock cycles after enabling the transmitter or receiver.
The transmitter and receiver frame sync can be configured independently with any of the following options:
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• Externally generated or internally generated
• Active high or active low
• Assert with the first bit in frame or asserts one bit early
• Assert for a duration between 1 bit clock and the first word length
• Frame length from 1 to 2 words per frame
• Word length to support 8 to 32 bits per word
• First word length and remaining word lengths can be configured separately
• Words can be configured to transmit/receive MSB first or LSB first
These configuration options cannot be changed after the SAI transmitter or receiver is enabled.
41.4.5 Data FIFO
Each transmit and receive channel includes a FIFO of size 1 × 32-bit. The FIFO data is accessed using the SAI Transmit/Receive Data Registers.
41.4.5.1 Data alignment
Data in the FIFO can be aligned anywhere within the 32-bit wide register through the use of the First Bit Shifted configuration field, which selects the bit index (between 31 and 0) of the first bit shifted.
Examples of supported data alignment and the required First Bit Shifted configuration are illustrated in
Figure 41-39 for LSB First configurations and
configurations.
Figure 41-39. SAI first bit shifted, LSB first
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Functional description
Figure 41-40. SAI first bit shifted, MSB first
41.4.5.2 FIFO pointers
When writing to a TDR, the WFP of the corresponding TFR increments after each valid write. The SAI supports 8-bit, 16-bit and 32-bit writes to the TDR and the FIFO pointer will increment after each individual write. Note that 8-bit writes should only be used when transmitting up to 8-bit data and 16-bit writes should only be used when transmitting up to 16-bit data.
Writes to a TDR are ignored if the corresponding bit of TCR3[TCE] is clear or if the
FIFO is full. If the Transmit FIFO is empty, the TDR must be written at least three bit clocks before the start of the next unmasked word to avoid a FIFO underrun.
When reading an RDR, the RFP of the corresponding RFR increments after each valid read. The SAI supports 8-bit, 16-bit and 32-bit reads from the RDR and the FIFO pointer will increment after each individual read. Note that 8-bit reads should only be used when receiving up to 8-bit data and 16-bit reads should only be used when receiving up to 16bit data.
Reads from an RDR are ignored if the corresponding bit of RCR3[RCE] is clear or if the
FIFO is empty. If the Receive FIFO is full, the RDR must be read at least three bit clocks before the end of an unmasked word to avoid a FIFO overrun.
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41.4.6 Word mask register
The SAI transmitter and receiver each contain a word mask register, namely TMR and
RMR, that can be used to mask any word in the frame. Because the word mask register is double buffered, software can update it before the end of each frame to mask a particular word in the next frame.
The TMR causes the Transmit Data pin to be tri-stated for the length of each selected word and the transmit FIFO is not read for masked words.
The RMR causes the received data for each selected word to be discarded and not written to the receive FIFO.
41.4.7 Interrupts and DMA requests
The SAI transmitter and receiver generate separate interrupts and separate DMA requests, but support the same status flags. Asynchronous versions of the transmitter and receiver interrupts are generated to wake up the CPU from stop mode.
41.4.7.1 FIFO warning flag
The FIFO warning flag is set based on the number of entries in the FIFO.
The transmit warning flag is set when the number of entries in any of the enabled transmit FIFOs is empty and is cleared when the number of entries in each enabled transmit FIFO is not empty.
The receive warning flag is set when the number of entries in any of the enabled receive
FIFOs is full and is cleared when the number of entries in each enabled receive FIFO is not full.
The FIFO warning flag can generate an Interrupt or a DMA request.
41.4.7.2 FIFO error flag
The transmit FIFO error flag is set when the any of the enabled transmit FIFOs underflow. After it is set, all enabled transmit channels repeat the last valid word read from the transmit FIFO until TCSR[FEF] is cleared and the next transmit frame starts.
All enabled transmit FIFOs must be reset and initialized with new data before
TCSR[FEF] is cleared.
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RCSR[FEF] is set when the any of the enabled receive FIFOs overflow. After it is set, all enabled receive channels discard received data until RCSR[FEF] is cleared and the next next receive frame starts. All enabled receive FIFOs should be emptied before
RCSR[FEF] is cleared.
The FIFO error flag can generate only an interrupt.
41.4.7.3 Sync error flag
The sync error flag, TCSR[SEF] or RCSR[SEF], is set when configured for an externally generated frame sync and the external frame sync asserts when the transmitter or receiver is busy with the previous frame. The external frame sync assertion is ignored and the sync error flag is set. When the sync error flag is set, the transmitter or receiver continues checking for frame sync assertion when idle or at the end of each frame.
The sync error flag can generate an interrupt only.
41.4.7.4 Word start flag
The word start flag is set at the start of the second bit clock for the selected word, as configured by the Word Flag register field.
The word start flag can generate an interrupt only.
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Chapter 42
General-purpose input/output (GPIO)
The general-purpose input and output (GPIO) module is accessible via the peripheral bus and also communicates to the processor core via a zero wait state interface (IOPORT) for maximum pin performance. The GPIO data direction and output data registers control the direction and output data of each pin when the pin is configured for the GPIO function.
42.1 Introduction
NOTE
For the chip-specific implementation details of this module's instances, see the chip configuration information.
The general-purpose input and output (GPIO) module is accessible via the peripheral bus and also communicates to the processor core via a zero wait state interface (IOPORT) for maximum pin performance. The GPIO registers support 8-bit, 16-bit or 32-bit accesses.
The GPIO data direction and output data registers control the direction and output data of each pin when the pin is configured for the GPIO function. The GPIO input data register displays the logic value on each pin when the pin is configured for any digital function, provided the corresponding Port Control and Interrupt module for that pin is enabled.
Efficient bit manipulation of the general-purpose outputs is supported through the addition of set, clear, and toggle write-only registers for each port output data register.
42.1.1 Features
• Features of the GPIO module include:
• Port Data Input register visible in all digital pin-multiplexing modes
• Port Data Input register with corresponding set/clear/toggle registers
• Port Data Direction register
• Zero wait state access to GPIO registers through IOPORT
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Introduction
NOTE
The GPIO module is clocked by system clock.
42.1.2 Modes of operation
The following table depicts different modes of operation and the behavior of the GPIO module in these modes.
Table 42-1. Modes of operation
Modes of operation Description
Run The GPIO module operates normally.
Wait
Stop
Debug
The GPIO module operates normally.
The GPIO module is disabled.
The GPIO module operates normally.
42.1.3 GPIO signal descriptions
Table 42-2. GPIO signal descriptions
GPIO signal descriptions
PORTA31–PORTA0
PORTB31–PORTB0
PORTC31–PORTC0
PORTD31–PORTD0
PORTE31–PORTE0
Description
General-purpose input/output
General-purpose input/output
General-purpose input/output
General-purpose input/output
General-purpose input/output
NOTE
Not all pins within each port are implemented on each device.
See the chapter on signal multiplexing for the number of GPIO ports available in the device.
I/O
I/O
I/O
I/O
I/O
I/O
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Chapter 42 General-purpose input/output (GPIO)
42.1.3.1 Detailed signal description
Table 42-3. GPIO interface-detailed signal descriptions
Signal
PORTA31–PORTA0
PORTB31–PORTB0
PORTC31–PORTC0
PORTD31–PORTD0
PORTE31–PORTE0
I/O
I/O
Description
General-purpose input/output
State meaning Asserted: The pin is logic 1.
Timing
Deasserted: The pin is logic 0.
Assertion: When output, this signal occurs on the risingedge of the system clock. For input, it may occur at any time and input may be asserted asynchronously to the system clock.
Deassertion: When output, this signal occurs on the rising-edge of the system clock. For input, it may occur at any time and input may be asserted asynchronously to the system clock.
42.2 Memory map and register definition
Any read or write access to the GPIO memory space that is outside the valid memory map results in a bus error.
NOTE
For simplicity, each GPIO port's registers appear with the same width of 32 bits, corresponding to 32 pins. The actual number of pins per port (and therefore the number of usable control bits per port register) is chip-specific. Refer to the Chip
Configuration chapter to see the exact control bits for the nonidentical port instance.
GPIO memory map
Absolute address
(hex)
Register name
400F_F000 Port Data Output Register (GPIOA_PDOR)
Width
(in bits)
Access Reset value
32
Section/ page
0000_0000h
400F_F004 Port Set Output Register (GPIOA_PSOR) 32
R/W
W
(always reads 0)
0000_0000h
Table continues on the next page...
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Memory map and register definition
Absolute address
(hex)
GPIO memory map (continued)
Register name
400F_F008 Port Clear Output Register (GPIOA_PCOR)
400F_F00C Port Toggle Output Register (GPIOA_PTOR)
400F_F010 Port Data Input Register (GPIOA_PDIR)
400F_F014 Port Data Direction Register (GPIOA_PDDR)
400F_F040 Port Data Output Register (GPIOB_PDOR)
400F_F044 Port Set Output Register (GPIOB_PSOR)
400F_F048 Port Clear Output Register (GPIOB_PCOR)
400F_F04C Port Toggle Output Register (GPIOB_PTOR)
400F_F050 Port Data Input Register (GPIOB_PDIR)
400F_F054 Port Data Direction Register (GPIOB_PDDR)
400F_F080 Port Data Output Register (GPIOC_PDOR)
400F_F084 Port Set Output Register (GPIOC_PSOR)
400F_F088 Port Clear Output Register (GPIOC_PCOR)
400F_F08C Port Toggle Output Register (GPIOC_PTOR)
400F_F090 Port Data Input Register (GPIOC_PDIR)
400F_F094 Port Data Direction Register (GPIOC_PDDR)
400F_F0C0 Port Data Output Register (GPIOD_PDOR)
400F_F0C4 Port Set Output Register (GPIOD_PSOR)
400F_F0C8 Port Clear Output Register (GPIOD_PCOR)
400F_F0CC Port Toggle Output Register (GPIOD_PTOR)
400F_F0D0 Port Data Input Register (GPIOD_PDIR)
400F_F0D4 Port Data Direction Register (GPIOD_PDDR)
Width
(in bits)
Access Reset value
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Section/ page
W
(always reads 0)
W
(always reads 0)
R
R/W
R/W
W
(always reads 0)
W
(always reads 0)
W
(always reads 0)
W
(always reads 0)
W
(always reads 0)
R
R/W
R/W
W
(always reads 0)
R
R/W
R/W
W
(always reads 0)
W
(always reads 0)
W
(always reads 0)
R
R/W
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
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Chapter 42 General-purpose input/output (GPIO)
GPIO memory map (continued)
Absolute address
(hex)
Register name
400F_F100 Port Data Output Register (GPIOE_PDOR)
Width
(in bits)
Access Reset value
32
Section/ page
400F_F104 Port Set Output Register (GPIOE_PSOR)
400F_F108 Port Clear Output Register (GPIOE_PCOR)
400F_F10C Port Toggle Output Register (GPIOE_PTOR)
400F_F110 Port Data Input Register (GPIOE_PDIR)
400F_F114 Port Data Direction Register (GPIOE_PDDR)
32
32
32
32
32
R/W
W
(always reads 0)
W
(always reads 0)
W
(always reads 0)
R
R/W
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
42.2.1 Port Data Output Register (GPIOx_PDOR)
This register configures the logic levels that are driven on each general-purpose output pins.
NOTE
Do not modify pin configuration registers associated with pins not available in your selected package. All unbonded pins not available in your package will default to DISABLE state for lowest power consumption.
Address: Base address + 0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_PDOR field descriptions
Description Field
31–0
PDO
Port Data Output
Register bits for unbonded pins return a undefined value when read.
0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
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Memory map and register definition
42.2.2 Port Set Output Register (GPIOx_PSOR)
This register configures whether to set the fields of the PDOR.
Address: Base address + 4h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_PSOR field descriptions
Description Field
31–0
PTSO
Port Set Output
Writing to this register will update the contents of the corresponding bit in the PDOR as follows:
0 Corresponding bit in PDORn does not change.
1 Corresponding bit in PDORn is set to logic 1.
42.2.3 Port Clear Output Register (GPIOx_PCOR)
This register configures whether to clear the fields of PDOR.
Address: Base address + 8h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_PCOR field descriptions
Description Field
31–0
PTCO
Port Clear Output
Writing to this register will update the contents of the corresponding bit in the Port Data Output Register
(PDOR) as follows:
0 Corresponding bit in PDORn does not change.
1 Corresponding bit in PDORn is cleared to logic 0.
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Chapter 42 General-purpose input/output (GPIO)
42.2.4 Port Toggle Output Register (GPIOx_PTOR)
Address: Base address + Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_PTOR field descriptions
Description Field
31–0
PTTO
Port Toggle Output
Writing to this register will update the contents of the corresponding bit in the PDOR as follows:
0 Corresponding bit in PDORn does not change.
1 Corresponding bit in PDORn is set to the inverse of its existing logic state.
42.2.5 Port Data Input Register (GPIOx_PDIR)
NOTE
Do not modify pin configuration registers associated with pins not available in your selected package. All unbonded pins not available in your package will default to DISABLE state for lowest power consumption.
Address: Base address + 10h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_PDIR field descriptions
Description Field
31–0
PDI
Port Data Input
Reads 0 at the unimplemented pins for a particular device. Pins that are not configured for a digital function read 0. If the Port Control and Interrupt module is disabled, then the corresponding bit in PDIR does not update.
0 Pin logic level is logic 0, or is not configured for use by digital function.
1 Pin logic level is logic 1.
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FGPIO memory map and register definition
42.2.6 Port Data Direction Register (GPIOx_PDDR)
The PDDR configures the individual port pins for input or output.
Address: Base address + 14h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_PDDR field descriptions
Description Field
31–0
PDD
Port Data Direction
Configures individual port pins for input or output.
0 Pin is configured as general-purpose input, for the GPIO function.
1 Pin is configured as general-purpose output, for the GPIO function.
42.3 FGPIO memory map and register definition
The GPIO registers are also aliased to the IOPORT interface on the Cortex-M0+ from address 0xF800_0000.
Accesses via the IOPORT interface occur in parallel with any instruction fetches and will therefore complete in a single cycle. This aliased Fast GPIO memory map is called
FGPIO.
Any read or write access to the FGPIO memory space that is outside the valid memory map results in a bus error. All register accesses complete with zero wait states, except error accesses which complete with one wait state.
NOTE
For simplicity, each FGPIO port's registers appear with the same width of 32 bits, corresponding to 32 pins. The actual number of pins per port (and therefore the number of usable control bits per port register) is chip-specific. Refer to the Chip
Configuration chapter to see the exact control bits for the nonidentical port instance.
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Chapter 42 General-purpose input/output (GPIO)
FGPIO memory map
Absolute address
(hex)
Register name
F800_0000 Port Data Output Register (FGPIOA_PDOR)
F800_0004 Port Set Output Register (FGPIOA_PSOR)
F800_0008 Port Clear Output Register (FGPIOA_PCOR)
F800_000C Port Toggle Output Register (FGPIOA_PTOR)
F800_0010 Port Data Input Register (FGPIOA_PDIR)
F800_0014 Port Data Direction Register (FGPIOA_PDDR)
F800_0040 Port Data Output Register (FGPIOB_PDOR)
F800_0044 Port Set Output Register (FGPIOB_PSOR)
F800_0048 Port Clear Output Register (FGPIOB_PCOR)
F800_004C Port Toggle Output Register (FGPIOB_PTOR)
F800_0050 Port Data Input Register (FGPIOB_PDIR)
F800_0054 Port Data Direction Register (FGPIOB_PDDR)
F800_0080 Port Data Output Register (FGPIOC_PDOR)
F800_0084 Port Set Output Register (FGPIOC_PSOR)
F800_0088 Port Clear Output Register (FGPIOC_PCOR)
F800_008C Port Toggle Output Register (FGPIOC_PTOR)
F800_0090 Port Data Input Register (FGPIOC_PDIR)
F800_0094 Port Data Direction Register (FGPIOC_PDDR)
F800_00C0 Port Data Output Register (FGPIOD_PDOR)
F800_00C4 Port Set Output Register (FGPIOD_PSOR)
F800_00C8 Port Clear Output Register (FGPIOD_PCOR)
Width
(in bits)
Access Reset value
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
W
(always reads 0)
W
(always reads 0)
W
(always reads 0)
R
R/W
R/W
W
(always reads 0)
W
(always reads 0)
W
(always reads 0)
R
R/W
R/W
W
(always reads 0)
W
(always reads 0)
R/W
W
(always reads 0)
W
(always reads 0)
W
(always reads 0)
R
R/W
R/W
Section/ page
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
Table continues on the next page...
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FGPIO memory map and register definition
FGPIO memory map (continued)
Absolute address
(hex)
Register name
Width
(in bits)
Access Reset value
F800_00CC Port Toggle Output Register (FGPIOD_PTOR)
F800_00D0 Port Data Input Register (FGPIOD_PDIR)
F800_00D4 Port Data Direction Register (FGPIOD_PDDR)
F800_0100 Port Data Output Register (FGPIOE_PDOR)
F800_0104 Port Set Output Register (FGPIOE_PSOR)
F800_0108 Port Clear Output Register (FGPIOE_PCOR)
F800_010C Port Toggle Output Register (FGPIOE_PTOR)
F800_0110 Port Data Input Register (FGPIOE_PDIR)
F800_0114 Port Data Direction Register (FGPIOE_PDDR)
32
32
32
32
32
32
32
32
32
Section/ page
W
(always reads 0)
R
R/W
R/W
W
(always reads 0)
W
(always reads 0)
W
(always reads 0)
R
R/W
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
42.3.1 Port Data Output Register (FGPIOx_PDOR)
This register configures the logic levels that are driven on each general-purpose output pins.
Address: Base address + 0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FGPIOx_PDOR field descriptions
Description Field
31–0
PDO
Port Data Output
Unimplemented pins for a particular device read as zero.
0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
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Chapter 42 General-purpose input/output (GPIO)
42.3.2 Port Set Output Register (FGPIOx_PSOR)
This register configures whether to set the fields of the PDOR.
Address: Base address + 4h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FGPIOx_PSOR field descriptions
Description Field
31–0
PTSO
Port Set Output
Writing to this register will update the contents of the corresponding bit in the PDOR as follows:
0 Corresponding bit in PDORn does not change.
1 Corresponding bit in PDORn is set to logic 1.
42.3.3 Port Clear Output Register (FGPIOx_PCOR)
This register configures whether to clear the fields of PDOR.
Address: Base address + 8h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FGPIOx_PCOR field descriptions
Description Field
31–0
PTCO
Port Clear Output
Writing to this register will update the contents of the corresponding bit in the Port Data Output Register
(PDOR) as follows:
0 Corresponding bit in PDORn does not change.
1 Corresponding bit in PDORn is cleared to logic 0.
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FGPIO memory map and register definition
42.3.4 Port Toggle Output Register (FGPIOx_PTOR)
Address: Base address + Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FGPIOx_PTOR field descriptions
Description Field
31–0
PTTO
Port Toggle Output
Writing to this register will update the contents of the corresponding bit in the PDOR as follows:
0 Corresponding bit in PDORn does not change.
1 Corresponding bit in PDORn is set to the inverse of its existing logic state.
42.3.5 Port Data Input Register (FGPIOx_PDIR)
Address: Base address + 10h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FGPIOx_PDIR field descriptions
Description Field
31–0
PDI
Port Data Input
Reads 0 at the unimplemented pins for a particular device. Pins that are not configured for a digital function read 0. If the Port Control and Interrupt module is disabled, then the corresponding bit in PDIR does not update.
0 Pin logic level is logic 0, or is not configured for use by digital function.
1 Pin logic level is logic 1.
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42.3.6 Port Data Direction Register (FGPIOx_PDDR)
The PDDR configures the individual port pins for input or output.
Address: Base address + 14h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FGPIOx_PDDR field descriptions
Description Field
31–0
PDD
Port Data Direction
Configures individual port pins for input or output.
0 Pin is configured as general-purpose input, for the GPIO function.
1 Pin is configured as general-purpose output, for the GPIO function.
42.4 Functional description
42.4.1 General-purpose input
The logic state of each pin is available via the Port Data Input registers, provided the pin is configured for a digital function and the corresponding Port Control and Interrupt module is enabled.
42.4.2 General-purpose output
The logic state of each pin can be controlled via the port data output registers and port data direction registers, provided the pin is configured for the GPIO function. The following table depicts the conditions for a pin to be configured as input/output.
If
A pin is configured for the GPIO function and the corresponding port data direction register bit is clear.
A pin is configured for the GPIO function and the corresponding port data direction register bit is set.
Then
The pin is configured as an input.
The pin is configured as an output and and the logic state of the pin is equal to the corresponding port data output register.
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Functional description
To facilitate efficient bit manipulation on the general-purpose outputs, pin data set, pin data clear, and pin data toggle registers exist to allow one or more outputs within one port to be set, cleared, or toggled from a single register write.
The corresponding Port Control and Interrupt module does not need to be enabled to update the state of the port data direction registers and port data output registers including the set/clear/toggle registers.
42.4.3 IOPORT
The GPIO registers are also aliased to the IOPORT interface on the Cortex-M0+ from address 0xF800_0000. Accesses via the IOPORT interface occur in parallel with any instruction fetches and will therefore complete in a single cycle. If the DMA attempts to access the GPIO registers on the same cycle as an IOPORT access, then the DMA access will stall until any IOPORT accesses have completed.
During Compute Operation, the GPIO registers remain accessible via the IOPORT interface only. Since the clocks to the Port Control and Interrupt modules are disabled during Compute Operation, the Pin Data Input Registers do not update with the current state of the pins.
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Chapter 43
Touch Sensing Input (TSI)
The touch sensing input (TSI) module provides capacitive touch sensing detection with high sensitivity and enhanced robustness. Each TSI pin implements the capacitive measurement by a current source scan, charging and discharging the electrode, once or several times.
43.1 Introduction
The touch sensing input (TSI) module provides capacitive touch sensing detection with high sensitivity and enhanced robustness.
Each TSI pin implements the capacitive measurement by a current source scan, charging and discharging the electrode, once or several times. A reference oscillator ticks the scan time and stores the result in a 16-bit register when the scan completes. Meanwhile, an interrupt request is submitted to CPU for post-processing if TSI interrupt is enabled and
DMA function is not selected.The TSI module can be periodically triggered to work in low power mode with ultra-low current adder and wake CPU at the end of scan or the conversion result is out of the range specified by TSI threshold. It provides a solid capacitive measurement module to the implementation of touch keyboard, rotaries and sliders.
43.1.1 Features
TSI features includes:
• Support up to 16 external electrodes
• Automatic detection of electrode capacitance across all operational power modes
• Internal reference oscillator for high-accuracy measurement
• Configurable software or hardware scan trigger
• Fully support Freescale touch sensing software (TSS) library, see www.freescale.com/touchsensing .
• Capability to wake MCU from low power modes
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Introduction
• Compensate for temperature and supply voltage variations
• High sensitivity change with 16-bit resolution register
• Configurable up to 4096 scan times.
• Support DMA data transfer
• For electrode design recommendations refer to AN3863: Designing Touch Sensing
Electrodes
43.1.2 Modes of operation
This module supports the following operation modes.
Table 43-1. Operating modes
Mode
Stop and low power stop
Wait
Run
Description
TSI module is fully functional in all of the stop modes as long as TSI_GENCS[STPE] is set. The channel specified by
TSI_DATA[TSICH] will be scanned upon the trigger. After scan finishes, either end-of-scan or out-of-range interrupt can be selected to bring MCU out of low power modes.
TSI module is fully functional in this mode. When a scan completes, TSI submits an interrupt request to CPU if the interrupt is enabled.
TSI module is fully functional in this mode. When a scan completes, TSI submits an interrupt request to CPU if the interrupt is enabled.
43.1.3 Block diagram
The following figure is a block diagram of the TSI module.
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TSIEN TSIIEN
Chapter 43 Touch Sensing Input (TSI)
STPE
Int. 1.8V
DVOLT
TSI0
TSI1
TSI2
TSI3
TSI14
TSI15
TSI_PENx
Hardware Trigger
Write SWTS “1”
Voltage
Divider
TSICH
STM
–
+
Electrode
Oscillator
2
PS NSCN
Reference
Oscillator
16-bit Counter
Reference Clock
Control
Logic
EXTCHRG REFCHRG CURSW EOSF
Figure 43-1. TSI module block diagram
TSIIEN
TSI_CNTH
TSI_CNTL
Interrupt
SCNIP
43.2 External signal description
The TSI module contains up to 16 external pins for touch sensing. The table found here describes each of the TSI external pins.
Table 43-2. TSI signal description
TSI[15:0]
Name
TSI
Port
I/O
Direction Function
TSI capacitive pins.
Switches driver that connects directly to the electrode pins TSI[15:0] can operate as GPIO pins.
I/O
Reset state
43.2.1 TSI[15:0]
When TSI functionality is enabled , the TSI analog portion uses the corresponding channel to connect external on-board touch capacitors. The PCB connection between the pin and the touch pad must be kept as short as possible to reduce distribution capacity on board.
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Register definition
43.3 Register definition
This section describes the memory map and control/status registers for the TSI module.
TSI memory map
Absolute address
(hex)
Register name
4004_5000 TSI General Control and Status Register (TSI0_GENCS)
4004_5004 TSI DATA Register (TSI0_DATA)
4004_5008 TSI Threshold Register (TSI0_TSHD)
Width
(in bits)
Access Reset value
32
32
32
R/W
R/W
R/W
Section/ page
0000_0000h
0000_0000h
0000_0000h
43.3.1 TSI General Control and Status Register (TSIx_GENCS)
This control register provides various control and configuration information for the TSI module.
NOTE
When TSI is working, the configuration bits (GENCS[TSIEN],
GENCS[TSIIEN], and GENCS[STM]) must not be changed.
The EOSF flag is kept until the software acknowledge it.
Address: 4004_5000h base + 0h offset = 4004_5000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0
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Chapter 43 Touch Sensing Input (TSI)
4 3 2 1 0
R
W
Reset 0
Field
31
OUTRGF
30–29
Reserved
28
ESOR
27–24
MODE
23–21
REFCHRG
0 0 0 0 0 0 0 0 0
TSIx_GENCS field descriptions
Description
0 0 0 0 0
Out of Range Flag.
This flag is set if the result register of the enabled electrode is out of the range defined by the
TSI_THRESHOLD register. This flag is set only when TSI is configured in non-noise detection mode. It can be read once the CPU wakes. Write "1" , when this flag is set, to clear it.
This field is reserved.
This read-only field is reserved and always has the value 0.
End-of-scan or Out-of-Range Interrupt Selection
0
This bit is used to select out-of-range or end-of-scan event to generate an interrupt.
0 Out-of-range interrupt is allowed.
1 End-of-scan interrupt is allowed.
TSI analog modes setup and status bits.
Set up TSI analog modes, especially, setting MODE[3:2] to not 2'b00 will configure TSI to noise detection modes. MODE[1:0] take no effect on TSI operation mode and should always write to 2'b00 for setting up.
When reading this field will return the analog status. Refer to chapter "Noise detection mode" for details.
0000 Set TSI in capacitive sensing(non-noise detection) mode.
0100 Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is disabled.
1000 Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is enabled to work in higher frequencies operations.
1100 Set TSI analog to work in automatic noise detection mode.
REFCHRG
These bits indicate the reference oscillator charge and discharge current value.
000 500 nA.
001 1 μA.
010 2 μA.
011 4 μA.
100 8 μA.
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Register definition
Field
20–19
DVOLT
101 16 μA.
110 32 μA.
111 64 μA.
DVOLT
TSIx_GENCS field descriptions (continued)
Description
These bits indicate the oscillator's voltage rails as below.
18–16
EXTCHRG
15–13
PS
12–8
NSCN
00 DV = 1.03 V; V
P
= 1.33 V; V m
= 0.30 V.
01 DV = 0.73 V; V
P
= 1.18 V; V m
= 0.45 V.
10 DV = 0.43 V; V
P
= 1.03 V; V m
= 0.60 V.
11 DV = 0.29 V; V
P
= 0.95 V; V m
= 0.67 V.
EXTCHRG
These bits indicate the electrode oscillator charge and discharge current value.
000 500 nA.
001 1 μA.
010 2 μA.
011 4 μA.
100 8 μA.
101 16 μA.
110 32 μA.
111 64 μA.
PS
These bits indicate the prescaler of the output of electrode oscillator.
000 Electrode Oscillator Frequency divided by 1
001 Electrode Oscillator Frequency divided by 2
010 Electrode Oscillator Frequency divided by 4
011 Electrode Oscillator Frequency divided by 8
100 Electrode Oscillator Frequency divided by 16
101 Electrode Oscillator Frequency divided by 32
110 Electrode Oscillator Frequency divided by 64
111 Electrode Oscillator Frequency divided by 128
NSCN
These bits indicate the scan number for each electrode. The scan number is equal to NSCN + 1, which allows the scan time ranges from 1 to 32. By default, NSCN is configured as 0, which asserts the TSI scans once on the selected eletrode channel.
00000 Once per electrode
00001 Twice per electrode
00010 3 times per electrode
00011 4 times per electrode
00100 5 times per electrode
00101 6 times per electrode
00110 7 times per electrode
00111 8 times per electrode
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Field
7
TSIEN
6
TSIIEN
5
STPE
4
STM
Chapter 43 Touch Sensing Input (TSI)
TSIx_GENCS field descriptions (continued)
Description
01000 9 times per electrode
01001 10 times per electrode
01010 11 times per electrode
01011 12 times per electrode
01100 13 times per electrode
01101 14 times per electrode
01110 15 times per electrode
01111 16 times per electrode
10000 17 times per electrode
10001 18 times per electrode
10010 19 times per electrode
10011 20 times per electrode
10100 21 times per electrode
10101 22 times per electrode
10110 23 times per electrode
10111 24 times per electrode
11000 25 times per electrode
11001 26 times per electrode
11010 27 times per electrode
11011 28 times per electrode
11100 29 times per electrode
11101 30 times per electrode
11110 31 times per electrode
11111 32 times per electrode
Touch Sensing Input Module Enable
This bit enables TSI module.
0 TSI module disabled.
1 TSI module enabled.
Touch Sensing Input Interrupt Enable
This bit enables TSI module interrupt request to CPU when the scan completes. The interrupt will wake
MCU from low power mode if this interrupt is enabled.
0 TSI interrupt is disabled.
1 TSI interrupt is enabled.
TSI STOP Enable
This bit enables TSI module function in low power modes (stop, VLPS, LLS and VLLS{3,2,1}).
0 TSI is disabled when MCU goes into low power mode.
1 Allows TSI to continue running in all low power modes.
Scan Trigger Mode
This bit specifies the trigger mode. User is allowed to change this bit when TSI is not working in progress.
0 Software trigger scan.
1 Hardware trigger scan.
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Register definition
Field
3
SCNIP
TSIx_GENCS field descriptions (continued)
Description
Scan In Progress Status
This read-only bit indicates if scan is in progress. This bit will get asserted after the analog bias circuit is stable after a trigger and it changes automatically by the TSI.
2
EOSF
1
CURSW
0
Reserved
0 No scan in progress.
1 Scan in progress.
End of Scan Flag
This flag is set when all active electrodes are finished scanning after a scan trigger. Write "1" , when this flag is set, to clear it.
0 Scan not complete.
1 Scan complete.
CURSW
This bit specifies if the current sources of electrode oscillator and reference oscillator are swapped.
0 The current source pair are not swapped.
1 The current source pair are swapped.
This field is reserved.
This read-only field is reserved and always has the value 0.
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43.3.2 TSI DATA Register (TSIx_DATA )
Address: 4004_5000h base + 4h offset = 4004_5004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
R
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
W
Reset 0
Field
31–28
TSICH
0 0 0 0 0 0 0 0 0
TSIx_DATA field descriptions
Description
0 0 0 0 0 0
TSICH
These bits specify current channel to be measured. In hardware trigger mode (TSI_GENCS[STM] = 1), the scan will not start until the hardware trigger occurs. In software trigger mode (TSI_GENCS[STM] = 0), the scan starts immediately when TSI_DATA[SWTS] bit is written by 1.
0000 Channel 0.
0001 Channel 1.
0010 Channel 2.
0011 Channel 3.
0100 Channel 4.
0101 Channel 5.
0110 Channel 6.
0111 Channel 7.
1000 Channel 8.
1001 Channel 9.
1010 Channel 10.
1011 Channel 11.
1100 Channel 12.
1101 Channel 13.
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Functional description
Field
27–24
Reserved
23
DMAEN
TSIx_DATA field descriptions (continued)
Description
1110 Channel 14.
1111 Channel 15.
This field is reserved.
This read-only field is reserved and always has the value 0.
DMA Transfer Enabled
This bit is used together with the TSI interrupt enable bits(TSIIE, ESOR) to generate a DMA transfer request instead of an interrupt.
22
SWTS
21–16
Reserved
15–0
TSICNT
0 Interrupt is selected when the interrupt enable bit is set and the corresponding TSI events assert.
1 DMA transfer request is selected when the interrupt enable bit is set and the corresponding TSI events assert.
Software Trigger Start
This write-only bit is a software start trigger. When STM bit is clear, write "1" to this bit will start a scan.
The electrode channel to be scanned is determinated by TSI_DATA[TSICH] bits.
0 No effect.
1 Start a scan to determine which channel is specified by TSI_DATA[TSICH].
This field is reserved.
This read-only field is reserved and always has the value 0.
TSI Conversion Counter Value
These read-only bits record the accumulated scan counter value ticked by the reference oscillator.
43.3.3 TSI Threshold Register (TSIx_TSHD)
Address: 4004_5000h base + 8h offset = 4004_5008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–16
THRESH
TSIx_TSHD field descriptions
Description
TSI Wakeup Channel High-threshold
15–0
THRESL
This half-word specifies the high threshold of the wakeup channel.
TSI Wakeup Channel Low-threshold
This half-word specifies the low threshold of the wakeup channel.
43.4 Functional description
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43.4.1 Capacitance measurement
The electrode pin capacitance measurement uses a dual oscillator approach. The frequency of the TSI electrode oscillator depends on the external electrode capacitance and the TSI module configuration. After going to a configurable prescaler, the TSI electrode oscillator signal goes to the input of the module counter. The time for the module counter to reach its module value is measured using the TSI reference oscillator.
The measured electrode capacitance is directly proportional to the time.
43.4.1.1 TSI electrode oscillator
The TSI electrode oscillator circuit is illustrated in the following figure. A configurable constant current source is used to charge and discharge the external electrode capacitance. A buffer hysteresis defines the oscillator delta voltage. The delta voltage defines the margin of high and low voltage which are the reference input of the comparator in different time.
Figure 43-8. TSI electrode oscillator circuit
The current source applied to the pad capacitance is controlled by the
SCANC[EXTCHRG]. The hysteresis delta voltage is defined in the module electrical specifications present in the device Data Sheet. The figure below shows the voltage amplitude waveform of the electrode capacitance charging and discharging with a programmable current.
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Functional description
Electrode
Voltage
Electrode Capacitor Charging and
Discharging with constant current
Hysteresis
Voltage Delta
Figure 43-9. TSI electrode oscillator chart
Time
The oscillator frequency is give by the following equation
F elec
I
2 * C elec
*
Δ
V
Figure 43-10. TSI electrode oscillator frequency
Where:
I: constant current
C elec
: electrode capacitance
Δ V: Hysteresis delta voltage
So by this equation, for example, an electrode with C elec
= 20 pF, with a current source of
I = 16 µA and Δ V = 600 mV have the following oscillation frequency:
F elec
16 µA
2 * 20pF
*
600mV 0.67MHz
Figure 43-11. TSI electrode oscillator frequency
The current source is used to accommodate the TSI electrode oscillator frequency with different electrode capacitance sizes.
43.4.1.2 Electrode oscillator and counter module control
The TSI oscillator frequency signal goes through a prescaler defined by the GENCS[PS] and then enters in a modulus counter. GENCS[NSCN] defines the maximum count value of the modulus counter.
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The pin capacitance sampling time is given by the time the module counter takes to go from 0 to its maximum value, defined by NSCN. The electrode sample time is expressed by the following equation:
T cap_samp
PS * NSCN
F elec
Using Equation 1
T cap_samp
2 * PS * NSCN * C elec
* Δ V
I
Figure 43-12. Electrode sampling time
Where:
PS: prescaler value
NSCN: module counter maximum value
I: constant current
C elec
: electrode capacitance
Δ V: Hysteresis delta voltage
By this equation we have that an electrode with C = 20 pF, with a current source of I = 16
µA and Δ V = 600 mV, PS = 2 and NSCN = 16 have the following sampling time:
T cap_samp
2*2*16*20pF*600mV
16µA
48µs
43.4.1.3 TSI reference oscillator
The TSI reference oscillator has the same topology of the TSI electrode oscillator. The
TSI reference oscillator instead of using an external capacitor for the electrode oscillator has an internal reference capacitor.
The TSI reference oscillator has an independent programmable current source controlled by SCANC[REFCHRG].
The reference oscillator frequency is given by the following equation:
F ref_osc
I ref
2 *C ref
*
Δ
V
Figure 43-13. TSI reference oscillator frequency
Where:
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C ref
: Internal reference capacitor
I ref
: Reference oscillator current source
∆V : Hysteresis delta voltage
Considering C ref
= 1.0 pF, I ref
= 12 µA and ∆V = 600 mV, follows
F ref_osc
12µA
2 *1.0pF
* 600mV
10.0MHz
43.4.2 TSI measurement result
The capacitance measurement result is defined by the number of TSI reference oscillator periods during the sample time and is stored in the TSICHnCNT register.
TSICHnCNT = T cap_samp
* F ref_osc
Using Equation 2 and Equation 1 follows:
TSICHnCNT
I ref
* PS *NSCN
C ref
* I elec
* C elec
Figure 43-14. Capacitance result value
In the example where F ref_osc
= 10.0MHz and T cap_samp
= 48 µs, TSICHnCNT = 480
43.4.3 Enable TSI module
The TSI module can be fully functional in run, wait and low power modes. The
TSI_GENCS[TSIEN] bit must be set to enable the TSI module in run and wait mode.
When TSI_GENCS[STPE] bit is set, it allows the TSI module to work in low power mode.
43.4.4 Software and hardware trigger
The TSI module allows a software or hardware trigger to start a scan. When a software trigger is applied ( TSI_GENCS[STM] bit clear), the TSI_GENCS[SWTS] bit must be written "1" to start the scan electrode channel that is identified by TSI_DATA[TSICH].
When a hardware trigger is applied ( TSI_GENCS[STM] bit set), the TSI will not start scanning until the hardware trigger arrives. The hardware trigger is different depending on the MCU configuration. Generally, it could be an event that RTC overflows. See chip configuration section for details.
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43.4.5 Scan times
The TSI provides multi-scan function. The number of scans is indicated by
TSI_GENCS[NSCN] that allow the scan number from 1 to 32. When
TSI_GENCS[NSCN] is set to 0 (only once), the single scan is engaged. The 16-bit counter accumulates all scan results until the NSCN time scan completes, and users can read TSI_DATA[TSICNT] to get this accumulation. When DMA transfer is enabled, the counter values can also be read out by DMA engine.
43.4.6 Clock setting
TSI is built with dual oscillator architecture. In normal sensing application, the reference oscillator clock is the only clock source for operations. The reference clock is used to measure the electrode oscillator by ticking a 16-bit counter. The reference oscillator
frequency depends on the current source setting. Please refer to the Current source
for more details.
The output of electrode oscillator has several prescalers up to 128 indicated by
TSI_GENCS[PS]. This allows a flexible counter configuration for different electrode oscillator frequency.
43.4.7 Reference voltage
The TSI module offers a internal reference voltage for both electrode oscillator and reference oscillator. The internal reference voltage can work in low power modes even when the MCU regulator is partially powered down, which is ideally for low-power touch detection.
The charge and discharge difference voltage is configurable upon the setting of
TSI_GENCS[DVOLT]. The following table shows the all the delta voltage configurations.
NOTE
Note this table doesn't apply to noise mode, where the details should be consult form noise modes chapters.
DVOLT
00
Table 43-11. Delta voltage configuration
V p
(V)
1.328
V m
(V)
0.302
Table continues on the next page...
Δ V (V)
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DVOLT
01
10
11
Table 43-11. Delta voltage configuration (continued)
V p
(V)
1.111
0.986
0.914
V m
(V)
0.519
0.644
0.716
Δ V (V)
0.592
0.342
0.198
43.4.8 Current source
The TSI module supports eight different current source power to increment from 500 nA to 64 µA. TSI_GENCS[EXTCHRG] determines the current of electrode oscillator that charges and discharges external electrodes. The TSI_GENCS[REFCHRG] determines the current of reference oscillator on which the internal reference clock depends. The lower current source takes more time for charge and discharge, which is useful to detect highaccuracy change. The higher current source takes less time, which can be used to charge a big electrode by less power consumption.
TSI_GENCS[CURSW] allows the current source to swap, so that the reference oscillator and electrode oscillator use the opposite current sources. When TSI_GENCS[CURSW] is set and the current sources are swapped, TSI_GENCS[EXTCHRG] and
TSI_GENCS[REFCHRG] still control the corresponding current sources, that is,
TSI_GENCS[EXTCHRG] controls the reference oscillator current and
TSI_GENCS[REFCHRG] controls the electrode oscillator current.
43.4.9 End of scan
As a scan starts, [SCNIP] bit is set to indicate scan is in progress. When the scan completes, the [EOSF] bit is set. Before clearing the [EOSF] bit, the value in
TSI_DATA[TSICNT] must be read. If the TSI_GENCS[TSIIEN] and
TSI_GENCS[ESOR] are set andTSI_GENCS[DMAEN]is not set, an interrupt is submitted to CPU for post-processing immediately. The interrupt is also optional to wake
MCU to execute ISR if it is in low power mode. When DMA function is enabled by setting TSI_GENCS[TSIIEN] and TSI_GENCS[ESOR], as soon as scan completes, a
DMA transfer request is asserted to DMA controller for data movement, generally, DMA engine will fetch TSI conversion result from TSI_DATA register,store it to other memory space and then refresh the TSI scan channel index(TSI_DATA[TSICH]) for next loop.
When DMA transfer is done, TSI_GENCS[EOSF] is cleared automatically.
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43.4.10 Out-of-range interrupt
If enabled, TSI will scan the electrode specified by TSI_DATA[TSICH] as soon as the trigger arrives. The TSI_GENCS[OUTRGF] flag generates a TSI interrupt request if the
TSI_GENCS[TSIIE] bit is set and GENCS[ESOR] bit is cleared. With this configuration, after the end-of-electrode scan, the electrode capacitance will be converted and stored to the result register TSI_DATA[TSICNT], the out-of-range interrupt is only requested if there is a considerable capacitance change defined by the TSI_TSHD. For instance, if in low power mode the electrode capacitance does not vary, the out-of-range interrupt does not interrupt the CPU. This interrupt will not happen in noise detection mode. It is worthy to note that when the counter value reaches 0xFFFF is treated as an extreme case the outof-range will not happen. Also in noise detection mode, the out-of-range will not assert either.
43.4.11 Wake up MCU from low power modes
In low power modes, once enabled by TSI_GENCS[STPE] and TSI_GENCS[TSIIE],
TSI can bring MCU out of its low power modes(STOP, VLPS, VLLS,etc) by either end of scan or out of range interrupt, that is, if TSI_GENCS[ESOR] is set, end of scan interrupt is selected and otherwise, out of range is selected.
43.4.12 DMA function support
Transmit by DMA is supported only when TSI_DATA[DMAEN] is set. A DMA transfer request is asserted when all the flags based on TSI_GENCS[ESOR] settings and
TSI_GENCS[TSIIE] are set. Then the on-chip DMA controller detects this request and transfers data between memory space and TSI register space. After the data tranfer, DMA
DONE is asserted to clear TSI_GENCS[EOSF] automatically. This function is normally used by DMA controller to get the conversion result from TSI_DATA[TSICNT] upon a end-of-scan event and then refresh the channel index(TSI_DATA[TSICH]) for next trigger. DMA function is not available when MCU is in stop modes.
43.4.13 Noise detection mode
The noise detection mode change the circuit configuration as shown in the following figure. With this configuration, it is possible to detect touch with high levels of EMC noise present. To enter the test mode, see TSIx_GENCS[MODE] register field.
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In noise detection mode the reference oscillator has the same configuration except the output goes to Counter2 and this counter will have the it's maximum count set by NSCN.
2^(PS). This means this oscillator will setup the noise detection mode sense duration.
The blocks of external oscillator is changed and instead of an oscillator the circuit implements an RF amplitude detection. The thrshold for this amplitude detection is set by
DVOLT register bits.
Also the external voltage is biased by vmid voltage with a Rs series resistance.
The vmid voltage is defined as V(vmid) = (V(vp) + V(vm))/2.
The Rs value is defined by i_ext_3v<2:0> register bits.
Figure 43-15. TSI circuit in noise detection mode
To determine the noise level the below algorithm can be used:
1. Initialize Rs = maxrs; Dvolt = minDv (set other configurations also)
2. Perform a noise cycle.
3. If TSIcounter < 3, go to step 8
4. If Rs = minrs, go to step 6.
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5. Reduce value of Rs. go to step 2
6. If Dvolt = maxDv, go to END
7. Increase value of Dvolt. Set Rs = maxrs. go to step 2
8. If Rs > minrs, (Reduce value of Rs, go to END)
9. Rs = maxrs, reduce value of Dvolt.
10. END Get value of Rs and Dvolt.
One example of noise detection mode is shown in the following figure. in this figure the
TSI is working in capacitive mode until 30uS when it is changed to noise detection mode.
In noise detection mode the selected pad is biased with 0.815V and all AC waveform in this pad is caused by a noise source external to IC.
It is possible to observe in the following figure that, in noise detection mode, the clkref output has the peak detection and the number of detected peaks can be counted or used by digital block. The clkext output has the internal oscillator output and can be used to set the maximum noise detection time window.
The waveform of the following figure shows two operations during noise detection mode:
• The V(vp) and V(vm) thresholds are changed in 34.4 µs.
• The Rs series resistance value is changed between 184 k Ω ( iext<2:0>=011) and 32 k Ω ( iext<2:0>=101). Because of this Rs change the amplitude of noise waveform change also.
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Functional description
Figure 43-16. TSI noise detection mode waveform
43.4.13.1 Automatic noise mode
This mode is set by MODE[3:2] = 11 (noise mode 3). In this mode, the thresholds are incremented internally by the module until the point that there is no noise voltage trepassing the threshold.
The following diagram shows how it is done. The threshold comparator output goes to a counter and as the DVOLT control bits are increased the DVOLT thresholds are increased as well. The four bits are counted until 1111 (=15) and the counter is stop with this maximum value.
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Figure 43-17. Block diagram automatic noise threshold operation
The signals that have different behavior in this noise mode (wrt capacitive mode) are shown in the following table.
MODE[3:2]
Table 43-12. Signal properties in automatic noise operation mode
Name
EXTCHRG[2:1]
EXTCHRG[0]
Function
11—Noise mode operation with frequency limitation and automatic threshold counter.
In this operation mode, these bits select the number of filter bits.
00—3 filter bits
01—2 filter bits
10—1 filter bit
11—no filter bit
In this operation mode, this bit selects the series resistance.
0—uses Rs=32 kΩ
I
1—uses Rs=187 kΩ
Independent of this bit selection, the threshold 15 is done with Rs = 5.5 kΩ
I
I
I/O type
Table continues on the next page...
00
00
0
Power Up/Reset state
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Functional description
Table 43-12. Signal properties in automatic noise operation mode (continued)
DVOLT[1:0]
Name
MODE[3:0]
Function
Selects voltage rails of the internal oscillator
DVOLT counter bits output.
This field keeps 0000b if
MODE[3:2] is not 11 after entering automatic noise mode.
I
O
I/O type
00
Power Up/Reset state
0000
43.4.13.2 Single threshold noise modes
These modes are reset by MODE[3:2]=01 and 10. The difference between these two modes is that in mode 2 (MODE[3:2]=10), there is a frequency limitation circuit that enables the circuit to operate in higher frequencies. In mode 1 (MODE[3:2]=01), this frequency limitation circuit is not enabled.
In this mode, the thresholds are set by user via register bits as described in the following table.
During these modes the internal oscillator rails are set to the maximum (equivalent to
DVOLT[1:0]=00).
MODE[3:2]
Name
Table 43-13. Signal properties in single noise modes (1,2)
Function
01 or 10- Single thrshold noise mode operation.
Table continues on the next page...
I/O type Power up / reset
I 00
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Table 43-13. Signal properties in single noise modes (1,2) (continued)
Name
DVOLT[1:0],
EXTCHRG[2:1]
Function I/O type Power up / reset
I XXXX
EXTCHRG[0]
In this operation mode these 4 bits are used select the noise threshold.
0000 - DVpm = 0.038 V, Vp = 0.834 V, Vm = 0.796 V
0001 - DVpm = 0.050 V, Vp = 0.830 V, Vm = 0.790 V
0010 - DVpm = 0.066 V, Vp = 0.848 V, Vm = 0.782 V
0011 - DVpm = 0.087 V, Vp = 0.858 V, Vm = 0.772 V
0100 - DVpm = 0.114 V, Vp = 0.872 V, Vm = 0.758 V
0101 - DVpm = 0.150 V, Vp = 0.890 V, Vm = 0.740 V
0110 - DVpm = 0.197 V, Vp = 0.914 V, Vm = 0.716 V
0111 - DVpm = 0.260 V, Vp = 0.945 V, Vm = 0.685 V
1000 - DVpm = 0.342 V, Vp = 0.986 V, Vm = 0.644 V
1001 - DVpm = 0.450 V, Vp = 1.040 V, Vm = 0.590 V
1010 - DVpm = 0.592 V, Vp = 1.111 V, Vm = 0.519 V
1011 - DVpm = 0.780 V, Vp = 1.205 V, Vm = 0.425 V
1100 - DVpm = 1.026 V, Vp = 1.328 V, Vm = 0.302 V
1101 - DVpm = 1.350 V, Vp = 1.490 V, Vm = 0.140 V
1110 - DVpm = 1.630 V, Vp = 1.630 V, Vm = 0 V
1111 - DVpm = 1.630 V, Vp = 1.630 V, Vm = 0 V
In this operation mode this bits selects the series resistance.
0 - uses Rs = 32 kΩ .
1- uses Rs = 187 kΩ .
Independent of this bit selection the threshold 15 is done with Rs =
5.5 kΩ .
I XX
KL26 Sub-Family Reference Manual, Rev. 3.2, October 2013
Freescale Semiconductor, Inc.
875
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© 2013 Freescale Semiconductor, Inc.
Document Number: KL26P121M48SF4RM
Rev. 3.2
10/2013
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