Initialization/application information
1. Update the Control Register 1 (SPIx_C1) to enable the SPI and to control interrupt enables. This register also sets the SPI as master or slave, determines clock phase and polarity, and configures the main SPI options.
2. Update the Control Register 2 (SPIx_C2) to enable additional SPI functions such as the SPI match interrupt feature, the master mode-fault function, and bidirectional mode output as well as to control 8- or 16-bit mode selection and other optional features.
3. Update the Baud Rate Register (SPIx_BR) to set the prescaler and bit rate divisor for an SPI master.
4. Update the Hardware Match Register (SPIx_MH:SPIx_ML) with the value to be compared to the receive data register for triggering an interrupt if hardware match interrupts are enabled.
5. In the master, read SPIx_S while S[SPTEF] = 1, and then write to the transmit data register (SPIx_DH:SPIx_DL) to begin transfer.
37.5.2 Pseudo-Code Example
In this example, the SPI module is set up for master mode with only hardware match interrupts enabled. The SPI runs in 16-bit mode at a maximum baud rate of SPI module clock divided by 2. Clock phase and polarity are set for an active-high SPI clock where the first edge on SPSCK occurs at the start of the first cycle of a data transfer.
SPIx_C1=0x54(%01010100)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
0
0
0
1
0
1
0
1
=
=
=
=
=
=
=
=
Disables receive and mode fault interrupts
Enables the SPI system
Disables SPI transmit interrupts
Sets the SPI module as a master SPI device
Configures SPI clock as active-high
First edge on SPSCK at start of first data transfer cycle
Determines SS pin function when mode fault enabled
SPI serial data transfers start with most significant bit
SPIx_C2 = 0xC0(%11000000)
Bit 7
Bit 6
Bit 5
Bit 4
SPMIE
SPIMODE
TXDMAE
MODFEN
=
=
=
=
1
1
0
0
SPI hardware match interrupt enabled
Configures SPI for 16-bit mode
DMA request disabled
Disables mode fault function
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SPIx_C2 = 0xC0(%11000000)
Bit 3
Bit 2
Bit 1
Bit 0
BIDIROE
RXDMAE
SPISWAI
SPC0
Chapter 37 Serial Peripheral Interface (SPI)
=
=
=
=
0
0
0
0
SPI data I/O pin acts as input
DMA request disabled
SPI clocks operate in wait mode uses separate pins for data input and output
SPIx_BR = 0x00(%00000000)
Bit 7
Bit 6:4
Bit 3:0
SPIx_S = 0x00(%00000000)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3:0
SPRF
SPMF
SPTEF
MODF
=
=
=
0 Reserved
000 Sets prescale divisor to 1
0000 Sets baud rate divisor to 2
=
=
=
=
=
0
0
0
0
0
Flag is set when receive data buffer is full
Flag is set when SPIx_MH/ML = receive data buffer
Flag is set when transmit data buffer is empty
Mode fault flag for master mode
FIFOMODE is not enabled
SPIx_MH = 0xXX
In 16-bit mode, this register holds bits 8–15 of the hardware match buffer. In 8-bit mode, writes to this register will be ignored.
SPIx_ML = 0xXX
Holds bits 0–7 of the hardware match buffer.
SPIx_DH = 0xxx
In 16-bit mode, this register holds bits 8–15 of the data to be transmitted by the transmit buffer and received by the receive buffer.
SPIx_DL = 0xxx
Holds bits 0–7 of the data to be transmitted by the transmit buffer and received by the receive buffer.
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Initialization/application information
RESET
INITIALIZE SPI
SPIxC1 = 0x54
SPIxC2 = 0xC0
SPIxBR = 0x00
SPIxMH = 0xXX
YES
SPTEF = 1
?
YES
WRITE TO
SPIxDH:SPIxDL
NO
SPRF = 1
?
YES
READ
SPIxDH:SPIxDL
NO
SPMF = 1
?
YES
READ SPMF WHILE SET
TO CLEAR FLAG,
THEN WRITE A 1 TO IT
NO
CONTINUE
Figure 37-40. Initialization Flowchart Example for SPI Master Device in 16-bit Mode for
FIFOMODE = 0
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Chapter 37 Serial Peripheral Interface (SPI)
RESET
INITIALIZE SPI
SPIxC1 = 0x54
SPIxC2 = 0xC0
SPIxBR = 0x00
SPIxMH = 0xXX
Set FIFOMODE
WRITE TO
SPIxDH:SPIxDL
YES
TXFULLF = 1
?
YES
RNFULLF = 1/
SPRF = 1
?
YES
READ
SPIxDH:SPIxDL
RFIFOEF = 1
?
YES
CONTINUE
Figure 37-41. Initialization Flowchart Example for SPI Master Device in 16-bit Mode for
FIFOMODE = 1
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