Initialization information
28.5 Initialization information
This section gives an example that provides some basic direction on how to initialize and configure the ADC module.
The user can configure the module for 16-bit, 12-bit, 10-bit, or 8-bit single-ended resolution or 16-bit, 13-bit, 11-bit, or 9-bit differential resolution, single or continuous conversion, and a polled or interrupt approach, among many other options. For
information used in this example, refer to Table 28-73 , Table 28-74
, and Table 28-75
.
Note
Hexadecimal values are designated by a preceding 0x, binary values designated by a preceding %, and decimal values have no preceding character.
28.5.1 ADC module initialization example
28.5.1.1 Initialization sequence
Before the ADC module can be used to complete conversions, an initialization procedure must be performed. A typical sequence is:
1. Calibrate the ADC by following the calibration instructions in
Calibration function
.
2. Update CFG to select the input clock source and the divide ratio used to generate
ADCK. This register is also used for selecting sample time and low-power configuration.
3. Update SC2 to select the conversion trigger, hardware or software, and compare function options, if enabled.
4. Update SC3 to select whether conversions will be continuous or completed only once
(ADCO) and whether to perform hardware averaging.
5. Update SC1:SC1n registers to select whether conversions will be single-ended or differential and to enable or disable conversion complete interrupts. Also, select the input channel which can be used to perform conversions.
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KL26 Sub-Family Reference Manual, Rev. 3.2, October 2013
Freescale Semiconductor, Inc.
Chapter 28 Analog-to-digital converter (ADC)
28.5.1.2 Pseudo-code example
In this example, the ADC module is set up with interrupts enabled to perform a single 10bit conversion at low-power with a long sample time on input channel 1, where ADCK is derived from the bus clock divided by 1.
CFG1 = 0x98 (%10011000)
Bit 7 ADLPC 1 Configures for low power, lowers maximum clock speed.
Bit 6:5 ADIV 00 Sets the ADCK to the input clock ÷ 1.
Bit 4 ADLSMP 1 Configures for long sample time.
Bit 3:2 MODE 10 Selects the single-ended 10-bit conversion, differential 11bit conversion.
Bit 1:0 ADICLK 00 Selects the bus clock.
SC2 = 0x00 (%00000000)
Bit 7 ADACT 0 Flag indicates if a conversion is in progress.
Bit 6 ADTRG 0 Software trigger selected.
Bit 5 ACFE 0 Compare function disabled.
Bit 4 ACFGT 0 Not used in this example.
Bit 3 ACREN 0 Compare range disabled.
Bit 2 DMAEN 0 DMA request disabled.
Bit 1:0 REFSEL 00 Selects default voltage reference pin pair (External pins V
REFH and V
REFL
).
SC1A = 0x41 (%01000001)
Bit 7 COCO 0 Read-only flag which is set when a conversion completes.
Bit 6 AIEN 1 Conversion complete interrupt enabled.
Bit 5 DIFF 0 Single-ended conversion selected.
Bit 4:0 ADCH 00001 Input channel 1 selected as ADC input channel.
RA = 0xxx
Holds results of conversion.
CV = 0xxx
Holds compare value when compare function enabled.
KL26 Sub-Family Reference Manual, Rev. 3.2, October 2013
Freescale Semiconductor, Inc.
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