10.8 Features Register. Hitachi IC25N080ATMR04, IC25N040ATMR04-0 - Travelstar 40GB Laptop Hard Drive 9.5mm 2.5 Inch Notebook HDD, IC25N080ATMR04-0 - 3E034 - Dell 80GB Laptop Hard Drive, Travelstar 80GN, IC25N020ATMR04, 08K0910, IC25N040ATMR04, IC25N060ATMR04, IC25N030ATMR04

10.8 Features Register

This register is command specific. This register is used with the Set Features command, the S.M.A.R.T. Function

Set command, and the Format Unit command.

10.9 LBA High Register

This register is command specific. This is used with the Set Features command, S.M.A.R.T. Function Set command and Format Unit command.

When 48-bit addressing commands are used, the "most recently written" content contains LBA Bits 16-23, and the

"previous content" contains Bits 40-47. The 48-bit Address feature set is described in Section 11.15, "48-bit

Address Feature Set," on page 89.

10.10 LBA Mid Register

This register contains Bits 8-15. At the end of the command, this register is updated to reflect the current LBA

Bits 8-15.

When 48-bit addressing commands are used, the "most recently written" content contains LBA Bits 8-15 and the

"previous content" contains Bits 32-39.

10.11 Sector Count Register

This register contains the number of sectors of data requested to be transferred on a read or write operation between the host and the device. If the value in the register is set to 0, a count of 256 sectors (in 28-bit addressing) or 65,536 sectors (in 48-bit addressing) is specified.

If the register is zero at command completion, the command was successful. If not successfully completed, the register contains the number of sectors which need to be transferred in order to complete the request.

The contents of the register are defined otherwise on some commands. These definitions are given in the command descriptions.

10.12 Status Register

Table 43: Status Register

7

BSY

6

DRDY

5

DF

4

DSC

3

DRQ

2

COR

1

IDX

0

ERR

This register contains the device status. The contents of this register are updated whenever an error occurs and at the completion of each command.

If the host reads this register when an interrupt is pending, it is considered to be the interrupt acknowledge. Any pending interrupt is cleared whenever this register is read.

If BSY=1, no other bits in the register are valid.

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Bit Definitions

BSY

DRDY

(RDY)

DF

DSC

DRQ

CORR

IDX

ERR

Busy. Bit BSY=1 whenever the device is accessing the registers. The host should not read or write any registers when BSY=1. If the host reads any register when BSY=1, the contents of the Status

Register will be returned.

Device Ready. When bit RDY=1 it indicates that the device is capable of responding to a command. Bit RDY will be set to 0 during power on until the device is ready to accept a command.

Device Fault. It DF=1 it indicates that the device has detected a write fault condition. Bit DF is set to 0 after the Status Register is read by the host.

Device Seek Complete. If DSC=1, it indicates that a Seek has completed and the device head is settled over a track. Bit DSC is set to 0 by the device just before a Seek begins. When an error occurs, this bit is not changed until the Status Register is read by the host and at that time the bit again indicates the current Seek complete status. When the device enters into or is in Standby mode or Sleep mode, this bit is set by device in spite of the drive not spinning up.

Data Request. Bit DRQ=1 indicates that the device is ready to transfer a word or byte of data between the host and the device. The host should not write the Command register when DRQ=1.

Corrected Data. Always 0

IDXIndex. Bit IDX=1 once per revolution. Since IDX=1, only for a very short time during each revolution, the host may not see it set to 1 even if the host is reading the Status Register continuously. Therefore the host should not attempt to use IDX bit for timing purposes.

Error. Bit ERR=1 indicates that an error occurred during execution of the previous command. The

Error Register should be read to determine the error type. The device sets bit ERR=0 when the next command is received from the host.

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