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- Intel
- AT80571RG0601ML
- Data Sheet
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Electrical Specifications
Figure 1.
2.6.3
Table 6.
Processor V
CC
Static and Transient Tolerance
VID - 0.088
VID - 0.100
VID - 0.113
VID - 0.125
VID - 0.138
VID - 0.150
VID - 0.163
VID - 0.175
VID - 0.188
VID - 0.000
0
VID - 0.013
VID - 0.025
VID - 0.038
VID - 0.050
VID - 0.063
VID - 0.075
5 10 15
Vcc Typical
20 25 30
Vcc Minimum
35
Icc [A]
40 45 50
Vcc Maximum
55 60 65 70 75
NOTES:
1.
The loadline specification includes both static and transient limits except for overshoot allowed as shown in
2.
This loadline specification shows the deviation from the VID set point.
3.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Design Guide for socket loadline guidelines and VR implementation details.
V
CC
Overshoot
The processor can tolerate short transient overshoot events where V
CC
exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + V
OS_MAX
(V
OS_MAX
is the maximum allowable overshoot voltage).
The time duration of the overshoot event must not exceed T
OS_MAX
(T
OS_MAX
is the maximum allowable time duration above VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.
V
CC
Overshoot Specifications
Symbol Parameter Min Max Unit Figure Notes
V
OS_MAX
Magnitude of V
CC
VID
overshoot above
— 50 mV
1
T
OS_MAX
Time duration of V
CC
VID
overshoot above
— 25 µs
NOTES:
1.
Adherence to these specifications is required to ensure reliable processor operation.
20 Datasheet
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Key Features
- IntelĀ® CeleronĀ® E3200 2.4 GHz
- 1 MB L2 LGA 775 (Socket T)
- Processor cores: 2 45 nm 64-bit 65 W
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Table of contents
- 9 Introduction
- 9 Terminology
- 10 Processor Terminology Definitions
- 11 References
- 13 Electrical Specifications
- 13 Power and Ground Lands
- 13 Decoupling Guidelines
- 13 VCC Decoupling
- 13 VTT Decoupling
- 14 FSB Decoupling
- 14 Voltage Identification
- 16 Reserved, Unused, and TESTHI Signals
- 16 Power Segment Identifier (PSID)
- 17 Voltage and Current Specification
- 17 Absolute Maximum and Minimum Ratings
- 18 DC Voltage and Current Specification
- 20 VCC Overshoot
- 21 Die Voltage Validation
- 21 Signaling Specifications
- 22 FSB Signal Groups
- 23 CMOS and Open Drain Signals
- 24 Processor DC Specifications
- 25 Platform Environment Control Interface (PECI) DC Specifications
- 26 GTL+ Front Side Bus Specifications
- 27 Clock Specifications
- 27 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
- 28 FSB Frequency Select Signals (BSEL[2:0])
- 29 Phase Lock Loop (PLL) and Filter
- 29 BCLK[1:0] Specifications
- 33 Package Mechanical Specifications
- 33 Package Mechanical Drawing
- 37 Processor Component Keep-Out Zones
- 37 Package Loading Specifications
- 37 Package Handling Guidelines
- 38 Package Insertion Specifications
- 38 Processor Mass Specification
- 38 Processor Materials
- 38 Processor Markings
- 39 Processor Land Coordinates
- 41 Land Listing and Signal Descriptions
- 41 Processor Land Assignments
- 64 Alphabetical Signals Reference
- 75 Thermal Specifications and Design Considerations
- 75 Processor Thermal Specifications
- 75 Thermal Specifications
- 78 Thermal Metrology
- 78 Processor Thermal Features
- 78 Thermal Monitor
- 80 On-Demand Mode
- 81 PROCHOT# Signal
- 81 THERMTRIP# Signal
- 82 Platform Environment Control Interface (PECI)
- 82 Introduction
- 82 TCONTROL and TCC activation on PECI-Based Systems
- 83 PECI Specifications
- 83 PECI Device Address
- 83 PECI Command Support
- 83 PECI Fault Handling Requirements
- 83 PECI GetTemp0() Error Code Support
- 85 Features
- 85 Power-On Configuration Options
- 85 Clock Control and Low Power States
- 86 Normal State
- 86 HALT and Extended HALT Powerdown States
- 86 HALT Powerdown State
- 87 Extended HALT Powerdown State
- 87 Stop Grant and Extended Stop Grant States
- 87 Stop-Grant State
- 88 Extended Stop Grant State
- 88 Stop Grant Snoop State, and Stop Grant Snoop State
- 88 HALT Snoop State, Stop Grant Snoop State
- 88 Extended HALT Snoop State, Extended Stop Grant Snoop State
- 88 Sleep State
- 89 Deep Sleep State
- 89 Deeper Sleep State
- 90 Technology
- 90 Processor Power Status Indicator (PSI) Signal
- 91 Boxed Processor Specifications
- 91 Introduction
- 92 Mechanical Specifications
- 92 Boxed Processor Cooling Solution Dimensions
- 93 Boxed Processor Fan Heatsink Weight
- 93 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly
- 93 Electrical Requirements
- 93 Fan Heatsink Power Supply
- 95 Thermal Specifications
- 95 Boxed Processor Cooling Requirements
- 97 Variable Speed Fan
- 99 Debug Tools Specifications
- 99 Logic Analyzer Interface (LAI)
- 99 Mechanical Considerations
- 99 Electrical Considerations