User manual

PCI-1202/1602/1800/1802 Hardware User’s Manual

3.6.2 The status register

The format of the status register is given as follows:

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

MSB LSB

Bit 7: FIFO half-full : 0 Æ FIFO is half-full.

Bit 6: FIFO full : 0 Æ FIFO is full.

Bit 5: FIFO empty : 0 Æ FIFO is empty.

Bit 4: ADC busy : 0 Æ ADC is busy.

Bit 3: External trigger : For PCI-180x Ver. C: 0 Æ timer-1 is disable

1 Æ timer-1 is enable

For PCI-180x Ver. F: 0 Æ waiting external trigger signal

1 Æexternal trigger signal is active.

Bit 2: handshake signal between host (PC) and MagicScan controller.

Bit 1: ODM indicator: non-ODM version Æ 0.

Bit 0: Output of machine independent timer. This bit is equal to 0 if the machine independent timer is start. This bit will be set to 1 if the machine independent timer is up.

Version: 3.8 (Mar.2007, PPH-014-38) ---- 59