Signal Name
Address Bus
Address Strobe
Autovector
Bus Error
Bus Grant
Bus Grant Acknowledge
Breakpoint
Bus Request
System Clockout
Chip Selects
Boot Chip Select
Data Bus
Data Strobe
Data and Size Acknowledge
Development Serial In, Out,
Clock
Crystal Oscillator
Function Codes
Freeze
Halt
Instruction Pipeline
Interrupt Request Level
Master In Slave Out
Clock Mode Select
Master Out Slave In
Port C
Peripheral Chip Select
Port E
Port F
Port QS
Freescale Semiconductor, Inc.
Table 5 MCU Signal Characteristics (Continued)
Signal Name
TSC
TXD
XFC
XTAL
MCU Module
SIM
QSM
SIM
SIM
Signal Type
Input
Output
Input
Output
2.5 Signal Function
Active State
—
—
—
—
Table 6 MCU Signal Function
Mnemonic
ADDR[23:0] 24-bit address bus
AS
AVEC
Function
Indicates that a valid address is on the address bus
Requests an automatic vector during interrupt acknowledge
BERR
BG
BGACK
BKPT
Indicates that a bus error has occurred
Indicates that the MCU has relinquished the bus
Indicates that an external device has assumed bus mastership
Signals a hardware breakpoint to the CPU
BR
CLKOUT
CS[10:0]
CSBOOT
Indicates that an external device requires bus mastership
System clock output
Select external devices at programmed addresses
Chip select for external boot start-up ROM
DATA[15:0] 16-bit data bus
DS During a read cycle, indicates when it is possible for an external device to place data on the data bus. During a write cycle, indicates that valid data is on the data bus.
DSACK[1:0] Provide asynchronous data transfers and dynamic bus sizing
DSI, DSO,
DSCLK
Serial I/O and clock for background debugging mode
EXTAL, XTAL Connections for clock synthesizer circuit reference; a crystal or an external oscillator can be used
FC[2:0]
FREEZE
HALT
IFETCH
IPIPE
IRQ[7:1]
MISO
Identify processor state and current address space
Indicates that the CPU has entered background mode
Suspend external bus activity
Indicate instruction pipeline activity
MODCLK
MOSI
PC[6:0]
PCS[3:0]
PE[7:0]
PF[7:0]
PQS[7:0]
Provides an interrupt priority level to the CPU
Serial input to QSPI in master mode; serial output from QSPI in slave mode
Selects the source and type of system clock
Serial output from QSPI in master mode; serial input to QSPI in slave mode
SIM digital output port signals
QSPI peripheral chip selects
SIM digital I/O port signals
SIM digital I/O port signals
QSM digital I/O port signals
MC68332
MC68332TS/D For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
13
Signal Name
Quotient Out
Reset
Read-Modify-Write Cycle
Read/Write
SCI Receive Data
QSPI Serial Clock
Size
Slave Select
TCR2 Clock
TPU Channel Pins
Three-State Control
SCI Transmit Data
External Filter Capacitor
Freescale Semiconductor, Inc.
Table 6 MCU Signal Function (Continued)
Mnemonic
QUOT
RESET
Function
Provides the quotient bit of the polynomial divider
System reset
RMC
R/W
RXD
SCK
Indicates an indivisible read-modify-write instruction
Indicates the direction of data transfer on the bus
Serial input to the SCI
Clock output from QSPI in master mode; clock input to QSPI in slave mode
Indicates the number of bytes to be transferred during a bus cycle SIZ[1:0]
SS Causes serial transmission when QSPI is in slave mode; causes mode fault in master mode
T2CLK External clock source for TCR2 counter
TPUCH[15:0] Bidirectional pins associated with TPU channels
TSC
TXD
XFC
Places all output drivers in a high-impedance state
Serial output from the SCI
Connection for external phase-locked loop filter capacitor
MOTOROLA
14 For More Information On This Product,
Go to: www.freescale.com
MC68332
MC68332TS/D
