Address Map. NXP MC68332

Freescale Semiconductor, Inc.

6.2 Address Map

The “Access” column in the QSM address map below indicates which registers are accessible only at the supervisor privilege level and which can be assigned to either the supervisor or user privilege level, according to the value of the SUPV bit in the QSMCR.

Table 24 QSM Address Map

S/U

S/U

S/U

S/U

S/U

S/U

S/U

S/U

S/U

S/U

Access

S

S

S

S/U

S/U

S/U

S/U

S/U

S/U

S/U

Address 15 8 7 0

$YFFC00 QSM MODULE CONFIGURATION (QSMCR)

$YFFC02

$YFFC04

QSM TEST (QTEST)

QSM INTERRUPT LEVEL (QILR) QSM INTERRUPT VECTOR (QIVR)

$YFFC06

$YFFC08

$YFFC0A

$YFFC0C

NOT USED

SCI CONTROL 0 (SCCR0)

SCI CONTROL 1 (SCCR1)

SCI STATUS (SCSR)

$YFFC0E

$YFFC10

SCI DATA (SCDR)

NOT USED

$YFFC12

$YFFC14 NOT USED

NOT USED

PQS DATA (PORTQS)

$YFFC16 PQS PIN ASSIGNMENT (PQSPAR) PQS DATA DIRECTION (DDRQS)

$YFFC18

$YFFC1A

$YFFC1C

$YFFC1E

SPI CONTROL 0 (SPCR0)

SPI CONTROL 1 (SPCR1)

SPI CONTROL 2 (SPCR2)

SPI CONTROL 3 (SPCR3)

NOT USED

SPI STATUS (SPSR)

$YFFC20–

$YFFCFF

$YFFD00–

$YFFD1F

$YFFD20–

$YFFD3F

$YFFD40–

$YFFD4F

RECEIVE RAM (RR[0:F])

TRANSMIT RAM (TR[0:F])

COMMAND RAM (CR[0:F])

Y = M111, where M is the logic state of the MM bit in the SIMCR.

MC68332

MC68332TS/D For More Information On This Product,

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MOTOROLA

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