1.1.2. Intel Download Cables Supporting Configuration in Intel Stratix 10 Devices. Intel Stratix 10

1. Intel ® Stratix ® 10 Configuration Overview

UG-S10CONFIG | 2018.11.02

1.1.2. Intel Download Cables Supporting Configuration in Intel Stratix 10

Devices

Intel provides the following cables to download your design to the Intel Stratix 10 device on the PCB. Download cables support prototyping activity by providing detailed debug messages via Intel Quartus Prime Programmer. You must use Intel download cables for advanced debugging using the Signal Tap logic analyzer the System

Console.

Table 2.

Intel Stratix 10-Supported Download Cable Capabilities

Download Cable

Intel FPGA Download Cable II

(formerly the USB-Blaster II)

Intel FPGA Ethernet Cable (formerly the EthernetBlaster II)

Protocol Support Intel Stratix 10

Device

JTAG, AS

JTAG, AS

Cable Connection to PCB

10-pin female plug

3M Part number: 2510-6002UB

10-pin female plug

For more information about download cables refer to Intel FPGAs and Programmable

Devices / Download Cables . This web page includes links to the user guides for all the cables listed in Table 2 on page 8.

1.2. Intel Stratix 10 Configuration Architecture

The Secure Device Manager (SDM) is a triple-redundant processor-based module that manages configuration and the security features of Intel Stratix 10 devices. The SDM is available on all Intel Stratix 10 FPGAs and SoC devices.

The block diagram below provides an overview of the Intel Stratix 10 configuration architecture which includes the following blocks:

• Secure device manager (SDM): More information about SDM is contained in later sections.

• Configuration network: The SDM uses this dedicated, parallel configuration network to distribute the configuration bitstream to Local Sector Managers (LSMs).

You cannot access this network.

• LSMs: The LSM is a microprocessor. Each configuration sector includes an LSM.

The LSM parses configuration bitstream and configures the logic elements for its sector. After configuration, the microprocessors perform the following functions:

— Monitors for single event upsets at the sector level

— Processes responses to SEUs

— Performs hashing or integrity checks in real time

• Specific blocks for Intel Stratix 10 variants:

— SX devices include the hard processor system (HPS) in addition to FPGA logic.

— MX devices include a High Bandwidth Memory (HBM) in addition to FPGA logic.

— GX devices include FPGA logic and L- and H-Tile transceivers.

TX devices include FPGA logic and E- and H-Tile transceivers.

Intel Stratix 10 Configuration User Guide

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