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5. Remote System Upgrade
UG-S10CONFIG | 2018.11.02
5.4. Remote System Upgrade Flash Device Layout
The Intel Quartus Prime Programming Files Generator populates the flash memory when you generate the remote system upgrade programming files.
Table 30.
Offset
0k
256k
512k
768k
1M
1M+64k
Next
Next + 32k
Next + 32k
Next + 32k
Varies
Varies
Varies
Remote System Upgrade Flash Memory Layout
The start of flash address 0, or the A2 partition within a partitioned flash address 0, must be set up as shown in the following table.
Size (Byte) Usage Sub-Partition Name
BOOT_INFO
(remote system upgrade boot image)
Sub-Partition Flag
Reserved
Address
(Bit 0)
YES
Read-Only
(Bit 1)
YES 256k
256k
256k
256k
64k
Varies
32k
32k
32k
32k
Varies
Varies
Varies
Static Firmware Section
Static Firmware Section
Static Firmware Section
Static Firmware Section
Reserved
Factory Image
Sub-partition table
Sub-partition table
(Back-up copy)
Configuration firmware pointer block
Configuration firmware pointer block (Back-up copy)
Application image 1
Application image 2
Application image N
FACTORY_IMAGE
SPT0
SPT1
CPB0
CPB1
APP_IMAGE1
( 14 )
APP_IMAGE2
( 14 )
APP_IMAGEN
( 14 )
YES
YES
NO
NO
NO
YES
YES
YES
NO
NO
NO
YES
NO
NO
NO
NO
5.4.1. Configuration Firmware Pointer Block (CPB)
The configuration firmware accesses the configuration firmware pointer block when performing remote system upgrade. The Intel Quartus Prime Programming Files
Generator sets up the initial configuration firmware pointer block. Each copy of the configuration firmware pointer block (CPB0/CPB1) must be exactly 4 KB.
(14) User-assigned sub-partition name.
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Intel Stratix 10 Configuration User Guide
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Table of contents
- 4 10 Configuration Overview
- 7 1.1.1. Configuration and Related Signals
- 8 1.1.2. Intel Download Cables Supporting Configuration in Intel Stratix 10 Devices
- 8 1.2. Intel Stratix 10 Configuration Architecture
- 9 1.2.1. Secure Device Manager
- 12 2. Intel Stratix 10 Configuration Details
- 12 2.1. Configuration Flow Diagram
- 14 2.2. Intel Stratix 10 Configuration Timing Diagram
- 16 Memory (HBM2) and SmartVID
- 17 2.4. Intel Stratix 10 Configuration Pins
- 17 2.4.1. SDM Pin Mapping
- 18 2.4.2. MSEL Settings
- 19 2.4.3. Device Configuration Pins
- 21 2.4.4. Setting Additional Configuration Pins
- 22 2.4.5. Enabling Dual-Purpose Pins
- 23 2.5. Setting Configuration Clock Source
- 24 2.6. Configuration Clocks
- 24 2.6.1. OSC_CLK_1 Clock Input
- 25 2.7. Configuration and Programming Files
- 27 3. Intel Stratix 10 Configuration Schemes
- 27 3.1. Avalon-ST Configuration
- 28 3.1.1. Enabling Avalon-ST Device Configuration
- 28 3.1.2. Avalon-ST Configuration Timing
- 30 3.1.3. Avalon-ST Single-Device Configuration
- 32 3.1.4. RBF Configuration File Format
- 33 3.1.5. Debugging Guidelines for the Avalon-ST Configuration Scheme
- 34 Flash Loader II IP Core
- 51 3.2. AS Configuration
- 51 3.2.1. AS Single-Device Configuration
- 52 3.2.2. AS Using Multiple Serial Flash Devices
- 53 3.2.3. AS Configuration Timing
- 54 3.2.4. Programming Serial Flash Devices
- 56 3.2.5. Serial Flash Memory Layout
- 57 3.2.6. AS_CLK
- 58 3.2.7. Active Serial Configuration Software Settings
- 59 3.2.8. Generating and Programming AS Configuration Programming Files
- 61 3.2.9. Debugging Guidelines for the AS Configuration Scheme
- 62 3.3. Configuration from SD MMC
- 62 3.3.1. SD MMC Single-Device Configuration
- 63 3.4. JTAG Configuration
- 64 3.4.1. JTAG Single-Device Configuration
- 66 3.4.2. JTAG Multi-Device Configuration
- 67 3.4.3. Debugging Guidelines for the JTAG Configuration Scheme
- 69 4. Stratix 10 Configuration Features
- 69 4.1. Device Security
- 69 4.2. Configuration via Protocol
- 71 4.3. Partial Reconfiguration
- 72 5. Remote System Upgrade
- 74 5.1. Remote System Upgrade Functional Description
- 74 5.1.1. Remote System Upgrade Using AS Configuration
- 75 5.1.2. Remote System Upgrade Configuration Images
- 76 5.1.3. Remote System Upgrade Configuration Sequence
- 77 5.2. Guidelines for Performing Remote System Upgrade Functions for Non-HPS
- 78 5.3. Commands and Error Codes
- 79 5.3.1. Operation Commands
- 82 5.3.2. Error Code Responses
- 83 5.4. Remote System Upgrade Flash Device Layout
- 83 5.4.1. Configuration Firmware Pointer Block (CPB)
- 84 5.5. Generating Remote System Upgrade Image Files using Programming File Generator
- 84 5.5.1. Generating a Standard RSU Image
- 85 5.5.2. Generating a Single RSU Image
- 86 5.6. Remote System Upgrade from FPGA Core Example
- 87 5.7. Prerequisites
- 87 Application Image
- 91 5.9. Programming Flash Memory with Initial Remote System Upgrade Image
- 92 5.10. Reconfiguring the Device with an Application or Factory Image
- 93 5.11. Adding an Application Image
- 96 5.12. Removing Application Image
- 98 6. Intel Stratix 10 Debugging Guide
- 98 6.1. Intel Stratix 10 Debugging Overview
- 98 6.2. Configuration Pin Differences from Previous Device Families
- 100 6.3. Configuration File Format Differences
- 100 6.4. Understanding and Troubleshooting Configuration Pin Behavior
- 101 6.4.1. nCONFIG
- 102 6.4.2. nSTATUS
- 102 6.4.3. CONF_DONE and INIT_DONE
- 103 6.4.4. SDM_IO Pins
- 106 7. Intel Stratix 10 Configuration User Guide Archives
- 107 8. Document Revision History for the Intel Stratix 10 Configuration User Guide